A planar gate silicon carbide IGBT device and method of manufacture

Abstract

The application discloses a planar gate silicon carbide IGBT device and a manufacturing method thereof. The device comprises, from bottom to top, a P+ collector region layer, an N-drift region layer and an N-type carrier storage layer. Two P-type base region layers are formed on the top of the N-type carrier storage layer, and an N+ emitter region layer is arranged on the top of the P-type base region layer. A gate structure is arranged between the two P-type base region layers. The device is also provided with an emitter and a collector. Two first P-type shielding layers and second P-type shielding layers are arranged in a staggered mode in the N-type carrier storage layer. The staggered P-type shielding structure optimizes the internal electric field distribution of the device, shifts the electric field peak value, greatly reduces the electric field intensity of the gate structure, effectively protects the gate structure, and improves the long-term working reliability of the device. Meanwhile, the doping parameters of the N-type carrier storage layer are optimized, the on-state voltage drop of the device is reduced, the breakdown voltage of the device is improved, and the compromise relationship between the on-state voltage drop and the breakdown voltage is optimized.

Description

Technical Field

[0001] This application relates to the field of silicon carbide semiconductor device technology, and in particular to a planar gate silicon carbide IGBT device and its manufacturing method. Background Technology

[0002] As power electronics technology develops towards higher efficiency, miniaturization, and higher frequency, power semiconductor devices, as the core of energy conversion and control, directly determine the operating efficiency and reliability of power electronic systems. Although traditional silicon-based insulated-gate bipolar transistors (Si IGBTs) dominate the medium- and high-voltage fields, they are gradually showing bottlenecks in high-voltage, high-temperature, and high-frequency scenarios due to the limitations of the physical properties of silicon materials.

[0003] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, offers significantly superior device performance compared to Si IGBTs, making it a core component in fields such as new energy power generation, new energy vehicles, and smart grids. However, the difference in carrier mobility in SiC materials leads to a severely uneven carrier distribution in the N-drift region layer when SiC IGBTs are turned on: the carrier concentration near the active region is much lower than that on the collector side, significantly weakening the conductivity modulation effect and limiting further reductions in the on-state voltage drop.

[0004] To address these issues, existing technologies primarily employ either a carrier storage layer (CSL) structure to increase the carrier concentration in the N-drift region or high-temperature thermal oxidation to extend the bipolar carrier lifetime. However, these methods all have significant drawbacks: the uneven carrier concentration distribution within the N-drift region weakens the conductivity modulation effect, making it difficult to further reduce the on-state voltage drop; and the introduction of a carrier storage layer structure significantly increases the peak electric field at the gate oxide layer, reducing the long-term reliability of the device and making it difficult to balance the trade-off between on-state voltage drop and breakdown voltage. Summary of the Invention

[0005] This application aims to solve at least one of the technical problems existing in the prior art. To this end, this application proposes a planar gate silicon carbide IGBT device and its fabrication method. The planar gate silicon carbide IGBT device can optimize the electric field distribution, reduce the electric field strength, protect the gate structure, and improve the breakdown voltage.

[0006] A planar gate silicon carbide IGBT device according to a first aspect of this application includes, from bottom to top, a P+ collector layer, an N- drift region layer, and an N-type carrier storage layer; a P-type base layer, with two P-type base layers formed on top of the N-type carrier storage layer; an N+ emitter layer, with the N+ emitter layer formed on top of the P-type base layer; a gate structure, formed above the N-type carrier storage layer, with a gap between the two P-type base layers, and the gate structure located above the gap; an emitter, electrically connected to the N+ emitter layer; a collector, electrically connected to the P+ collector layer; a first P-type shielding layer, with two first P-type shielding layers formed within the N-type carrier storage layer, the first P-type shielding layers located at the bottom of the N-type carrier storage layer; and a second P-type shielding layer, formed within the N-type carrier storage layer, and the second P-type shielding layer located above the two first P-type shielding layers.

[0007] The planar gate silicon carbide IGBT device according to the embodiments of this application has at least the following beneficial effects: two first P-type shielding layers and one second P-type shielding layer are added to the N-type carrier storage layer to form an interleaved P-type shielding layer, which optimizes the electric field distribution, changes the direction of the electric field lines from the collector, shields a large number of electric field lines that originally pointed to the gate structure, and transfers the electric field peak from the gate structure to the P-type shielding layer and the N-type carrier storage layer, significantly reducing the electric field intensity of the gate structure, avoiding premature aging due to excessive electric field, and ensuring the long-term reliability of the device.

[0008] Because the gate structure is protected, the N-type carrier storage layer does not need to limit the doping concentration and thickness in order to control the electric field of the gate structure. It can safely adopt a design with higher doping concentration and greater thickness, effectively reducing the on-state voltage drop. The overall breakdown voltage of the device does not decrease but increases, optimizing the trade-off between on-state voltage drop and breakdown voltage.

[0009] The first P-type shielding layer, located at the bottom of the N-type carrier storage layer, can adjust the injection and distribution of carriers, making the carrier concentration distribution inside the N-drift region layer more uniform. This avoids the problem that carriers are only concentrated at the top of the drift region in traditional carrier storage layer structures, further enhancing the conductivity modulation effect of the entire drift region and providing room for further reduction of the on-state voltage drop.

[0010] According to some embodiments of this application, there is a gap between the two P-type base regions, the gap being a JFET region, and the gate structure is located above the JFET region; the second P-type shielding layer is located below the JFET region, and the JFET region is used to connect the N-type carrier storage layer and the emitter to form a carrier path controlled by the gate structure.

[0011] According to some embodiments of this application, the lower boundary of the first P-type shielding layer coincides with the lower boundary of the N-type carrier storage layer.

[0012] According to some embodiments of this application, the doping concentration of the second P-type shielding layer is greater than the doping concentration of the first P-type shielding layer.

[0013] According to some embodiments of this application, both the first P-type shielding layer and the second P-type shielding layer are in a floating potential state within the N-type carrier storage layer.

[0014] According to some embodiments of this application, an N-type buffer layer is further disposed between the P+ collector layer and the N- drift layer. The N-type buffer layer is used to suppress the rapid extraction of holes injected into the P+ collector layer, thereby forming a hole barrier.

[0015] According to some embodiments of this application, the gate structure includes a gate and an oxide layer, the oxide layer surrounding the outside of the gate.

[0016] According to some embodiments of this application, a P+ contact layer is also included, the P+ contact layer being formed on the P-type base layer, and the emitter being electrically connected to the P+ contact layer.

[0017] A method for manufacturing a planar gate silicon carbide IGBT device according to a second aspect embodiment of the present application and according to the first aspect embodiment of the present application includes the following steps: The N-drift region layer is formed on the P+ collector region layer, and the N-type carrier storage layer is formed on the N-drift region layer; Ions are injected into both sides of the N-type carrier storage layer. The ions flow from the side of the N-type carrier storage layer to the middle of the N-type carrier storage layer, forming two first P-type shielding layers symmetrically arranged with the center line of the N-type carrier storage layer. An N-type silicon carbide material is deposited on the N-type carrier storage layer in a direction away from the N-drift region layer to increase the thickness of the N-type carrier storage layer; Ion implantation is performed at the centerline of the thickened N-type carrier storage layer, and ions flow from the center to both sides to form the second P-type shielding layer. N-type silicon carbide material is deposited again on the N-type carrier storage layer in a direction away from the N-drift region layer to increase the thickness of the N-type carrier storage layer; Ions are injected into both sides of the N-type carrier storage layer away from the N-drift region layer. The ions flow from the side of the N-type carrier storage layer to the middle of the N-type carrier storage layer to form two P-type base regions. Ions are injected into each P-type base region layer to form an N+ emitter region layer. An oxide layer is sequentially grown, annealed, and polysilicon is deposited on the surface of the N-type carrier storage layer and the surface of the P-type base region layer to form a gate structure. Metal is deposited and annealed at the end of the P+ collector region layer away from the N- drift region layer to form a collector electrode, and metal is deposited and annealed at the end of the N+ emitter region layer away from the N-type carrier storage layer to form an emitter electrode.

[0018] According to some embodiments of this application, when ions are injected into both sides of the N-type carrier storage layer to form the first P-type shielding layer, a mask injection is used; when ions are injected into both sides of the N-type carrier storage layer away from the N-drift region layer to form the P-type base region layer, a mask injection is used; and the mask used in both steps is the same mask.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0020] The present application will be further illustrated below with reference to the accompanying drawings and embodiments. It should be noted that the embodiments illustrated in the following drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0021] Figure 1 This is a schematic diagram of a traditional planar gate silicon carbide IGBT device structure. Figure 2 This is a schematic diagram of the planar gate silicon carbide IGBT device structure according to an embodiment of this application; Figure 3 This is a schematic diagram of the device structure in step S1 of the planar gate silicon carbide IGBT device manufacturing method according to an embodiment of this application; Figure 4 This is a schematic diagram of the device structure in step S2 of the planar gate silicon carbide IGBT device manufacturing method according to an embodiment of this application; Figure 5 This is a schematic diagram of the device structure in steps S3 and S4 of the planar gate silicon carbide IGBT device manufacturing method according to an embodiment of this application; Figure 6 This is a schematic diagram of the device structure in steps S5 and S6 of the planar gate silicon carbide IGBT device manufacturing method according to an embodiment of this application; Figure 7This is a schematic diagram of the device structure in step S7 of the planar gate silicon carbide IGBT device manufacturing method according to an embodiment of this application; Figure 8 This is a schematic diagram of the device structure in step S8 of the planar gate silicon carbide IGBT device manufacturing method according to an embodiment of this application; Figure 9 These are the conduction characteristic curves of the conventional device and the device of this application in a simulation comparison of embodiments of this application; Figure 10 This is a comparison diagram of the two-dimensional electric field distribution along the cell edge of a conventional device and the device of this application in a simulation comparison of embodiments of this application under a forward blocking voltage of 20kV; Figure 11 This is a comparison diagram of the two-dimensional electric field intensity distribution at the emission extreme of the conventional device and the device of this application when they break down in the simulation comparison of the embodiments of this application, and a comparison of the maximum electric field intensity of the gate oxide layer; Figure 12 This is a comparison of the trade-off curves between the on-state voltage drop and breakdown voltage of the conventional device and the device of this application under different N-type carrier storage layer doping concentrations in the simulation comparison of the embodiments of this application.

[0022] Figure label: 100, P+ collector region layer; 200, N- drift region layer; 210, N-type buffer layer; 300, N-type carrier storage layer; 400, P-type base region layer; 500, N+ emitter region layer; 610, gate; 620, oxide layer; 700, P+ contact region layer; 710, emitter; 720, collector; 810, first P-type shielding layer; 820, second P-type shielding layer. Detailed Implementation

[0023] The embodiments of this application are described in detail below with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0024] In the description of this application, it should be understood that the terms "center", "middle", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0025] In the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0026] In the description of this application, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0027] In the description of this application, the use of terms such as "one embodiment," "some embodiments," "an example," "some instances," "some embodiments," "illustrative embodiment," "example," "specific example," and "some examples" indicates that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0028] Reference Figure 1 The diagram shows a traditional planar gate silicon carbide IGBT structure. The hole barrier formed by the concentration difference between the N-type carrier storage layer and the N-drift region layer 200, to some extent, prevents the holes above the N-drift region layer 200 from being extracted by the emitter 710, increasing the hole concentration, i.e., carrier concentration, on the active region side of the N-drift region layer 200. This enhances the conductivity modulation effect and reduces the on-state voltage drop. However, the introduced N-type carrier storage layer 300 exacerbates the electric field concentration in the active region, significantly increasing the electric field strength of the gate structure. This leads to problems such as gate oxide degradation, threshold voltage drift, and a surge in gate leakage current, affecting the long-term reliability of the device. It also significantly reduces the breakdown voltage, making it impossible to balance the performance relationship between on-state voltage drop and breakdown voltage.

[0029] Reference Figure 2According to an embodiment of this application, a planar gate silicon carbide IGBT includes, from bottom to top, a P+ collector layer 100, an N- drift region layer 200, and an N-type carrier storage layer 300, and further includes a P-type base layer 400, an N+ emitter layer 500, a gate structure, a first P-type shielding layer 810, and a second P-type shielding layer 820. Two P-type base layers 400 are formed on top of the N-type carrier storage layer 300, and the two P-type base layers 400 are respectively located on opposite sides of the top of the N-type carrier storage layer 300. An N+ emitter layer 500 is formed on top of each P-type base layer 400; a gate structure is formed above the N-type carrier storage layer 300, with a gap between the two P-type base layers 400, and the gate structure is located above the gap; an emitter 710 is electrically connected to the N+ emitter layer 500, and a collector 720 is electrically connected to the P+ collector layer 100. Two first P-type shielding layers 810 are formed within the N-type carrier storage layer 300, and are disposed at the bottom of the N-type carrier storage layer 300. A second P-type shielding layer 820 is formed within the N-type carrier storage layer 300, with a gap between the two first P-type shielding layers 810, and the second P-type shielding layer 820 is located above the gap.

[0030] When the device is in the forward blocking state, the staggered structure composed of the two first P-type shielding layers 810 and the second P-type shielding layer 820 changes the direction of the electric field lines from the collector 720, shielding a large number of electric field lines that originally pointed to the gate structure, greatly reducing the electric field concentration on the active region side. In conventional devices, the PN junction formed by the P-type base layer 400 and the N-type carrier storage layer 300 bears the peak electric field. However, in this device, the peak electric field is borne by the PN junction formed by the two first P-type shielding layers 810 and the N-drift region layer 200, and the PN junction formed by the second P-type shielding layer 820 and the N-type carrier storage layer 300, significantly reducing the electric field strength of the gate oxide layer. Through this design, the reliability problem of the gate structure caused by the N-type carrier storage layer 300 in the traditional planar gate 610 silicon carbide IGBT structure can be effectively solved, effectively protecting the gate structure and ensuring the long-term reliability of the device.

[0031] Reference Figure 2In some embodiments, the X direction in the figure represents upward, and the P-type shielding layer is configured in an alternating layout with two first P-type shielding layers 810 below and one second P-type shielding layer 820 above. The second P-type shielding layer 820 is located on the centerline axis of the device cell, while a pair of first P-type shielding layers 810 are symmetrically distributed below the second P-type shielding layer 820 on both sides. In the forward blocking state, the two first P-type shielding layers 810 are completely depleted, changing the direction of the electric field and alleviating the concentration of electric field lines below the P-type base layer 400. At the same time, the second P-type shielding layer 820 is not completely depleted, attracting electric field lines from the collector 720 end, causing the electric field lines to terminate in the undepleted region of the second P-type shielding layer 820. The first P-type shielding layer 810 and the second P-type shielding layer 820 form a more uniform and controlled electric field shielding region, avoiding local electric field concentration and greatly reducing the electric field strength of the JFET region between the gate structure and the two P-type base layers 400. This makes the breakdown voltage capability of the entire device more stable and provides protection for the gate structure.

[0032] Because the gate structure is protected, the N-type carrier storage layer 300 does not need to limit the doping concentration and thickness in order to control the electric field of the gate structure. It can safely adopt a design with higher doping concentration and greater thickness, effectively reducing the on-state voltage drop. The overall breakdown voltage of the device does not decrease but increases, thus optimizing the trade-off between the on-state voltage drop and the breakdown voltage.

[0033] In some embodiments, the N-type carrier storage layer 300 in the planar gate silicon carbide IGBT device of this application adopts a design with higher doping concentration and greater thickness than the N-type carrier storage layer 300 of the conventional planar gate silicon carbide IGBT device. Doping concentration refers to the number of impurity atoms incorporated into a unit volume of semiconductor material. The higher the doping concentration, the stronger the blocking ability for holes. A higher doping concentration can form a stronger hole barrier. The carrier concentration, i.e., the hole concentration, of the N-drift region layer 200 near the N-type carrier storage layer 300 is greater, which can significantly enhance the conductivity modulation effect. While reducing the on-state voltage drop, it also increases the breakdown voltage and reduces the gate structure electric field strength. Therefore, it has a better trade-off between conduction and breakdown performance.

[0034] According to some embodiments of this application, there is a gap between the two P-type base regions 400, which is a JFET region. The gate structure is located above the JFET region; the second P-type shielding layer 820 is located below the JFET region. The gate structure is above the JFET region, and there are P-type base regions 400 on both sides. The JFET region is located on the central axis of the planar gate silicon carbide IGBT device cell of this application. The second P-type shielding layer 820 is directly below the JFET region. The FET region is used to connect the N-type carrier storage layer 300 and the emitter 710 side to form a carrier path controlled by the gate structure. The two first P-type shielding layers 810 are arranged on both sides below the second P-type shielding layer 820 to form an interleaved shielding structure, which can effectively reduce the electric field of the gate structure and improve reliability.

[0035] According to some embodiments of this application, the lower boundary of the first P-type shielding layer 810 coincides with the lower boundary of the N-type carrier storage layer 300. That is, the lower boundary of the first P-type shielding layer 810 is flush with the upper boundary of the N-drift region layer 200. With this design, the PN junction formed by the P-type base region layer 400 and the N-type carrier storage layer 300 no longer bears the electric field peak. Instead, the electric field peak is borne by the PN junction formed by the two symmetrically arranged first P-type shielding layers 810 and the N-shielding region. Concentrating the electric field stress here, away from the gate structure, can significantly reduce the electric field strength of the gate structure, effectively protect the gate structure, and ensure the long-term reliability of the device.

[0036] According to some embodiments of this application, the doping concentration of the second P-type shielding layer 820 is greater than that of the first P-type shielding layer 810. For semiconductor shielding layers, the higher the doping concentration, the more difficult it is to be completely depleted under the same electric field, and the stronger the electric field shielding capability.

[0037] The second P-type shielding layer 820, with a higher doping concentration, is less likely to be completely depleted. It attracts electric field lines from the collector 720, causing the electric field to terminate in the undepleted region of the second P-type shielding layer 820, thus acting as the primary shield. Conversely, the first P-type shielding layer 810, with a lower doping concentration, is more easily depleted, thereby altering the direction of the electric field lines and alleviating the concentration of electric field lines below the P-type base layer 400. Through the design of both structures and doping concentrations, more efficient and precise control of the blocking electric field distribution is achieved, reducing the electric field strength in the JFET region and gate structure, and protecting the gate structure.

[0038] According to some embodiments of this application, both the first P-type shielding layer 810 and the second P-type shielding layer 820 are in a floating potential state within the N-type carrier storage layer 300. That is, the first P-type shielding layer 810 and the second P-type shielding layer 820 are not electrically connected to any electrode and have no fixed potential. The first P-type shielding layer 810 and the second P-type shielding layer 820 in the floating potential state are interleaved to form an interleaved P-type shielding layer, which optimizes the electric field distribution in the active region of the IGBT device, not only reducing the electric field strength and protecting the gate structure, but also improving the breakdown voltage.

[0039] According to some embodiments of this application, an N-type buffer layer 210 is further disposed between the P+ collector layer 100 and the N- drift layer 200. The N-type buffer layer 210 forms a hole barrier, suppressing the rapid extraction of holes injected into the P+ collector layer 100, increasing the carrier concentration at the bottom of the N- drift layer 200, enhancing the conductivity modulation effect of the drift region, thereby reducing the on-state voltage drop of the device; at the same time, the N-type buffer layer 210 can also serve as a field cutoff layer, suppressing the excessive extension of the PN junction depletion layer of the P+ collector layer 100 to the N- drift layer 200, preventing punch-through breakdown of the device, and rapidly absorbing excess carriers during the turn-off process, reducing tail current and lowering turn-off losses.

[0040] According to some embodiments of this application, the gate structure includes a gate 610 and an oxide layer 620, with the oxide layer 620 surrounding the gate 610. The oxide layer 620 is formed between two P-type base regions 400 and serves as an insulating dielectric, isolating the gate 610 from the underlying region.

[0041] According to some embodiments of this application, a P+ contact layer 700 is also included. The P+ contact layer 700 forms a low-resistance ohmic contact with the emitter 710 metal, providing a current path for the P-type base layer 400. This allows for the timely removal of excess holes accumulated in the P-type base layer 400 during conduction, clamping the potential of the P-type base layer 400 to a level close to the emitter 710 potential. Here, potential clamping refers to preventing the potential from rising due to the accumulation of excess holes in the base region through a low-resistance current path, keeping it at a low potential close to the emitter, and fundamentally preventing latch-up effects in the device.

[0042] The method for manufacturing the planar gate silicon carbide IGBT device according to the embodiments of this application can be referred to in detail. Figures 3-8 The process includes the following steps: Reference Figure 3 An N-drift region layer 200 is formed on the P+ collector region layer 100, and an N-type carrier storage layer 300 is formed on the N-drift region layer 200. In this step, an N-type buffer layer 210 can be formed on the P+ collector region layer 100 according to the needs of the actual application, and an N-drift region layer 200 can be formed on the N-type buffer layer 210.

[0043] Reference Figure 4 Ion implantation is performed from both sides of the N-type carrier storage layer 300. Ions flow from the sides of the N-type carrier storage layer towards the center to form two first P-type shielding layers 810. The two first P-type shielding layers are symmetrically arranged around the centerline of the N-type carrier storage layer 300. In this step, the mask used for ion implantation is shared with the subsequent implantation step to form the P-type base layer 400, reducing the use of mask. The lower boundaries of the two first P-type shielding layers 810 coincide with the upper boundary of the N-drift region layer 200.

[0044] After the injection of the first P-type shielding layer 810 is completed, N-type silicon carbide material is deposited on the N-type carrier storage layer 300 in a direction away from the N-drift region layer 200 to increase the thickness of the N-type carrier storage layer 300 and grow an additional part of the N-type carrier storage layer 300, completely burying the two first P-type shielding layers 810.

[0045] Reference Figure 5 Ion implantation is performed at the center of the thickened N-type carrier storage layer 300, with ions flowing from the center outwards to form a second P-type shielding layer 820. In this step, the ion implantation dose of the second P-type shielding layer 820 is greater than that of the first P-type shielding layer 810, so that the doping concentration of the second P-type shielding layer 820 is greater than that of the first P-type shielding layer 810. A gap exists between the two first P-type shielding layers 810, and the second P-type shielding layer 820 is located above this gap, forming an alternating shielding region.

[0046] After the second P-type shielding layer 820 is injected, the thickness of the N-type carrier storage layer 300 is increased again in the direction away from the N-drift region layer 200, so as to completely bury the second P-type shielding layer 820 and grow the remaining N-type carrier storage layer 300.

[0047] Reference Figure 6 Ion implantation is performed on both sides of the N-type carrier storage layer 300 away from the N-drift region layer 200. A P-type base layer 400 is formed by Al high-temperature force implantation and N-temperature high-temperature ion implantation. An N+ emitter layer 500 is formed by implanting ions on top of the P-type base layer 400 and next to the N+ emitter layer 500. Simultaneously, a P+ contact layer 700 is formed by ion implantation on top of the P-type base layer 400 and next to the N+ emitter layer 500. Then, a carbon film is applied for coverage, followed by high-temperature annealing to activate impurities and repair lattice damage. The ion implantation of the P-type base layer 400 and the ion implantation of the first P-type shielding layer 810 share a single mask, eliminating the need for an additional mask.

[0048] Reference Figure 7Next, a high-quality gate oxide layer is grown on the surface of the N-type carrier storage layer 300 and the P-type base region layer 400 by high-temperature dry oxidation, and the channel mobility is improved by oxidation annealing in N2O atmosphere. Then, polysilicon is deposited and patterned to form the gate structure, interlayer dielectric is deposited, the interlayer dielectric is patterned and ohmic contact vias are etched.

[0049] Reference Figure 8 Metal is deposited and annealed at the end of the P+ collector layer 100 away from the N- drift layer to form a collector electrode 720 electrically connected to the P+ collector layer 100, and an emitter 710 is formed at the end of the N+ emitter layer 500 away from the N-type carrier storage layer 300, thus completing the fabrication of the entire planar gate silicon carbide IGBT device.

[0050] To more comprehensively demonstrate the effect of the planar gate silicon carbide IGBT in the embodiments of the present invention, a simulation comparison was performed on the planar gate silicon carbide IGBT provided by the present invention and the traditional planar gate SiC IGBT using the two-dimensional simulation software TCAD. The simulation parameters are shown in Table 1 below.

[0051] Table 1 Simulation parameters of conventional planar gate silicon carbide IGBT devices and the planar gate silicon carbide IGBT device of this application.

[0052] Reference Figure 9 This is a simulation comparison of the conduction characteristic JV curves of the planar gate silicon carbide IGBT device of this application and a conventional planar gate silicon carbide IGBT device at a gate voltage of 20V. The horizontal axis is Vce (V is the forward voltage between the collector 720 and the emitter 710, which is the on-state voltage drop of the IGBT), and the vertical axis is Jce (A / cm). 2 The collector current density is 720A / cm², which represents the current carrying capacity of the device, i.e., the current that can pass through a unit chip area. We take the current density as 50A / cm². 2 The voltage across the collector 720 and emitter 710 is the on-state voltage drop. The on-state voltage drops of the planar gate silicon carbide IGBT device of this application and those of the conventional planar gate silicon carbide IGBT device are 4.32V and 4.8V, respectively. Compared with the conventional planar gate silicon carbide IGBT device, the on-state voltage drop of the planar gate silicon carbide IGBT device of this application is 10%, and the conduction characteristics are significantly optimized.

[0053] Reference Figure 10The figures show a simulation comparison of the two-dimensional electric field distribution and magnified views along the cell edges of the planar gate silicon carbide IGBT device of this application and a conventional planar gate silicon carbide IGBT device under the same forward blocking voltage of 20kV. The horizontal axis y (μm) represents the vertical depth of the device, with the end of y close to 0 being the emitter 710 of the device. The vertical axis Electric Field (MV / cm) represents the electric field strength at that vertical depth. As shown in the figure, under a voltage of 20kV, the peak electric field at the emitter 710 of the planar gate silicon carbide IGBT device of this invention is reduced by approximately 0.2 MV / cm compared to the peak electric field at the emitter 710 of the conventional planar gate silicon carbide IGBT device, representing a reduction of 10%. This invention, through the synergistic effect of the upper and lower shielding layers, disperses the electric field stress originally concentrated at the interface of the oxide layer 620 at the emitter 710 end to two different depths inside the N-drift region layer 200. Without sacrificing the overall withstand voltage capability of the device, it significantly reduces the electric field strength at the weakest point of the emitter 710 end.

[0054] Reference Figure 11 This figure shows a comparison of the two-dimensional electric field intensity distribution at the emitter 710 terminal of the planar gate silicon carbide IGBT device of this application and a conventional planar gate silicon carbide IGBT device during breakdown, as well as simulation results comparing the maximum electric field intensity of the oxide layer 620. The left side of the figure shows the planar gate silicon carbide IGBT device of this application, and the right side shows the conventional planar gate silicon carbide IGBT device.

[0055] As shown in the figure, during breakdown, the maximum electric field strength of the oxide layer 620 in a traditional planar gate silicon carbide IGBT device is 3.89 MV / cm, which is greater than 3 MV / cm. Long-term operation can lead to aging and failure of the oxide layer 620. However, the planar gate silicon carbide IGBT device of this application, through the synergistic electric field shielding effect of the upper and lower P-type shielding layers, reduces the peak electric field at the corner of the oxide layer 620 to 1.82 MV / cm, significantly less than 3 MV / cm, a reduction of 50.7%. This transfers the high electric field stress originally concentrated at the gate structure to the P-type shielding layer, ensuring the long-term reliability of the device. The planar gate silicon carbide IGBT device of this application optimizes the electric field distribution at the emitter 710 terminal, increasing the breakdown voltage from 21.5 kV for the planar gate silicon carbide IGBT device to 23.3 kV, improving the breakdown voltage while ensuring that the electric field strength of the oxide layer 620 is significantly less than 3 MV / cm.

[0056] Reference Figure 12The above is a simulation result comparing the trade-off curves between the on-state voltage drop and breakdown voltage of the planar gate silicon carbide IGBT device of the present invention and the traditional planar gate silicon carbide IGBT device under different N-type carrier storage layer doping concentrations. The horizontal axis is On-state Voltage Drop (V), which is the on-state voltage drop, and the vertical axis is Breakdown Voltage (kV), which is the breakdown voltage.

[0057] In the figure, the doping concentration of the N-type carrier storage layer in a traditional planar gate silicon carbide IGBT device ranges from 1 × 10⁻⁶. 16 cm -3 Up to 4×10 16 cm -3 As the doping concentration increases, the on-state voltage drop decreases, and the breakdown voltage decreases. The doping concentration of the N-type carrier storage layer in the planar gate silicon carbide IGBT device of this invention varies from 2 × 10⁻⁶ to 10⁻⁶. 16 cm -3 Up to 5×10 16 cm -3 As the doping concentration increases from the lowest to the highest, the on-state voltage drop decreases from 4.7V to 4.3V, while the breakdown voltage of the device remains stable at 30kV over a long period, never falling below 20kV. As shown in the figure, at the same breakdown voltage, the proposed planar gate silicon carbide IGBT with an interlaced P-type shielding layer exhibits a smaller on-state voltage drop, indicating a better trade-off between on-state voltage drop and breakdown voltage. This achieves a significant simultaneous improvement in both conduction performance and withstand voltage, overcoming the core deficiency in existing technologies where it is difficult to balance on-state voltage drop and breakdown voltage.

[0058] The planar gate silicon carbide IGBT device of this application incorporates two first P-type shielding layers 810 and one second P-type shielding layer 820 in the N-type carrier storage layer 300, forming an interleaved P-type shielding structure. This optimizes the electric field distribution, changes the direction of the electric field lines from the collector 720 segment, shields part of the electric field lines, and shifts the peak electric field from the gate structure to the P-type shielding layer and the N-type carrier storage layer 300. This significantly reduces the electric field intensity of the gate structure, prevents it from aging prematurely due to excessively high electric fields, and ensures the long-term reliability of the device.

[0059] Because the gate structure is protected, the N-type carrier storage layer 300 can be safely designed with higher doping concentration and greater thickness, effectively reducing the on-state voltage drop. The overall breakdown voltage of the device does not decrease but increases, optimizing the trade-off between on-state voltage drop and breakdown voltage.

[0060] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application. Furthermore, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

Claims

1. A planar gate silicon carbide IGBT device, comprising: The P+ collector region layer, N- drift region layer, and N-type carrier storage layer are arranged sequentially from bottom to top. The side of the N-type carrier storage layer away from the N- drift region layer forms two P-type base regions and a gate structure. An N+ emitter region layer is formed on the P-type base layer. The N+ emitter region layer is electrically connected to the emitter. The P+ collector region layer is electrically connected to the collector. Its characteristic is that it further includes: A first P-type shielding layer, two first P-type shielding layers are formed within the N-type carrier storage layer, and the first P-type shielding layer is located at the bottom of the N-type carrier storage layer; A second P-type shielding layer is formed within the N-type carrier storage layer; Wherein, there is a gap between the two first P-type shielding layers, the second P-type shielding layer is located above the gap, there is a gap between the two P-type base regions, the gap is configured as the JFET region of the N-type carrier storage layer, and the second P-type shielding layer is located below the JFET region; The two first P-type shielding layers and the second P-type shielding layer change the direction of the electric field lines from the collector and reduce the electric field strength of the gate structure. The doping concentration of the second P-type shielding layer is greater than that of the first P-type shielding layer; Both the first P-type shielding layer and the second P-type shielding layer are in a floating potential state within the N-type carrier storage layer.

2. The planar gate silicon carbide IGBT device according to claim 1, characterized in that: The gate structure is located above the JFET region; The JFET region is used to connect the N-type carrier storage layer and the emitter, forming a carrier path controlled by the gate structure.

3. The planar gate silicon carbide IGBT device according to claim 1, characterized in that: The lower boundary of the first P-type shielding layer coincides with the lower boundary of the N-type carrier storage layer.

4. The planar gate silicon carbide IGBT device according to claim 1, characterized in that: An N-type buffer layer is also provided between the P+ collector layer and the N- drift layer. The N-type buffer layer is used to suppress the rapid extraction of holes injected by the P+ collector layer in order to form a hole barrier.

5. The planar gate silicon carbide IGBT device according to claim 1, characterized in that: The gate structure includes a gate and an oxide layer, with the oxide layer surrounding the outside of the gate.

6. The planar gate silicon carbide IGBT device according to claim 1, characterized in that: It also includes a P+ contact layer, which is formed on the P-type base layer, and the emitter is electrically connected to the P+ contact layer.

7. A method for manufacturing a planar gate silicon carbide IGBT device, applied to the planar gate silicon carbide IGBT device as described in any one of claims 1-6, characterized in that, Includes the following steps: The N-drift region layer is formed on the P+ collector region layer, and the N-type carrier storage layer is formed on the N-drift region layer; Ions are injected into both sides of the N-type carrier storage layer. The ions flow from the side of the N-type carrier storage layer to the middle of the N-type carrier storage layer, forming two first P-type shielding layers symmetrically arranged with the center line of the N-type carrier storage layer. An N-type silicon carbide material is deposited on the N-type carrier storage layer in a direction away from the N-drift region layer to increase the thickness of the N-type carrier storage layer; Ion implantation is performed at the centerline of the thickened N-type carrier storage layer, and ions flow from the center to both sides to form the second P-type shielding layer. N-type silicon carbide material is deposited again on the N-type carrier storage layer in a direction away from the N-drift region layer to increase the thickness of the N-type carrier storage layer; Ions are injected into both sides of the N-type carrier storage layer away from the N-drift region layer. The ions flow from the side of the N-type carrier storage layer to the middle of the N-type carrier storage layer to form two P-type base regions. Ions are injected into each P-type base region layer to form an N+ emitter region layer. An oxide layer is sequentially grown, annealed, and polysilicon is deposited on the surface of the N-type carrier storage layer and the surface of the P-type base region layer to form a gate structure. Metal is deposited and annealed at the end of the P+ collector region layer away from the N- drift region layer to form a collector electrode, and metal is deposited and annealed at the end of the N+ emitter region layer away from the N-type carrier storage layer to form an emitter electrode.

8. The method for manufacturing a planar gate silicon carbide IGBT device according to claim 7, characterized in that, When ions are injected into both sides of the N-type carrier storage layer to form the first P-type shielding layer, a mask injection is used. When ions are injected into both sides of the N-type carrier storage layer away from the N-drift region layer to form the P-type base region layer, a mask injection is used. The mask used in both steps is the same mask.

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