Method of forming a metal silicide and semiconductor structure

Abstract

The application provides a metal silicide forming method and a semiconductor structure, and particularly relates to the technical field of semiconductors. The forming method comprises the following steps: providing a substrate, the surface of the substrate having exposed silicon; sequentially forming a barrier layer and a first metal film on the substrate; forming a patterned mask layer on the first metal film, the patterned mask layer having openings corresponding to non-metal silicide regions; etching the first metal film with the patterned mask layer as a mask, and removing the first metal film located in the non-metal silicide regions; performing metal-assisted catalytic etching with a wet etching liquid, selectively removing the barrier layer under the first metal film, so that the first metal film is settled and contacts the exposed silicon on the surface of the substrate; selectively depositing a second metal film on the first metal film; and performing annealing treatment on the substrate to form a metal silicide. The application can avoid abnormal silicification in non-target regions, solve the problem of metal residues, and improve the reliability and yield of devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming metal silicides and a semiconductor structure. Background Technology

[0002] Metal silicides are critical process materials in semiconductor device manufacturing. They reduce contact resistance in specific areas of semiconductor devices (such as gate and active regions), ensuring electrical performance and operational stability, and are widely used in the manufacturing processes of various semiconductor chips. However, for specific functional areas such as electrostatic discharge (ESD) protection circuits, the presence of metal silicides can compromise the protection performance of the circuit, adversely affecting the reliability of the device. Therefore, in non-silicide regions, a self-aligned block (SAB) must be pre-deposited. The SAB prevents the subsequently deposited metal from reacting and bonding with the silicon substrate, thereby achieving precise separation between the metal silicide and non-silicide regions and ensuring the normal operation of each functional area of ​​the device.

[0003] Currently, the mainstream method for preparing metal silicides is a self-aligned process: first, a thin film of metal such as NiPt is deposited on the surface of a silicon substrate, allowing only the target area to react with silicon to form silicides, and then excess metal is removed by wet etching. However, this process has two major drawbacks: first, Ni is easily oxidized, requiring pretreatment to remove oxides before deposition, but this also etches the SAB barrier layer in the non-metal silicide area, causing damage to the SAB barrier layer and failure of its isolation effect, resulting in the formation of excess metal silicides in the non-metal silicide area and damaging device function; second, Pt has stable chemical properties, and traditional wet etching is difficult to completely remove it, resulting in metal residues. These residues can lead to poor device contact, abnormal electrical performance, and even device failure.

[0004] Therefore, there is an urgent need to provide a new method for forming metal silicides to effectively improve the shortcomings of the existing processes. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the present invention provides a method for forming metal silicides and a semiconductor structure to improve the problem of excess metal silicides forming in non-metal silicide regions.

[0006] To achieve the above and other related objectives, the present invention provides a method for forming metal silicides, the method comprising the following steps: A substrate is provided, the surface of which has exposed silicon, the exposed silicon comprising metal silicide regions and non-metal silicide regions; A barrier layer and a first metal film are sequentially formed on the substrate, wherein the material of the first metal film includes platinum; A patterned mask layer is formed on the first metal film, the patterned mask layer having openings corresponding to the non-metallic silicide regions; Using the patterned mask layer as a mask, the first metal film is etched to remove the first metal film located in the non-metallic silicide region, while retaining the first metal film located in the metallic silicide region. Metal-assisted catalytic etching is performed using a wet etching solution, with the retained first metal film as a catalyst, to selectively remove the barrier layer beneath the first metal film, causing the first metal film to settle and come into contact with the exposed silicon on the substrate surface. A second metal film is selectively deposited on the first metal film, wherein the material of the second metal film includes nickel; The substrate is annealed to cause a silicide reaction at the contact points between the second metal film, the first metal film and the exposed silicon on the surface of the substrate, forming metal silicides.

[0007] In one embodiment of the present invention, the material of the barrier layer is selected from silicon oxynitride or titanium nitride.

[0008] In one embodiment of the present invention, in the step of etching the first metal film using the patterned mask layer as a mask, a dry etching process is used to etch the first metal film, and the etching gas for the dry etching is a mixture of carbon monoxide and chlorine.

[0009] In one embodiment of the present invention, in the step of using a wet etching solution for metal-assisted catalytic etching, the wet etching solution includes an oxidant, an etchant, and water. The oxidant includes any one of hydrogen peroxide, ozone, and nitric acid, and the etchant is hydrofluoric acid.

[0010] In one embodiment of the present invention, the oxidant accounts for 1 ppm to 30 ppm of the total volume of the wet etching solution, and the etchant accounts for 0.1% to 10% of the total volume of the wet etching solution.

[0011] In one embodiment of the present invention, the method for selectively depositing a second metal film on the first metal film includes: chemical reduction.

[0012] In one embodiment of the present invention, the thickness ratio of the second metal film to the first metal film is (80:20) to (99:1).

[0013] In one embodiment of the present invention, the annealing temperature is 400℃~600℃.

[0014] In one embodiment of the present invention, the step of forming a patterned mask layer on the first metal film includes: A photoresist layer is spin-coated onto the first metal film; The photoresist layer is exposed and developed according to a preset pattern to form a patterned photoresist layer that matches the target non-metallic silicide region. The patterned photoresist layer is etched back to maintain a thickness of 3nm~50nm, forming a patterned mask layer.

[0015] The present invention also provides a semiconductor structure comprising a metal silicide prepared by the above-described formation method.

[0016] The unexpected technical effects of this invention are as follows: This invention introduces metal-assisted catalytic etching technology, utilizing a first metal film as a catalyst to rapidly etch the barrier layer beneath it during the etching process, thereby causing the first metal film to settle onto the substrate surface. Meanwhile, the barrier layer in non-metallic silicide regions not covered by the first metal film, lacking the catalytic effect of the metal, experiences an extremely low etching rate and is thus completely preserved. This mechanism fundamentally avoids the thinning and perforation damage to the barrier layer caused by chemical erosion during pretreatment in traditional processes, effectively improving potential problems such as device leakage and abnormal silicide formation in non-target areas, and significantly enhancing device reliability and yield.

[0017] After the first metal film settles, the present invention selectively deposits metal on its surface and performs annealing treatment, which can completely convert platinum into the target alloy product, eliminating the problem of metal residue caused by the high chemical stability of platinum and its difficulty in removal in traditional processes.

[0018] This invention utilizes the strong catalytic activity of platinum to achieve selective nickel deposition, simplifying the traditional two-step annealing process into a single-step annealing process. This optimization not only significantly simplifies the semiconductor device manufacturing process and reduces production complexity, but also effectively reduces the thermal budget during device manufacturing, avoids damage to the device structure caused by multi-step high-temperature annealing, and further improves process compatibility and device performance stability. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0020] In the attached diagram: Figures 1-8 The diagram shows the structure of each step in the existing method for forming self-aligned metal silicides. Figure 9 A schematic diagram of metal silicides formed by existing processes; Figure 10This is a flowchart of a method for forming metal silicides according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a substrate provided in one embodiment of the present invention; Figure 12 This is a schematic diagram of a substrate provided in one embodiment of the present invention, wherein a barrier layer and a first metal film are formed on the substrate; Figure 13 This is a schematic diagram of the structure for forming a patterned photoresist layer according to one embodiment of the present invention; Figure 14 This is a schematic diagram of the structure for forming a patterned mask layer provided in one embodiment of the present invention; Figure 15 This is a schematic diagram of the structure of the first metal film etched away in one embodiment of the present invention; Figure 16 This is a schematic diagram of the structure after metal-assisted catalytic etching according to one embodiment of the present invention; Figure 17 This is a schematic diagram of a structure for selectively depositing a second metal film on a first metal film according to an embodiment of the present invention; Figure 18 This is a schematic diagram of the structure after annealing in one embodiment of the present invention.

[0021] The attached figures are labeled as follows: 100, Substrate; 101, Metal silicide region; 102, Non-metal silicide region; 103, Gate structure; 200, Barrier layer; 300, First metal film; 310, Nickel-platinum alloy layer; 400, Photoresist layer; 401, Patterned photoresist layer; 410, Patterned mask layer; 500, Second metal film; 600, Metal silicide; 610, Initial metal silicide. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0024] In this document, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0025] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0026] Metal silicide technology is one of the core processes commonly used in semiconductor fabrication. Its core principle is to generate stable metal silicides by chemically reacting metal materials with silicon-based materials, thereby effectively reducing the contact resistance of specific areas of semiconductor devices and ensuring the stability of device electrical performance. It is widely used in the manufacturing processes of various semiconductor chips.

[0027] Figures 1 to 8 A schematic diagram of the structure corresponding to each step of a conventional method for forming metal silicides is shown. The method specifically includes the following steps: like Figure 1 As shown, a substrate 100 is provided, the surface of which has exposed silicon; in addition, local structures of semiconductor devices, such as gate structures, source and drain structures (not shown in the figure), can also be pre-formed on the substrate 100 to lay the foundation for the subsequent preparation of metal silicides.

[0028] like Figure 2 As shown, a barrier layer 200 and a photoresist layer 400 are sequentially formed on the entire surface of the substrate 100. The photoresist layer 400 is used to define the target formation area of ​​the metal silicide through subsequent photolithography processes. The core function of the barrier layer 200 is to isolate the metal from the silicon-based material and prevent the metal in the non-metal silicide region from reacting and bonding with the silicon. The material can be conventional isolation materials such as silicon oxide.

[0029] like Figure 3 As shown, a series of processes such as exposure and development are performed on the photoresist layer 400 using photolithography to transfer the pattern of the metal silicide region onto the photoresist layer 400, forming a patterned photoresist layer 401. The opening area of ​​the patterned photoresist layer 401 corresponds to the target formation area of ​​the metal silicide.

[0030] like Figure 4 As shown, using the patterned photoresist layer 401 as a mask, the barrier layer 200 is etched to remove the barrier layer 200 in the target area of ​​the metal silicide, exposing the exposed silicon surface of the substrate 100 in this area, while retaining the barrier layer 200 in the non-metal silicide area to ensure that the metal in the non-metal silicide area does not react and bond with the silicon after subsequent metal deposition; after etching, conventional processes such as ashing are used to remove the patterned photoresist layer 401.

[0031] like Figure 5 As shown, a nickel-platinum alloy layer 310 is deposited on the surface of the substrate 100 after the above treatment. During the deposition process, the nickel-platinum alloy layer 310 will cover the entire surface of the substrate 100, that is, it will not only cover the exposed silicon area, but also the surface of the barrier layer 200 will be deposited with the nickel-platinum alloy layer 310. The deposition thickness of the nickel-platinum alloy layer 310 can be flexibly selected according to actual production needs.

[0032] like Figure 6 As shown, the substrate 100 with the deposited nickel-platinum alloy layer 310 is subjected to a first annealing treatment. Under the annealing conditions, the nickel-platinum alloy that is in direct contact with the exposed silicon surface of the substrate 100 will react chemically with the silicon to generate the initial metal silicide 610. However, the nickel-platinum alloy layer 310 on the surface of the barrier layer 200 cannot contact the substrate silicon due to the isolation effect of the barrier layer 200, so it will not undergo silicide reaction and will still exist in the form of unreacted nickel-platinum alloy.

[0033] like Figure 7 As shown, the nickel-platinum alloy layer 310 on the surface of the barrier layer 200 that has not undergone silicide reaction is removed by wet etching and other methods, leaving only the initial metal silicide 610 generated on the substrate 100.

[0034] like Figure 8 As shown, after removing the unreacted nickel-platinum alloy layer 310, the substrate 100 undergoes a second annealing process. The initial metal silicide PtNiSi2 is converted into stable PtNiSi through the annealing process, and finally metal silicide 600 that meets the device design requirements is formed.

[0035] However, the existing metal silicide manufacturing process has two major technical defects that seriously affect the yield and reliability of semiconductor devices: First, nickel (Ni) is easily oxidized in air or the process environment to form Ni oxide. This Ni oxide directly hinders the normal chemical reaction between Ni and the substrate silicon. Therefore, before depositing the nickel-platinum alloy layer 310, the substrate 100 needs to be pretreated (e.g., acid pickling) to remove the oxide. At the same time, the barrier layer 200 in the non-metal silicide region will inevitably be etched, resulting in damage to the barrier layer 200 and failure of its isolation function. Consequently, the non-metal silicide region, which should have avoided the formation of metal silicides, will undergo a mis-reaction between metal and silicon, generating excess metal silicides and damaging the normal function of the semiconductor device. Second, platinum (Pt) has extremely high chemical stability. Traditional wet etching solutions have limited etching ability on the unreacted nickel-platinum alloy layer 310 and cannot completely remove the unreacted NiPt metal remaining on the surface of the barrier layer 200 and the substrate 100. Figure 9 In the I region, these metal residues can lead to poor device contact, abnormal electrical performance, and in severe cases, even device failure, thus limiting the performance improvement of semiconductor devices.

[0036] To improve the aforementioned process defects, this invention provides a method for forming metal silicides: introducing metal-assisted catalytic etching technology, using a first metal film as a catalyst to rapidly etch the barrier layer below it and cause the first metal film to sink to the substrate surface. The barrier layer in the non-metal silicide region not covered by the first metal film is completely preserved due to the lack of catalytic effect, avoiding barrier layer damage and abnormal silicide formation in non-target areas; at the same time, a second metal film is selectively deposited on the first metal film, eliminating the need to remove the unreacted metal layer separately, completely solving the metal residue problem, and improving device reliability and yield.

[0037] Please see Figure 10 The method for forming metal silicides according to the present invention includes the following steps: S1. A substrate 100 is provided, the surface of which has exposed silicon, and the exposed silicon includes metal silicide regions 101 and non-metal silicide regions 102 (see...). Figure 11 ); S2. A barrier layer 200 and a first metal film 300 are sequentially formed on the substrate 100, wherein the material of the first metal film 300 includes platinum (see...). Figure 12 ); S3. A patterned mask layer 410 is formed on the first metal film 300. The patterned mask layer 410 has openings corresponding to the non-metallic silicide regions 102 (see...). Figure 13 and Figure 14 ); S4. Using the patterned mask layer 410 as a mask, etch the first metal film 300 to remove the first metal film 300 located in the non-metallic silicide region 102, while retaining the first metal film 300 located in the metallic silicide region 101 (see...). Figure 15 ); S5. Metal-assisted catalytic etching is performed using a wet etching solution, with the retained first metal film 300 as a catalyst. The barrier layer 200 below the first metal film 300 is selectively removed, causing the first metal film 300 to settle and contact the exposed silicon on the surface of the substrate 100 (see...). Figure 16 ); S6. Selectively deposit a second metal film 500 on the first metal film 300, the material of the second metal film 500 including nickel (see...). Figure 17 ); S7. Anneal the substrate 100 to induce a silicide reaction at the contact points between the second metal film 500, the first metal film 300, and the exposed silicon on the surface of the substrate 100, forming a metal silicide 600 (see...). Figure 18 ).

[0038] The following is combined Figures 11 to 18 The steps in the method for forming metal silicides of the present invention are described in detail.

[0039] Please see Figure 11 In step S1, the surface of the substrate 100 has exposed silicon. Here, silicon generally refers to a film / region containing silicon atoms. For example, it can be a portion of the surface of the active region AA of the substrate 100, or it can be a portion of the surface of the polysilicon layer within the gate structure 103 above the substrate 100. This application does not specifically limit this.

[0040] In some embodiments, exposed silicon is a local region of substrate 100 (such as active region AA). In this case, substrate 100 includes at least a silicon substrate or a silicon-based substrate. For example, substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, etc.; or, a stacked structure of the above materials, such as a stack of Si and SiGe, a stack of Si and SiC, or a composite substrate such as silicon-on-insulator (SOI), etc.

[0041] In other embodiments, the exposed silicon is the surface of other structures (such as the polysilicon layer of gate structure 103) located above substrate 100. In this case, substrate 100 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. For example, substrate 100 can be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates; or substrate 100 can also be a composite substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0042] To facilitate the explanation of the implementation process of each process step in the metal silicide formation method provided in this application, the following embodiments and accompanying drawings will use exposed silicon on the surface of substrate 100 as an example for detailed description. It is understood that exposed silicon on the surface of other structures (e.g., gate structures) located on substrate 100 can undergo the same process steps simultaneously, and this application does not limit this.

[0043] Please see Figure 12 Step S2 is executed to sequentially form a barrier layer 200 and a first metal film 300 on the substrate 100.

[0044] To more clearly illustrate the subsequent process steps, the exposed silicon on the surface of substrate 100 is exemplarily divided into metal silicide regions 101 ( Figure 11 Exposed silicon to the left of the dashed line) and non-metallic silicide region 102 ( Figure 11 (Exposed silicon to the right of the dashed line). The metal silicide region 101 is the target region where metal silicide is expected to form, while the non-metal silicide region 102 is the region where metal silicide formation is not required and isolation protection is necessary. Correspondingly, the barrier layer 200 completely covers the exposed silicon surface of the substrate 100 and the entire surface of the semiconductor structure formed on it, that is, it simultaneously covers the metal silicide region 101, the non-metal silicide region 102, and the gate structure 103, thereby achieving full surface isolation protection.

[0045] In some alternative embodiments, the barrier layer 200 is made of silicon oxynitride (SiON) or titanium nitride (TiN). Both materials exhibit extremely high chemical stability in conventional weakly acidic or peroxide solutions, ensuring a very low natural etching rate of the barrier layer 200 in the non-metallic silicide region 102 where no metal catalyst is present. This provides the necessary material support for subsequent highly selective catalytic etching, effectively preventing thinning damage to the barrier layer 200 during etching and ensuring the structural integrity of the non-metallic silicide region 102.

[0046] The barrier layer 200 can be formed using conventional techniques in the art. Specifically, silicon oxynitride can be prepared using chemical vapor deposition (CVD), such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD); titanium nitride can be prepared using conventional processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Furthermore, the thickness of the barrier layer 200 is not specifically limited and can be flexibly adjusted by those skilled in the art according to actual production needs to adapt to the structural design and performance requirements of different semiconductor devices.

[0047] The first metal film 300 covers the surface of the barrier layer 200. During the subsequent etching process, the first metal film 300 will act as a metal catalyst, providing catalytic sites for the etching reaction to ensure etching efficiency and selectivity. The formation process of the first metal film 300 can be selected from conventional Pt deposition methods such as physical vapor deposition and chemical vapor deposition. Its thickness needs to be precisely adapted to the deposition requirements of the Pt layer in the subsequent metal silicide to ensure the formation quality of the metal silicide and the stability of the device's electrical performance.

[0048] In some other embodiments, the platinum material of the first metal film 300 may be replaced with other precious metals, such as palladium (Pd).

[0049] Please see Figure 13 and Figure 14 Step S3 is executed, forming a patterned mask layer 410 on the first metal film 300. The patterned mask layer 410 has an opening corresponding to the non-metallic silicide region 102. That is, the patterned mask layer 410 covers the first metal film 300 above the metal silicide region 101 and exposes the first metal film 300 above the non-metallic silicide region 102.

[0050] In one embodiment, the pattern of the non-metallic silicide region 102 is defined by photolithography. Specifically, photoresist is first spin-coated onto the surface of the first metal film 300. Then, the photoresist is exposed and developed according to a preset pattern (i.e., the pattern of the non-metallic silicide region 102). After development, the photoresist layer above the metallic silicide region 101 is retained as a protective mask, so that the first metal film 300 above the non-metallic silicide region 102 is fully exposed, forming a patterned photoresist layer 401 that matches the target non-metallic silicide region 102. Then, the patterned photoresist layer 401 is etched back to maintain its thickness at 3nm~50nm, such as 3nm, 10nm, 30nm, or 50nm, etc., to form a patterned mask layer 410. The etch-back method of the photoresist layer is, for example, a conventional method such as dry plasma etching.

[0051] Please see Figure 15 Step S4 is executed, using the patterned mask layer 410 as a mask to etch the first metal film 300.

[0052] Because the patterned mask layer 410 has an opening at the location corresponding to the non-metallic silicide region 102, the first metal film 300 in the opening region is exposed, while the first metal film 300 in the metal silicide region 101 is covered and protected by the patterned mask layer 410 (photoresist). Therefore, during the etching process, the first metal film 300 of the exposed non-metallic silicide region 102 is selectively removed, while the first metal film 300 of the metal silicide region 101 is completely preserved.

[0053] In one embodiment, a dry etching process is used to etch the first metal film 300, and the etching gas is a mixture of carbon monoxide (CO) and chlorine (Cl2). During the etching process, CO and Cl2 react synergistically with the material of the first metal film 300, such as Pt, to generate volatile dicarbonyl dichloroplatinum ([Pt(CO)2Cl2]). This product can be rapidly desorbed from the Pt surface, effectively avoiding etching product residue that could hinder subsequent etching processes. Simultaneously, it achieves a high etching rate, ensuring process efficiency. Furthermore, this mixed etching gas has a high etching selectivity for underlying thin films such as silicon oxynitride and titanium nitride, effectively protecting the substrate and underlying film structure from damage while efficiently etching Pt.

[0054] Furthermore, in the etching gas, the molar ratio of CO to Cl2 is 2:1. This ratio perfectly matches the chemical composition of the etching product [Pt(CO)2Cl2], maximizing the reaction between Pt and the mixed gas and achieving the optimal etching rate. If there is an excess of Cl2 in the etching gas (i.e., the molar ratio of CO to Cl2 < 2:1), the excess Cl2 will form a stable Pt-Cl adsorption layer on the Pt surface, hindering the binding of CO and Pt. This results in insufficient generation of the volatile [Pt(CO)2Cl2], making it difficult for the etching product to detach from the Pt surface, significantly reducing the etching rate, and potentially increasing residues on the Pt surface. Conversely, if there is an excess of CO in the etching gas (i.e., the molar ratio of CO to Cl2 > 2:1), the excess CO will preferentially occupy the catalytically active sites on the Pt surface, inhibiting the reaction between Cl2 and Pt. Similarly, this will also prevent the efficient generation of the target etching product, leading to a decrease in the etching rate. Furthermore, excess CO may form carbon residues on the etched surface, affecting the compatibility of subsequent processes.

[0055] After etching, a conventional process combining dry ashing and wet cleaning is used to remove residual photoresist (i.e., patterned mask layer 410).

[0056] Please see Figure 16Then, step S5 is performed, in which a wet etching solution is used to perform metal-assisted catalytic etching, using the retained first metal film 300 as a catalyst to selectively remove the barrier layer 200 below the first metal film 300, so that the first metal film 300 settles and comes into contact with the exposed silicon on the surface of the substrate 100, laying the foundation for the formation of subsequent metal silicides.

[0057] The wet etching solution used in this step includes an oxidant, an etchant, and water. The oxidant decomposes under the catalysis of the first metal film 300, generating a large number of hydroxyl radicals (·OH). These hydroxyl radicals have strong oxidizing properties and can selectively oxidize the barrier layer 200 (SiON or TiN). For example, SiON is oxidized to silicon dioxide (SiO2), and TiN is oxidized to titanium dioxide (TiO2). The etchant rapidly removes the oxides formed by oxidation, while water is used to disperse the oxidant and etchant.

[0058] In some alternative embodiments, the oxidant includes any one of hydrogen peroxide (H2O2), ozone (O3), and nitric acid (HNO3). Taking hydrogen peroxide as an oxidant as an example, SiON is oxidized to silicon dioxide (SiO2), and the reaction can be represented as SiON + H2O2 → SiO2 + NO. x TiN is oxidized to titanium dioxide (TiO2) by H2O; the reaction can be represented as TiN + H2O2 → TiO2 + NO. x + H2O, the reaction produces NO x It is a nitrogen oxide and can volatilize or dissolve in the etching solution along with the reaction system.

[0059] Hydrofluoric acid, as an etchant, exhibits extremely low etching rates for SiON or TiN under conventional conditions (without noble metal catalysis or oxidant oxidation), typically less than 1 nm / min, making efficient etching impossible. However, when the barrier layer 200 is converted to SiO2 or TiO2 through noble metal catalysis and oxidant oxidation, hydrofluoric acid can rapidly react with SiO2 and TiO2, as shown in the reactions: SiO2 + HF → SiF4 + H2O, TiO2 + HF → TiF4 + H2O, thereby dissolving and removing them. This increases the etching rate to 2 nm / min to 10 nm / min, achieving efficient and selective removal of the barrier layer 200 without significant damage to the first metal film 300 or the substrate 100. As the bottom barrier layer 200 is etched away, the first metal film 300 loses its physical support, causing it to settle and eventually come into direct contact with the exposed silicon on the substrate 100 surface. Since the surface of the non-metallic silicide region 102 is not covered by the first metal film 300 and lacks catalytic effect, the barrier layer 200 in this region is etched at a very slow rate in the etching solution, thus it is preserved and continues to play a barrier role.

[0060] In some optional embodiments, the oxidant in the wet etching solution used in this invention accounts for 1 ppm to 30 ppm of the total volume of the wet etching solution, for example, 1 ppm, 10 ppm, 20 ppm, or 30 ppm; the etchant accounts for 0.1% to 10% of the total volume of the wet etching solution, for example, 0.1%, 1%, 3%, 5%, 7%, or 10%, etc. By appropriately increasing the concentration of HF etchant, this invention can significantly enhance the system's ability to dissolve and capture the in-situ generated SiF4 and TiF4 gaseous intermediate products, promoting the rapid further reaction of trace amounts of gaseous fluorides into stable liquid products such as completely water-soluble fluorosilicic acid (H2SiF6), eliminating the potential for interfacial disturbances caused by the accumulation of gaseous products. On the other hand, the overall reaction rate of this noble metal-assisted catalytic etching system is dominated by the interfacial oxidation step of oxidants such as H2O2, and HF only participates in the subsequent rapid dissolution process of oxides and is not a rate-controlling factor. Therefore, increasing the HF concentration only enhances the product dissolution and removal capabilities and optimizes etching smoothness and cleanliness; it does not change the overall reaction rate or material etching selectivity of the system, and the process window remains stable and controllable. In practical applications, the content of each component in the wet etching solution can be specifically adjusted according to the thickness of the barrier layer 200, its material (SiON or TiN), and the target etching rate to ensure thorough removal of the barrier layer 200 in the target area, while effectively avoiding problems such as over-etching and interface damage.

[0061] Furthermore, when using a wet etching solution for metal-assisted catalytic etching, the reaction temperature is controlled between -15℃ and 5℃, with exemplary values ​​including -15℃, -10℃, 0℃, or 5℃. This low-temperature reaction environment provides significant process gains without affecting the etching effect: since the rate-limiting step of the system is the interfacial oxidation reaction of the oxidant, noble metal catalysis can maintain stable oxidation efficiency. Coupled with sufficient dissolution mass transfer redundancy from high-concentration HF, the low-temperature condition does not reduce the overall etching rate and etching uniformity. At the same time, the low-temperature environment can effectively suppress the rapid overflow of gaseous byproducts such as SiF4 and TiF4, reduce the generation and aggregation rate of interfacial gaseous products, and significantly weaken the micro-disturbance of the gas phase at the interface, thus ensuring the interfacial adhesion stability between the first metal film 300 and the barrier layer 200 from the source.

[0062] In addition, the inherent structural characteristics of the device further ensure the stability of the etching system. After the barrier layer 200 is fabricated, the aspect ratio of the gap between adjacent gate structures can reach 100:1, forming a high aspect ratio narrow gap structure. This structure can significantly reduce the fluid flow and convection disturbance of the etching solution, greatly limit the interfacial material exchange rate inside the gap, effectively weaken the lateral impact of the etching solution flow on the first metal film 300, and maximize the interfacial adhesion state of the first metal film 300, further improving the overall stability of the film layer from a structural perspective.

[0063] Based on the aforementioned optimized formulation, low-temperature control, and high aspect ratio structural constraints, the small amount of intermediate gaseous products such as SiF4 and TiF4 generated during the etching process can be rapidly dissolved, transformed, and discharged by the system. There is no gas accumulation or pressure buildup at the interface, preventing film bubbling, loosening, or peeling failure. This ensures the stable and precise placement of the first metal film 300 during the etching of the barrier layer 200. The specific mechanism is as follows: This process is an open liquid-phase etching system. Combined with low-temperature gas suppression and high HF gas dissolution, trace amounts of gaseous products can rapidly diffuse and dissolve along the edge of the metal film, transforming into stable liquid-phase products, keeping the interface clean and free of accumulation. Simultaneously, the first metal film 300 maintains a stable bond with the underlying medium, exhibiting excellent interface adhesion. Furthermore, noble metal catalytic etching possesses strict localized reaction characteristics; the oxidation and dissolution etching processes are concentrated only in the region directly below the first metal film 300, where only the barrier layer 200 is removed layer by layer, directionally, and uniformly. Throughout the etching process, the first metal film 300 remains in close contact with the bottom etching interface. Under the combined effect of interface adhesion stress, etching fluid static pressure and metal weight, the first metal film 300 can sink vertically in sync with the etching consumption of the barrier layer 200, smoothly and accurately filling the space of the original barrier layer 200, and achieving a stable in-situ sedimentation etching effect.

[0064] Please see Figure 17 Step S6 is executed to selectively deposit a second metal film 500 on the first metal film 300.

[0065] In one embodiment, a second metal film 500 is formed by selective reduction deposition on the surface of the first metal film 300 using a chemical reduction method. Taking the material of the first metal film 300 as Pt and the material of the second metal film 500 as Ni as an example, the core principle of the chemical reduction method is: to use the catalytic activity of Pt to trigger the reduction reaction of Ni ions (Pt can serve as a catalytic site without additional activation), so that Ni ions preferentially nucleate and grow on the surface of the first metal film 300, thereby achieving selective deposition of Ni on the Pt surface and avoiding misdeposition in non-metallic areas (such as barrier layers).

[0066] The specific process is as follows: First, a deposition solution is prepared, which includes soluble nickel salt, reducing agent, complexing agent, and deionized water. The soluble nickel salt serves as the Ni ion supply source and can be selected from nickel nitrate (Ni(NO3)2), nickel chloride (NiCl2), etc. A mild and selective reducing agent is chosen to avoid excessive reduction that could lead to Ni deposition in non-Pt regions; examples include ascorbic acid (AA) and sodium hypophosphite (NaH2PO2). The complexing agent stabilizes the Ni in the solution. 2+To prevent premature hydrolysis and formation of Ni oxide, and to improve the uniformity of Ni deposition, defects such as pinholes and nodules in the coating are avoided, ensuring the adhesion between the second metal film 500 and the first metal film 300. Complexing agents such as citric acid and EDTA are used. Deionized water is used to dissolve these substances, preparing a uniform and stable deposition solution. The specific concentrations of each substance in the deposition solution can be flexibly adjusted according to actual production needs and are not specifically limited here. Subsequently, the sample obtained in step S5 is placed in the above deposition solution to initiate the deposition reaction. After the reaction is completed, the second metal film 500 is formed on the surface of the first metal film 300.

[0067] The deposition thickness of the second metal film 500 can be adapted to the thickness of the final metal silicide. In some optional embodiments, the thickness ratio of the second metal film 500 to the thickness of the first metal film 300 is (80:20) to (99:1), specifically 80:20, 90:10, or 99:1, etc.

[0068] Please see Figure 18 Step S7 is executed to anneal the substrate 100, so that the contact positions between the second metal film 500, the first metal film 300 and the exposed silicon on the surface of the substrate 100 undergo silicide reaction to form metal silicide 600.

[0069] In one embodiment, a one-step annealing process is used to cause the second metal film 500, the first metal film 300, and the exposed silicon on the surface of the substrate 100 to undergo a thermochemical reaction, ultimately forming nickel-platinum silicide (NiPtSi). In this embodiment, the annealing temperature is 400℃~600℃. Exemplarily, the temperature can be selected as 400℃, 500℃, or 600℃, etc.; the annealing time can be selected according to the thickness of the first metal film 300, the second metal film 500, and the target nickel-platinum silicide layer, and is not specifically limited here.

[0070] Traditional processes typically require two annealing steps: a first low-temperature annealing to form a metal-rich silicide phase and remove unreacted metal, followed by a second high-temperature annealing to form a low-resistivity silicide phase. In this invention, since the second metal film 500 is selectively deposited on the surface of the first metal film 300, the non-metallic silicide region 102 contains no unreacted metal, eliminating the need for an additional metal removal step. This invention optimizes the traditional two-step annealing process into a single-step process, significantly simplifying the semiconductor device manufacturing process, shortening the production cycle, and substantially reducing the overall thermal budget during device manufacturing. This contributes to improving the performance stability and reliability of semiconductor devices at advanced process nodes.

[0071] After completing steps S1 to S7, you can obtain the following: Figure 18 The semiconductor structure shown.

[0072] In some embodiments, it can be based on Figure 18 The structure shown can be used to fabricate any adapted semiconductor structure, which will not be elaborated here.

[0073] The method for forming metal silicides provided by this invention introduces metal-assisted catalytic etching technology. A first metal film acts as a catalyst, rapidly etching the underlying barrier layer during the etching process, thereby causing the first metal film to settle onto the substrate surface. The barrier layer in non-metallic silicide regions not covered by the first metal film, lacking the catalytic effect of platinum, experiences an extremely low etching rate and is thus completely preserved, avoiding damage to the barrier layer and abnormal silicide formation in non-target areas. Simultaneously, nickel is selectively deposited on the first metal film, eliminating the need for separate removal of unreacted metal layers, thoroughly resolving the metal residue problem, and improving device reliability and yield. This invention effectively overcomes some practical problems in existing technologies, thus possessing high utilization value and practical significance.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming a metal silicide, characterized in that, Includes the following steps: A substrate is provided, the surface of which has exposed silicon, the exposed silicon comprising metal silicide regions and non-metal silicide regions; A barrier layer and a first metal film are sequentially formed on the substrate, wherein the material of the first metal film includes platinum; A patterned mask layer is formed on the first metal film, the patterned mask layer having openings corresponding to the non-metallic silicide regions; Using the patterned mask layer as a mask, the first metal film is etched to remove the first metal film located in the non-metallic silicide region, while retaining the first metal film located in the metallic silicide region. Metal-assisted catalytic etching is performed using a wet etching solution, with the retained first metal film as a catalyst, to selectively remove the barrier layer beneath the first metal film, causing the first metal film to settle and come into contact with the exposed silicon on the substrate surface. A second metal film is selectively deposited on the first metal film, wherein the material of the second metal film includes nickel; The substrate is annealed to cause a silicide reaction at the contact points between the second metal film, the first metal film and the exposed silicon on the substrate surface, forming metal silicides.

2. The method for forming metal silicides according to claim 1, characterized in that, The material of the barrier layer is selected from silicon oxynitride or titanium nitride.

3. The method for forming metal silicides according to claim 1, characterized in that, In the step of etching the first metal film using the patterned mask layer as a mask, a dry etching process is used to etch the first metal film, and the etching gas for the dry etching is a mixture of carbon monoxide and chlorine.

4. The method for forming metal silicides according to claim 1, characterized in that, In the step of using a wet etching solution for metal-assisted catalytic etching, the wet etching solution includes an oxidant, an etchant, and water. The oxidant includes any one of hydrogen peroxide, ozone, and nitric acid, and the etchant is hydrofluoric acid.

5. The method for forming metal silicides according to claim 4, characterized in that, The oxidant accounts for 1 ppm to 30 ppm of the total volume of the wet etching solution, and the etchant accounts for 0.1% to 10% of the total volume of the wet etching solution.

6. The method for forming metal silicides according to claim 1, characterized in that, Methods for selectively depositing a second metal film on the first metal film include: chemical reduction.

7. The method for forming metal silicides according to claim 1, characterized in that, The thickness ratio of the second metal film to the first metal film is (80:20) to (99:1).

8. The method for forming metal silicides according to claim 1, characterized in that, The annealing temperature is 400℃~600℃.

9. The method for forming metal silicides according to claim 1, characterized in that, The step of forming a patterned mask layer on the first metal film includes: A photoresist layer is spin-coated onto the first metal film; The photoresist layer is exposed and developed according to a preset pattern to form a patterned photoresist layer that matches the target non-metallic silicide region. The patterned photoresist layer is etched back to maintain a thickness of 3nm~50nm to obtain a patterned mask layer.

10. A semiconductor structure, characterized in that, Including metal silicides prepared by the formation method according to any one of claims 1 to 9.

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