A memory cell layout structure based on local routing optimization and a preparation method thereof

Abstract

This application relates to the fields of semiconductor manufacturing and integrated circuit design technology, and discloses a memory cell layout structure and fabrication method based on local trace optimization. The layout structure includes a semiconductor substrate on which an active region layer, a polysilicon layer, contact holes, and a first metal layer are sequentially disposed. The contact holes form a specific rectangular structure that is long vertically and narrow horizontally. The first metal layer has a non-linear corner structure in a local area connected to the contact holes, and the edge of this corner structure extends outward beyond the physical boundary of the contact holes, so that the first metal layer completely covers and encloses the contact holes. The fabrication method strictly controls the safety spacing parameters and patterning etching process deviations of each layer. This invention, while maintaining the physical isolation spacing of the traces, utilizes a locally non-linear outward expansion configuration to completely enclose the contact holes, eliminating interface edge overhang defects, and ensuring the longitudinal contact area through specific rectangular holes, thereby improving the reliability of the memory array.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor manufacturing and integrated circuit design technology, specifically to a memory cell layout structure and fabrication method based on local routing optimization. Background Technology

[0002] As integrated circuit process nodes continue to evolve, the demand for high density and miniaturization in semiconductor memory devices is increasing, which requires the physical layout size of basic memory cells to continue to shrink. In conventional memory cell layout design, a combination of standard square contact holes and unidirectional linear metal wiring is typically used to achieve signal interconnection between device layers.

[0003] To accommodate the overall reduction in unit area, the conventional technique is to directly and proportionally reduce the geometric dimensions of the aforementioned square contact holes. However, this proportional reduction in physical size directly leads to a decrease in the physical contact area between the upper and lower layers of the device, which in turn drastically increases the interface contact resistance, severely limiting the signal conduction efficiency and high-frequency access performance of the memory device.

[0004] Without the ability to infinitely reduce the size of contact holes to maintain normal impedance characteristics, attempts to reduce the layout area by forcibly compressing the spacing of metal interconnects will encounter physical limitations in the manufacturing process during the design phase. Constrained by the alignment precision of photolithography equipment and the inherent dimensional drift effect of etching processes, straight upper-layer metal traces in a compact array arrangement cannot provide sufficient overlap tolerance for the lower-layer contact holes while maintaining safe physical isolation spacing. If even a slight physical offset occurs during actual wafer manufacturing, this straight upper-layer metal cannot completely cover the bottom contact holes, resulting in structural defects such as edge overhangs, microscopic voids, or residual insulating media at the junctions. This incomplete physical connection not only causes drastic fluctuations in local impedance at nodes but also easily leads to signal short circuits between adjacent components or open circuit failures within the circuit itself, causing memory arrays under high-density integration conditions to face technical dilemmas of low yield and deteriorating long-term operational reliability. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a memory cell layout structure and fabrication method based on local routing optimization. This solves the problem that conventional memory cell layouts, when achieving high-density integration and miniaturization, are prone to increased contact resistance and incomplete coverage of contact holes by the metal layer due to limitations in the physical spacing of metal wiring lines and photolithography overlay accuracy, leading to reduced device reliability.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] The first aspect of this invention provides a memory cell layout structure based on local routing optimization, comprising: Semiconductor substrate; An active region layer and a polysilicon layer are disposed on a semiconductor substrate, wherein the spacing between adjacent active region layers is greater than or equal to 10.0 μm; The contact hole is disposed above the polysilicon layer, and the spatial distance between the contact hole and the polysilicon layer is greater than or equal to 4.0 μm; A first metal layer is disposed above the contact hole, and the physical spacing between the first metal layers is greater than or equal to 7.0 μm.

[0008] The first metal layer has a non-linear corner structure in the local area where it connects with the contact hole, and the contact hole is a rectangular structure with a lateral width between 4.8 μm and 5.2 μm and a longitudinal length between 7.3 μm and 7.7 μm. The corner structure of the first metal layer extends outward beyond the physical boundary of the contact hole so that the first metal layer completely covers and encloses the contact hole.

[0009] In one specific implementation, the corner structure of the first metal layer, along the basic straight routing line of the first metal layer, manifests as any one of the following: an arc-shaped transition structure, an obtuse-angle corner structure, a zigzag routing structure, or a locally widened structure formed by connecting the local area of ​​the contact hole. Simultaneously, in the horizontal cross-section, the edges of the corner structure of the first metal layer extend outwards in all directions beyond the edge of the contact hole, and the contact interface formed by the first metal layer and the contact hole is a continuous solid connection surface without any insulating residue or gaps.

[0010] Furthermore, the ratio of the lateral width to the longitudinal length of the contact hole is fixed at 0.8:1.25; the physical channel length of the gate transistor composed of the active region layer is greater than or equal to 4.0 μm, and the physical channel width is greater than or equal to 18.5 μm.

[0011] The innovative principle of the first aspect of this invention lies in: By altering the conventional proportional geometry of the contact holes and adopting a specific rectangular structure with a long vertical axis and a narrow horizontal axis, the horizontal area occupied by the layout is reduced while providing a vertical contact area sufficient for electrical transmission, thus avoiding an increase in contact resistance. Combined with changing the single linear arrangement of the first metal layer to a non-linear corner structure in local areas, this results in a horizontal or vertical area increase at the nodes. This structural layout, while maintaining a 7.0μm physical isolation spacing of the first metal layer, utilizes outward redundancy at the nodes to create an overlap tolerance, eliminating edge overhangs caused by alignment deviations. From a structural perspective, this ensures the physical continuity and electrical consistency of the contact interfaces of each basic unit in the memory array.

[0012] A second aspect of the present invention provides a method for fabricating a memory cell layout structure based on local routing optimization, used to fabricate the memory cell layout structure described in the first aspect, comprising the following steps: Provide a semiconductor substrate, deposit an active region layer on the semiconductor substrate and use reactive ion etching technology to pattern the active region layer, and control the actual process size of the spacing between adjacent active region layers to 10.0 μm and above. A polysilicon layer is deposited in a preset area, and patterned by mask exposure and dry etching. The reserved area for contact holes is defined simultaneously, and the spatial distance between the reserved area for contact holes and the polysilicon layer is controlled to be 4.0 μm or more. An insulating dielectric layer is deposited between layers. Contact holes are formed by dry etching in the reserved area of ​​the contact holes. The target size of the contact holes is controlled to be between 4.8 μm and 5.2 μm in lateral width and between 7.3 μm and 7.7 μm in longitudinal length. A conductive medium is filled into the contact hole, and a first metal layer is deposited. The first metal layer is patterned to form a non-linear corner structure in the local area connecting the contact holes, and the minimum physical spacing between the patterned first metal layers is controlled to be 7.0 μm. During the patterning process, by adjusting the photolithography and etching parameters, the physical boundary of the corner structure pattern of the top first metal layer is controlled to extend outward beyond the physical boundary of the contact hole, so that the first metal layer completely covers and wraps the edge of the contact hole.

[0013] In one specific process implementation, the etching size deviation of the active area layer is controlled within ±0.5μm when patterning. When etching the contact holes, the target aspect ratio is fixed at 0.8:1.25, and a high selectivity fluorine-based gas system is used for deep silicon and dielectric dry etching, controlling the process deviation of the etched hole diameter profile within ±0.2μm.

[0014] Furthermore, the patterning of the first metal layer specifically includes: using a photomask pattern to employ a non-linear compensation design in the local area connecting the contact hole, and then using anisotropic dry etching technology to etch obtuse angle corners, zigzag trace structures, or locally widened structures, controlling the etching size deviation within the range of ±0.3μm.

[0015] Before filling the contact hole with conductive dielectric, a pretreatment with dilute hydrofluoric acid is used to remove the underlying native oxide layer. The conductive dielectric, made of tungsten or copper, is filled using chemical vapor deposition or atomic layer deposition. After forming a fully encapsulated structure, a chemical mechanical planarization process is used to grind away residual photoresist and overflowing conductive dielectric, followed by megasonic cleaning and deionized water rinsing.

[0016] The second innovative principle of this invention lies in establishing rigid error tolerance conditions for various patterning processes by transforming the physical parameter boundaries of the layout structure into specific process control specifications. A photomask with nonlinear compensation data is used in conjunction with anisotropic dry etching technology to precisely transfer external augmentation patterns. Specifically, by applying specific dimensional deviation control to the contact hole pattern size and the metal layer trace corner shape (e.g., controlling the hole diameter profile deviation within ±0.2μm and the metal layer pattern deviation within ±0.3μm), combined with high-selectivity etching and interface pretreatment processes, morphological distortion caused by micro-load effects and optical proximity effects is suppressed during actual wafer fabrication. The limitation of process parameters and the node expansion design of the front-end layout work synergistically to establish a physical short-circuit isolation benchmark after device formation, ensuring high-density integration and operational reliability of the finished device.

[0017] This invention provides a memory cell layout structure and fabrication method based on local routing optimization. It offers the following advantages: 1. By setting the contact hole as a rectangular structure that is long in the vertical direction and narrow in the horizontal direction, the present invention can effectively reduce the horizontal area occupied by the memory cell to meet the requirements of high-density array integration, while providing sufficient vertical contact physical area for signal interconnection between upper and lower layers, thereby avoiding the problem of increased contact resistance caused by the overall shrinkage of contact size.

[0018] 2. The present invention enables the first metal layer to have a non-linear corner structure that extends outward beyond the physical boundary of the contact hole in the local area where it is connected to the contact hole. This allows the metal traces to completely cover the bottom contact hole by using the area increment at the node while maintaining the basic physical isolation spacing limit. This eliminates the residual insulation at the junction and edge suspension defects and constructs a continuous solid connection surface with good electrical consistency.

[0019] 3. Because the present invention applies strict process tolerance control to the etching aperture contour deviation of the contact hole and the patterned etching size deviation of the first metal layer in the preparation method, it can effectively suppress the physical size drift phenomenon in the photolithography and etching process, so that the non-linear encapsulation expansion configuration can be accurately restored in wafer manufacturing, thereby blocking the risk of short circuit or open circuit failure caused by overlay alignment deviation at the physical process level. Attached Figure Description

[0020] Figure 1 This is a memory cell layout structure block diagram provided in one embodiment of the present invention; Figure 2 This is a partial schematic diagram of the memory cell layout structure provided in an embodiment of the present invention; Figure 3 A top view schematic diagram of a memory cell layout structure provided in another embodiment of the present invention; Figure 4 A scatter plot of physical dimensional characteristics provided for embodiments of the present invention; Figure 5 This is a comparison diagram of etching size deviation distribution provided in an embodiment of the present invention; Figure 6 A comparative distribution diagram of contact resistance characteristics and array connectivity measurement data of various wafer samples provided in the embodiments of the present invention; Figure 7 A reliability lifetime data distribution diagram provided for embodiments of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] See attached document Figure 1 To be continued Figure 3 To achieve high-density integration of basic cells and stable transmission of electrical signals in semiconductor memory devices, embodiments of the present invention provide a memory cell layout structure based on local routing optimization. In this embodiment, the memory cell layout structure is constructed on a semiconductor substrate. An active region layer and a polysilicon layer are disposed on the semiconductor substrate.

[0023] In one specific implementation, the active region layer constitutes the doped region of the device (e.g., source and drain), and the polysilicon layer serves as the gate structure. The two are spatially overlapped to form a gating transistor for data access control. When a specific voltage is applied to the polysilicon layer, a conductive channel is formed in the bottom active region layer, thereby enabling signal conduction.

[0024] Those skilled in the art can make conventional selections and settings for the doping type of the semiconductor substrate and the specific material of the interlayer insulating medium according to the actual manufacturing process node requirements.

[0025] Because strict electrical isolation needs to be maintained between active regions to prevent signal crosstalk between adjacent memory cells, this embodiment sets the spacing between adjacent active regions to be greater than or equal to 10.0 μm. This threshold is chosen to allow sufficient space for the depletion layer edges generated by semiconductor doping diffusion. Based on this spacing setting, leakage current control standards in complementary metal-oxide-semiconductor (CMOS) manufacturing processes can still be met without introducing additional isolation media (such as shallow trench isolation structures).

[0026] Based on the aforementioned spatial arrangement of the active region layer and the polysilicon layer, the formed gate transistor has specific physical size definitions. In this embodiment, the physical channel length of the gate transistor is limited to greater than or equal to 4.0 μm, and the physical channel width is greater than or equal to 18.5 μm. By limiting the physical channel width-to-length ratio within a specific range, it is ensured that the device has a drive current that meets a preset threshold when it is in the on state, thereby supporting high-frequency access operations of the array.

[0027] Combination Figure 2 As can be seen from the cross-sectional structure, in order to bring out the source and drain signals of the gate transistor, contact holes are provided above the polysilicon layer and the active region layer, passing through the insulating dielectric. Considering the interlayer alignment deviation during the manufacturing etching process, the spatial distance between the contact holes and the polysilicon layer is strictly set to be greater than or equal to 4.0 μm. This parameter is determined based on the overlay accuracy tolerance of the lithography equipment at the current process node, and the above-mentioned spatial distance limit avoids short circuits between the contact holes and the surrounding gate structure due to physical misalignment.

[0028] Conventional memory layouts often employ square contact holes, but this design limits the reduction of the vertical area of ​​the cells due to the fixed spacing of the metal wiring. Therefore, this embodiment uses a non-proportional design for the geometry of the contact holes. As a preferred approach, it is set as a rectangular structure with a horizontal width between 4.8μm and 5.2μm and a vertical length between 7.3μm and 7.7μm.

[0029] Specifically, the baseline size of the contact hole is set to 6.0 μm, which corresponds to the nominal minimum resolution feature size of the current photolithography system. The ratio of its lateral width to its vertical length is fixed at 0.8:1.25. This rectangular structure, which is long in the middle and narrow in the middle, reduces the lateral area occupied by the layout while providing a vertical contact interface that meets the requirements of electrical transmission, thus compensating for the risk of increased contact resistance caused by the reduction in lateral size.

[0030] A first metal layer is further disposed above the contact hole to realize signal interconnection of memory cells in the array. Due to the limitations on the physical spacing of metal wires caused by optical proximity effect and micro-load effect in the photolithography and etching processes, in this embodiment, the physical spacing between the first metal layers is limited to greater than or equal to 7.0 μm. Meanwhile, to match the requirements of high-density wiring, the basic straight trace width of the first metal layer is set to 4.0 μm to 4.5 μm, which is smaller than the lateral width of the contact hole. Based on the above limitations, if a traditional straight trace design is followed, this metal spacing will result in a limitation on the vertical dimension of the underlying transistors.

[0031] To address this technical bottleneck, this embodiment alters the traditional single-straight-line arrangement rule, resulting in a non-straight-line corner structure in the local area where the first metal layer connects with the contact hole. This non-straight-line corner structure manifests as a local outward expansion of the first metal layer's contour along the basic straight-line routing line.

[0032] Combination Figure 1 and Figure 3 The top view layout shows that POLY represents the polysilicon layer; AA represents the active region layer; CONTACT represents the contact hole; and METAL1 represents the first metal layer. This non-linear corner structure has specific implementation forms to fully support the manufacturing needs under different process nodes.

[0033] like Figure 1 As shown, in one embodiment, the structure is specifically manifested as an obtuse-angled corner structure with a fixed included angle formed in a local area connecting the contact hole, or a zigzag routing structure composed of multiple bends.

[0034] For example Figure 3 As shown, as another implementation, the structure is specifically manifested as an arc-shaped transition structure formed in a local area connecting the contact hole, or a local widening structure that keeps the main routing direction unchanged.

[0035] Any change in the local morphology mentioned above will cause the first metal layer to have a lateral or vertical area increase at the node, thereby avoiding conflicts between adjacent wiring spaces and effectively reducing the overall vertical dimension of the memory cell while maintaining the 7.0μm physical spacing baseline.

[0036] Based on the outward expansion of the first metal layer at local nodes and the specific longitudinal and transverse narrow structure of the contact hole, the corner structure of the first metal layer extends outward beyond the physical boundary of the contact hole. In the horizontal cross-section, the outer edge of the corner structure of the first metal layer extends outward beyond the boundary of the contact hole in all directions, forming a wrapping overlap tolerance. Based on this spatial dimension matching setting, the first metal layer completely covers and wraps around the contact hole.

[0037] Correspondingly, the contact interface formed by the first metal layer and the contact holes at their intersection is constructed as a continuous solid connection surface without any insulating residue or gaps. In practical applications, the continuous solid connection surface eliminates the edge suspension problem caused by incomplete coverage, avoids local impedance anomalies, and ensures the consistency of the electrical characteristics of each basic cell in the memory array from a physical perspective.

[0038] Furthermore, to maintain the geometric stability of the aforementioned locally expanded encapsulated architecture and prevent failures caused by optical proximity effects, this invention limits process dimensional deviations as rigid boundary conditions. Specifically, through process parameter control, the etching dimensional deviation during contact hole patterning is strictly limited to within ±0.2μm, while the etching dimensional deviation during the first metal layer patterning process is controlled within ±0.3μm. These specific process tolerance control specifications, in conjunction with the non-linear expansion configuration, jointly prevent the risk of short circuits or open circuits caused by physical misalignment of the metal layer.

[0039] To further verify and illustrate the technical features and practical effects of the present invention, the following will provide a detailed description in conjunction with specific preparation examples, embodiments, and comparative examples. In this embodiment and various comparative examples, the basic manufacturing raw materials, such as the semiconductor silicon wafer used to construct the underlying transistor structure, the silane precursor gas used to form the insulating dielectric layer, and the conductive metal target used to fill the contact holes, are all commercially available high-purity products that are standard in the semiconductor manufacturing field, unless otherwise stated.

[0040] Meanwhile, the chemical vapor deposition equipment and anisotropic dry etching stage involved can all be obtained through commercial channels. Because the specific physical layout features in this embodiment require precise optical pattern transfer, a photomask carrying locally optimized structural data must be prepared before proceeding to the specific wafer device fabrication embodiment.

[0041] Preparation Examples 1-2: Preparation Example 1: This example provides a method for fabricating a photomask for patterning a first metal layer, comprising the following steps: Initial routing data for the first metal layer is generated using electronic design automation (EDA) tools. The trace width of the basic straight traces is set to 4.0 μm to 4.5 μm, which is smaller than the lateral width of the bottom contact holes, and the physical spacing threshold between traces is set to be greater than or equal to 7.0 μm. For this initial routing data, non-straight corner structure data compensation is introduced in the preset local areas connected to the underlying structure.

[0042] As a preferred approach, the linear vector graphics of a local area are modified into obtuse-angled corners or arc transition structures with specific outward redundancy according to spatial arrangement rules, so as to pre-assign the horizontal or vertical area increment of the node area at the data level.

[0043] Optical proximity correction is performed on the modified wiring data with corner features. By adding optical auxiliary features at key corners of the pattern, the shrinkage of metal lines or distortion of rounded corners caused by optical diffraction in subsequent actual photolithography processes is compensated, ensuring the restoration of the physical shape.

[0044] The corrected graphic data is inscribed onto a chromium-plated quartz glass substrate coated with electron beam resist using an electron beam exposure system. The resist in the unexposed areas is removed by a development process, and the exposed chromium layer is removed by a high-selectivity dry etching method, thereby forming the physical distribution of transparent and opaque areas.

[0045] After cleaning and defect screening, a first metal layer photomask with local trace optimization features is obtained.

[0046] Preparation Example 2: This example provides a method for fabricating a photomask for etching and positioning irregularly shaped contact holes, including the following steps: Obtain the spatial layout coordinates of the memory cell contact hole array. Set the basic dimension reference value of the contact holes to 6.0μm. Based on this reference parameter, break the conventional proportional graphic design rules and generate a vertically elongated and horizontally narrow rectangular data pattern with a strictly fixed ratio of horizontal width to vertical length of 0.8:1.25.

[0047] Based on the aforementioned asymmetric aspect ratio parameters, and considering the micro-loading effect during subsequent deep-hole etching, exposure dose compensation parameters with different weights are applied to the major and minor axes of the rectangular data pattern. By fine-tuning the local transmittance of the photomask, the consistency of photoresist development under anisotropic shrinkage conditions is ensured.

[0048] Using an electron beam direct writing device, a rectangular pattern with accompanying compensation parameters is precisely transferred to the surface of a mask substrate. After removing residual resist, the physical shape of the light-transmitting apertures is completed, resulting in a photomask specifically designed for exposing contact holes with a specific aspect ratio. This provides an alignment reference for simplifying the contact hole dimensions in subsequent wafer implementations.

[0049] Examples 1-4: Example 1: This embodiment provides a method for fabricating a memory cell layout structure based on local routing optimization. The fabrication method includes the following steps: S101: Provides a semiconductor substrate, deposits an active region layer on the semiconductor substrate, and patterns the active region layer using reactive ion etching. To ensure electrical isolation between doped regions and reserve depletion layer spread margin, the actual process dimension of the spacing between adjacent active region layers is controlled to be 10.0 μm.

[0050] In this embodiment, considering that the roughness of the active region layer edge directly affects the leakage current level, the etching size deviation of the active region layer is strictly controlled within ±0.5μm during the patterning step. This tolerance range avoids both insufficient physical width of the active region due to over-etching and excessive isolation spacing caused by insufficient etching.

[0051] Based on the forming requirements of the bottom transistor gate, a polysilicon layer is deposited in a predetermined area, and patterned by mask exposure and dry etching. During the pattern transfer process, the reserved area for contact holes is defined simultaneously, and the spatial distance between the reserved area for contact holes and the polysilicon layer is controlled to 4.0 μm, thereby reserving sufficient photolithography overlay margin.

[0052] S102: Deposit an interlayer insulating dielectric layer to cover the underlying device structure. For the contact hole reserved area, a high selectivity fluorine-based gas system is used for deep silicon and dielectric dry etching to penetrate the dielectric layer and form the contact hole.

[0053] In this embodiment, based on the basic size reference value of 6.0 μm, the etching target size of the contact hole is controlled to be 5.0 μm in width and 7.5 μm in length. That is, in the step of etching to form the contact hole, the length-to-width ratio of the etching target of the contact hole is fixed at 0.8:1.25.

[0054] Furthermore, since the final morphology of the contact hole directly determines whether the upper metal layer can be completely encapsulated, the etching process controls the process deviation of the etched hole diameter profile within ±0.2μm by adjusting the ratio of RF bias power to fluorine-based gas flow rate. This high-precision profile control avoids excessive expansion at the top of the hole, providing a rigid geometric basis for the subsequent construction of the solid connection surface.

[0055] S103: To reduce the interfacial contact resistance, dilute hydrofluoric acid is used for pretreatment to remove the native oxide layer at the bottom of the contact hole. Subsequently, tungsten metal as a conductive medium is filled into the contact hole using chemical vapor deposition, and after filling is completed, a first metal layer for global wiring is sputtered and deposited on top of the dielectric layer.

[0056] S104: Patterning the first metal layer specifically includes: using a photomask pattern to apply a non-linear compensation design to the local area connecting the contact hole, and then using anisotropic dry etching technology to etch obtuse angle corners, zigzag trace structures, or locally widened structures.

[0057] In this embodiment, specifically, an outwardly expanding obtuse-angled corner structure is etched onto the basic straight trace of the first metal layer. To meet the metal isolation requirements in the layout design rule check, the minimum physical spacing between the patterned first metal layers is controlled to be 7.0 μm.

[0058] Furthermore, in order to achieve a balance between the local area increment and the strict physical spacing red line, the etching size deviation of this step must be controlled within ±0.3μm.

[0059] During the patterning process, by finely adjusting the step alignment parameters of the photolithography equipment, the physical boundary of the obtuse corner structure pattern of the top first metal layer is controlled to extend outward beyond the physical boundary of the contact hole in all directions.

[0060] Based on this redundant expansion design, the first metal layer completely covers and wraps the edge of the contact hole, creating a continuous solid connection surface at the interface without any insulating residue or gaps.

[0061] S105: A chemical mechanical planarization process is used to polish the wafer surface to remove residual photoresist and overflowing conductive metal layers. Finally, megasonic cleaning and deionized water rinsing are performed sequentially to remove surface particulate contaminants and free ions, completing the fabrication of the high-density memory cell physical structure.

[0062] Example 2: This embodiment provides a method for fabricating a memory cell layout structure based on local routing optimization. The fabrication method includes the following steps: S201: An active region layer and a polysilicon layer are formed on a semiconductor substrate according to the basic process flow of Example 1. To verify the isolation performance under extreme arrangement, the actual process size of the spacing between adjacent active region layers is controlled to be 10.5 μm, and the spatial spacing between the reserved area of ​​the contact hole and the polysilicon layer is controlled to be 4.2 μm.

[0063] S202: Perform downward dry etching on the reserved area of ​​the contact hole. In order to achieve the ultimate reduction in the lateral area of ​​the cell, the etching target size of the contact hole is controlled to be close to the process technology, specifically set to a lateral width of 4.8μm and a vertical length of 7.3μm.

[0064] S203: After removing the oxide at the bottom of the hole using a pretreatment process, an atomic layer deposition technique is used to fill the contact hole with a copper conductive medium and deposit the first metal layer.

[0065] S204: Localized patterning of the first metal layer. As a morphological variation, a smooth, arc-shaped transition structure is etched in the local area connecting the contact holes. This smooth arc edge effectively alleviates the stress concentration phenomenon at the sharp corners of the pattern during photolithography. The physical spacing between the patterned first metal layers is controlled at 7.2 μm, and alignment compensation is used to extend the arc-shaped transition structure outward beyond the edge of the contact holes, achieving 100% coverage of the miniaturized contact holes.

[0066] S205: Perform standard chemical mechanical planarization and subsequent cleaning processes to complete the manufacturing of memory cell devices.

[0067] Example 3: This embodiment provides a method for fabricating a memory cell layout structure based on local routing optimization. The fabrication method includes the following steps: S301: The active region layer and polysilicon layer are deposited and etched sequentially on the semiconductor substrate. To accommodate the large contact interface area requirement, the arrangement density of the underlying structure is relaxed, the actual spacing between adjacent active region layers is controlled at 11.0 μm, and the spatial spacing between the contact hole reserved area and the polysilicon layer is defined as 4.5 μm.

[0068] S302: Etching to form contact holes in the reserved area. The target dimensions for the etching of the contact holes are controlled to be a lateral width of 5.2 μm and a longitudinal length of 7.7 μm. This enlarged longitudinal morphology increases the longitudinal physical contact area of ​​the metal interconnect node.

[0069] S303: After completing the bottom cleaning, fill with tungsten metal and cover with the target material for depositing the first metal layer.

[0070] S304: Pattern the first metal layer using a mask with corresponding data. While maintaining the direction of the main trace vector of the first metal layer, etch a locally widened structure extending to both sides at the node positions connecting the contact holes. Control the physical spacing between the first metal layers to reach 7.5μm at the narrowest local point. Relying on the lateral area increase provided by this locally widened structure, the first metal layer completely spans and encloses the edge of the outward-expanding contact hole.

[0071] S305: Perform surface planarization and cleaning steps to complete the process.

[0072] Example 4: This embodiment provides a method for fabricating a memory cell layout structure based on local routing optimization. The fabrication method includes the following steps: S401: Performs bottom structure patterning process, controls the spacing between adjacent active regions to be 10.0μm, controls the spacing between the contact hole reserved area and the polysilicon layer to be 4.0μm, and constructs a compliant physical base for the upper configuration.

[0073] S402: Through-layer etching to form contact holes, precisely anchoring the etch target size within the parameter specification of 5.0μm lateral width and 7.5μm longitudinal length.

[0074] S403: Performs seamless filling of conductive tungsten metal within the contact hole and completes physical vapor deposition of the top first metal layer film.

[0075] S404: Patterning operation is performed on the first metal layer. In this embodiment, instead of a simple node expansion pattern, a multi-angle bending method is used to etch a zigzag trace structure in the connection area. This zigzag trace configuration can more flexibly avoid vertical via conflicts in complex multi-layer wiring environments. The physical isolation spacing between adjacent traces of the zigzag is controlled at 7.0 μm. Through the area redundancy naturally formed at the turning nodes of the zigzag, it is ensured that its outer boundary fully exceeds the contact hole boundary, thereby completing a reliable physical enclosure.

[0076] S405: Planarization process is completed through chemical mechanical grinding and ultrasonic water washing.

[0077] Comparative Examples 1-4: Comparative Example 1: Compared with Example 1, the difference is that the geometry of the contact hole adopts a traditional square structure with a size of 5.0μm×5.0μm; and the first metal layer adopts a completely straight-line routing in the local area connecting the contact hole, without setting any form of non-straight-line corner structure. The remaining steps and structural parameters are the same.

[0078] Comparative Example 2: Compared with Example 1, the difference is that the aspect ratio of 0.8:1.25 was not followed. The etching target size of the contact hole was modified to a super-large square structure of 7.5μm×7.5μm with equal horizontal and vertical proportions. Due to the physical limitations of the metal wiring space, the physical boundary of the obtuse corner structure of the first metal layer could not extend outward beyond the physical boundary of the contact hole, resulting in the first metal layer not being able to completely cover and wrap the edge of the contact hole, resulting in a local area of ​​suspended area. The remaining steps and structural parameters are the same.

[0079] Comparative Example 3: Compared to Example 1, the difference lies in that, while maintaining the contact hole's lateral width of 5.0 μm and longitudinal length of 7.5 μm, and forcibly reducing the overall longitudinal dimension of the memory cell, a corner expansion design was not adopted. Instead, the first metal layer was forced to maintain a purely straight-line trace structure. This layout resulted in the physical spacing between the patterned first metal layers being forced to be reduced to 6.2 μm, lower than the 7.0 μm process setting. The remaining steps and structural parameters were the same.

[0080] Comparative Example 4: Compared with Example 1, the difference is that the pretreatment step of using dilute hydrofluoric acid was omitted before the process of filling the contact hole with conductive tungsten dielectric. The original oxide layer generated at the bottom of the hole during the dielectric etching process was not removed. The conductive metal was directly deposited on the uncleaned bottom surface of the hole. The remaining steps and structural parameters are the same.

[0081] Test Examples 1-4: Test Example 1: Using electronic design automation tools, the physical coordinates of the mask layouts corresponding to each embodiment and comparative example are converted into standard GDSII format files and imported into the verification environment.

[0082] Load the physical design rule file of the target process node and set hard constraint indicators for the lower limit of the first metal layer spacing and the tolerance of the metal layer's wrapping overlap with the contact hole.

[0083] The design rule check module is activated to perform Boolean logic operations and spatial range calculations on the entire graphic area, locate and output the coordinates of all violations of spatial spacing and wrapping edge tolerance, as well as the total number of errors.

[0084] Use the layout parameter extraction tool to select the repeating boundary of a single basic memory cell and calculate the orthogonal projection overlap area between the effective wiring area and the transistor physical layer by integration.

[0085] For the boundary region between the first metal layer and the contact hole, the minimum physical spacing extreme value between adjacent traces of the metal layer is extracted, and the minimum wrapping overlap offset from the physical boundary of the contact hole to the outer boundary of the metal layer is measured.

[0086] Table 1. Data Extracted from Memory Cell Layout Physical Dimensions and Design Rules Check

[0087] in conclusion: According to Table 1 and Figure 4 The layout structure provided by this invention resolves the constraint conflict between memory cell area miniaturization and semiconductor manufacturing design rules.

[0088] observe Figure 4 (a) shows the histogram data distribution, where the unit cell area occupied in Examples 1 to 4 remained at a low level of 46.85 μm. 2 ~55.43μm 2 Interval. Synchronous combination Figure 4 (b) shows the broken line trend. The minimum physical spacing data points in the four embodiments are all stably distributed above the 7.0μm lower limit baseline of the design rule. Overlaying the positive minimum wrapping overlap tolerance index in Table 1 proves that the non-linear corner expansion configuration introduced in the embodiments can construct a compliant node overlap area through horizontal or vertical contour extension without triggering any physical space short circuit error.

[0089] Compare the comparative data in the chart. Figure 4 In (a) the columnar unit cell area of ​​Comparative Example 1 is relatively high, reaching 63.77 μm. 2 Although this sample was in Figure 4(b) is located within the metal spacing safety zone, but its area occupied is increased by approximately 27% compared to Example 1. This data contrast reflects the limitations of traditional pure linear arrangement and proportional square contact hole configuration in restricting the vertical miniaturization of underlying devices.

[0090] Comparative Example 3 attempts to forcibly compress the layout without changing the routing pattern. Figure 4 (a) shows that its single-cell area decreased to 49.95 μm. 2 But Figure 4 In (b), the corresponding metal spacing data point experienced a precipitous drop, bottoming out at 6.18 μm, directly breaching the 7.0 μm process lower limit. This result confirms that a single area compression method detached from node morphology reconstruction inevitably leads to the failure of physical isolation of the metal layer, thereby causing an electrical short circuit in adjacent signal lines.

[0091] Comparative Example 2 employed an ultra-large contact hole size with proportionally enlarged dimensions in both the horizontal and vertical directions. Table 1 data shows that this resulted in a -5.6 μm overlap tolerance, triggering a design rule error indicating wrapping failure. Meanwhile, Figure 4 (a) This reflects that the configuration occupies 65.12 μm. 2 The maximum unit cell area. This indicates that simply increasing the size of a conventional square contact hole not only fails to adapt to high-density wiring environments, but also causes the outer boundary of the metal layer to recede inward to within the physical boundary of the contact hole, resulting in local physical suspension at the contact interface.

[0092] The correspondence between the above chart data confirms the technical synergy between the contact hole design with a specific aspect ratio and the local node area gain design. Based on the contact hole arrangement with an aspect ratio of 0.8:1.25 and the extension of the non-linear topography of the metal layer at the edge of the connection area, the semiconductor layout of this invention, under the constraints of fixed lithographic resolution and metal spacing rules, achieves the simplification of the device logic area and the solid coverage of the bottom aperture by the upper metal layer.

[0093] Test Example 2: Extract the layout and routing data of each test sample and input it as the target pattern into the photolithography simulation engine. Set the light source parameters required for the simulation, including the center wavelength, numerical aperture, and off-axis illumination mode, and establish a photoresist response model that matches the specific process node.

[0094] The optical proximity effect correction processing module is activated. For the non-linear corner structure of the first metal layer and the edge of the contact hole with a specific aspect ratio, sub-resolution auxiliary graphics are automatically generated and edge offset fine-tuning is performed to obtain the compensated mask data.

[0095] Set multiple sets of process window parameters, including nominal exposure dose, optimal focal length, and defocus offset. Perform spatial image simulation and 3D contour calculation of photoresist development to simulate the physical morphology of the wafer surface after photolithography and etching.

[0096] Virtual measurement lines are arranged at the boundary areas of the contact holes and at the connection nodes of the first metal layer corners. Key dimensional data of the contours of each sample under different process windows are extracted, and the maximum dimensional deviation extreme value relative to the design reference value is calculated and output. At the same time, it is recorded whether resist peeling or residue occurs in the simulation image.

[0097] Table 2. Data from lithographic spatial image simulation and critical size deviation extraction of memory cells

[0098] in conclusion: Based on the data in Table 2, combined with the appendix Figure 5 (a) and appendix Figure 5 (b) The deviation distribution state, the non-linear corner structure and specific aspect ratio contact hole arrangement defined in this invention have optical printing anti-disturbance capability. In semiconductor manufacturing processes, local changes in pattern density can lead to light diffraction and etching micro-load effects, thereby causing the actual formed contour to deviate from the design dimensions. (See attached diagram) Figure 5 (a) and appendix Figure 5 (b) In Examples 1 to 4, the data point distribution shows that the maximum etching size deviation of the first metal layer is distributed between -0.182 μm and +0.217 μm, and the maximum etching size deviation of the contact hole is distributed between -0.092 μm and +0.136 μm. The measurement data points of all examples strictly converge within the tolerance baselines of ±0.3 μm and ±0.2 μm marked in the figure.

[0099] This distribution confirms that the arc transition, obtuse angle expansion, and broken line structure used in the embodiment alleviate the spatial image stress at the sharp corners of the pattern, ensuring that the metal layer still has sufficient physical edge overlap margin after being subjected to deviations in the photolithography and etching processes. The long and narrow contact hole design, with its short axis dimension maintained within the nominal resolution, suppresses lateral incision failure caused by aspect ratio misalignment during deep hole etching.

[0100] Observation Appendix Figure 5 In Comparative Example 3 (a), without introducing outward expansion topography and forcibly compressing the wiring spacing, the maximum etching size deviation of the first metal layer surged to +0.415 μm. This data point clearly exceeded the tolerance upper limit of +0.3 μm. Table 2 simultaneously records that this sample generated edge bridging risk in the dense wiring area. At the physical level of wafer manufacturing, this magnitude of positive dimensional expansion consumes the preset metal isolation spacing margin, causing physical contact and electrical short circuits between adjacent wirings.

[0101] Regarding the appendix Figure 5 (b) shows the data feedback from Example 2, which features an extra-large equilateral square contact hole exceeding conventional proportions. The corresponding data point deviates from zero, reaching +0.312 μm, exceeding the ±0.2 μm tolerance limit. This large, uniform opening induces a micro-loading effect during the dry etching stage, with excessive consumption of reactive groups leading to overexposure and expansion at the hole tip. This flared tip morphology directly exacerbates the failure probability of the overlying first metal layer failing to fully cover the edge.

[0102] Limiting the contact hole etching deviation to within ±0.2 μm and controlling the first metal layer etching deviation to within ±0.3 μm are rigid boundary conditions that prevent short circuits or open circuits in the locally expanded encapsulated architecture. The structural morphology of this invention, combined with this specific process dimensional deviation control specification, blocks the metal layer interconnect failure path caused by optical proximity effects.

[0103] Test Example 3: Select wafer samples that have completed the surface planarization process, place them on the test chuck of the fully automated probe station, and keep the test environment temperature constant at 25°C to eliminate interference from hot carrier fluctuations.

[0104] The Kelvin four-wire test setup is used to drive the probe station to precisely insert micron-sized probes into the surface of the reserved test pads, establishing physical and electrical connections with the first metal layer and the active area lead-out terminal at the bottom.

[0105] A semiconductor parameter analyzer is used to apply a scanning voltage to the test link, and the current response data is measured and recorded simultaneously. The contact resistance value of a single contact hole node is then extracted by converting Ohm's law.

[0106] Within the center, middle ring, and edge regions of the wafer, 1000 independent memory cell arrays are randomly selected according to preset spatial sampling coordinates. The probe dwell and parameter extraction operations are repeated to obtain a sample set of contact resistance and the standard deviation of resistance value dispersion.

[0107] The engineering failure threshold for contact resistance is set at 50.0Ω. The number of cells with resistance values ​​exceeding this threshold or exhibiting a high-resistance open circuit state is counted, and the wafer-level electrical connectivity yield of each wafer sample is calculated accordingly.

[0108] Table 3. Statistical data on contact resistance and wafer-level electrical yield for each test sample.

[0109] in conclusion: Based on the data trends in Table 3 and the accompanying figures, the layout structure and pretreatment cleaning process defined in this invention synergistically ensure the electrical reliability of signal transmission at the bottom-layer nodes. The measured value of wafer-level contact resistance is directly controlled by the effective conductive cross-sectional area between the metal and the underlying silicon interface and the state of impurities remaining at the interface.

[0110] observe Figure 6 (a) shows the column height and error line segment. In Examples 1 to 4, the average contact resistance is consistently below 20Ω, indicating a low resistance range, and the error line segment characterizing the resistance dispersion is extremely short. (Synchronous combination) Figure 6 (b) The data point distribution shows that the wafer-level electrical yield of the four embodiments described above consistently exceeds the 95% engineering pass rate. This data distribution verifies the effectiveness of the specific aspect ratio setting. The longitudinally extending physical morphology compensates for the cross-sectional area loss caused by the lateral narrowing of the contact holes, and together with the outward wrapping of the first metal layer at the connection node, it constructs an ample and uniform carrier transport path.

[0111] contrast Figure 6 In Comparative Example 1 (a), the average contact resistance column rises to 26.43Ω, and the resistance dispersion increases simultaneously. This sample maintains the conventional straight trace and square contact hole arrangement. Due to the physical restriction on the lateral expansion of the square pattern by the metal isolation spacing, its actual physical contact area is limited, confirming the limitation of maintaining low-resistance ohmic contacts under the extreme compression of the traditional proportional configuration.

[0112] Comparative Example 2 shows that the package failed due to the use of an unsuitable, oversized proportional opening size. Figure 6 In (a), the elongated error line segment of this sample indicates random edge suspension and reduced conductive cross-section at numerous contact hole interfaces within the array. This incomplete coverage in the physical structure causes current congestion at this node in the test signal. This is reflected in... Figure 6 In (b), the overall yield data point fell below the 95% engineering baseline lower limit.

[0113] Figure 6 (a) and Figure 6 (b) The data in Comparative Example 4 show extreme degradation characteristics. Figure 6 (a) This indicates that the average resistance value spiked abnormally and the error segment spanned a large range. Figure 6 The yield curve in (b) shows a sharp drop, bottoming out at 35.8%. This sample had its dilute hydrofluoric acid cleaning step omitted during the process. The unremoved native silicon oxide layer at the bottom created a high-impedance parasitic barrier between the metal layer and the active layer, blocking the electron tunneling path that the physical structure should provide. This set of deviation data confirms the necessity of the chemical deoxidation pretreatment process in the bottom-layer contact via interconnect process.

[0114] Test Example 4: Wafer samples that pass the basic electrical yield screening are extracted from each batch, diced and packaged in standard ceramic, and then loaded into the test tank of a high-temperature accelerated aging test system (HTOL).

[0115] The ambient background temperature of the test chamber was set to a constant 150°C to provide the initial thermal energy for the wafer to excite the diffusion of metal lattice atoms and the proliferation of defects inside the medium.

[0116] Electromigration accelerated aging tests were performed on the physical connection interface between the first metal layer and the bottom contact hole. The memory cell was injected with a constant density of 1.5 × 10⁻⁶ through the test channel. 6 A / cm 2 DC electrical stress. Real-time recording of resistance drift data at both ends of the metal connection, defining the point at which the test link resistance rises to 120% of its initial value as the electromigration failure time.

[0117] A dielectric breakdown aging test was performed on the gap between adjacent first metal layers. A progressively increasing lateral bias voltage was applied to the adjacent parallel metal traces until the internal electric field strength reached three times the rated operating field strength. The leakage current between the metals was continuously monitored, and the point at which the leakage current experienced a step-like change that could not be recovered was defined as the dielectric breakdown time.

[0118] Failure time data of all samples in each test group were collected, imported into the Weibull statistical distribution model, and the average failure time value when the cumulative failure probability reached 50% was extracted. The early dominant failure mechanism of each sample group was also recorded.

[0119] Table 4. Extracted data on mean time to failure (MTBF) of memory cells under accelerated aging conditions.

[0120] in conclusion: Based on the data in Table 4 and the accompanying figures, the layout structure of this invention achieves physical space miniaturization while avoiding local electrical failures caused by early degradation mechanisms at the device physical level. The long-term reliability lifetime of a semiconductor structure is highly dependent on the uniformity of current distribution within the conductor cross-section and the level of control over the electric field strength between adjacent conductors.

[0121] Analysis Appendix Figure 7 (a) and appendix Figure 7(b) Statistical distribution of Examples 1 to 4 shows that the mean electromigration failure time remains in the high range of 4983h to 5411h, and the mean dielectric breakdown failure time is in the range of 8241h to 9054h. All data points are much higher than the 2000h engineering baseline lifespan indicated in the figure. The dominant mechanism recorded in Table 4 is late wear failure. The structure of the examples achieves complete encapsulation of the physical boundary of the contact hole through area compensation at the corner of the first metal layer. The complete encapsulation morphology suppresses the current congestion effect when electrons flow at the contact interface and slows down the momentum exchange of the metal lattice caused by local Joule heating, thereby extending the electromigration failure lifetime. In addition, the isolation spacing of more than 7.0μm maintained during the patterning of the metal layer effectively reduces the local electric field distortion inside the interlayer dielectric, ensuring the insulation strength of the material under long-term electrical stress.

[0122] Compared with the test data of Comparative Example 2, attached Figure 7 (a) This indicates that the electromigration failure time has been reduced to 615 hours, breaking through the lower limit of the engineering reference. Combined with the physical calculations from previous tests, the large, proportionally-sized opening caused localized suspending of the first metal layer. In accelerated testing, the uncovered area of ​​the interface forced current to flow through the remaining narrow metal edges at a high density. This severe current congestion accelerated the momentum migration of metal atoms and the hole nucleation process, resulting in early open-circuit failure characteristics of the device.

[0123] Observation Appendix Figure 7 In Comparative Example 3 (b), the lifetime curve shows a precipitous drop in the mean time to dielectric breakdown, at only 142 hours. This sample, in order to retain traditional straight wiring, forcibly compressed the spacing between adjacent traces, breaking the 7.0 μm safety process lower limit. In the lateral high electric field bias aging test, the extremely narrow dielectric spacing caused the local electric field strength to exceed the intrinsic insulation limit of silicon dioxide, triggering rapid proliferation of electron traps and through-circuit short circuits within the insulating layer. The aging failure data of the two sets of comparative examples demonstrate that forcibly scaling down or compressing the wiring spacing will lead to sudden hard failure of the device in the early stages of application.

Claims

1. A memory cell layout structure based on local routing optimization, comprising: include: Semiconductor substrate; An active region layer and a polysilicon layer are disposed on the semiconductor substrate, wherein the spacing between adjacent active region layers is greater than or equal to 10.0 μm; A contact hole is disposed above the polysilicon layer, and the spatial distance between the contact hole and the polysilicon layer is greater than or equal to 4.0 μm; A first metal layer is disposed above the contact hole, and the physical spacing between the first metal layers is greater than or equal to 7.0 μm; The first metal layer has a non-linear corner structure in the local area connected to the contact hole, and the contact hole is a rectangular structure with a lateral width between 4.8μm and 5.2μm and a longitudinal length between 7.3μm and 7.7μm; The corner structure of the first metal layer extends outward beyond the physical boundary of the contact hole, so that the first metal layer completely covers and encloses the contact hole; The ratio of the lateral width to the longitudinal length of the contact hole is fixed at 0.8:1.25; The physical channel length of the gate transistor formed by the active region layer is greater than or equal to 4.0 μm, and the physical channel width is greater than or equal to 18.5 μm. In a horizontal cross-section, the edges of the corner structure of the first metal layer extend outward in all directions beyond the edges of the contact hole; The contact interface formed by the first metal layer and the contact hole is a continuous solid connection surface without any insulating residue or gaps.

2. The memory cell layout structure based on local routing optimization according to claim 1, characterized in that, The corner structure of the first metal layer is specifically: any one of the following: an arc-shaped transition structure, an obtuse-angle corner structure, a broken line routing structure, or a locally widened structure formed on the basic straight line routing of the first metal layer in the local area connecting the contact hole.

3. A method for fabricating a memory cell layout structure based on local routing optimization, characterized in that, Preparing a memory cell layout structure based on local routing optimization as described in any one of claims 1-2 includes the following steps: A semiconductor substrate is provided, an active region layer is deposited on the semiconductor substrate, and the active region layer is patterned using reactive ion etching technology, and the actual process size of the spacing between adjacent active region layers is controlled to be 10.0 μm or more. A polysilicon layer is deposited in a preset area, and patterned by mask exposure and dry etching. The reserved area for contact holes is defined simultaneously, and the spatial distance between the reserved area for contact holes and the polysilicon layer is controlled to be 4.0 μm or more. An insulating dielectric layer is deposited between the layers. The contact hole is formed by etching downwards in the reserved area of ​​the contact hole using a dry etching technique. The target size of the contact hole is controlled to be between 4.8 μm and 5.2 μm in lateral width and between 7.3 μm and 7.7 μm in longitudinal length. A conductive medium is filled into the contact hole, and a first metal layer is deposited. The first metal layer is patterned to form a non-linear corner structure in the local area connecting the contact hole, and the minimum physical spacing between the patterned first metal layers is controlled to be 7.0 μm. During the patterning process, by adjusting the photolithography and etching parameters, the physical boundary of the corner structure pattern of the first metal layer at the top is controlled to extend outward beyond the physical boundary of the contact hole, so that the first metal layer completely covers and wraps the edge of the contact hole.

4. The preparation method according to claim 3, characterized in that, In the step of patterning the active region layer, the etching size deviation of the active region layer is controlled within ±0.5μm.

5. The preparation method according to claim 3, characterized in that, Patterning the first metal layer specifically includes: The photolithography mask pattern employs a non-linear compensation design in the local area connecting the contact holes, and then anisotropic dry etching technology is used to etch obtuse angle corners, zigzag trace structures, or locally widened structures. Furthermore, the etching size deviation in this step is controlled within ±0.3μm.

6. The preparation method according to claim 3, characterized in that, In the step of etching to form the contact hole, the aspect ratio of the etching target of the contact hole is fixed at 0.8:1.25; The etching process employs a high selectivity fluorine-based gas system for deep silicon and dielectric dry etching, and controls the process deviation of the etched aperture profile within ±0.2μm.

7. The preparation method according to claim 3, characterized in that, Before the step of filling the conductive medium into the contact hole, a pretreatment with dilute hydrofluoric acid is performed to remove the bottom native oxide layer; The conductive medium is tungsten or copper, and is filled using chemical vapor deposition or atomic layer deposition techniques.

8. The preparation method according to claim 3, characterized in that, After ensuring that the first metal layer completely covers and wraps the edges of the contact hole, post-processing and planarization processes are also included: The residual photoresist and overflowing conductive medium are removed by chemical mechanical planarization (CMP) grinding, followed by mega-sonic cleaning and deionized water rinsing to remove surface particulate contaminants and metal ion residues.

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