Patterned sapphire substrate and method for preparing the same, and light emitting diode epitaxial wafer

Abstract

The application discloses a patterned sapphire substrate and a preparation method thereof and a light emitting diode epitaxial wafer, and relates to the field of semiconductor photoelectric devices. The preparation method of the patterned sapphire substrate comprises the following steps: forming periodic distribution of convex structures on a first surface of a sapphire substrate; wherein, a preset distance is arranged between adjacent convex structures to form a planar region; forming a dielectric layer on the convex structures and the planar region; wherein, the refractive index of the dielectric layer is less than the refractive index of the sapphire substrate; forming a hole on the top of the dielectric layer to expose the convex structures; wherein, the hole extends to the convex structures along the thickness direction of the sapphire substrate by a preset depth to form a nucleation surface on the top of the convex structures to expose the C surface of the sapphire substrate. By implementing the application, the light extraction efficiency and the light emitting efficiency of the light emitting diode can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic devices, and more particularly to a patterned sapphire substrate and its preparation method, and a light-emitting diode epitaxial wafer. Background Technology

[0002] Patterned SiO2 sapphire substrates (SPSS) involve first forming a SiO2 layer on a sapphire substrate, then etching the SiO2 layer and part of the sapphire substrate to form conical, pyramidal, or other patterns (see Li Sihong, Hou Xiang, Luo Ronghuang, et al. Influence of patterned SiO2 sapphire substrates on GaN growth and LED luminous performance [J]. Journal of Luminescence, 2021, 42(04): 526-533.). This type of patterned SiO2 substrate, due to the introduction of a SiO2 layer with a lower refractive index, can improve light extraction efficiency. However, the SiO2 layer typically only covers the top of the protrusions, leaving the flat C-plane exposed. This causes dislocations to penetrate directly upwards from the flat area, resulting in limited dislocation annihilation efficiency and relatively poor crystal quality of the subsequently grown epitaxial layer, leading to low luminous efficiency. Furthermore, the incomplete coverage of the SiO2 layer results in a discontinuous refractive index gradient, further contributing to relatively low light extraction efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a patterned sapphire substrate and its preparation method, which can improve the luminous efficiency and light extraction efficiency of light-emitting diodes.

[0004] Another technical problem that the present invention needs to solve is to provide a light-emitting diode epitaxial wafer.

[0005] To address the aforementioned technical problems, this invention provides a method for preparing a patterned sapphire substrate, comprising: A periodically distributed protrusion structure is formed on the first surface of a sapphire substrate; wherein a predetermined distance is provided between adjacent protrusion structures to form a planar region; A dielectric layer is formed on the protruding structure and the planar region; wherein the refractive index of the dielectric layer is less than the refractive index of the sapphire substrate; A hole is formed on the top of the dielectric layer to expose the protruding structure; The hole extends a predetermined depth along the thickness direction of the sapphire substrate into the protrusion structure to form a nucleation surface at the top of the protrusion structure that exposes the C-face of the sapphire substrate.

[0006] As an improvement to the above technical solution, the ratio of the depth to the width of the hole is ≥2; and / or The depth of the hole is ≥100nm, and its width is ≥50nm; and / or Each of the protruding structures has 1 to 4 holes formed on its top; and / or The dielectric layer is a stacked structure formed by one or more of SiO2 layers, MgF2 layers, and BaF2 layers; and / or The thickness of the dielectric layer is 50nm~1500nm.

[0007] As an improvement to the above technical solution, the ratio of the depth to the width of the hole is 2 to 4; and / or The depth of the pore is 100nm~1.5μm, and its width is 50nm~500nm; and / or Each of the protruding structures has one hole at its top; and / or The dielectric layer is a SiO2 layer with a thickness of 50nm~500nm.

[0008] As an improvement to the above technical solution, the protruding structure is frustum-shaped, prism-shaped, truncated cone-shaped, or dome-shaped; The height of the protrusion is 0.5μm to 5μm, the width of its bottom is 1μm to 8μm, and the spacing between adjacent protrusions is 1.5μm to 10μm.

[0009] As an improvement to the above technical solution, the protruding structure is a truncated cone shape; The height of the protrusion is 1.5μm to 3μm, the width of its bottom is 2μm to 5μm, and the spacing between adjacent protrusions is 2μm to 6μm.

[0010] As an improvement to the above technical solution, the step of forming a periodically distributed protrusion structure on the first surface of the sapphire substrate includes: A mask layer is formed on a sapphire substrate; An opening is formed in the mask layer; The sapphire substrate is first etched along the opening to obtain a preliminary protrusion structure; The initial protrusion structure is then etched a second time to obtain the protrusion structure; The first etching is ICP etching, and its process conditions include: etching gases are Cl2, BCl3 and Ar, the flow rate of Cl2 is 10 sccm~25 sccm, the flow rate of BCl3 is 10 sccm~25 sccm, the flow rate of Ar is 5 sccm~15 sccm, the ICP power is 800W~1500W, the RF power is 100W~200W, and the chamber pressure is 1 mtorr~10 mtorr. The second etching is a wet etching process, and its process conditions include: The etching solution is a mixture of sulfuric acid and phosphoric acid, with the concentration of sulfuric acid being 95wt%~98wt% and the concentration of phosphoric acid being 75wt%~85wt%. The volume ratio of sulfuric acid to phosphoric acid is 2:1~4:1, and the etching temperature is 150℃~300℃.

[0011] As an improvement to the above technical solution, in the step of forming a dielectric layer on the protruding structure and the planar region, a SiO2 layer is formed by PECVD, and the process conditions include: using TEOS and O2 as reaction gases, the flow rate of TEOS is 20 sccm~50 sccm, the flow rate of O2 is 150 sccm~300 sccm, the RF power is 80W~200W, the chamber pressure is 1 torr~10 torr, and the temperature of the sapphire substrate is 200℃~350℃.

[0012] As an improvement to the above technical solution, the step of forming a hole exposing the protruding structure on the top of the dielectric layer includes: A third etching is performed on the dielectric layer to form a first hole that exposes the protruding structure; A fourth etching is performed along the first hole to form a second hole in the protrusion structure; The third etching is ICP etching, and its process conditions include: etching gases are CF4 and CHF3, the flow rate of CF4 is 3sccm~15sccm, the flow rate of CHF3 is 30sccm~60sccm; ICP power is 600W~800W, RF power is 50W~100W, and chamber pressure is 1mtorr~10mtorr. The fourth etching is ICP etching, and its process conditions include: etching gases are CHF3 and BCl3, the flow rate of CHF3 is 5 sccm~15 sccm, the flow rate of BCl3 is 10 sccm~30 sccm, the ICP power is 600W~800W, the RF power is 250W~400W, and the chamber pressure is 3 mtorr~10 mtorr.

[0013] Accordingly, the present invention also discloses a patterned sapphire substrate, which is prepared by the above-described method for preparing a patterned sapphire substrate.

[0014] Accordingly, the present invention also discloses a light-emitting diode epitaxial wafer, which includes the patterned sapphire substrate described above.

[0015] Implementing this invention has the following beneficial effects: In one embodiment of the present invention, a method for fabricating a patterned sapphire substrate involves first forming a raised structure on a first surface of the sapphire substrate, then forming a dielectric layer, and finally forming a hole in the dielectric layer at the top of the raised structure, extending the hole into the raised structure. Based on this fabrication method, firstly, a hole is formed at the top of the raised structure, and a nucleation surface exposing the C-plane of the sapphire substrate is formed at the bottom of this hole. This nucleation surface is the initial nucleation site during the subsequent growth of the epitaxial layer. This allows dislocations to grow vertically from the C-plane, then deflect downwards after the dielectric layer is grown, and achieve lateral expansion and annihilation upon encountering the dielectric layer on the sidewall of the raised structure. This forms a downward bending → lateral merging growth path, significantly improving the efficiency of dislocation annihilation, optimizing the crystal quality of the epitaxial layer, and improving the luminescence efficiency. Secondly, after the raised structure is fabricated, a dielectric layer is deposited in both the raised structure and the planar regions between adjacent raised structures, and then the hole is etched. This process ensures that the sides and planar areas of the raised structure completely cover the dielectric layer, significantly improving reflectivity and light extraction efficiency. Thirdly, due to the high coverage of the dielectric layer, the subsequently grown epitaxial layer primarily contacts the dielectric layer, resulting in a more uniform distribution of interfacial thermal stress. This, in turn, improves the stress distribution uniformity of the epitaxial layer, reduces the risk of cracks and warping, increases yield, and enhances wavelength uniformity. Attached Figure Description

[0016] Figure 1 This is a flowchart of a method for preparing a patterned sapphire substrate according to an embodiment of the present invention; Figure 2 This is a cross-sectional view of a patterned sapphire substrate according to an embodiment of the present invention; Figure 3 This is a top view of a patterned sapphire substrate in one embodiment of the present invention; In the figure, 100 is the sapphire substrate, 110 is the first surface, 120 is the raised structure, 130 is the planar area, 200 is the dielectric layer, 300 is the hole, 310 is the first hole, and 320 is the second hole. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0018] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0022] Please see Figures 1-3 As a first aspect of the present invention, the present invention provides a method for preparing a patterned sapphire substrate, which includes the following steps: S1: A periodically distributed protrusion structure is formed on the first surface of the sapphire substrate; S2: A dielectric layer is formed on the raised structure and the planar region; S3: Forming holes on the top of the dielectric layer to expose the protruding structure; The adjacent protrusions 120 are spaced at a predetermined distance to form a planar region 130; the refractive index of the dielectric layer 200 is less than that of the sapphire substrate 100. The aperture 300 extends a predetermined depth along the thickness direction of the sapphire substrate 100 into the protrusion 120 to form a nucleation surface at the top of the protrusion 120 that exposes the C-plane of the sapphire substrate 100.

[0023] Based on the above preparation method, firstly, a hole 300 is formed at the top of the protrusion structure 120, and a nucleation surface exposing the C-plane of the sapphire substrate 100 is formed at the bottom of the hole 300. This nucleation surface is the starting nucleation position during the subsequent growth of the epitaxial layer. This allows dislocations to grow vertically from the C-plane, and then deflect downwards after the growth of the dielectric layer 200. Upon encountering the dielectric layer 200 on the sidewall of the protrusion structure 120, they undergo lateral expansion and annihilation. This forms a growth path of downward bending → lateral merging, which significantly improves the efficiency of dislocation annihilation, optimizes the crystal quality of the epitaxial layer, and improves the luminescence efficiency. Secondly, after the protrusion structure 120 is prepared, a dielectric layer 200 is deposited in both the protrusion structure 120 and the planar region 130 between adjacent protrusion structures 120, and then the hole 300 is etched. This process ensures that the sides of the protrusion structure 120 and the planar region 130 completely cover the dielectric layer 200, significantly improving reflectivity and light extraction efficiency. Thirdly, due to the high coverage of the dielectric layer 200, the subsequent epitaxial layer mainly contacts the dielectric layer 200, which makes the distribution of interfacial thermal stress more uniform, thereby improving the stress distribution uniformity of the epitaxial layer, reducing the risk of cracks, warping, etc., improving the yield, and improving the wavelength uniformity.

[0024] Specifically, in step S1, the protrusion structure 120 is shaped like a frustum, prism, truncated cone, dome, or other shapes with a planar or near-planar top surface. This facilitates the formation of a smooth dielectric layer 200 cover surface, ensuring the formation of pores 300 with a certain aspect ratio, and providing a good foundation for the subsequent low dislocation density growth of epitaxial layers. Preferably, in some embodiments, the protrusion structure 120 is shaped like a frustum, prism, truncated cone, or dome, as these shapes are easy to fabricate. More preferably, the protrusion structure 120 is truncated cone.

[0025] Specifically, the height of the protrusion structure 120 is 0.5 μm to 5 μm. If the height of the protrusion structure 120 is too small, it is difficult to effectively guide the downward bending of dislocations, resulting in a high dislocation density. If the height of the protrusion structure 120 is too large, the lateral expansion path during subsequent epitaxial layer growth is long, which easily leads to stress concentration in the epitaxial layer and reduces its crystal quality. For example, the height of the protrusion structure 120 is 0.7 μm, 1.1 μm, 1.5 μm, 1.9 μm, 2.3 μm, 2.8 μm, 3.5 μm, 4.2 μm, or 4.8 μm, but is not limited to these. Preferably, in some embodiments, the height of the protrusion structure 120 is 1.5 μm to 3 μm. More preferably, it is 2 μm to 3 μm.

[0026] Specifically, the width of the bottom of the protrusion structure 120 is 1μm to 8μm. If the bottom width is too large, the spacing between adjacent protrusion structures 120 is too small, resulting in a small lateral expansion space for the epitaxial layer and difficulty in effectively reducing dislocation density. If the bottom width is too small, the aspect ratio of the protrusion structure 120 is too large, making it difficult for the dielectric layer 200 to provide stable and uniform coverage. For example, the width of the bottom of the protrusion structure 120 is 1.2μm, 2.5μm, 3.8μm, 4.6μm, 5.3μm, 6.1μm, or 7.4μm, but is not limited to these. Preferably, in some embodiments, the width of the bottom of the protrusion structure 120 is 2μm to 5μm, more preferably 2μm to 4μm. It should be noted that the width of the bottom of the protrusion structure 120 refers to its characteristic width. For example, when its bottom is circular, the width is its diameter; when its bottom is regular hexagonal, the width is its circumscribed circle diameter, but is not limited to these.

[0027] Specifically, the spacing between adjacent protrusions 120 is 1.5 μm to 10 μm. If the spacing is too small, the lateral expansion path during subsequent epitaxial layer growth will be long, easily leading to stress concentration in the epitaxial layer and reducing its crystal quality. If the spacing is too large, the dislocation deflection guiding effect will be weakened. For example, the spacing between adjacent protrusions 120 is 1.8 μm, 2.4 μm, 3.2 μm, 4.0 μm, 5.5 μm, 6.7 μm, 7.9 μm, or 9.3 μm, but is not limited to these. Preferably, in some embodiments, the spacing between adjacent protrusions 120 is 2 μm to 6 μm. More preferably, it is 3 μm to 5 μm. It should be noted that the spacing between protrusions 120 is the center-to-center distance of the protrusions 120, that is, the straight-line distance between the geometric centers of adjacent protrusions 120.

[0028] Specifically, the width of the top surface of the protrusion structure 120 is 0.5μm to 2μm, exemplarily 0.6μm, 0.8μm, 1.0μm, 1.3μm, 1.6μm or 1.8μm, but not limited thereto.

[0029] Specifically, in step S1, a periodically distributed protrusion structure 120 can be formed on the surface of the sapphire using wet etching or dry etching processes, but is not limited thereto. Preferably, in some embodiments, step S1 includes: S11: Forming a mask layer on a sapphire substrate; The mask layer can be a SiO2 layer or a photoresist layer, but is not limited to these.

[0030] S12: Forming openings in the mask layer; Openings can be formed through either exposure and development or etching. Specifically, when the mask layer is a SiO2 layer, openings are formed using a wet etching process. When the mask layer is a photoresist layer, openings are formed using an exposure and development process.

[0031] S13: The sapphire substrate is first etched along the opening to obtain a preliminary protrusion structure; Specifically, the first etching can be dry etching or wet etching, but is not limited to these. Preferably, in some embodiments, the first etching is ICP etching, and the process conditions include: etching gases are Cl2, BCl3 and Ar, the flow rate of Cl2 is 10 sccm~25 sccm, the flow rate of BCl3 is 10 sccm~25 sccm, the flow rate of Ar is 5 sccm~15 sccm, the ICP power is 800W~1500W, the RF power is 100W~200W, and the chamber pressure is 1 mtorr~10 mtorr.

[0032] S14: Perform a second etching on the initial protrusion structure to obtain the protrusion structure; The second etching can be dry etching or wet etching, but is not limited to these. Preferably, in some embodiments, the second etching is wet etching, and the process conditions include: the etching solution is a mixed solution of sulfuric acid and phosphoric acid, the concentration of sulfuric acid is 95wt%~98wt%, the concentration of phosphoric acid is 75wt%~85wt%, the volume ratio of sulfuric acid to phosphoric acid is 2:1~4:1, and the etching temperature is 150℃~300℃.

[0033] Through the above-mentioned dry etching + wet etching process, not only was a raised structure 120 with a flat top obtained, laying a good foundation for the subsequent formation of the hole 300; but the surface roughness of the raised structure 120 was also reduced, providing an ideal interface for the subsequent formation of a uniformly distributed dielectric layer 200.

[0034] Specifically, in step S2, the dielectric layer 200 is a stacked structure formed from one or more of SiO2, MgF2, BaF2, and silicon oxyfluoride layers, but is not limited thereto. Preferably, in some embodiments, the dielectric layer 200 is a stacked structure formed from one or more of SiO2, MgF2, and BaF2 layers. These dielectric layers 200 have low refractive index, strong thermal stability, and are easy to form and etch.

[0035] Specifically, in step S2, the thickness of the dielectric layer 200 is 50nm to 1600nm, exemplarily 150nm, 300nm, 450nm, 600nm, 750nm, 900nm, 1050nm, 1200nm, 1350nm, or 1500nm, but not limited thereto. Preferably, the thickness of the dielectric layer 200 is 50nm to 1500nm, more preferably 50nm to 500nm.

[0036] Preferably, in some embodiments, the dielectric layer 200 is a SiO2 layer with a thickness of 50nm to 500nm.

[0037] Specifically, in step S2, a dielectric layer 200 can be prepared on the sapphire substrate 100 using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), but is not limited thereto. Preferably, in some embodiments, a SiO2 layer is formed by PECVD, and the process parameters include: using TEOS and O2 as reactant gases, with a TEOS flow rate of 20 sccm to 50 sccm, an O2 flow rate of 150 sccm to 300 sccm, an RF power of 80 W to 200 W, a chamber pressure of 1 torr to 10 torr, and a sapphire substrate 100 temperature of 200°C to 350°C. Based on the above process parameters, a uniform and dense SiO2 layer can be formed on the surface of the protrusion structure 120 and in the planar region 130 between adjacent protrusion structures 120.

[0038] Specifically, in step S3, holes 300 are formed on the top of the protruding structure 120. Specifically, the holes 300 are formed in the plane of the top of the protruding structure 120, and each protruding structure 120 has a hole 300 on its top. For a single protruding structure 120, its top can have 1 to 4 holes 300. Preferably, each protruding structure 120 has 1 hole 300 on its top.

[0039] Specifically, the depth-to-width ratio of the hole 300 is ≥2 to effectively improve the crystal quality of the subsequent epitaxial layer. More specifically, the depth-to-width ratio of the hole 300 is 2 to 5, exemplarily 2.5, 3, 3.5, 4, or 4.5, but not limited thereto. Preferably, in some embodiments, the depth-to-width ratio of the hole 300 is 2 to 4, more preferably 2 to 3.5.

[0040] Specifically, the depth of the hole 300 is ≥100nm to ensure uniform nucleation of the epitaxial layer at the bottom of the hole 300, and effective bending and annihilation of dislocations. More specifically, the depth of the hole 300 is 100nm~3000nm, exemplarily 150nm, 300nm, 500nm, 1100nm, 1400nm, 2000nm, 2200nm, 2400nm or 2800nm, but not limited thereto. Preferably, in some embodiments, the depth of the hole 300 is 100nm~1500nm, more preferably 200nm~1000nm. It should be noted that the depth of the hole 300 in this invention refers to the sum of the depth of the first hole 310 in the dielectric layer 200 portion and the depth of the second hole 320 in the protrusion structure 120 portion.

[0041] Specifically, please refer to Figure 2 The longitudinal section of the hole 300 (i.e., the section perpendicular to the first surface 110) is narrower at the top and wider at the bottom, wider at the top and narrower at the bottom, or of equal width, but is not limited thereto. Preferably, in some embodiments, the longitudinal section of the hole 300 is wider at the top and narrower at the bottom, and the inclination angle of its sidewall is 85° to 89°.

[0042] Specifically, the width of the hole 300 is ≥50nm to ensure sufficient nucleation space during the initial stage of epitaxial layer growth. More specifically, the width of the hole 300 is 50nm~800nm, exemplarily 100nm, 250nm, 400nm, 550nm, 700nm or 750nm, but not limited thereto. Preferably, in some embodiments, the width of the hole 300 is 50nm~500nm. More preferably, it is 100nm~400nm. It should be noted that the width of the hole 300 in this invention refers to the characteristic width of the bottom of the hole 300. For example, when its bottom is circular, the width is its diameter; when its bottom is regular hexagonal, the width is its circumcircle diameter, but not limited thereto.

[0043] Specifically, the hole 300 can be formed by a dry etching process or a wet etching process, but is not limited thereto. Preferably, in some embodiments, step S3 includes: S31: Perform a third etching on the dielectric layer 200 to form a first hole 310 that exposes the protrusion structure 120; The third etching process is ICP etching, and its process conditions include: etching gases are CF4 and CHF3, with a CF4 flow rate of 3 sccm to 15 sccm and a CHF3 flow rate of 30 sccm to 60 sccm; ICP power is 600W to 800W, RF power is 50W to 100W, and chamber pressure is 1 mtorr to 10 mtorr. S32: A fourth etching is performed on the protrusion structure 120 along the first hole 310 to form a second hole 320 on the protrusion structure 120; The fourth etching process is ICP etching, and its process conditions include: etching gases are CHF3 and BCl3, CHF3 flow rate is 5 sccm~15 sccm, BCl3 flow rate is 10 sccm~30 sccm, ICP power is 600W~800W, RF power is 250W~400W, and chamber pressure is 3 mtorr~10 mtorr.

[0044] Based on the above etching process, holes 300 with high sidewall verticality can be formed, providing a good foundation for reducing dislocation density in the epitaxial layer.

[0045] Accordingly, please refer to Figures 2-3As a second aspect of the present invention, a patterned sapphire substrate is also provided, which is prepared by the above-described preparation method. Specifically, the patterned sapphire substrate includes a sapphire substrate 100, on which periodically distributed protrusions 120 are formed on a first surface 110, with a predetermined distance between adjacent protrusions 120 to form a planar region 130. A dielectric layer 200 with a refractive index lower than that of the sapphire substrate 100 is covered on both the protrusions 120 and the planar region 130. A hole 300 exposing the protrusions 120 is formed at the top of the dielectric layer 200, and the hole 300 extends a predetermined depth along the thickness direction of the sapphire substrate 100 toward the protrusions 120 to form a nucleation surface exposing the C-plane of the sapphire substrate 100 at the top of the protrusions 120. Based on the above structural design, firstly, the bottom of the hole 300 forms a nucleation surface exposing the C-plane of the sapphire substrate 100. This nucleation surface is the starting nucleation position during the subsequent growth of the epitaxial layer. This allows dislocations to grow vertically from the C-plane, then deflect downwards after the growth of the dielectric layer 200, and achieve lateral expansion and annihilation upon encountering the dielectric layer 200 on the sidewall of the protrusion structure 120. This forms a growth path of downward bending → lateral merging, significantly improving the efficiency of dislocation annihilation, optimizing the crystal quality of the epitaxial layer, and improving the luminescence efficiency. Secondly, the side surface and planar region 130 of the protrusion structure 120 completely cover the dielectric layer 200, significantly improving reflectivity and light extraction efficiency. Thirdly, due to the high coverage of the dielectric layer 200, the subsequently grown epitaxial layer mainly contacts the dielectric layer 200, resulting in a more uniform distribution of interfacial thermal stress. This also improves the stress distribution uniformity of the epitaxial layer, reduces the risk of cracks and warping, improves the yield, and enhances wavelength uniformity.

[0046] Accordingly, as a third aspect of the present invention, a light-emitting diode epitaxial wafer is also disclosed, comprising the patterned sapphire substrate described above. Specifically, the patterned sapphire substrate comprises a sapphire substrate 100, on which periodically distributed protrusions 120 are formed on a first surface 110, with a predetermined distance between adjacent protrusions 120 to form a planar region 130. A dielectric layer 200, with a refractive index lower than that of the sapphire substrate 100, is covered on both the protrusions 120 and the planar region 130. A hole 300 is formed at the top of the dielectric layer 200 to expose the protrusions 120, and the hole 300 extends a predetermined depth along the thickness direction of the sapphire substrate 100 toward the protrusions 120 to form a nucleation surface at the top of the protrusions 120 exposing the C-plane of the sapphire substrate 100. Based on the above structural design, firstly, the bottom of the hole 300 forms a nucleation surface exposing the C-plane of the sapphire substrate 100. This nucleation surface is the starting nucleation position during the subsequent growth of the epitaxial layer. This allows dislocations to grow vertically from the C-plane, then deflect downwards after the growth of the dielectric layer 200, and achieve lateral expansion and annihilation upon encountering the dielectric layer 200 on the sidewall of the protrusion structure 120. This forms a growth path of downward bending → lateral merging, significantly improving the efficiency of dislocation annihilation, optimizing the crystal quality of the epitaxial layer, and improving the luminescence efficiency. Secondly, the side surface and planar region 130 of the protrusion structure 120 completely cover the dielectric layer 200, significantly improving reflectivity and light extraction efficiency. Thirdly, due to the high coverage of the dielectric layer 200, the subsequently grown epitaxial layer mainly contacts the dielectric layer 200, resulting in a more uniform distribution of interfacial thermal stress. This also improves the stress distribution uniformity of the epitaxial layer, reduces the risk of cracks and warping, improves the yield, and enhances wavelength uniformity.

[0047] Specifically, the epitaxial layer subsequently grown on the LED epitaxial wafer can be a GaN-based epitaxial layer, an AlGaN-based epitaxial layer, or an InGaAsP-based epitaxial layer, but is not limited to these. Preferably, the epitaxial layer is a GaN-based epitaxial layer.

[0048] Specifically, the light-emitting diode epitaxial wafer can be used to form standard-sized LEDs, Micro-LEDs, or mini-LEDs, but is not limited to these.

[0049] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a method for preparing a patterned sapphire substrate, which includes the following steps: (1) Forming a mask layer on a sapphire substrate; (2) Forming openings in the mask layer; (3) The sapphire substrate is first etched along the opening to obtain a preliminary protrusion structure; The first etching process is ICP etching, and its process conditions include: etching gases are Cl2, BCl3 and Ar, the flow rate of Cl2 is 12 sccm, the flow rate of BCl3 is 20 sccm, the flow rate of Ar is 8 sccm, the ICP power is 800W, the RF power is 180W, and the chamber pressure is 3 mtorr. (4) The initial protrusion structure is etched a second time to obtain the protrusion structure; The second etching process is a wet etching process, and its process conditions include: the etching solution is a mixed solution of sulfuric acid and phosphoric acid, the concentration of sulfuric acid is 98 wt%, the concentration of phosphoric acid is 85 wt%, the volume ratio of sulfuric acid to phosphoric acid is 3:1, the etching temperature is 160℃, and the etching time is 3 min.

[0050] Specifically, the resulting protrusions are arranged in a regular hexagonal pattern, which is a truncated cone with a base diameter of 2.8 μm, a height of 2.5 μm, a spacing of 4 μm, and a top diameter of 1.8 μm.

[0051] (5) A dielectric layer is formed on the protruding structure and the planar region; The SiO2 layer was formed by PECVD, with the following process conditions: TEOS and O2 were used as reactant gases, with a TEOS flow rate of 25 sccm and an O2 flow rate of 220 sccm, an RF power of 100 W, a chamber pressure of 1.5 torr, and a sapphire substrate temperature of 220 °C. The SiO2 layer thickness was 200 nm.

[0052] (6) A third etching is performed on the dielectric layer to form a first hole that exposes the protrusion structure; The third etching process is ICP etching, and its process conditions include: etching gases are CF4 and CHF3, with a CF4 flow rate of 6 sccm and a CHF3 flow rate of 50 sccm; ICP power is 750W, RF power is 50W, and chamber pressure is 3 mtorr.

[0053] (7) A fourth etching is performed along the first hole to form a second hole in the protrusion structure; The fourth etching process is ICP etching, and its process conditions include: etching gases are CHF3 and BCl3, CHF3 flow rate is 12 sccm, BCl3 flow rate is 20 sccm, ICP power is 650W, RF power is 300W, and chamber pressure is 5 mtorr.

[0054] Specifically, the first and second holes together form a cavity with a depth of 500 nm and a width of 230 nm. The cross-section of the cavity is trapezoidal, and the inclination angle of the sidewalls is 86°.

[0055] Example 2 This embodiment provides a method for preparing a patterned sapphire substrate, which differs from Embodiment 1 in that: The depth of the hole is 340 nm.

[0056] Everything else is the same as in Example 1.

[0057] Example 3 This embodiment provides a method for preparing a patterned sapphire substrate, which differs from Embodiment 1 in that: The depth of the hole is 720 nm.

[0058] Everything else is the same as in Example 1.

[0059] Example 4 This embodiment provides a method for preparing a patterned sapphire substrate, which differs from Embodiment 1 in that: The bottom of the protruding structure has a width of 2.7 μm, a spacing of 3.8 μm, and a height of 1.9 μm; the top has a width of 1.2 μm.

[0060] The SiO2 layer is 210 nm thick. The pores are 235 nm wide and 520 nm deep.

[0061] Everything else is the same as in Example 1.

[0062] Comparative Example 1 This comparative example provides a method for preparing a patterned sapphire substrate, which differs from Example 1 in that: Steps (6) and (7) are excluded, meaning no hole is formed.

[0063] Everything else is the same as in Example 1.

[0064] Comparative Example 2 This comparative example provides a method for preparing a patterned sapphire substrate, which differs from Example 1 in that: Step (7) is excluded, meaning that the hole does not extend into the protruding structure, but only penetrates the SiO2 layer.

[0065] Everything else is the same as in Example 1.

[0066] Examples 1-4, Comparative Examples 1-2, and the conventional SiO2 patterned sapphire substrate (SPSS) were tested respectively, as follows: (1) A GaN-based epitaxial layer was grown on a patterned sapphire substrate, and its dislocation density was tested; (2) A GaN-based epitaxial layer was grown on a patterned sapphire substrate and a 20mil*20mil upright structure chip was fabricated. Its luminous brightness was tested, and the brightness improvement rate was calculated based on a traditional SiO2 patterned sapphire substrate.

[0067] The specific results are as follows:

[0068] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for preparing a patterned sapphire substrate, characterized in that, include: A periodically distributed protrusion structure is formed on the first surface of a sapphire substrate; wherein a predetermined distance is provided between adjacent protrusion structures to form a planar region; A dielectric layer is formed on the protruding structure and the planar region; wherein the refractive index of the dielectric layer is less than the refractive index of the sapphire substrate, and the thickness of the dielectric layer is less than the height of the protrusion; A hole is formed on the top of the dielectric layer to expose the protruding structure; The hole extends a predetermined depth along the thickness direction of the sapphire substrate into the protrusion structure to form a nucleation surface at the top of the protrusion structure that exposes the C-face of the sapphire substrate.

2. The method for preparing a patterned sapphire substrate as described in claim 1, characterized in that, The ratio of the depth to the width of the hole is ≥2; and / or The depth of the hole is ≥100nm, and its width is ≥50nm; and / or Each of the protruding structures has 1 to 4 holes formed on its top; and / or The dielectric layer is a stacked structure formed by one or more of SiO2 layers, MgF2 layers, and BaF2 layers; and / or The thickness of the dielectric layer is 50nm~1500nm.

3. The method for preparing a patterned sapphire substrate as described in claim 1, characterized in that, The ratio of the depth to the width of the hole is 2 to 4; and / or The depth of the pore is 100nm~1.5μm, and its width is 50nm~500nm; and / or Each of the protruding structures has one hole at its top; and / or The dielectric layer is a SiO2 layer with a thickness of 50nm~500nm.

4. The method for preparing a patterned sapphire substrate as described in any one of claims 1 to 3, characterized in that, The protruding structure is frustum-shaped, prism-shaped, truncated cone-shaped, or dome-shaped. The height of the protrusion is 0.5μm to 5μm, the width of its bottom is 1μm to 8μm, and the spacing between adjacent protrusions is 1.5μm to 10μm.

5. The method for preparing a patterned sapphire substrate as described in any one of claims 1 to 3, characterized in that, The protruding structure is truncated conical in shape; The height of the protrusion is 1.5μm to 3μm, the width of its bottom is 2μm to 5μm, and the spacing between adjacent protrusions is 2μm to 6μm.

6. The method for preparing a patterned sapphire substrate as described in claim 1, characterized in that, The step of forming a periodically distributed protrusion structure on the first surface of the sapphire substrate includes: A mask layer is formed on a sapphire substrate; An opening is formed in the mask layer; The sapphire substrate is first etched along the opening to obtain a preliminary protrusion structure; The initial protrusion structure is then etched a second time to obtain the protrusion structure; The first etching is ICP etching, and its process conditions include: etching gases are Cl2, BCl3 and Ar, the flow rate of Cl2 is 10 sccm~25 sccm, the flow rate of BCl3 is 10 sccm~25 sccm, the flow rate of Ar is 5 sccm~15 sccm, the ICP power is 800W~1500W, the RF power is 100W~200W, and the chamber pressure is 1 mtorr~10 mtorr. The second etching is a wet etching process, and its process conditions include: The etching solution is a mixture of sulfuric acid and phosphoric acid, with the concentration of sulfuric acid being 95wt%~98wt% and the concentration of phosphoric acid being 75wt%~85wt%. The volume ratio of sulfuric acid to phosphoric acid is 2:1~4:1, and the etching temperature is 150℃~300℃.

7. The method for preparing a patterned sapphire substrate as described in claim 1, characterized in that, In the step of forming a dielectric layer on the protruding structure and the planar region, a SiO2 layer is formed by PECVD. The process conditions include: using TEOS and O2 as reaction gases, with a TEOS flow rate of 20 sccm to 50 sccm, an O2 flow rate of 150 sccm to 300 sccm, an RF power of 80 W to 200 W, a chamber pressure of 1 torr to 10 torr, and a sapphire substrate temperature of 200 °C to 350 °C.

8. The method for preparing a patterned sapphire substrate as described in claim 1, characterized in that, The step of forming a hole on top of the dielectric layer to expose the protrusion structure includes: A third etching is performed on the dielectric layer to form a first hole that exposes the protruding structure; A fourth etching is performed along the first hole to form a second hole in the protrusion structure; The third etching is ICP etching, and its process conditions include: etching gases are CF4 and CHF3, the flow rate of CF4 is 3sccm~15sccm, the flow rate of CHF3 is 30sccm~60sccm; ICP power is 600W~800W, RF power is 50W~100W, and chamber pressure is 1mtorr~10mtorr. The fourth etching is ICP etching, and its process conditions include: etching gases are CHF3 and BCl3, the flow rate of CHF3 is 5 sccm~15 sccm, the flow rate of BCl3 is 10 sccm~30 sccm, the ICP power is 600W~800W, the RF power is 250W~400W, and the chamber pressure is 3 mtorr~10 mtorr.

9. A patterned sapphire substrate, characterized in that, It is prepared by the method for preparing a patterned sapphire substrate as described in any one of claims 1 to 8.

10. A light-emitting diode epitaxial wafer, characterized in that, Includes the patterned sapphire substrate as described in claim 9.

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