Method of manufacturing a co-packaged optical structure and co-packaged optical structure

Abstract

The application provides a preparation method of a co-encapsulated optical structure and the co-encapsulated optical structure, and relates to the technical field of chip packaging. First, the substrate is thinned to expose the end of the conductive column. Then, the interposer is attached to the substrate, wherein the conductive column is accommodated in the accommodation groove of the interposer. The repair metal layer is arranged in part of the accommodation groove, and after the interposer is attached to the substrate, the repair metal layer can be welded to the damaged conductive column. Then, the first redistribution layer and the second redistribution layer are formed. Finally, the heterogeneous chip and the optical module are attached. Compared with the prior art, the application realizes the repair of the damaged conductive column through the repair metal layer in the accommodation groove, and protects the conductive column through the interposer and the insulating film, so that the risk of fracture, fault or interface layer delamination of the conductive column can be effectively reduced, and the electrical performance and transmission efficiency of the entire packaging structure are ensured.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a method for preparing a co-packaging optical structure and the co-packaging optical structure itself. Background Technology

[0002] CPO (Co) The core design of Packaged Optics (COOP) is the introduction of a silicon interposer. Its key value lies in drastically reducing the interconnect distance between the electrical chip and the optical engine from the centimeter level of traditional PCB substrates to the millimeter or even micrometer level, achieving a short-distance upgrade in optoelectronic interconnection. Leveraging the four core advantages of silicon material itself—high-density redistribution (RDL), thermal expansion coefficient matching the chip (thermal matching), TSV (Through Silicon Via) vertical interconnection, and optoelectronic synergistic integration capabilities—the silicon interposer can systematically overcome the core bottlenecks faced by high-speed electrical interconnects, such as excessive power consumption, insufficient bandwidth, significant signal loss, and heat dissipation difficulties. It has become an indispensable core carrier in the current mainstream 2.5D packaging solutions for Co-packaged Optics (CPO).

[0003] In conventional techniques, the fabrication of silicon interposers typically requires an exposed copper process, which involves chemically polishing to expose the metal pillars inside the interposer (interposer). However, during polishing, the copper pillars are easily subjected to direct physical contact with the polishing pad, which can generate corresponding shear stress, tensile stress, and / or compressive stress, leading to problems such as copper pillar fracture, delamination, or interface layer delamination.

[0004] Furthermore, in the CPO packaging structure, the breakage or damage of the metal pillars can affect the transmission efficiency of the subsequent optical engine chip or even render it unusable, thereby affecting the electrical performance of the entire CPO packaging structure. Summary of the Invention

[0005] The purpose of this invention is to provide a method for preparing a co-encapsulated optical structure and the co-encapsulated optical structure, which can effectively reduce the risk of conductive pillar breakage, delamination or interface layer delamination, and ensure the electrical performance and transmission efficiency of the entire encapsulation structure.

[0006] In a first aspect, the present invention provides a method for fabricating a co-encapsulated optical structure, comprising: A substrate is provided, wherein a conductive pillar is disposed in the substrate, one end of the conductive pillar is exposed on the front side of the substrate, and the other end is spaced apart from the back side of the substrate; The front side of the substrate is attached to the first carrier; Thin the back side of the substrate and expose the end of the conductive pillar so that the conductive pillar protrudes from the back side of the substrate; An intermediate layer covered with an insulating film is provided, wherein the front side of the intermediate layer is provided with a receiving groove for corresponding to receiving the conductive post, the insulating film covers the front side of the intermediate layer and extends to the inner wall of the receiving groove, and a repair metal layer is provided in the receiving groove corresponding to the damaged conductive post. The front side of the interposer is attached to the back side of the substrate, wherein the conductive post is correspondingly accommodated in the receiving groove, and the repair metal layer is correspondingly soldered to the defective conductive post; A first rewiring layer is formed on the back side of the interposer layer, wherein the first rewiring layer is electrically connected to the conductive pillar; Remove the first carrier and expose the front side of the substrate; A second redistribution layer is formed on the front side of the substrate, wherein the second redistribution layer is electrically connected to the conductive pillars; Multiple heterogeneous chips and optical modules are mounted on the second wiring layer.

[0007] In an optional implementation, the step of providing an intermediary layer covered with an insulating film includes: Provide an intermediary layer; A receiving groove is formed by slotting the front side of the intermediate layer; An insulating film is deposited on the front side of the intermediate layer, wherein the insulating film extends to cover the sidewalls and bottom wall of the receiving groove; A repair metal layer is provided in the receiving groove corresponding to the damaged conductive post.

[0008] In an optional embodiment, the step of providing a repair metal layer in the receiving groove corresponding to the defective conductive post includes: The conductive posts are inspected, and any damaged conductive posts are marked. A repair metal layer is electroplated in the receiving groove corresponding to the defective conductive post to form a repair metal layer, wherein the repair metal layer is used to weld the defective conductive post.

[0009] In an optional implementation, after the steps of detecting the conductive post and marking the defective conductive post, the method further includes: Laser removal of the damaged end of the conductive post.

[0010] In an optional implementation, prior to the step of forming a first redistribution layer on the back side of the interposer layer, the method further includes: Thin the back side of the interposer to expose the end face of the conductive post.

[0011] In an optional implementation, the step of providing an intermediary layer covered with an insulating film includes: Provide an intermediary layer; A photoresist layer is formed on the back side of the interposer layer; Grooves are cut into the photoresist layer and electroplated to form metal pads; A receiving groove is formed by slotting the front side of the interposer layer, wherein the receiving groove corresponds to exposing the metal pad; An insulating film is deposited on the front side of the interposer layer, wherein the insulating film extends to cover the sidewalls of the receiving groove and exposes the metal pads; A repair metal layer is provided in the receiving groove corresponding to the damaged conductive post; Remove the photoresist layer.

[0012] In an optional embodiment, the step of thinning the back side of the substrate and exposing the ends of the conductive pillars includes: The back side of the substrate is ground to expose the end face of the conductive pillar; The back side of the substrate is micro-etched to expose the ends of the conductive pillars, so that the conductive pillars protrude from the back side of the substrate.

[0013] In an optional implementation, the step of micro-etching the back side of the substrate to expose the ends of the conductive pillars includes: The back side of the substrate is micro-etched to expose the end of the conductive pillar, so that the conductive pillar protrudes from the back side of the substrate; The back edge of the substrate is micro-etched, and an edge protrusion ring is formed at the edge of the substrate; The intermediate layer is further provided with an edge ring groove corresponding to the edge protrusion ring.

[0014] In an optional embodiment, prior to the step of attaching the front side of the substrate to the first carrier, the method further includes: Stepped annular grooves are formed by cutting along the edge of the substrate.

[0015] In an optional implementation, after the step of mounting multiple heterogeneous chips and optical modules on the second redistribution layer, the method further includes: A molding layer is formed on the second redistribution layer, wherein the molding layer encapsulates the plurality of heterogeneous chips and the optical module; The molding layer is circumferentially cut along the edge of the substrate so that the edge of the molding layer is flush with the edge of the substrate.

[0016] In an optional implementation, the step of mounting multiple heterogeneous chips and optical modules on the second redistribution layer includes: The first chip, the second chip, the third chip, and the optical module are mounted on the second redistribution layer; A first adhesive layer, a second adhesive layer, a third adhesive layer, and a fourth adhesive layer are formed by applying adhesive to the bottom of the first chip, the second chip, the third chip, and the optical module, respectively.

[0017] In an optional embodiment, prior to the step of forming a second redistribution layer on the front side of the substrate, the method further includes: The first rewiring layer is attached to the second vehicle.

[0018] In an optional embodiment, prior to the step of forming a first redistribution layer on the surface of the insulating film away from the substrate, the method includes: Thin out and remove the intermediate layer until the surface of the insulating film is exposed.

[0019] In a second aspect, the present invention provides a co-packaged optical structure, which is prepared by the method for preparing a co-packaged optical structure as described in any of the foregoing embodiments, wherein the co-packaged optical structure comprises: A substrate with a conductive pillar running through it, one end of which is exposed on the front side of the substrate and the other end protruding on the back side of the substrate; An interposer layer has a receiving groove on its front side, and the front side of the interposer layer is also covered with an insulating film. The insulating film extends to the inner wall of the receiving groove. The front side of the interposer layer is attached to the back side of the substrate. The conductive pillar is correspondingly received in the receiving groove. The insulating film also covers the end sidewall of the conductive pillar. A first wiring layer is disposed on the back side of the intermediate layer and is electrically connected to the conductive pillars. A second wiring layer is disposed on the front side of the substrate and is electrically connected to the conductive pillars. Multiple heterogeneous chips are disposed on the second wiring layer.

[0020] Thirdly, the present invention provides a co-packaged optical structure, which is prepared by the method for preparing a co-packaged optical structure as described in any of the foregoing embodiments, wherein the co-packaged optical structure comprises: A substrate with a conductive pillar running through it, one end of which is exposed on the front side of the substrate and the other end protruding on the back side of the substrate; An interposer layer has a receiving groove on its front side, and the front side of the interposer layer is also covered with an insulating film. The insulating film extends to the inner wall of the receiving groove. The front side of the interposer layer is attached to the back side of the substrate. The conductive pillar is correspondingly received in the receiving groove. The insulating film also covers the end sidewall of the conductive pillar. A first wiring layer is disposed on the back side of the intermediate layer and is electrically connected to the conductive pillars. A second wiring layer is disposed on the front side of the substrate and is electrically connected to the conductive pillars. Multiple heterogeneous chips and optical modules are disposed on the second rewiring layer.

[0021] In an optional embodiment, a molding compound is further disposed on the second redistribution layer, the molding compound covering the plurality of heterogeneous chips and the optical module, and the edge of the molding compound is flush with the edge of the substrate.

[0022] Fourthly, embodiments of the present invention provide a co-packaged optical structure, which is fabricated using the aforementioned method for fabricating a co-packaged optical structure, the co-packaged optical structure comprising: A substrate with a conductive pillar running through it, one end of which is exposed on the front side of the substrate and the other end protruding on the back side of the substrate; An insulating film is disposed on the substrate and extends to the periphery of the conductive pillar; The first wiring layer is disposed on the insulating film and electrically connected to the conductive pillar; A second wiring layer is disposed on the front side of the substrate and is electrically connected to the conductive pillars. Multiple heterogeneous chips and optical modules are disposed on the second rewiring layer.

[0023] The beneficial effects of the embodiments of the present invention include: The method for fabricating a co-packaged optical structure and the co-packaged optical structure provided in this embodiment of the invention first involves setting conductive pillars in a substrate, with one end of each pillar exposed on the front side of the substrate. Then, the front side of the substrate is attached to a first carrier, and the back side of the substrate is thinned to expose the ends of the conductive pillars, making the ends of the conductive pillars protrude from the back side of the substrate. Next, the front side of a pre-prepared interposer is attached to the back side of the substrate, with the conductive pillars correspondingly housed in receiving grooves provided on the interposer. The front side of the interposer is also covered with an insulating film extending to the inner wall of the receiving grooves. This insulating film can cover the ends of the conductive pillars. Simultaneously, a repair metal layer can be pre-set in the receiving grooves corresponding to the missing conductive pillars. After the interposer is attached to the substrate, the repair metal layer can be soldered to the missing conductive pillars to repair them. Then, a first multi-wiring layer is formed on the back side of the interposer, and a second multi-wiring layer is formed on the front side of the substrate after removing the first carrier. Finally, the heterogeneous chip and optical module are mounted.

[0024] Compared with the prior art, the method for fabricating a co-encapsulated optical structure provided in this invention repairs the damaged conductive pillars by accommodating the repair metal layer in the groove, and protects the conductive pillars by the interlayer and insulating film. This effectively reduces the risk of conductive pillar breakage, delamination or interface layer delamination, and ensures the electrical performance and transmission efficiency of the entire encapsulation structure. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating the steps of a method for fabricating a co-encapsulated optical structure according to the first embodiment of the present invention. Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 5 This is a schematic diagram of step S3 in another method for preparing a co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 6 This is a schematic diagram of the structure corresponding to step S4 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 7 This is a schematic diagram of the structure corresponding to step S5 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention; Figure 8 This is a schematic diagram of step S5 in another method for preparing a co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 9 This is a schematic diagram of the structure corresponding to step S6 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 10 This is a schematic diagram of the structure corresponding to step S7 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 11This is a schematic diagram of the structure corresponding to step S8 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 12 This is a schematic diagram of the structure corresponding to step S9 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention; Figure 13 This is a schematic diagram of the structure corresponding to step S10 in the method for preparing the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 14 This is a schematic diagram of the structure corresponding to step S11 in the preparation method of the co-encapsulated optical structure provided in the first embodiment of the present invention. Figure 15 This is a schematic diagram of the common packaging optical structure provided in the first embodiment of the present invention; Figure 16 This is a schematic diagram of the CPO packaging component provided in the first embodiment of the present invention; Figure 17 A schematic diagram of another CPO packaging component provided in the first embodiment of the present invention; Figure 18 This is a schematic diagram of the structure corresponding to step S4 in the method for preparing the co-encapsulated optical structure provided in the second embodiment of the present invention; Figure 19 This is a schematic diagram of the structure corresponding to steps S5 and S6 in the method for preparing the co-encapsulated optical structure provided in the third embodiment of the present invention. Figure 20 This is a schematic diagram of the common packaging optical structure provided in the third embodiment of the present invention.

[0027] Icons: 100 - Common package optical structure; 110 - Substrate; 111 - Conductive pillar; 112 - Stepped annular groove; 113 - Edge protrusion ring; 120 - Intermediate layer; 121 - Insulating film; 122 - Receiving groove; 123 - Repair metal layer; 124 - Metal pad; 125 - Edge annular groove; 126 - Photoresist layer; 130 - First redistribution layer; 140 - Second redistribution layer; 150 - Optical module; 160 - Molding layer; 170 - Heterogeneous chip; 171 - First chip; 172 - Second chip; 173 - Third chip; 200a - First carrier; 200b - Second carrier; 300 - CPO package assembly; 310 - Substrate; 320 - Fiber optic module; 330 - Metal ring. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0031] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0032] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0033] In conventional CPO packaging technology, a silicon interposer is typically used. During actual fabrication, electroplated metal pillars are formed within the silicon interposer to achieve vertical interconnects. To achieve double-sided conductivity, an exposed copper process is usually required to expose the end faces of the copper pillars. This involves using chemical polishing to expose the metal pillars inside the interposer (interposer) before wiring. However, during polishing, the metal pillars are easily subjected to direct physical contact with the polishing pad, generating corresponding shear stress, tensile stress, and / or compressive stress. This can lead to problems such as metal pillar breakage, delamination, or interface layer delamination. The breakage or damage of the metal pillars will affect the transmission efficiency of the subsequent optical engine chip, thus affecting the electrical performance of the entire CPO packaging structure, and even rendering the packaging structure unusable.

[0034] To address the aforementioned issues, embodiments of the present invention provide a method for preparing a co-encapsulated optical structure and a co-encapsulated optical structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0035] First Embodiment This invention provides a method for preparing a co-encapsulated optical structure 100, which can effectively reduce the risk of breakage, delamination or interface layer delamination of the conductive pillar 111, repair damaged conductive pillars 111, and ensure the electrical performance and transmission efficiency of the entire encapsulation structure.

[0036] See Figure 1 The present invention provides a method for fabricating a co-packaged optical structure 100, which includes the following steps: S1: Provide a substrate 110.

[0037] See also Figure 2 The substrate 110 contains conductive pillars 111, one end of which is exposed on the front side of the substrate 110, while the other end is spaced apart from the back side of the substrate 110. Specifically, a substrate 110 is first selected. This substrate 110 can be made of silicon-based or germanium-based materials, such as silicon oxide, phosphosilicate glass, fluorinated glass, or glass. The thickness of the substrate 110 is 600-1500 micrometers. Then, dry etching is performed, and the etching gas can be carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), hydrogen (H2), etc., or a chemical etching method can be used, and the etching solution can be a mixture of hydrofluoric acid (HF), buffered oxide etching solution, sulfuric acid (H2SO4), and hydrogen peroxide (H2O2), etc. Conductive vias are formed on the front side of substrate 110 by etching. The depth of the vias is selected according to the process and needs to be less than the minimum thickness of substrate 110. Then, the substrate 110 is plated or the cavity is plated into the plating solution by electroplating to form conductive pillars 111.

[0038] Furthermore, before attaching the substrate 110 to the first carrier 200a, a stepped annular groove 112 can be cut to form the edge of the substrate 110. Specifically, the stepped annular groove 112 is formed by cutting the edge of the substrate 110 using an annular cutting process. By setting the stepped annular groove 112, the colloid can be prevented from crawling to the surface of the substrate 110 and contaminating the substrate 110 and the conductive pillar 111.

[0039] S2: Attach the front side of the substrate 110 to the first carrier 200a.

[0040] See also Figure 3Specifically, a carrier can be used, the first carrier 200a can be made of materials such as metal or glass, and then the front side of the substrate 110 is fixedly attached to the first carrier 200a using a bonding adhesive layer. The bonding adhesive layer is a temporary bonding adhesive, which can be debonded using UV light or laser. The temporary bonding adhesive layer can be composed of self-crosslinking resins such as water-based acrylic emulsion or water-based styrene-acrylic emulsion.

[0041] S3: Thin the back side of the substrate 110 and expose the end of the conductive post 111 so that the conductive post 111 protrudes from the back side of the substrate 110.

[0042] See also Figure 4 Specifically, after the substrate 110 is mounted, the back side of the substrate 110 can be first ground using a polishing process to thin the substrate 110 and expose the end faces of the conductive pillars 111. Then, the back side of the substrate 110 is micro-etched to expose the ends of the conductive pillars 111, so that the conductive pillars 111 protrude from the back side of the substrate 110. The back side of the substrate 110 can be further thinned using dry etching or chemical etching, and the conductive pillars 111 in the substrate 110 can be micro-etched to expose the ends (heads) of the conductive pillars 111, with the exposed end height between 2-30 μm.

[0043] See Figure 5 In other preferred embodiments of the present invention, in the step of micro-etching the back side of the substrate 110 to expose the ends of the conductive pillars 111, the middle of the back side of the substrate 110 is first micro-etched using a micro-etching process to expose the ends of the conductive pillars 111, so that the conductive pillars 111 protrude from the back side of the substrate 110. Then, the edge of the back side of the substrate 110 is micro-etched to form an edge protrusion ring 113 at the edge of the substrate 110. The provision of this edge protrusion ring 113 can significantly improve the adhesion of the subsequent interposer layer 120.

[0044] S4: Provide an interlayer 120 covered with an insulating film 121.

[0045] See Figure 6 The front side of the intermediate layer 120 is provided with a receiving groove 122 for corresponding to the receiving post 111. An insulating film 121 covers the front side of the intermediate layer 120 and extends to the inner wall of the receiving groove 122. A repair metal layer 123 is provided in the receiving groove 122 corresponding to the damaged conductive post 111.

[0046] In the actual fabrication of the interposer 120, an interposer 120 can be provided first. The material of the interposer 120 can be silicon-based or germanium-based, such as phosphosilicate glass, fluorinated glass, or glass. Alternatively, the interposer 120 can be an ABF film or a prepreg made of polyimide. Then, a receiving groove 122 is formed on the front side of the interposer 120. Specifically, dry etching or chemical etching can be used to form the receiving groove 122 on the front side of the interposer 120. Next, an insulating film 121 is deposited on the front side of the interposer 120. For example, it can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The insulating film 121 extends to cover the sidewalls and bottom wall of the receiving groove 122. Furthermore, the material of the insulating film 121 can be silicon dioxide, silicon nitride, silicon oxynitride, etc. Finally, a repair metal layer 123 is formed in the receiving groove 122 corresponding to the damaged conductive post 111 using a coating process (sputtering, electroless plating, electroplating). The repair metal layer 123 can be at least one of copper, titanium, and gold.

[0047] It should be noted that the receiving grooves 122 on the interposer layer 120 can be located by the pattern of the conductive pillars 111 on the substrate 110, ensuring that the distribution of the receiving grooves 122 corresponds one-to-one with the conductive pillars 111.

[0048] Furthermore, when setting the repair metal layer 123 in the receiving groove 122 corresponding to the defective conductive post 111, the substrate 110 after step S2 can be scanned and inspected first to detect the conductive posts 111 and mark the defective conductive posts 111 (the defective conductive posts 111 may be damaged or broken during the grinding process). Then, the repair metal layer 123 is electroplated in the receiving groove 122 corresponding to the defective conductive post 111, wherein the repair metal layer 123 is used to weld the defective conductive post 111. Preferably, both the conductive post 111 and the repair metal layer 123 can be copper.

[0049] In some other preferred embodiments, when a defective conductive post 111 is detected, the end of the defective conductive post 111 can be removed using a laser to ensure the accuracy of the repair.

[0050] S5: The front side of the interposer 120 is attached to the back side of the substrate 110.

[0051] See also Figure 7The conductive post 111 is housed in the receiving groove 122, and the repair metal layer 123 is welded to the damaged conductive post 111. Specifically, after the intermediate layer 120 is attached, the repair metal layer 123 can be welded to the conductive post 111 using a copper-copper welding process, thereby repairing the exposed copper conductive post 111. Of course, a hybrid bonding process can also be used here, so that while the repair metal layer 123 is welded to the conductive post 111, the intermediate layer 120 is also bonded to the back side of the substrate 110.

[0052] See also Figure 8 It should be noted that, in other preferred embodiments of the present invention, when an edge protrusion 113 is formed at the edge of the substrate 110, an edge annular groove 125 corresponding to the edge protrusion 113 is also provided on the interposer layer 120. The cooperative arrangement of the edge protrusion 113 and the edge annular groove 125 can significantly improve the bonding force between the interposer layer 120 and the substrate 110.

[0053] S6: Thin the back side of the interposer 120 and expose the end face of the conductive post 111.

[0054] See also Figure 9 Specifically, a grinding process can be used again, in which a grinding slurry (ammonia, HF, citric acid, etc.) is used to grind the back side of the intermediate layer 120 under the action of centrifugal force and the transmission of the grinding pad until the end face of the conductive post 111 in the intermediate layer 120 is exposed. During the grinding process, the intermediate layer 120 acts as a protective layer, preventing the insulating film 121 from cracking due to grinding pressure. Since the insulating film 121 covers the ends of the conductive posts 111, it also provides sidewall protection, effectively preventing further breakage or damage to the conductive posts 111. Similarly, the intermediate layer 120 also protects the conductive posts 111. Without the intermediate layer 120, the conductive posts 111 would be damaged. Figure 9 If the resulting structure undergoes a planarization process, pressure may concentrate on the protruding portions of the conductive pillars 111, and therefore, these protruding portions may crack. Cracks in the conductive material can cause various defects within the semiconductor chip. Intermediate layer 120 can prevent this pressure concentration.

[0055] S7: A first redistribution layer 130 is formed on the back side of the intermediary layer 120.

[0056] See Figure 10The first wiring layer 130 is electrically connected to the conductive pillars 111. Specifically, a dielectric material can be first formed on the back side of the interposer 120 using a spin coating process, then an image aperture layer can be formed using an exposure and development process, followed by an electroplating process to form a metal layer, thus forming a wiring layer. Then, another dielectric material is formed, and a seed layer is formed after exposure and aperture formation. Finally, solder balls are formed using a ball-planting process or electroplating. The solder ball material can be SnAg, SnAgCu, Sn-Bi, or Sn-Ag-Cu, etc. During the fabrication of the first wiring layer 130, the interposer 120 can mitigate thermal and mechanical stresses during the process, acting as a buffer to protect the insulating film.

[0057] It should be noted that the first rewiring layer 130 here can also use metal pads. The metal pads serve as electrical connection pads, realizing the electrical connection of the conductive pillars 111, and at the same time facilitating the formation of solder balls to achieve external electrical connections. Of course, in other preferred embodiments of the present invention, the first rewiring layer 130 can also be a multi-layer rewiring structure.

[0058] S8: Remove the first carrier 200a and expose the front side of the substrate 110.

[0059] See Figure 11 Specifically, the first carrier 200a can be removed by debonding (e.g., by irradiating with UV light) to expose the front side of the substrate 110. Then, a second carrier 200b can be taken and the first redistribution layer 130 can be attached to the second carrier 200b using temporary bonding adhesive.

[0060] S9: A second redistribution layer 140 is formed on the front side of the substrate 110.

[0061] See Figure 12 The second wiring layer 140 is electrically connected to the conductive pillars 111. Specifically, its preparation process is similar to that of the first wiring layer 130. First, a dielectric material can be formed on the back side of the intermediate layer 120 using a spin coating process. Then, an image opening layer can be formed using an exposure and development process. Next, a metal layer can be formed using an electroplating process to form a wiring layer. Then, a dielectric material can be formed again, and a seed layer can be formed after exposure and opening. Finally, solder balls can be formed using a ball-planting process or an electroplating process. The solder ball material can be SnAg, SnAgCu, Sn-Bi, or Sn-Ag-Cu, etc.

[0062] It should be noted that the second wiring layer 140 can also use metal pads. The metal pads serve as electrical connection pads, realizing the electrical connection of the conductive pillars 111 and facilitating external electrical connections. Of course, in other preferred embodiments of the present invention, the second wiring layer 140 can also be a multi-layer rewiring structure.

[0063] S10: Multiple heterogeneous chips 170 and optical modules 150 are mounted on the second wiring layer 140.

[0064] See Figure 13 Specifically, the first chip 171, the second chip 172, the third chip 173 and the optical module 150 can be mounted on the second redistribution layer 140 again using a hot-press soldering process or a flip-chip process. Then, adhesive is applied to the bottom of the first chip 171, the second chip 172, the third chip 173 and the optical module 150 to form a first adhesive layer, a second adhesive layer, a third adhesive layer and a fourth adhesive layer, respectively.

[0065] The first chip 171 can be high-bandwidth memory (HBM), DRAM, HBF (High-bandwidth Flash) flash memory, DDR random access memory, etc.; the second chip 172 can be a central processing unit (CPU) die, a graphics processing unit (GPU) die, etc.; and the third chip 173 can be a system-on-a-chip (SoC) or system-on-a-chip (SoIC) die, an application processor (AP) die, a MEMS die, etc. The optical module 150 can be a photonic engine chip, whose photonic integrated circuit design utilizes the unique properties of light to provide advantages such as high bandwidth, low power consumption, and faster data transmission speeds compared to its electronic counterpart. The photonic engine chip includes components such as waveguides, couplers, lasers, light-emitting diodes (or other coherent light sources), modulators, detectors, and other optical components (such as mirrors and reflectors), photonic chips (PIC), electronic chips (EIC), etc.

[0066] S11: A molding layer 160 is formed on the second redistribution layer 140.

[0067] See Figure 14The molding compound 160 encapsulates multiple heterogeneous chips 170 and optical modules 150, and is thinned through a grinding process to expose the optical port structure of the optical modules 150. At this point, a stepped structure can be formed in the stepped annular groove 112 region at the edge of the interposer 120. The molding compound 160 encapsulates the stepped structure formed at the edge of the substrate 110, which can improve the bonding force between the molding compound 160 and the interposer 120, thereby avoiding delamination caused by uneven stress between the molding compound 160 and the interposer 120 during the thinning process. Then, the molding compound 160 can be circumferentially cut along the edge of the substrate 110, for example using a laser circumferential cutting process, to remove the molding compound 160 and the protective ring at the edge of the interposer 120, making the edge of the molding compound 160 flush with the edge of the substrate 110, avoiding microcracks or delamination of the insulating film caused by the cutting tool pulling. Finally, after removing the second carrier 200b through a debonding process, it is cut into individual products along the cutting path using a cutting process (mechanical cutting or laser cutting), completing the process.

[0068] See Figure 15 This invention also provides a co-packaged optical structure 100, which is fabricated using the aforementioned method. The co-packaged optical structure 100 includes a substrate 110, an interposer 120, a first redistribution layer 130, a second redistribution layer 140, an optical module 150, a molding compound 160, and multiple heterogeneous chips 170. A conductive post 111 is disposed through the interior of the substrate 110, with one end of the conductive post 111 exposed on the front side of the substrate 110 and the other end protruding on the back side of the substrate 110. The interposer 120 has a receiving groove 122 on its front side, and an insulating film 121 is also covered on the front side of the interposer 120, extending to the inner wall of the receiving groove 122. The front side of the interposer 120 is attached to the back side of the substrate 110, and the conductive post 111 is correspondingly accommodated in the receiving groove 122. The insulating film 121 also covers the end sidewalls of the conductive post 111. A first wiring layer 130 is disposed on the back side of the interposer 120 and electrically connected to the conductive pillars 111. A second wiring layer 140 is disposed on the front side of the substrate 110 and electrically connected to the conductive pillars 111. Multiple heterogeneous chips 170 and optical modules 150 are disposed on and electrically connected to the second wiring layer 140. A molding compound 160 is disposed on the second wiring layer 140 and covers the multiple heterogeneous chips 170 and optical modules 150, wherein the edge of the molding compound 160 is flush with the edge of the substrate 110.

[0069] Of course, in other preferred embodiments of the present invention, only a plurality of heterogeneous chips 170 may be provided on the second wiring layer 140.

[0070] Furthermore, the multiple heterogeneous chips 170 include a first chip 171, a second chip 172, a third chip 173, and an optical module 150, and the bottoms of the first chip 171, the second chip 172, the third chip 173, and the optical module 150 are respectively coated with adhesive to form a first adhesive layer, a second adhesive layer, a third adhesive layer, and a fourth adhesive layer. The first chip 171 may be high-bandwidth memory (HBM), DRAM, HBF (High Bandwidth Flash), DDR, etc.; the second chip 172 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, etc.; the third chip 173 may be a system-on-a-chip (SoC) or integrated chip system (SoIC) die, an application processor (AP) die, a MEMS die, etc. The optical module 150 can be a photonic engine chip, whose photonic integrated circuit is designed to utilize the unique properties of light, offering advantages such as high bandwidth, low power consumption, and faster data transmission speeds compared to its electronic counterpart. The photonic engine chip includes components such as waveguides, couplers, lasers, light-emitting diodes (or other coherent light sources), modulators, detectors, and other optical components (such as mirrors and reflectors), photonic chips (PIC), and electronic chips (EIC).

[0071] In this embodiment, the optical module 150 includes a stacked PIC chip and an EIC chip, wherein the EIC chip is stacked on top of the PIC chip, and the PIC chip is flip-chip mounted and soldered onto the second redistribution layer 140. Furthermore, the optical areas of the EIC chip and the PIC chip are staggered. A transparent adhesive layer is also provided on the back of the PIC chip, and a lens is provided on the top side of the transparent adhesive layer, corresponding to the optical area of ​​the PIC chip, forming an optical port structure.

[0072] See Figure 16Furthermore, this embodiment of the invention also provides a CPO packaging assembly 300, which includes a substrate 310, an optical fiber module 320, and the aforementioned common packaging optical structure 100. Solder balls on the first redistribution layer 130 of the common packaging optical structure 100 are correspondingly soldered and fixed to the pads of the substrate 310 for fixation and electrical connection. A metal ring 330 is provided at the edge of the substrate 310, and the optical fiber module 320 is disposed on the metal ring 330, close to the optical module 150, and overlaps the optical port structure to achieve optical signal transmission. Specifically, the optical fiber module 320 can overlap the top side of the transparent adhesive layer and cover the lens. Direct contact between the transparent adhesive layer and the optical fiber module 320 can bond and fix the optical fiber module 320, improving structural stability. The metal ring 330 provides support and also improves heat dissipation.

[0073] It should be noted that the fiber optic module 320 here may include a fiber optic array unit (FAU), which can realize the output or input of the optical path channel and achieve low-loss, high-precision, batch coupling and alignment between optical fibers and optical chips, waveguides, and optical devices.

[0074] See Figure 17 In other preferred embodiments of the present invention, the optical module 150 can also be disposed separately on the substrate 310. Specifically, a metal ring 330 is disposed on the substrate 310, and the optical module 150 is disposed on the outer side of the metal ring 330. An optical fiber module 320 is bonded and fixed to the optical module 150. The metal ring 330 here can play a role in preventing warping and heat dissipation.

[0075] In summary, this invention provides a method for fabricating a co-packaged optical structure 100 and the co-packaged optical structure 100 itself. First, conductive pillars 111 are formed in a substrate 110, with one end of each pillar exposed on the front side of the substrate 110. Then, the front side of the substrate 110 is attached to a first carrier 200a, and the back side of the substrate 110 is thinned to expose the end of the conductive pillar 111, making the end of the conductive pillar 111 protrude from the back side of the substrate 110. Next, the front side of a pre-prepared interposer 120 is attached to the back side of the substrate 110, with the conductive pillars 111 correspondingly accommodated in receiving grooves 122 formed on the interposer 120. The front side of the interposer 120 is also covered with an insulating film 121 extending to the inner wall of the receiving groove 122. This insulating film 121 can cover the end of the conductive pillar 111. Simultaneously, a repair metal layer 123 can be pre-formed in the receiving groove 122 corresponding to the damaged conductive post 111. After the interposer 120 is bonded to the substrate 110, the repair metal layer 123 can be correspondingly soldered to the damaged conductive post 111, thereby repairing the damaged conductive post 111. Then, a first redistribution layer 130 is formed on the back side of the interposer 120, and a second redistribution layer 140 is formed on the front side of the substrate 110 after removing the first carrier 200a. Finally, the heterogeneous chip 170 and the optical module 150 are mounted. Compared with the prior art, the method for fabricating the co-packaged optical structure 100 provided in this embodiment of the invention repairs the damaged conductive post 111 through the repair metal layer 123 in the receiving groove 122, and protects the conductive post 111 with the interposer 120 and the insulating film 121, which can effectively reduce the risk of the conductive post 111 breaking, delaminating, or delaminating the interface layer, and ensure the electrical performance and transmission efficiency of the entire packaging structure.

[0076] Second Embodiment This invention provides a method for preparing a co-encapsulated optical structure 100. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0077] In this embodiment, the difference from the first embodiment lies in the fabrication of the interposer layer 120. The fabrication method provided in this embodiment includes the following steps: S1: Provide a substrate 110.

[0078] S2: Attach the front side of the substrate 110 to the first carrier 200a.

[0079] S3: Thin the back side of the substrate 110 and expose the end of the conductive post 111 so that the conductive post 111 protrudes from the back side of the substrate 110.

[0080] S4: Provide an interlayer 120 covered with an insulating film 121.

[0081] See Figure 18 In the actual fabrication of the interposer 120, an interposer 120 can be provided first. The material of the interposer 120 can be silicon-based or germanium-based, such as silicon oxide, phosphosilicate glass, fluorinated glass, or glass. Alternatively, the interposer 120 can be an ABF film or a prepreg made of polyimide. Then, a photoresist layer 126 is formed on the back side of the interposer 120. Grooves are then formed on the photoresist layer 126 and electroplated to form metal pads 124. The metal pads 124 can be a seed layer UBM, which can be at least one of copper, titanium, or gold. Next, grooves are formed on the front side of the interposer 120 to form receiving grooves 122, which expose the metal pads 124. Specifically, dry etching or chemical etching can be used to form the receiving grooves 122 on the front side of the interposer 120. Finally, an insulating film 121 is deposited on the front side of the interposer 120, extending to cover the sidewalls of the receiving grooves 122 and exposing the metal pads 124. Then, a repair metal layer 123 is placed in the receiving groove 122 corresponding to the defective conductive post 111, and finally the photoresist layer 126 is removed.

[0082] S5: The front side of the interposer 120 is attached to the back side of the substrate 110.

[0083] S6: A first redistribution layer 130 is formed on the back side of the intermediary layer 120.

[0084] Since the metal pads 124 have already been prepared and exposed on the back side of the interposer layer 120, unlike the first embodiment, there is no need to grind again to expose the conductive pillars 111. During the formation of the first super-wiring layer 130, the metal pads 124 can serve as wiring metal, thus simplifying the preparation steps of the first super-wiring layer 130. By setting the metal pads 124, the alignment between the metal pads 124 and the conductive pillars 111 can be improved compared to the first embodiment. Furthermore, the interposer layer 120 can be prepared and sold as a separate module, thus adapting to standard pin mounting (of course, for non-standard products, the pad positions only need to be redistributed).

[0085] Subsequent steps can refer to steps S8 to S11 in the first embodiment.

[0086] It is worth noting that the metal pads 124 are pre-fabricated on the interposer layer 120, which enables precise alignment between the metal pads 124 and the conductive posts 111, thereby avoiding the problem of inaccurate alignment between the wiring metal and the conductive posts 111 during the routing process. At the same time, the interposer layer 120 acts as a support, allowing for separate routing on both sides, which effectively reduces the number of routing layers and thus effectively mitigates warping.

[0087] Third Embodiment This invention provides a method for preparing a co-encapsulated optical structure 100. Its basic steps, principles, and resulting technical effects are the same as those in the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0088] S1: Provide a substrate 110.

[0089] S2: Attach the front side of the substrate 110 to the first carrier 200a.

[0090] S3: Thin the back side of the substrate 110 and expose the end of the conductive post 111 so that the conductive post 111 protrudes from the back side of the substrate 110.

[0091] S4: Provide an interlayer 120 covered with an insulating film 121.

[0092] S5: The front side of the interposer 120 is attached to the back side of the substrate 110.

[0093] S6: Thin out and remove the interlayer 120 until the surface of the insulating film 121 is exposed.

[0094] See also Figure 19 Specifically, a grinding process can be used, in which a grinding slurry (ammonia, HF, citric acid, etc.) is used to grind the back side of the intermediate layer 120 under the action of centrifugal force and the transmission of the grinding pad until the intermediate layer 120 is completely removed, exposing the surface of the insulating film 121. During the grinding process, the intermediate layer 120 acts as a protective layer, preventing the insulating film from cracking due to grinding pressure. Since the insulating film covers the ends of the conductive posts 111, it also provides sidewall protection, effectively preventing further breakage or damage to the conductive posts 111. The intermediate layer 120 also protects the conductive posts 111; without the intermediate layer 120, further damage would occur. Figure 9 If the resulting structure undergoes a planarization process, pressure may concentrate on the protruding portions of the conductive pillars 111, and therefore, these protruding portions may crack. Cracks in the conductive material can cause various defects within the semiconductor chip. Intermediate layer 120 can prevent this pressure concentration.

[0095] It should be noted that by completely removing the interposer layer 120, the package height and package size can be effectively reduced.

[0096] S8: Remove the first carrier 200a and expose the front side of the substrate 110.

[0097] S9: A second redistribution layer 140 is formed on the front side of the substrate 110.

[0098] S10: Multiple heterogeneous chips 170 and optical modules 150 are mounted on the second wiring layer 140.

[0099] S11: A molding layer 160 is formed on the second redistribution layer 140.

[0100] See Figure 20 This invention also provides a co-packaged optical structure 100, which is fabricated using the aforementioned method. The co-packaged optical structure 100 includes a substrate 110, an insulating film 121, a first redistribution layer 130, a second redistribution layer 140, an optical module 150, a molding compound 160, and multiple heterogeneous chips 170. A conductive post 111 is disposed through the interior of the substrate 110, with one end of the conductive post 111 exposed on the front side of the substrate 110 and the other end protruding from the back side of the substrate 110. The insulating film 121 is disposed on the substrate 110 and extends to the periphery of the conductive post 111. The first redistribution layer 130 is disposed on the insulating film 121 and electrically connected to the conductive post 111. The second redistribution layer 140 is disposed on the front side of the substrate 110 and electrically connected to the conductive post 111. Multiple heterogeneous chips 170 and the optical module 150 are all disposed on the second redistribution layer 140 and electrically connected to it. A molding layer 160 is disposed on the second redistribution layer 140 and covers multiple heterogeneous chips 170 and optical modules 150, wherein the edge of the molding layer 160 is flush with the edge of the substrate 110.

[0101] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a co-encapsulated optical structure, characterized in that, include: A substrate is provided, wherein a conductive pillar is disposed in the substrate, one end of the conductive pillar is exposed on the front side of the substrate, and the other end is spaced apart from the back side of the substrate; The front side of the substrate is attached to the first carrier; Thin the back side of the substrate and expose the end of the conductive pillar so that the conductive pillar protrudes from the back side of the substrate; An intermediate layer covered with an insulating film is provided, wherein conductive posts are detected and marked as defective conductive posts. The front side of the intermediate layer is provided with a receiving groove for correspondingly accommodating the conductive posts. The insulating film covers the front side of the intermediate layer and extends to the inner wall of the receiving groove. A repair metal layer is provided in the receiving groove corresponding to the defective conductive post. The front side of the interposer is attached to the back side of the substrate, wherein the conductive post is correspondingly accommodated in the receiving groove, and the repair metal layer is correspondingly soldered to the defective conductive post; A first redistribution layer is formed on the back side of the interposer or on the surface of the insulating film away from the substrate, wherein the first redistribution layer is electrically connected to the conductive pillar; Remove the first carrier and expose the front side of the substrate; A second redistribution layer is formed on the front side of the substrate, wherein the second redistribution layer is electrically connected to the conductive pillars; Multiple heterogeneous chips and optical modules are mounted on the second wiring layer.

2. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of providing an interlayer covered with an insulating film includes: Provide an intermediary layer; A receiving groove is formed by slotting the front side of the intermediate layer; An insulating film is deposited on the front side of the intermediate layer, wherein the insulating film extends to cover the sidewalls and bottom wall of the receiving groove; A repair metal layer is provided in the receiving groove corresponding to the damaged conductive post.

3. The method for fabricating the co-encapsulated optical structure according to claim 2, characterized in that, The step of setting a repair metal layer in the receiving groove corresponding to the damaged conductive post includes: The conductive posts are inspected, and any damaged conductive posts are marked. A repair metal layer is electroplated in the receiving groove corresponding to the defective conductive post to form a repair metal layer, wherein the repair metal layer is used to weld the defective conductive post.

4. The method for fabricating the co-encapsulated optical structure according to claim 3, characterized in that, After the steps of detecting the conductive post and marking the defective conductive post, the method further includes: Laser removal of the damaged end of the conductive post.

5. The method for fabricating the co-encapsulated optical structure according to claim 2, characterized in that, Prior to the step of forming a first redistribution layer on the back side of the interposer layer, the method further includes: Thin the back side of the interposer to expose the end face of the conductive post.

6. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of providing an interlayer covered with an insulating film includes: Provide an intermediary layer; A photoresist layer is formed on the back side of the interposer layer; Grooves are cut into the photoresist layer and electroplated to form metal pads; A receiving groove is formed by slotting the front side of the interposer layer, wherein the receiving groove corresponds to exposing the metal pad; An insulating film is deposited on the front side of the interposer layer, wherein the insulating film extends to cover the sidewalls of the receiving groove and exposes the metal pads; A repair metal layer is provided in the receiving groove corresponding to the damaged conductive post; Remove the photoresist layer.

7. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of thinning the back side of the substrate and exposing the ends of the conductive pillars includes: The back side of the substrate is ground to expose the end face of the conductive pillar; The back side of the substrate is micro-etched to expose the ends of the conductive pillars, so that the conductive pillars protrude from the back side of the substrate.

8. The method for fabricating the co-encapsulated optical structure according to claim 7, characterized in that, The step of micro-etching the back side of the substrate to expose the ends of the conductive pillars includes: The back side of the substrate is micro-etched to expose the end of the conductive pillar, so that the conductive pillar protrudes from the back side of the substrate; The back edge of the substrate is micro-etched, and an edge protrusion ring is formed at the edge of the substrate; The intermediate layer is further provided with an edge ring groove corresponding to the edge protrusion ring.

9. The method for fabricating the co-encapsulated optical structure according to claim 1 or 8, characterized in that, Prior to the step of attaching the front side of the substrate to the first carrier, the method further includes: Stepped annular grooves are formed by cutting along the edge of the substrate.

10. The method for fabricating the co-encapsulated optical structure according to claim 9, characterized in that, After the step of mounting multiple heterogeneous chips and optical modules on the second redistribution layer, the method further includes: A molding layer is formed on the second redistribution layer, wherein the molding layer encapsulates the plurality of heterogeneous chips and the optical module; The molding layer is circumferentially cut along the edge of the substrate so that the edge of the molding layer is flush with the edge of the substrate.

11. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, The step of mounting multiple heterogeneous chips and optical modules on the second redistribution layer includes: The first chip, the second chip, the third chip, and the optical module are mounted on the second redistribution layer; A first adhesive layer, a second adhesive layer, a third adhesive layer, and a fourth adhesive layer are formed by applying adhesive to the bottom of the first chip, the second chip, the third chip, and the optical module, respectively.

12. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, Prior to the step of forming a second redistribution layer on the front side of the substrate, the method further includes: The first rewiring layer is attached to the second vehicle.

13. The method for fabricating the co-encapsulated optical structure according to claim 1, characterized in that, Prior to the step of forming a first redistribution layer on the surface of the insulating film away from the substrate, the method includes: Thin out and remove the intermediate layer until the surface of the insulating film is exposed.

14. A co-encapsulated optical structure, fabricated using the method for fabricating a co-encapsulated optical structure as described in any one of claims 1-13, characterized in that, The common packaging optical structure includes: A substrate with a conductive pillar running through it, one end of which is exposed on the front side of the substrate and the other end protruding on the back side of the substrate; An interposer layer has a receiving groove on its front side, and the front side of the interposer layer is also covered with an insulating film. The insulating film extends to the inner wall of the receiving groove. The front side of the interposer layer is attached to the back side of the substrate. The conductive pillar is correspondingly received in the receiving groove. The insulating film also covers the end sidewall of the conductive pillar. A first wiring layer is disposed on the back side of the intermediate layer and is electrically connected to the conductive pillars. A second wiring layer is disposed on the front side of the substrate and is electrically connected to the conductive pillars. Multiple heterogeneous chips are disposed on the second wiring layer.

15. A co-packaged optical structure, fabricated using the method for fabricating a co-packaged optical structure as described in any one of claims 1-13, characterized in that, The common packaging optical structure includes: A substrate with a conductive pillar running through it, one end of which is exposed on the front side of the substrate and the other end protruding on the back side of the substrate; An interposer layer has a receiving groove on its front side, and the front side of the interposer layer is also covered with an insulating film. The insulating film extends to the inner wall of the receiving groove. The front side of the interposer layer is attached to the back side of the substrate. The conductive pillar is correspondingly received in the receiving groove. The insulating film also covers the end sidewall of the conductive pillar. A first wiring layer is disposed on the back side of the intermediate layer and is electrically connected to the conductive pillars. A second wiring layer is disposed on the front side of the substrate and is electrically connected to the conductive pillars. Multiple heterogeneous chips and optical modules are disposed on the second rewiring layer.

16. The co-packaged optical structure according to claim 15, characterized in that, The second redistribution layer is further provided with a molding compound layer, which covers the plurality of heterogeneous chips and the optical module, and the edge of the molding compound layer is flush with the edge of the substrate.

17. A co-packaged optical structure, fabricated using the method for fabricating a co-packaged optical structure as described in any one of claims 1-13, characterized in that, The common packaging optical structure includes: A substrate with a conductive pillar running through it, one end of which is exposed on the front side of the substrate and the other end protruding on the back side of the substrate; An insulating film is disposed on the substrate and extends to the periphery of the conductive pillar; The first wiring layer is disposed on the insulating film and electrically connected to the conductive pillar; A second wiring layer is disposed on the front side of the substrate and is electrically connected to the conductive pillars. Multiple heterogeneous chips and optical modules are disposed on the second rewiring layer.

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