A low-stray inductance stacked silicon carbide power module package

Abstract

The application relates to the technical field of power semiconductor packaging, and provides a low-stray-inductance laminated silicon carbide power module package which comprises a heat-conducting bottom plate, a package shell and three single-phase bridge arm loop structures. Each single-phase bridge arm loop structure comprises a bottom layer, a middle layer and an upper layer of copper-clad ceramic substrate, a silicon carbide chip is arranged in an upper bridge arm area and a lower bridge arm area of the bottom layer of copper-clad ceramic substrate, a first upper layer of copper-clad ceramic substrate and a second upper layer of copper-clad ceramic substrate are connected with a front surface source electrode of the silicon carbide chip through a first copper block, the middle layer of copper-clad ceramic substrate of the upper bridge arm area is connected with the lower bridge arm area through a second copper block, and a third upper layer of copper-clad ceramic substrate is connected with a direct-current output area through a third copper block. The package is arranged through laminated rigid interconnection and parallel reverse current paths, stray inductance and voltage overshoot are reduced, and module operation reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor packaging technology, and more specifically, to a stacked silicon carbide power module package with low stray inductance. Background Technology

[0002] As silicon carbide power devices rapidly evolve towards higher frequencies and higher power densities, stacked packaging has become a key technological path to overcome the parasitic parameter bottlenecks of traditional planar layouts. However, although existing stacked structures compress the physical size of modules to some extent, the high-current commutation paths across layers within them often still rely on traditional wire bonding processes. This flexible interconnection method inherently suffers from high parasitic inductance, making it difficult to meet the stringent requirements for ultra-low stray inductance in SiC devices operating at extremely high di / dt conditions. Furthermore, under high current and high heat flux density conditions, its ultimate current-carrying capacity and thermomechanical reliability exhibit significant bottlenecks.

[0003] Meanwhile, most current stacked packaging solutions are merely simple three-dimensional stacking in physical space, lacking magnetic flux offsetting and cancellation designs for internal wiring from the perspective of electromagnetic field distribution. This results in a still relatively high stray inductance in the main commutation circuit of the module, which can easily cause severe turn-off voltage overshoot during high-speed switching transients. The high-frequency alternating magnetic field of this main power circuit, lacking effective spatial constraints, can easily penetrate the interlayer insulating medium, causing severe electromagnetic coupling and cross-interference with adjacent weak current drive circuits, leading to drive signal distortion, and even shoot-through failure or false conduction of bridge arm devices. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a stacked silicon carbide power module package with low stray inductance to solve the above problems.

[0005] The present invention adopts the following solution:

[0006] This application provides a low stray inductance stacked silicon carbide power module package, including a thermally conductive base plate and a package shell. The package shell is connected to the thermally conductive base plate and forms three loop regions. Each loop region is provided with a single-phase bridge arm loop structure. The single-phase bridge arm loop structure includes a bottom copper-clad ceramic substrate. The upper copper layer of the bottom copper-clad ceramic substrate forms an upper bridge arm region and a lower bridge arm region. Multiple silicon carbide chips are respectively connected to the upper bridge arm region and the lower bridge arm region, and multiple middle copper-clad ceramic substrates are respectively connected at intervals along a first direction. The middle copper-clad ceramic substrates placed in the upper bridge arm region... A first upper copper-clad ceramic substrate is connected to the substrate, and a second upper copper-clad ceramic substrate is connected to the middle copper-clad ceramic substrate located in the lower bridge arm region; the lower copper layers of the first and second upper copper-clad ceramic substrates are connected to the front source of the silicon carbide chip through a first copper block; the upper copper layer of the middle copper-clad ceramic substrate in the upper bridge arm region is connected to the upper copper layer of the bottom copper-clad ceramic substrate in the lower bridge arm region through a second copper block; the upper copper layer of the upper copper-clad ceramic substrate forms a driving circuit, which is connected to the gate and Kelvin source of the silicon carbide chip respectively through bonding wires.

[0007] Furthermore, a third upper copper-clad ceramic substrate is connected to the middle copper-clad ceramic substrate placed in the lower bridge arm region, and its lower copper layer is connected to the DC output area of ​​the upper copper layer of the bottom copper-clad ceramic substrate through a third copper block.

[0008] Furthermore, the DC output area and DC input area of ​​the upper copper layer of the bottom copper-clad ceramic substrate are arranged side by side on the same side and are respectively connected to DC output terminals and DC input terminals.

[0009] Furthermore, it also includes signal terminals, which include upper bridge gate signal terminals, upper bridge source signal terminals, upper bridge drain signal terminals, lower bridge gate signal terminals, lower bridge source signal terminals, and lower bridge drain signal terminals derived from the gate, source, and drain terminals of the silicon carbide chips corresponding to the upper and lower bridge arm regions; wherein the upper bridge gate signal terminals and the upper bridge source signal terminals are directly derived from the control pads on the front side of the silicon carbide chip; the upper bridge drain signal terminals, the lower bridge gate signal terminals, the lower bridge source signal terminals, and the lower bridge drain signal terminals are disposed on the third upper copper-clad ceramic substrate.

[0010] Furthermore, two conductive metal layers are provided in the weak current area at the edge of the bottom copper-clad ceramic substrate, which are insulated from each other. The two electrodes of the thermistor are respectively welded to the two conductive metal layers to form a surface mount bridging structure. Temperature signal terminals are respectively vertically welded to the two conductive metal layers.

[0011] Furthermore, the encapsulation shell is an aluminum shell, which is filled with insulating adhesive.

[0012] Furthermore, the main commutation current path formed by the upper copper layer of the bottom copper-clad ceramic substrate and the source power return path formed by the upper copper layer of the middle copper-clad ceramic substrate and the lower copper layers of the first upper copper-clad ceramic substrate and the second upper copper-clad ceramic substrate are at least partially parallel and arranged in opposite directions on the vertical projection plane.

[0013] By adopting the above technical solution, the present invention can achieve the following technical effects: This invention rigidly connects the front source of the silicon carbide chip to the lower copper layer of the upper copper-clad ceramic substrate via a first copper block, replacing the traditional long-distance, high-current bonding wire. This improves the current-carrying capacity of the main power circuit and reduces the parasitic inductance of the high-current interconnect path. By constructing a stacked power circuit using the bottom, middle, and top copper-clad ceramic substrates, the main power current path is conducted in layers in the vertical direction. The parallel and opposite current paths create a magnetic flux cancellation effect, thereby reducing the stray inductance of the main commutation circuit. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a front structural schematic diagram of a stacked silicon carbide power module package with low stray inductance according to an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram of the back structure of a stacked silicon carbide power module package with low stray inductance according to an embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram of a single-phase bridge arm circuit structure of a stacked silicon carbide power module package with low stray inductance according to an embodiment of the present invention.

[0018] Figure 4 yes Figure 3 A schematic diagram of the structure without the first upper copper-clad ceramic substrate installed.

[0019] Figure 5 yes Figure 3 A schematic diagram of the structure without the upper copper-clad ceramic substrate installed.

[0020] Figure 6 This is a simulation result diagram of a stacked silicon carbide power module package with low stray inductance according to an embodiment of the present invention.

[0021] Icons: 1. Bottom copper-clad ceramic substrate; 2. Middle copper-clad ceramic substrate; 4. First upper copper-clad ceramic substrate; 5. Second upper copper-clad ceramic substrate; 6. Third upper copper-clad ceramic substrate; 7. Silicon carbide chip; 8. DC input terminal; 9. DC output terminal; 10. Package casing; 11. Thermal conductive base plate; 12. Second copper block; 13. First copper block; 14. Thermistor; 15. Surface mount gate resistor; 16. Third copper block; 17. Temperature signal terminal; 18. Upper bridge gate signal terminal; 19. Upper bridge source signal terminal; 20. First upper bridge drain signal terminal; 21. Second upper bridge drain signal terminal; 22. Lower bridge gate signal terminal; 23. Lower bridge drain signal terminal; 24. First lower bridge source signal terminal; 25. Second lower bridge source signal terminal. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Example Combination Figures 1 to 6 As shown, this embodiment provides a low stray inductance stacked silicon carbide power module package, including a thermally conductive base plate 11 and a package shell 10. The package shell 10 is connected to the thermally conductive base plate 11 and together with the thermally conductive base plate 11, forms the internal mounting space of the module. Three loop regions are formed within the package shell 10, and each loop region is provided with a single-phase bridge arm loop structure. The three loop regions can be arranged sequentially along the length of the package shell 10 and correspond to the U phase, V phase, and W phase in a three-phase full-bridge topology, respectively. Since the single-phase bridge arm loop structures in the three loop regions can adopt the same or symmetrical structure, the following mainly describes the single-phase bridge arm loop structure in one of the loop regions.

[0024] In this embodiment, the attached figure includes 48 silicon carbide chips 7; the three bridge arms of U phase, V phase and W phase are completely symmetrical in internal physical structure, and in each phase bridge arm circuit, the corresponding upper bridge arm circuit contains eight silicon carbide chips 7, and the corresponding lower bridge arm circuit contains eight silicon carbide chips 7; the multiple silicon carbide chips 7 in the same bridge arm circuit are all mounted in a large area parallel form to synergistically improve the overall ultimate current carrying capacity and heat dissipation uniformity of the module.

[0025] The single-phase bridge arm circuit structure includes a bottom copper-clad ceramic substrate 1, a middle copper-clad ceramic substrate 2, and an upper copper-clad ceramic substrate. Each of the bottom, middle, and upper copper-clad ceramic substrates includes an upper copper layer, a ceramic layer, and a lower copper layer. The upper copper-clad ceramic substrate includes a first upper copper-clad ceramic substrate 4, a second upper copper-clad ceramic substrate 5, and a third upper copper-clad ceramic substrate 6.

[0026] The bottom copper-clad ceramic substrate 1 can be connected to the thermally conductive base plate 11 via a solder layer, so that the heat generated by the silicon carbide chip 7 during operation can be transferred to the thermally conductive base plate 11 via the bottom copper-clad ceramic substrate 1. An array of pin fin structures can be provided on the side of the thermally conductive base plate 11 away from the bottom copper-clad ceramic substrate 1 to increase the heat dissipation area and improve the heat dissipation capacity of the module.

[0027] The copper layer on the bottom copper-clad ceramic substrate 1 has an upper bridge arm region and a lower bridge arm region. The upper bridge arm region is used to arrange the silicon carbide chip 7 corresponding to the upper bridge arm and its main power conductive path, and the lower bridge arm region is used to arrange the silicon carbide chip 7 corresponding to the lower bridge arm and its main power conductive path. Multiple silicon carbide chips 7 are connected to the upper and lower bridge arm regions respectively. The multiple silicon carbide chips 7 can be arrayed in the corresponding bridge arm region to improve the current carrying capacity of the single-phase bridge arm circuit structure through parallel connection of multiple chips.

[0028] In this embodiment, multiple intermediate copper-clad ceramic substrates 2 are spaced apart in the upper and lower bridge arm regions along a first direction. The first direction can be understood as the direction in which the multiple intermediate copper-clad ceramic substrates 2 are arranged sequentially at intervals in the corresponding bridge arm regions. The intermediate copper-clad ceramic substrates 2 can be fixed to the upper copper layer of the bottom copper-clad ceramic substrate 1 by a solder layer, so as to form a cross-layer conductive and support structure between the bottom copper-clad ceramic substrate 1 and the upper copper-clad ceramic substrate.

[0029] A first upper copper-clad ceramic substrate 4 is connected to the middle copper-clad ceramic substrate 2 located in the upper bridge arm region, and a second upper copper-clad ceramic substrate 5 is connected to the middle copper-clad ceramic substrate 2 located in the lower bridge arm region. The first upper copper-clad ceramic substrate 4 and the second upper copper-clad ceramic substrate 5 are supported above the bottom copper-clad ceramic substrate 1 by the corresponding middle copper-clad ceramic substrate 2, thereby forming a stacked power circuit structure in the vertical direction.

[0030] The drain of the silicon carbide chip 7 is soldered to the upper copper layer of the bottom copper-clad ceramic substrate 1. The lower copper layers of the first upper copper-clad ceramic substrate 4 and the second upper copper-clad ceramic substrate 5 are connected to the front source of the silicon carbide chip 7 through a first copper block 13. Specifically, one end of the first copper block 13 is soldered to the front source of the silicon carbide chip 7, and the other end is soldered to the lower copper layer of the corresponding first upper copper-clad ceramic substrate 4 or second upper copper-clad ceramic substrate 5. With this structure, the source current of the silicon carbide chip 7 does not need to be transmitted through long-distance bonding wires, but instead forms a large-section vertical rigid conduction path through the first copper block 13, which helps to reduce the parasitic inductance of the source-side power circuit and improve the current carrying capacity.

[0031] The upper copper layer of the middle copper-clad ceramic substrate 2 in the upper bridge arm region is connected to the upper copper layer of the bottom copper-clad ceramic substrate 1 in the lower bridge arm region via the second copper block 12. Thus, the source-side power path in the upper bridge arm region can be bridging to the lower bridge arm region via the middle copper-clad ceramic substrate 2 and the second copper block 12, forming a compact bridge arm series node between the upper and lower bridge arms. The second copper block 12 is a rigid conductive component, which can replace traditional long-distance, high-current bonding wires or bypass wiring, thereby shortening the main commutation path and reducing the loop area.

[0032] A driving circuit is formed on the upper copper layer of the first upper copper-clad ceramic substrate 4 and the second upper copper-clad ceramic substrate 5. The driving circuit is connected to the gate and Kelvin source of the silicon carbide chip 7 respectively through bonding wires. Specifically, one end of the bonding wire is connected to the gate pad or Kelvin source pad on the front side of the silicon carbide chip 7, and the other end is connected to the driving wiring on the upper copper layer of the corresponding upper copper-clad ceramic substrate. Thus, the main power path is rigidly interconnected through the first copper block 13, and the driving control path is flexibly interconnected through the bonding wires, forming a rigid-flexible interconnect architecture. This architecture can meet the high current and low inductance requirements of the main power path, and can also adapt to the local stress changes generated by the stacked structure under temperature cycling by utilizing the flexibility of the bonding wires.

[0033] Furthermore, a surface-mount gate resistor 15 can be disposed on the upper copper layer of the first upper copper-clad ceramic substrate 4 and the second upper copper-clad ceramic substrate 5. The surface-mount gate resistor 15 is connected in series in the drive wiring of the drive circuit and is disposed close to the connection position of the bonding wire on the drive wiring to shorten the physical length of the gate drive loop, reduce the parasitic inductance of the gate drive loop, and suppress the high-frequency parasitic oscillation that may occur when multiple silicon carbide chips 7 are connected in parallel.

[0034] A third upper copper-clad ceramic substrate 6 is also connected to the middle copper-clad ceramic substrate 2 located in the lower bridge arm region. The lower copper layer of the third upper copper-clad ceramic substrate 6 is connected to the DC output region of the upper copper layer of the bottom copper-clad ceramic substrate 1 through a third copper block 16. By setting the third upper copper-clad ceramic substrate 6 and the third copper block 16, the source-side return path of the lower bridge arm region can be connected to the DC output region on the bottom copper-clad ceramic substrate 1 through a short path, thereby further optimizing the current return path of the lower bridge arm region.

[0035] The upper copper layer of the bottom copper-clad ceramic substrate 1 also forms a DC input area and a DC output area. The DC output area and the DC input area are arranged side by side on the same side and are respectively connected to the DC output terminal 9 and the DC input terminal 8. Arranging the DC output area and the DC input area side by side on the same side is beneficial for the compact connection of the external busbar or external DC terminal of the module and helps to reduce the additional loop area introduced by the external terminal.

[0036] During the main power current conduction process, the current can enter the DC input area of ​​the upper copper layer of the bottom copper-clad ceramic substrate 1 from the DC input terminal 8. After being commutated by the silicon carbide chip 7 in the upper bridge arm area, it enters the lower copper layer of the first upper copper-clad ceramic substrate 4 through the first copper block 13, and then crosses over to the upper copper layer of the bottom copper-clad ceramic substrate 1 in the lower bridge arm area via the upper copper layer of the middle copper-clad ceramic substrate 2 and the second copper block 12. Subsequently, the current is commutated by the silicon carbide chip 7 in the lower bridge arm area, and enters the lower copper layer of the second upper copper-clad ceramic substrate 5 through the corresponding first copper block 13. Finally, it flows to the DC output terminal 9 through the third upper copper-clad ceramic substrate 6, the third copper block 16, and the DC output area.

[0037] In the aforementioned main power current path, the main commutation current path formed by the upper copper layer of the bottom copper-clad ceramic substrate 1, and the source power return current path formed by the upper copper layer of the middle copper-clad ceramic substrate 2 and the lower copper layers of the first upper copper-clad ceramic substrate 4 and the second upper copper-clad ceramic substrate 5, are at least partially parallel and reversed on the vertical projection plane. This parallel and reversed current distribution can generate a magnetic flux cancellation effect between layers, reducing the equivalent loop area of ​​the main commutation circuit, thereby reducing the stray inductance of the power module and suppressing voltage overshoot during high-speed switching transients of the silicon carbide chip 7.

[0038] The low stray inductance stacked silicon carbide power module package of this embodiment also includes an upper bridge gate signal terminal 18, an upper bridge source signal terminal 19, a first upper bridge drain signal terminal 20, a second upper bridge drain signal terminal 21, a lower bridge gate signal terminal 22, a lower bridge drain signal terminal 23, a first lower bridge source signal terminal 24, and a second lower bridge source signal terminal 25.

[0039] The upper bridge gate signal terminal 18 and upper bridge source signal terminal 19 are directly connected to the control pads on the front side of the silicon carbide chip 7 to form a Kelvin drive signal path, reducing the impact of the main power current path on the drive reference signal. The first upper bridge drain signal terminal 20 and the second upper bridge drain signal terminal 21 are connected to the drain conductive layer of the silicon carbide chip 7 in the upper bridge arm region for external drive or protection circuits to detect the drain potential. The lower bridge gate signal terminal 22, lower bridge drain signal terminal 23, first lower bridge source signal terminal 24 and second lower bridge source signal terminal 25 are disposed on the third upper copper-clad ceramic substrate 6, thereby facilitating the centralized extraction of the control signal, drain detection signal and source reference signal in the lower bridge arm region.

[0040] The first lower bridge source signal terminal 24 and the second lower bridge source signal terminal 25 are independently configured. The first lower bridge source signal terminal 24 and the second lower bridge source signal terminal 25 are used to provide the drive reference ground signal and the fault detection signal ground, respectively. This configuration can reduce the common ground cross-interference between the control loop and the fault detection loop, and improve the accuracy of the external drive protection circuit in identifying the module's operating status.

[0041] Two electrically isolated conductive metal layers are disposed in the weak electrical region at the edge of the bottom copper-clad ceramic substrate 1. The two electrodes of the thermistor 14 are respectively soldered to the two conductive metal layers to form a surface mount bridging structure. Temperature signal terminals 17 are vertically soldered to the two conductive metal layers respectively. This structure allows the temperature detection signal of the thermistor 14 to be directly led out through the conductive metal layers and the temperature signal terminals 17 without the need for bonding wires, thereby improving the mechanical reliability of the temperature measurement signal path under conditions such as vibration and temperature cycling. At the same time, since the thermistor 14 is located in the weak electrical region at the edge of the bottom copper-clad ceramic substrate 1, its temperature measurement path maintains a certain physical distance from the main commutation area, which helps to reduce the interference of the high-frequency magnetic field of the main power circuit on the temperature measurement signal.

[0042] The encapsulation housing 10 can be an aluminum housing. The aluminum housing is connected to the heat-conducting base plate 11 and supports and protects the internal single-phase bridge arm circuit structure and various signal terminals. The encapsulation housing 10 is filled with insulating glue, which covers the bottom copper-clad ceramic substrate 1, the middle copper-clad ceramic substrate 2, the top copper-clad ceramic substrate, the silicon carbide chip 7, the second copper block 12, the first copper block 13, the third copper block 16, and the bonding wires, etc., to improve the electrical insulation performance, moisture resistance, and mechanical stability of the module.

[0043] like Figure 6As shown, as the switching frequency increases from low frequency to high frequency, within the high-frequency switching band of the silicon carbide power module package, the spatial flux cancellation mechanism generated by the parallel reverse wiring stabilizes and reduces the overall parasitic stray inductance of the main power commutation circuit to 4.28nH, thereby suppressing the voltage overshoot of the silicon carbide chip 7 under high-speed switching transients.

[0044] This embodiment uses a stacked packaging structure formed by a bottom copper-clad ceramic substrate 1, a middle copper-clad ceramic substrate 2, a first upper copper-clad ceramic substrate 4, a second upper copper-clad ceramic substrate 5, and a third upper copper-clad ceramic substrate 6, allowing the main power path, drive path, signal detection path, and temperature measurement path to be spatially arranged in layers. The main power path uses a first copper block 13, a second copper block 12, and a third copper block 16 for rigid cross-layer conduction, which helps reduce parasitic inductance and improve current carrying capacity. The drive path is connected to the upper copper layer of the upper copper-clad ceramic substrate using bonding wires, which helps to achieve short-path lead-out of the drive signal and stress relief. The temperature measurement path uses a thermistor 14, a conductive metal layer, and a temperature signal terminal 17 to form a rigid vertical lead-out, which helps to improve temperature measurement reliability. Thus, this invention can achieve low stray inductance, strong and weak current decoupling, and high-reliability signal transmission within a limited packaging space.

[0045] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions that fall within the scope of the present invention are within the scope of protection of the present invention.

[0046] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0049] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

Claims

1. A stacked silicon carbide power module package with low stray inductance, comprising a thermally conductive base plate and a package housing, wherein the package housing is connected to the thermally conductive base plate and forms three loop regions, each loop region being provided with a single-phase bridge arm loop structure; characterized in that, The single-phase bridge arm circuit structure includes a bottom copper-clad ceramic substrate; the upper copper layer of the bottom copper-clad ceramic substrate forms an upper bridge arm region and a lower bridge arm region; multiple silicon carbide chips are respectively connected to the upper bridge arm region and the lower bridge arm region, and multiple middle copper-clad ceramic substrates are respectively connected at intervals along a first direction; the first direction is the direction in which the multiple middle copper-clad ceramic substrates are arranged at intervals in the corresponding bridge arm region; a first upper copper-clad ceramic substrate is connected to the middle copper-clad ceramic substrate placed in the upper bridge arm region, and a second upper copper-clad ceramic substrate is connected to the middle copper-clad ceramic substrate placed in the lower bridge arm region; the lower copper layers of the first upper copper-clad ceramic substrate and the second upper copper-clad ceramic substrate are connected to the front source electrode of the silicon carbide chip through a first copper block; the upper copper layer of the middle copper-clad ceramic substrate in the upper bridge arm region... The copper layer is connected to the upper copper layer of the bottom copper-clad ceramic substrate in the lower bridge arm region via a second copper block; the upper copper layers of the first and second upper copper-clad ceramic substrates form a driving circuit, which is connected to the gate and Kelvin source of the silicon carbide chip respectively via bonding wires; a third upper copper-clad ceramic substrate is also connected to the middle copper-clad ceramic substrate in the lower bridge arm region, and its lower copper layer is connected to the DC output region of the upper copper layer of the bottom copper-clad ceramic substrate via a third copper block; the main commutation current path formed by the upper copper layer of the bottom copper-clad ceramic substrate and the source power return path formed by the upper copper layer of the middle copper-clad ceramic substrate and the lower copper layers of the first and second upper copper-clad ceramic substrates are at least partially parallel and oppositely arranged on the vertical projection plane.

2. The low stray inductance stacked silicon carbide power module package according to claim 1, characterized in that, The DC output area and DC input area of ​​the upper copper layer of the bottom copper-clad ceramic substrate are arranged side by side on the same side and are respectively connected to DC output terminals and DC input terminals.

3. The low stray inductance stacked silicon carbide power module package according to claim 1, characterized in that, It also includes signal terminals, which include upper bridge gate signal terminals, upper bridge source signal terminals, upper bridge drain signal terminals, lower bridge gate signal terminals, lower bridge source signal terminals, and lower bridge drain signal terminals derived from the gate, source, and drain terminals of the silicon carbide chips corresponding to the upper and lower bridge arm regions; wherein the upper bridge gate signal terminals and the upper bridge source signal terminals are directly derived from the control pads on the front side of the silicon carbide chip; the upper bridge drain signal terminals, the lower bridge gate signal terminals, the lower bridge source signal terminals, and the lower bridge drain signal terminals are disposed on the third upper copper-clad ceramic substrate.

4. The low stray inductance stacked silicon carbide power module package according to claim 1, characterized in that, Two conductive metal layers are provided in the weak current area at the edge of the bottom copper-clad ceramic substrate, which are insulated from each other. The two electrodes of the thermistor are respectively welded to the two conductive metal layers to form a surface mount bridging structure. Temperature signal terminals are respectively welded vertically to the two conductive metal layers.

5. The low stray inductance stacked silicon carbide power module package according to claim 1, characterized in that, The encapsulation shell is an aluminum shell, which is filled with insulating glue.

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