Eddy current testing system based on active differential bottom elimination

Abstract

This invention relates to an eddy current detection system based on active differential cancellation, belonging to the field of eddy current detection technology. An STM32 chip outputs an excitation voltage signal, which is converted into an excitation current signal by an AC constant current source circuit. The eddy current sensor outputs an initial sensing voltage signal containing the substrate signal, which is amplified by a primary amplifier circuit to obtain a primary amplified signal. The primary amplified signal and the substrate compensation signal output by the STM32 chip serve as inputs to a substrate cancellation circuit. The substrate cancellation circuit filters out the substrate signal, outputting only the defect signal caused by the defect. This defect signal is further amplified by a defect amplifier circuit to obtain a differential amplified signal, which is sampled by the STM32 chip for digital signal processing and feature extraction. The feature signal is transmitted to a host computer in real time for data visualization and storage. By actively canceling the sensor substrate, automatic zero-point suppression of the front-end circuit is achieved, effectively avoiding signal saturation under high gain.

Description

Technical Field

[0001] This invention relates to the field of eddy current detection technology, and in particular to an eddy current detection system based on active differential elimination. Background Technology

[0002] Eddy current testing, as an important branch of nondestructive testing (NDT), is primarily used for defect detection. It effectively identifies defects such as cracks, corrosion, voids, and inclusions that occur in metallic materials and components during manufacturing and use. Compared to other NDT methods, eddy current testing offers significant advantages, including simple structure, no need for coupling agents, high sensitivity to near-surface and surface defects in conductive materials, and applicability to special scenarios such as high temperatures, thin-walled tubes, and fine wires. Furthermore, this technology is widely used in coating thickness measurement, metal sheet or wall thickness measurement, and has become a key means for achieving rapid automated inspection and quality control in aerospace, petrochemical, and other fields.

[0003] However, eddy current detection technology still faces challenges such as insufficient resolution of micro-defects and the saturation of amplified signals caused by the inherent impedance of the probe, which limits the accuracy of quantitative defect assessment. To address these issues, scholars both domestically and internationally have conducted extensive research. For example, a planar differential eddy current sensor with self-zeroing characteristics can effectively suppress common-mode components in the induced voltage, improving the detection capability of angular cracks; a split-type magnetic transmission eddy current array probe was designed for pipe structural defects, and experiments show that the detection signal of this probe is less prone to saturation for deeply buried defects; a magnetic field differential probe constructs a near-zero background magnetic field region in space through a special magnetic circuit design to place the sensor, thereby suppressing initial excitation interference.

[0004] However, at the hardware suppression level, current technologies still largely rely on the optimized design of the probe structure, with most research focusing on the arrangement and morphological innovation of coil units. The effectiveness of existing methods in improving defect resolution and suppressing signal saturation remains limited. Furthermore, effectively suppressing high-frequency noise and extracting stable, interference-resistant features for characterization and analysis are also crucial aspects of eddy current testing technology research. Summary of the Invention

[0005] In view of this, it is necessary to provide an eddy current detection system based on active differential background elimination to solve the problem that the direct amplification signal is easily saturated due to the high background substrate in the identification of small defects by eddy current detection.

[0006] To address the aforementioned problems, in a first aspect, the present invention provides an eddy current detection system based on active differential culling, comprising: In one possible implementation, the components include an STM32 chip, an AC constant current source circuit, an eddy current sensor, a primary amplifier circuit, a substrate cancellation circuit, and a defect amplifier circuit. The STM32 chip is used to output the excitation voltage signal; The AC constant current source circuit is used to convert the excitation voltage signal into an excitation current signal; The eddy current sensor is used to perform eddy current detection based on the excitation current signal and generate an initial sensing voltage signal containing the base signal. The primary amplifier circuit is used to amplify the initial sensing voltage signal to obtain a primary amplified signal; The STM32 chip is also used to reconstruct a base compensation signal that is inverse of the base signal based on a pre-sampled base signal. The substrate cancellation circuit is used to inversely superimpose the primary amplified signal and the substrate compensation signal to generate a defect signal. The defect amplification circuit is used to amplify the defect signal to obtain a differential amplified signal; The STM32 chip is also used to extract features from the differential amplified signal and upload the feature signals to the host computer.

[0007] In one possible implementation, the AC constant current source circuit includes: First operational amplifier, transistor, first resistor, second resistor, third resistor, fourth resistor, fifth resistor and sixth resistor; The first resistor is connected to the inverting input terminal of the first operational amplifier; The second resistor is connected to the non-inverting input of the first operational amplifier; The fourth resistor is connected between the output terminal of the first operational amplifier and the base of the transistor; The emitter of the transistor is connected to the sixth resistor; The third resistor is connected between the inverting input terminal of the first operational amplifier and the emitter of the transistor; The fifth resistor is connected between the sixth resistor and the non-inverting input of the first operational amplifier.

[0008] In one possible implementation, the primary amplifier circuit includes: First capacitor, second capacitor, third capacitor, second operational amplifier, seventh resistor, eighth resistor, ninth resistor, tenth resistor, eleventh resistor and twelfth resistor; The first capacitor, the seventh resistor, and the eighth resistor are respectively connected to the non-inverting input terminal of the second operational amplifier; The ninth resistor is connected between the inverting input of the second operational amplifier and the third capacitor; The tenth resistor is connected between the inverting input terminal and the output terminal of the second operational amplifier; The output of the second operational amplifier is connected to the second capacitor; The eleventh resistor and the twelfth resistor are respectively connected to the second capacitor.

[0009] In one possible implementation, the connection node between the fifth resistor and the sixth resistor is connected through the first capacitor and the primary amplifier circuit.

[0010] In one possible implementation, the substrate cancellation circuit includes: Fourth capacitor, fifth capacitor, eighth capacitor, third operational amplifier, thirteenth resistor, fourteenth resistor, fifteenth resistor, sixteenth resistor, seventeenth resistor, eighteenth resistor and nineteenth resistor; The eighth capacitor, the eighteenth resistor, and the nineteenth resistor are respectively connected to the non-inverting input terminal of the third operational amplifier; The fourteenth resistor is connected to the inverting input terminal of the third operational amplifier; The thirteenth resistor is connected between the inverting input of the third operational amplifier and the fourth capacitor; The fifteenth resistor is connected between the inverting input terminal and the output terminal of the third operational amplifier; The output terminal of the third operational amplifier is connected to the fifth capacitor; The sixteenth resistor and the seventeenth resistor are respectively connected to the fifth capacitor.

[0011] In one possible implementation, the defect amplifier circuit includes: Sixth capacitor, seventh capacitor, ninth capacitor, fourth operational amplifier, twentieth resistor, twenty-first resistor, twenty-second resistor, and twenty-third resistor; The sixth capacitor is connected between the inverting input of the fourth operational amplifier and the twentieth resistor; The twenty-first resistor is connected between the inverting input terminal and the output terminal of the fourth operational amplifier; The seventh capacitor is connected in parallel across the twenty-first resistor; The output terminal of the fourth operational amplifier is connected to the ninth capacitor; The ninth capacitor is connected to the twenty-second and twenty-third resistors respectively.

[0012] In one possible implementation, the non-inverting input of the third operational amplifier is connected to the non-inverting input of the fourth operational amplifier.

[0013] In one possible implementation, the STM32 chip is specifically used for: After receiving the base cancellation command sent by the host computer, the base compensation signal that is inverse of the base signal is reconstructed. The phase of the voltage excitation signal at the sampling time is calculated using a sine fitting algorithm, and phase compensation is performed on the voltage excitation signal. Based on the substrate compensation signal, the phase-compensated voltage excitation signal is subjected to substrate elimination to obtain the defect signal.

[0014] In one possible implementation, the STM32 chip is further used for: The excitation voltage signal and the differential amplified signal are sampled synchronously to obtain two discrete-time digital signals; Sine fitting is performed on the two discrete-time digital signals respectively to determine two fitted complex vectors; The feature signal is obtained by calculating the dot product of the two fitted complex vectors.

[0015] In one possible implementation, during the initial calibration phase, the eddy current sensor is placed on a defect-free sample, and the signal output by the primary amplifier circuit is the substrate signal.

[0016] The beneficial effects of this invention are as follows: The eddy current detection system based on active differential cancellation provided by this invention includes an STM32 chip, an AC constant current source circuit, an eddy current sensor, a primary amplifier circuit, a substrate cancellation circuit, and a defect amplifier circuit. The STM32 chip outputs an excitation voltage signal, which the AC constant current source circuit converts into an excitation current signal. This results in the eddy current sensor outputting an initial sensing voltage signal containing the substrate signal. This initial signal is amplified by the primary amplifier circuit to obtain a primary amplified signal. The primary amplified signal and the substrate compensation signal output by the STM32 chip serve as inputs to the substrate cancellation circuit. The substrate cancellation circuit filters out the substrate signal, outputting only the defect signal caused by the defect. This defect signal is further amplified by the defect amplifier circuit to obtain a differential amplified signal, which is then sampled by the STM32 chip for digital signal processing and feature extraction. The feature signal is transmitted to the host computer in real time for data visualization and storage. By actively canceling the sensor substrate, automatic zero-point suppression of the front-end circuit is achieved, effectively avoiding signal saturation under high gain. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the eddy current detection circuit provided by the present invention; Figure 2 A schematic diagram of an embodiment of the eddy current detection system based on active differential elimination provided by the present invention; Figure 3 A schematic diagram of the AC constant current source circuit and primary amplifier circuit provided by the present invention; Figure 4 A schematic diagram of the substrate cancellation circuit and defect amplification circuit provided by the present invention; Figure 5 A schematic diagram of the software flow of the eddy current detection system based on active differential elimination provided by the present invention; Figure 6 This is a schematic diagram comparing the original signal and the reconstructed signal provided by the present invention. Figure 7 A schematic diagram illustrating the theoretical aspects of phase loss phenomenon provided by this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] In the description of the embodiments of the present invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0021] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Before demonstrating the embodiments, the eddy current sensor will be explained.

[0024] The working principle of an eddy current sensor is based on the law of electromagnetic induction. When a high-frequency alternating current passes through the probe coil, it generates a primary alternating magnetic field around it. When the coil approaches a conductive object, this magnetic field induces closed eddy currents inside the object. According to Lenz's law, the eddy currents generate a secondary magnetic field in the opposite direction to the primary magnetic field, which in turn acts on the probe coil, causing a change in the coil's equivalent impedance. Figure 1 This is a schematic diagram of the eddy current detection circuit provided by the present invention. Figure 1 (a) in the diagram is the schematic diagram when there are no defects. Figure 1 (b) in the diagram is the schematic diagram when there is a defect.

[0025] Under defect-free steady-state conditions, the probe has an inherent background impedance: (1) When the object under test has a minute defect, the equivalent complex impedance of the probe A slight shift will occur. This change... It can be decomposed into the change in inductance. and resistance change .

[0026] For minor surface defects, usually The variation is dominant, but its absolute value is extremely small. Mapped onto the sensor's output voltage signal, the effective signal voltage amplitude generated by the defect... Much smaller than the base voltage generated by the inherent impedance of the coil Due to effective defect signals The signal is extremely weak and must pass through a high-gain amplifier circuit to improve the signal-to-noise ratio and resolution before being sent to an analog-to-digital converter (ADC) for digitization. However, if the signal with the substrate superimposed is directly amplified, the substrate signal will be amplified proportionally, which can easily cause the operational amplifier to saturate, resulting in the complete loss of the weak defect signal. Therefore, effective measures must be taken to suppress the substrate signal before signal amplification in order to accurately extract the weak defect signal. Defect feature vector signal.

[0027] This invention provides an eddy current detection system based on active differential elimination, which will be described in detail below.

[0028] Figure 2 This is a schematic diagram of an embodiment of the eddy current detection system based on active differential bottoming provided by the present invention, as shown below. Figure 2 As shown, the eddy current detection system based on active differential elimination includes: STM32 chip, AC constant current source circuit, eddy current sensor, primary amplifier circuit, substrate cancellation circuit and defect amplifier circuit; The STM32 chip is used to output the excitation voltage signal; The AC constant current source circuit is used to convert the excitation voltage signal into an excitation current signal; The eddy current sensor is used to perform eddy current detection based on the excitation current signal and generate an initial sensing voltage signal containing the base signal. The primary amplifier circuit is used to amplify the initial sensing voltage signal to obtain a primary amplified signal; The STM32 chip is also used to reconstruct a base compensation signal that is inverse of the base signal based on a pre-sampled base signal. The substrate cancellation circuit is used to inversely superimpose the primary amplified signal and the substrate compensation signal to generate a defect signal. The defect amplification circuit is used to amplify the defect signal to obtain a differential amplified signal; The STM32 chip is also used to extract features from the differential amplified signal and upload the feature signals to the host computer.

[0029] It should be noted that the STM32 chip model is STM32F407. In the excitation signal generation section, the system uses direct digital synthesis (DDS) technology to output a specific frequency AC sinusoidal voltage as the excitation voltage signal through the STM32's internal digital-to-analog converter (DAC1).

[0030] The AC constant current source circuit is a voltage-to-current (V / I) conversion circuit. The excitation voltage signal is converted into an excitation current signal by the AC constant current source circuit and then applied to the eddy current sensor.

[0031] The excitation voltage signal is sampled and monitored by the ADC1 of the STM32 chip.

[0032] In the conditioning section of the eddy current sensor output signal, in view of the high floor and weak variation characteristics of the small defect signal, this invention designs a multi-stage analog signal processing link, including a primary amplifier circuit, a floor cancellation circuit and a defect amplifier circuit.

[0033] The eddy current sensor outputs an initial sensing voltage signal containing the base signal, which is amplified by the primary amplifier circuit to obtain a primary amplified signal, and then sampled and monitored by the ADC2 of the STM32 chip.

[0034] The primary amplified signal enters the substrate cancellation circuit, and the primary amplified signal and the substrate compensation signal output by the STM32 chip's DAC2 serve as the inputs to the substrate cancellation circuit.

[0035] It should be noted that during the initial calibration phase, the eddy current sensor is placed on a defect-free sample. At this time, the primary amplified signal contains only the pure substrate signal. The STM32 chip reconstructs the substrate compensation signal, which is inversely phase with the substrate signal, based on the pre-sampled substrate signal.

[0036] The substrate cancellation circuit filters out the common-mode substrate signal in hardware and outputs only the defect signal caused by the defect. The signal is then further amplified by the gain amplifier circuit (i.e. the defect amplifier circuit) to obtain the differential amplified signal, which is then sampled by the ADC3 of the STM32 chip.

[0037] By using an active differential cancellation sensor substrate, automatic zero-point suppression of the front-end circuit is achieved, effectively avoiding signal saturation under high gain.

[0038] The STM32 performs digital signal processing and feature extraction on the data acquired by the ADC3, and transmits the results to the host computer in real time via the serial port (USART) to complete the visualization and storage of the data.

[0039] In summary, the eddy current detection system based on active differential cancellation provided in this embodiment of the invention includes an STM32 chip, an AC constant current source circuit, an eddy current sensor, a primary amplifier circuit, a substrate cancellation circuit, and a defect amplification circuit. The STM32 chip outputs an excitation voltage signal, which the AC constant current source circuit converts into an excitation current signal. This results in the eddy current sensor outputting an initial sensing voltage signal containing the substrate signal. This initial signal is amplified by the primary amplifier circuit to obtain a primary amplified signal. The primary amplified signal and the substrate compensation signal output by the STM32 chip serve as inputs to the substrate cancellation circuit. The substrate cancellation circuit filters out the substrate signal, outputting only the defect signal caused by the defect. This defect signal is further amplified by the defect amplification circuit to obtain a differential amplified signal, which is then sampled by the STM32 chip for digital signal processing and feature extraction. The feature signal is transmitted to the host computer in real time for data visualization and storage. By actively canceling the sensor substrate, automatic zero-point suppression of the front-end circuit is achieved, effectively avoiding signal saturation under high gain.

[0040] In some embodiments of the present invention, the AC constant current source circuit includes: First operational amplifier, transistor, first resistor, second resistor, third resistor, fourth resistor, fifth resistor and sixth resistor; The first resistor is connected to the inverting input terminal of the first operational amplifier; The second resistor is connected to the non-inverting input of the first operational amplifier; The fourth resistor is connected between the output terminal of the first operational amplifier and the base of the transistor; The emitter of the transistor is connected to the sixth resistor; The third resistor is connected between the inverting input terminal of the first operational amplifier and the emitter of the transistor; The fifth resistor is connected between the sixth resistor and the non-inverting input of the first operational amplifier.

[0041] Figure 3 This is a schematic diagram of the AC constant current source circuit and primary amplifier circuit provided by the present invention, which provides a stable excitation current for the eddy current coil and appropriately amplifies the initial sensing voltage signal.

[0042] like Figure 3 As shown, the AC constant current source circuit includes: a first operational amplifier and a transistor. First resistor Second resistor Third resistor Fourth resistor Fifth resistor and the sixth resistor .

[0043] In some embodiments of the present invention, the primary amplifier circuit includes: First capacitor, second capacitor, third capacitor, second operational amplifier, seventh resistor, eighth resistor, ninth resistor, tenth resistor, eleventh resistor and twelfth resistor; The first capacitor, the seventh resistor, and the eighth resistor are respectively connected to the non-inverting input terminal of the second operational amplifier; The ninth resistor is connected between the inverting input of the second operational amplifier and the third capacitor; The tenth resistor is connected between the inverting input terminal and the output terminal of the second operational amplifier; The output of the second operational amplifier is connected to the second capacitor; The eleventh resistor and the twelfth resistor are respectively connected to the second capacitor.

[0044] In some embodiments of the present invention, the connection node between the fifth resistor and the sixth resistor is connected through the first capacitor and the primary amplifier circuit.

[0045] like Figure 3As shown, the primary amplifier circuit includes: a first capacitor. Second capacitor Third capacitor Second operational amplifier, seventh resistor The eighth resistor Ninth resistor 10th resistor Eleventh resistor and the twelfth resistor .

[0046] Defects of varying degrees directly alter the impedance characteristics of the detection coil. To convert impedance changes into a voltage signal that is easy to measure, an AC constant current source should be applied to the eddy current sensor; therefore, the AC voltage source generated by the DDS needs to be converted.

[0047] The STM32's DAC1 pin outputs an AC excitation signal. Connect it to the non-inverting input of the operational amplifier.

[0048] Based on the ideal model of the operational amplifier and Kirchhoff's current law, the following relationship can be established: (2) Resistor in circuit , , and The resistance value is selected as 10kΩ. Substituting this parameter into the above equation, the equation can be simplified to: (3) From equation (3), it can be seen that the resistance The total voltage drop across the terminals is always equal to the output voltage of DAC1. Therefore, flowing through current for: (4) because , , The resistance is much greater than the coil impedance, so , Since the shunt current is negligible, the excitation current flowing through the coil under test can be considered as... Proportional to the set This involves applying a constant-amplitude alternating current source to the coil under test. When a defect causes a change in the coil's impedance, the voltage across its terminals... Proportional to the change in coil impedance, thus achieving a linear conversion from impedance information to voltage signal.

[0049] In the circuit The resistance is 47Ω, and the amplitude of the excitation signal is approximately 180mV. Therefore, the effective value of the excitation current can be calculated using equation (4). 2.7mA. The heat dissipation generated by the tiny excitation current in the mA range is extremely low, which effectively avoids the self-heating effect of the coil, improves the thermal stability of the sensing system, and ensures the repeatability of long-term measurements.

[0050] Capacitors in amplifier circuits , Its function is to filter out the DC component in the signal; the capacitor To ensure signal accuracy, the amplification process must not affect the DC component. Considering the STM32's internal ADC module has a reference voltage of 2.5V, its ideal input range needs to cover 0V to 2.5V. This is to achieve the desired input range for AC signals. Bipolar measurement, via resistance and A 2.5V reference voltage is divided to generate a 1.25V DC bias voltage. This bias voltage is then compared with the amplified AC signal. By superimposing the signal, the overall signal is brought within the effective input range of the ADC, thus avoiding signal clipping.

[0051] In some embodiments of the present invention, the substrate cancellation circuit includes: Fourth capacitor, fifth capacitor, eighth capacitor, third operational amplifier, thirteenth resistor, fourteenth resistor, fifteenth resistor, sixteenth resistor, seventeenth resistor, eighteenth resistor and nineteenth resistor; The eighth capacitor, the eighteenth resistor, and the nineteenth resistor are respectively connected to the non-inverting input terminal of the third operational amplifier; The fourteenth resistor is connected to the inverting input terminal of the third operational amplifier; The thirteenth resistor is connected between the inverting input of the third operational amplifier and the fourth capacitor; The fifteenth resistor is connected between the inverting input terminal and the output terminal of the third operational amplifier; The output terminal of the third operational amplifier is connected to the fifth capacitor; The sixteenth resistor and the seventeenth resistor are respectively connected to the fifth capacitor.

[0052] Figure 4 The schematic diagram of the substrate cancellation circuit and defect amplification circuit provided by the present invention is shown below. Figure 4 As shown, the substrate cancellation circuit includes: a fourth capacitor. Fifth capacitor Eighth capacitor Third operational amplifier, thirteenth resistor Fourteenth resistor The fifteenth resistor Sixteenth resistor Seventeenth resistor The eighteenth resistor and the nineteenth resistor .

[0053] In some embodiments of the present invention, the defect amplification circuit includes: Sixth capacitor, seventh capacitor, ninth capacitor, fourth operational amplifier, twentieth resistor, twenty-first resistor, twenty-second resistor, and twenty-third resistor; The sixth capacitor is connected between the inverting input of the fourth operational amplifier and the twentieth resistor; The twenty-first resistor is connected between the inverting input terminal and the output terminal of the fourth operational amplifier; The seventh capacitor is connected in parallel across the twenty-first resistor; The output terminal of the fourth operational amplifier is connected to the ninth capacitor; The ninth capacitor is connected to the twenty-second and twenty-third resistors respectively.

[0054] In some embodiments of the present invention, the non-inverting input of the third operational amplifier and the non-inverting input of the fourth operational amplifier are connected.

[0055] like Figure 4 As shown, the defective amplifier circuit includes: a sixth capacitor. Seventh capacitor Ninth capacitor Fourth operational amplifier, twentieth resistor 21st resistor 22nd resistor Twenty-third resistor .

[0056] To effectively suppress the inherent substrate signal of the eddy current sensor, this invention designs as follows: Figure 4 The circuit shown is a substrate cancellation and defect amplification circuit. This circuit is an inverting adder circuit, using a reconstructed signal generated by DAC2 as an example. and the original sensor signal after pre-amplification As input.

[0057] In some embodiments of the present invention, during the initial calibration stage, the eddy current sensor is placed on a defect-free sample, and the signal output by the primary amplifier circuit is the substrate signal.

[0058] During the initial calibration phase, the sensor is placed on a defect-free sample. It contains only pure base signals, denoted as: (5) in, , , These represent the amplitude, angular frequency, and initial phase of the base signal, respectively.

[0059] The system generates its inverted signal through digital reconstruction, which is then output by DAC2, i.e.: (6) In actual defect inspection Weak defect feature components are superimposed in the middle.

[0060] Since the two signals are superimposed in opposite phase in the adder circuit, under ideal conditions, the base signal is completely canceled out, and the final output voltage becomes: (7) in, , These are the amplitude and phase, respectively, related to the defect signal.

[0061] For ADC sampling Verify the offsetting effect, by and Stabilize its DC bias at 1.25V.

[0062] To facilitate subsequent data acquisition and further improve detection sensitivity, the differential signal is amplified by an amplifier circuit and finally sampled and digitized by an ADC for subsequent analysis and identification.

[0063] In some embodiments of the present invention, the STM32 chip is specifically used for: After receiving the base cancellation command sent by the host computer, the base compensation signal that is inverse of the base signal is reconstructed. The phase of the voltage excitation signal at the sampling time is calculated using a sine fitting algorithm, and phase compensation is performed on the voltage excitation signal. Based on the substrate compensation signal, the phase-compensated voltage excitation signal is subjected to substrate elimination to obtain the defect signal.

[0064] Figure 5 This is a schematic diagram of the software flow of the eddy current detection system based on active differential elimination provided by the present invention, as shown below. Figure 5 As shown, it mainly includes two core stages: basis signal reconstruction and feature extraction.

[0065] Substrate Signal Reconstruction: After system startup, DAC1 first outputs an initial excitation signal, and the excitation signal and the sensor substrate signal are simultaneously sampled by the ADC. Upon receiving the "substrate cancellation" command from the host computer, a substrate compensation signal that is out of phase with the substrate is reconstructed using the pre-sampled substrate data. To eliminate phase delay, the system uses a sine fitting algorithm to calculate the phase of the excitation signal at the sampling time and performs precise phase compensation on the excitation signal accordingly. Finally, DAC1 and DAC2 synchronously output the phase-compensated excitation signal and the substrate compensation signal, achieving real-time cancellation of the substrate signals on the hardware side.

[0066] Feature extraction: Upon receiving the "test" command from the host computer, the ADC synchronously samples the excitation signal and the differential amplified signal. Then, a sine fitting algorithm is used again to calculate the vector expressions of the two signals, and feature values ​​are extracted through digital vector dot product. Finally, the feature values ​​are uploaded to the host computer.

[0067] The difficulty in generating the basis-compensated signal lies in the severe rate mismatch between the high-density data points required for DDS reconstruction and the number of sampling points per cycle of the actual ADC. Within a single high-frequency excitation cycle, the DAC's DDS output sequence can have as many as 60 discrete points, while the ADC, relying on conventional continuous sampling, can only capture a maximum of about 10 data points. This low sampling rate makes it impossible to directly extract and reconstruct a high-fidelity basis signal.

[0068] To address this challenge, the system introduces a uniform phase sampling algorithm to obtain the equivalent point for high sampling frequency under low sampling frequency conditions.

[0069] Uniform phase sampling is a multi-cycle sampling technique for periodic signals. This method utilizes the principle of equivalent time sampling to ensure that sampling points are uniformly distributed along the phase axis. Specifically, the method involves... Sampled within one integer sinusoidal signal period There are points, and they satisfy... , The relationship is coprime. After phase rounding... The phase corresponding to each sampling point is uniformly distributed within the interval (-π, π), which is equivalent to sampling within one period. There are 1 point, therefore it is called 1 point. Point-uniform phase sampling method. Compared with single-cycle sampling, this method can significantly improve the accuracy of signal reconstruction.

[0070] The excitation signal generation process is as follows: When outputting the excitation signal, the microcontroller's Timer 3 (TIM3) is used as the trigger clock for the DAC. The microcontroller's reference clock frequency is known. To improve the phase density of the output signal within a limited DAC conversion speed, 640 signal points are output within 11 complete sinusoidal signal cycles. Let the target frequency of the excitation signal be... =100kHz.

[0071] Based on the DDS principle, the relationship between the DAC update frequency and the signal frequency, and the timer reload value... The calculation formula is as follows: (8) in, This represents the number of equivalent points within a single period.

[0072] Substituting the relevant parameters, we can obtain =14.4375, to meet the integer requirement of the hardware register, take... =14, at which point the actual output frequency is approximately 103kHz.

[0073] The ADC sampling configuration process is as follows: Using TIM2 as the sampling trigger clock for the ADC, since the ADC needs to go through sampling, holding and quantization processes to complete one conversion, its total conversion time is significantly longer than the register update cycle of the DAC.

[0074] To ensure sampling stability, the ADC sampling period must be longer than the DAC update period. In terms of hardware configuration, the reload value of the ADC trigger timer needs to be set. for 7 times, that is: (9) ADC sampling period With excitation signal period They can be represented as: (10) (11) in, This is the reference clock cycle for the microcontroller.

[0075] According to the principle of uniform phase sampling, if... Completed within one signal cycle The sampling at each point must satisfy the time equation: (12) Since the system is linear, the reconstructed signal should have the same frequency as the excitation signal. Therefore, the ADC needs to sample 640 points to match the output points of the DAC2. =640.

[0076] Substituting equations (9), (10), and (11) into equation (12) for further derivation, we get: (13) Simplify to get =77.

[0077] In summary, when selecting =77, When the phase ratio is 640, the two phases satisfy the coprime relationship, and uniform phase sampling is successfully achieved.

[0078] The basis signal reconstruction process based on phase mapping is as follows: To achieve active cancellation of the base signal, the compensation signal output by DAC2 must be strictly synchronized with the excitation signal of DAC1, meaning that the 640 data points output must contain 11 signal cycles. However, the 640 base signal data points acquired by the ADC cover 77 complete sine wave cycles. Therefore, the system needs to resample and reconstruct the phase of the original data to generate a reconstructed signal containing 11 cycles, which is then inverted and output by DAC2.

[0079] The core of resampling lies in establishing a mapping relationship between the sampling point index and the signal phase, and rearranging the data points accordingly. Since the base signal is a sine wave, its phase increases linearly with time. For the ADC sampling point index... The corresponding phase It can be represented as: (14) During signal reconstruction, the goal is to obtain 640 points uniformly distributed over 11 complete cycles. Let the rearranged index be... The desired target phase is: (15) Based on the periodicity of the sinusoidal signal, the phase changes modulo... Equivalence in a meaningful sense, that is, any two differences Integer multiples of the phase correspond to the same position on the signal waveform. Therefore, to make the rearranged phase... Each point and the original sampling point If they represent the same signal phase, then and The following relationship must be satisfied: (16) This congruence relation can be further expressed as: (17) in, It is equivalent to: (18) Since 7 and 640 are coprime, this mapping forms a linear congruent bijection. When the original sampling point index... Reconstruct the index when traversing from 0 to 639. This will also uniquely cover all integer values ​​from 0 to 639. Through this mapping, the sampling points are rearranged, with their phase evenly distributed over 11 sinusoidal periods. Table 1 lists the results to illustrate this mapping more clearly. When taking a partially continuous value, the corresponding value: Table 1: Partial Mapping Between Original Sampling Index and Reconstructed Index

[0080] As can be seen from the table, even Continuously increasing, The values ​​of also exhibit regular jumps without repetition, ensuring a uniform distribution of phase.

[0081] To verify the effectiveness of this method, Figure 6 This is a schematic diagram comparing the original signal and the reconstructed signal provided by the present invention. Figure 6 (a) shows a set of 640 raw data points collected by the ADC over 77 cycles, with each cycle containing less than 9 data points; Figure 6 (b) shows the reconstructed sinusoidal signal for 11 cycles based on the above mapping relationship. The amount of data in each cycle is close to 60, which ensures that the reconstructed compensation signal is closer to the amplified base signal and the cancellation effect is more obvious.

[0082] The excitation signal phase compensation process is as follows: The substrate compensation signal needs to be obtained by ADC sampling and digital reconstruction of the original substrate signal after primary amplification. Considering the temporal randomness of ADC sampling, the sampling start time is not synchronized with the period start time of the excitation signal. Therefore, after obtaining the substrate compensation signal, phase compensation must be performed on the excitation signal according to the sampling start time to achieve synchronization between the compensation signal and the excitation signal.

[0083] Assuming that when DAC1 output is started, the excitation signal is output from zero phase, it can be expressed as: (19) in, These represent the amplitude and angular frequency of the excitation signal, respectively.

[0084] When the ADC is started for synchronous sampling, its sampling start time is... There is a random phase shift between the phase starting point and the excitation signal. .

[0085] Therefore, at the start of sampling, the actual excitation signal value is: (20) This system is a linear system, and its transfer function introduces an additional phase shift. Therefore, the sensor in The amplified base signal output at time t is: (twenty one) To achieve cancellation, the basis compensation signal output by DAC2 is: (twenty two) When DAC2 is activated to output the compensation signal, it is at a new time starting point. The output at this time for: (twenty three) At this time, since the excitation signal is continuously running, At that moment, the actual value of the sensor output signal is: (twenty four) contrast and It can be seen that, due to The randomness of both When two signals have different phases, their superposition will produce a residual signal, causing the cancellation to fail. Figure 7 This is a theoretical schematic diagram of the phase loss phenomenon provided by the present invention. Figure 7 This is a theoretical diagram used to illustrate the phase relationship, not actual measurement data.

[0086] To address the aforementioned issue of asynchronous DAC startup phases, a synchronous phase compensation method is proposed. The core idea is to synchronously restart the output of the excitation signal at the same time as the output base compensation signal, and then compensate for the phase of the excitation signal.

[0087] To obtain the phase information of the signal, a sine fitting algorithm can be used to calculate the ADC sampling sequence values.

[0088] Let a set of sampled sequence values ​​of the ADC be... Any value in the sequence can be represented as: (25) in, It is discrete sampled data; For amplitude, The initial phase of the signal; This represents the cumulative phase increment. DC bias; This represents the noise error of the sampled signal.

[0089] make , Equation (25) can be further expressed as: (26) As can be seen from the least squares linear fitting, and It can be represented as: (27) Therefore: (28) Therefore, the starting time of ADC sampling can be calculated. Initial phase of the excitation signal When at time When the cancellation process is initiated, both the excitation DAC and the cancellation DAC are restarted simultaneously, and the excitation DAC no longer starts from zero phase, but instead compensates for an initial phase. The new excitation signal output is: (29) This new excitation signal passes through the sensor again, generating the following output signal: (30) Through this series of operations, at a new starting point... Then, the sensor outputs a signal. The base compensation signal output by DAC2 They always maintain an antiphase relationship. When added in the time domain, they can theoretically completely cancel each other out, leaving only a small residual error, which mainly stems from factors such as amplitude matching accuracy.

[0090] In some embodiments of the present invention, the STM32 chip is further used for: The excitation voltage signal and the differential amplified signal are sampled synchronously to obtain two discrete-time digital signals; Sine fitting is performed on the two discrete-time digital signals respectively to determine two fitted complex vectors; The feature signal is obtained by calculating the dot product of the two fitted complex vectors.

[0091] Depend on Figure 4 As shown in the circuit, the complex impedance change of the sensor coil caused by the defect has been converted into amplitude and phase changes of the differential amplified signal: (31) To address the problem that this high-frequency coupled signal is susceptible to noise interference and difficult to directly separate and observe, and to achieve digital extraction from the AC response to stable eigenvalues, this invention proposes a phase-sensitive detection method based on digital vector dot product.

[0092] First, the excitation signal and the differential amplified signal are synchronously sampled using an ADC to obtain two discrete-time digital signals. Then, the sine fitting algorithm shown in equation (31) is applied to these two digital signals respectively, and the fitting parameters are used as the real and imaginary parts to form a fitting complex vector.

[0093] Let the fitted eigenvector of the excitation signal be... The fitted complex vector of the differential amplified signal is .

[0094] A stable DC digital signal can be demodulated by calculating the dot product of two complex vectors. : (32) Since the excitation signal complex vector is theoretically fixed, the output of the dot product operation... It is directly proportional to the magnitude of the projection of the complex vector of the response signal onto the direction of the reference vector, that is: (33) in, yes and The phase difference between them.

[0095] This corresponds precisely to the change in the real part of the sensor impedance, i.e., the resistivity, caused by defects. Through this design, the defect-sensitive information, which was originally mixed in with the AC carrier wave, is transformed into a DC characteristic value that is linearly related to the real part of the impedance and is suitable for accurate quantification and reliable discrimination.

[0096] Each measurement result is obtained by fitting and calculating the dot product of 640 data points each of the excitation signal sampled by the ADC and the differential amplified signal. Ignoring the computation time required by the fitting algorithm itself, under ideal conditions... output frequency for: (34) Substituting the ADC sampling parameters into the calculation yields 1339Hz. Therefore, the system has a high measurement speed.

[0097] To address the challenge of small defect signals being easily submerged by high carrier background in eddy current detection, this invention proposes a high-precision eddy current detection system based on active differential cancellation technology. Using an STM32F407 as its core, it leverages its internal digital-to-analog converter (DAC) and analog-to-digital converter (ADC) to achieve high-frequency excitation and synchronous sampling. By reconstructing and outputting an inverted signal through uniform phase sampling, and actively differentially cancelling the sensor substrate, automatic zero-position suppression of the front-end circuit is achieved, effectively avoiding signal saturation under high gain. Simultaneously, a phase-sensitive detection algorithm based on digital vector dot product is proposed, directly performing amplitude and phase demodulation and feature extraction in the digital domain. This invention has the following advantages: (1) By introducing a hardware differential circuit in the analog front end, the sensor base voltage is effectively canceled, and the saturation risk of the subsequent high-gain amplifier circuit is eliminated.

[0098] (2) To address the rate mismatch problem between high-frequency excitation of the microcontroller and low-frequency ADC sampling, a uniform phase sampling reconstruction algorithm is proposed. This method overcomes the physical limitation of single-cycle undersampling and realizes accurate digital reconstruction of high-frequency substrate signals.

[0099] (3) A phase-sensitive detection method based on digital vector dot product is proposed, which uses the vector dot product of the amplified pure defect signal and the excitation signal as the feature value, and realizes the robust extraction from AC response to the feature value characterizing the net intensity of the defect.

[0100] (4) Experimental results show that within the lift range of 1 mm to 2.1 mm, the goodness of fit of the detected feature values ​​is high. The accuracy is better than 0.97, and the RMSE% is less than 8.33%. The SNR for a 3mm deep defect is as high as 34.4dB at a 1mm lift-off distance. Even when detecting a 0.25mm deep micro-defect at a large lift-off distance of 2.1mm, the SNR still maintains an effective recognition level of 11.3dB. This invention provides a low-cost, high-performance solution for high-precision nondestructive testing.

[0101] The above provides a detailed description of the eddy current detection system based on active differential bottoming-out provided by the present invention. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An eddy current detection system based on active differential elimination, characterized in that, include: STM32 chip, AC constant current source circuit, eddy current sensor, primary amplifier circuit, substrate cancellation circuit and defect amplifier circuit; The STM32 chip is used to output the excitation voltage signal; The AC constant current source circuit is used to convert the excitation voltage signal into an excitation current signal; The eddy current sensor is used to perform eddy current detection based on the excitation current signal and generate an initial sensing voltage signal containing the base signal. The primary amplifier circuit is used to amplify the initial sensing voltage signal to obtain a primary amplified signal; The STM32 chip is also used to reconstruct a base compensation signal that is inverse of the base signal based on a pre-sampled base signal. The substrate cancellation circuit is used to inversely superimpose the primary amplified signal and the substrate compensation signal to generate a defect signal. The defect amplification circuit is used to amplify the defect signal to obtain a differential amplified signal; The STM32 chip is also used to extract features from the differential amplified signal and upload the feature signals to the host computer.

2. The eddy current detection system based on active differential bottoming as described in claim 1, characterized in that, The AC constant current source circuit includes: First operational amplifier, transistor, first resistor, second resistor, third resistor, fourth resistor, fifth resistor and sixth resistor; The first resistor is connected to the inverting input terminal of the first operational amplifier; The second resistor is connected to the non-inverting input of the first operational amplifier; The fourth resistor is connected between the output terminal of the first operational amplifier and the base of the transistor; The emitter of the transistor is connected to the sixth resistor; The third resistor is connected between the inverting input terminal of the first operational amplifier and the emitter of the transistor; The fifth resistor is connected between the sixth resistor and the non-inverting input of the first operational amplifier.

3. The eddy current detection system based on active differential elimination according to claim 2, characterized in that, The primary amplifier circuit includes: First capacitor, second capacitor, third capacitor, second operational amplifier, seventh resistor, eighth resistor, ninth resistor, tenth resistor, eleventh resistor and twelfth resistor; The first capacitor, the seventh resistor, and the eighth resistor are respectively connected to the non-inverting input terminal of the second operational amplifier; The ninth resistor is connected between the inverting input of the second operational amplifier and the third capacitor; The tenth resistor is connected between the inverting input terminal and the output terminal of the second operational amplifier; The output of the second operational amplifier is connected to the second capacitor; The eleventh resistor and the twelfth resistor are respectively connected to the second capacitor.

4. The eddy current detection system based on active differential elimination according to claim 3, characterized in that, The connection node between the fifth resistor and the sixth resistor is connected through the first capacitor and the primary amplifier circuit.

5. The eddy current detection system based on active differential elimination according to claim 1, characterized in that, The substrate cancellation circuit includes: Fourth capacitor, fifth capacitor, eighth capacitor, third operational amplifier, thirteenth resistor, fourteenth resistor, fifteenth resistor, sixteenth resistor, seventeenth resistor, eighteenth resistor and nineteenth resistor; The eighth capacitor, the eighteenth resistor, and the nineteenth resistor are respectively connected to the non-inverting input terminal of the third operational amplifier; The fourteenth resistor is connected to the inverting input terminal of the third operational amplifier; The thirteenth resistor is connected between the inverting input of the third operational amplifier and the fourth capacitor; The fifteenth resistor is connected between the inverting input terminal and the output terminal of the third operational amplifier; The output terminal of the third operational amplifier is connected to the fifth capacitor; The sixteenth resistor and the seventeenth resistor are respectively connected to the fifth capacitor.

6. The eddy current detection system based on active differential elimination according to claim 5, characterized in that, The defect amplification circuit includes: Sixth capacitor, seventh capacitor, ninth capacitor, fourth operational amplifier, twentieth resistor, twenty-first resistor, twenty-second resistor, and twenty-third resistor; The sixth capacitor is connected between the inverting input of the fourth operational amplifier and the twentieth resistor; The twenty-first resistor is connected between the inverting input terminal and the output terminal of the fourth operational amplifier; The seventh capacitor is connected in parallel across the twenty-first resistor; The output terminal of the fourth operational amplifier is connected to the ninth capacitor; The ninth capacitor is connected to the twenty-second and twenty-third resistors respectively.

7. The eddy current detection system based on active differential bottoming as described in claim 6, characterized in that, The non-inverting input of the third operational amplifier is connected to the non-inverting input of the fourth operational amplifier.

8. The eddy current detection system based on active differential bottoming as described in claim 1, characterized in that, The STM32 chip is specifically used for: After receiving the base cancellation command sent by the host computer, the base compensation signal that is inverse of the base signal is reconstructed; The phase of the voltage excitation signal at the sampling time is calculated using a sine fitting algorithm, and phase compensation is performed on the voltage excitation signal. Based on the substrate compensation signal, the phase-compensated voltage excitation signal is subjected to substrate elimination to obtain the defect signal.

9. The eddy current detection system based on active differential bottoming as described in claim 1, characterized in that, The STM32 chip is also used for: The excitation voltage signal and the differential amplified signal are sampled synchronously to obtain two discrete-time digital signals; Sine fitting is performed on the two discrete-time digital signals respectively to determine two fitted complex vectors; The feature signal is obtained by calculating the dot product of the two fitted complex vectors.

10. The eddy current detection system based on active differential bottoming as described in claim 1, characterized in that, During the initial calibration phase, the eddy current sensor is placed on a defect-free sample, and the signal output by the primary amplifier circuit is the substrate signal.

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