A frequency converter power module detector

Abstract

This invention relates to the field of power electronic equipment testing technology, specifically disclosing a frequency converter power module tester, including a control panel. The control panel is communicatively connected to the following modules: a multi-channel pulse analysis module, used to send PWM pulse signals to the drive board under test via a DSP control chip, and to filter and offset the output pulses using a conditioning circuit. Through synchronous acquisition and waveform feature comparison, it accurately locates abnormal channels on the drive board; a dual-source fault self-diagnosis isolation module, used to monitor the status of fault indicator lights on the drive board using the real-time fault diagnosis logic of the DSP control chip. This invention, by synchronously acquiring and comparing the waveform features of multiple PWM pulses, can accurately pinpoint abnormal channels in the drive board, significantly improving the accuracy and efficiency of fault location. It overcomes the limitation of traditional testing methods that rely solely on the presence or absence of pulses to identify specific channel anomalies, providing a reliable technical means for board-level repair.

Description

Technical Field

[0001] This invention relates to the field of power electronic equipment testing technology, and in particular to a frequency converter power module tester. Background Technology

[0002] As an important power control device, frequency converters are widely used in various industrial automation systems. One of their core components is the power module, which is responsible for regulating the voltage and current during the power conversion process to ensure the normal operation of the frequency converter. Therefore, the stability and reliability of the power module directly affect the performance of the entire system. However, as the operating years of wind turbine units increase, the failure rate of frequency converter power modules is rising year by year. There is a lack of dedicated testing equipment on site, and traditional fault diagnosis relies on spare parts replacement, which is cumbersome, time-consuming and labor-intensive.

[0003] In existing technologies, when testing drive boards, the lack of consistency analysis of multi-channel PWM waveforms makes it difficult to accurately locate specific abnormal channels by simply comparing input and output pulses. Furthermore, when the board is under load, the fault indicator light status makes it difficult to distinguish between drive board faults and IGBT module connection abnormalities. Additionally, during dynamic load testing of IGBT modules, the lack of a coordinated hardware protection mechanism when output voltage or current is abnormal results in the inability to dynamically adjust protection strategies when output voltage / current is abnormal during module load testing. To address these issues, a frequency converter power module tester is proposed. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention provides a frequency converter power module tester, which can effectively solve the problems involved in the prior art.

[0005] The objective of this invention can be achieved through the following technical solution: This invention provides a frequency converter power module tester, including a control panel, wherein the control panel is communicatively connected to the following modules: The multi-channel pulse analysis module is used to send PWM pulse signals to the driver board under test through the DSP control chip, and to filter and offset the output pulses in combination with the conditioning circuit. Through synchronous acquisition and waveform feature comparison, the abnormal channel of the driver board can be accurately located, which significantly improves the efficiency and accuracy of fault channel location and shortens the troubleshooting time. The dual-source fault self-diagnosis isolation module is used to monitor the status of fault indicator lights on the driver board by utilizing the real-time fault diagnosis logic of the DSP control chip. Combined with the self-diagnosis algorithm, it automatically distinguishes the fault source as an abnormality in the driver board or the IGBT module connection and displays the corresponding fault code on the touch screen, realizing intelligent differentiation of fault sources and reducing misjudgment and repeated troubleshooting. The high-voltage output sampling module is used to provide a programmable high voltage of 0-1000VDC in IGBT module load testing. At the same time, it uses a high-precision voltage / current sensor (with a 16-bit ADC) to sample the DC bus voltage, output voltage and current values ​​in real time, and quickly converts analog quantities into digital quantities for processing by the DSP control chip. This ensures that the high-voltage output is accurate and controllable, and the sampling data is reliable in real time, supporting dynamic testing requirements. The collaborative protection strategy adjustment module is based on a dual protection mechanism of preset hardware-level fast shutdown and software dynamic adjustment. When a sudden drop in output voltage, overcurrent or short circuit is detected, the hardware-level protection can quickly shut down the PWM output within <1μs. At the same time, the DSP control chip dynamically adjusts the PWM parameters according to the abnormal waveform and records the abnormal waveform data to avoid secondary impacts that may be caused by direct hard shutdown and ensure the absolute safety of the IGBT module in dynamic testing. The guided human-computer interaction module is used to graphically and step-by-step guide the board testing process and module testing process through an integrated touch screen. Testers only need to click to start and stop according to the on-screen prompts to complete the test. The module displays waveforms, data and fault codes in real time, reducing training costs and operational error rates.

[0006] Preferably, the multi-channel pulse analysis module includes a PWM generation and conditioning unit and a multi-channel synchronous comparison unit; The PWM generation and conditioning unit, based on the ePWM module of the DSP control chip (DSP28335), generates three pairs of complementary six-channel PWM pulse signals. The built-in conditioning circuit (operational amplifier + filter) offsets, amplifies and filters the output pulses, so that the signal maintains purity and driving capability before being transmitted to the board under test, eliminates high-frequency noise interference, effectively suppresses signal distortion, and ensures stable and reliable transmission of test signals. The multi-channel synchronous comparison unit is used to synchronously acquire the output pulses returned by the driver board. It uses the floating-point operation of the DSP control chip to perform real-time feature comparison of the input and output waveforms. When the waveform feature of a certain channel deviates from the preset threshold, the specific abnormal channel is immediately locked and identified, realizing sub-millisecond accurate fault location, greatly improving the fault response speed, and ensuring the immediate identification and location of abnormal channels.

[0007] Preferably, the PWM generation and conditioning unit specifically includes: In response to the test start command, the ePWM module configuration register of the DSP control chip is called to set the carrier frequency to 4kHz and the dead time, generating three pairs of complementary six-channel original PWM pulse signals to ensure that the upper and lower bridge arm drive signals are strictly complementary, thus fundamentally eliminating the risk of shoot-through short circuit. The original PWM pulse signal is introduced into an active filter and level offset circuit composed of an operational amplifier. By adjusting the feedback resistor and bias voltage, the signal level is calibrated to the receiving range of the interface of the driver board under test, so that the pulse level is precisely matched with the board input specification, ensuring that the signal is correctly identified and received. The conditioned PWM pulse signal is output to the test interface through an impedance matching network. At the same time, a high-frequency bypass capacitor is connected in parallel at the output to filter out common-mode and differential-mode high-frequency interference induced during transmission, eliminate signal reflection and interference, and ensure that the pulse transmitted to the board is pure and complete.

[0008] Preferably, the multi-channel synchronous comparison unit specifically includes: By using multiple parallel ADC sampling channels, the output pulses of each phase returned after being processed by the driver board under test are synchronously acquired, and the analog signals are converted into digital waveform data and stored in the buffer memory of the DSP control chip. This ensures the synchronization of multi-channel signal acquisition and the complete storage of data, providing a reliable foundation for subsequent accurate analysis. The floating-point arithmetic unit built into the DSP control chip is called to perform point-by-point correlation calculation between the actual waveform data of each channel and the standard waveform template stored in Flash, and extract amplitude, rise time and pulse width feature values ​​to achieve accurate extraction of waveform features and improve the accuracy and sensitivity of fault identification. The feature values ​​of each channel are compared with the preset tolerance threshold. When the feature value of any channel exceeds the tolerance threshold range, the channel identifier is immediately locked, and the abnormal channel information is uploaded to the control panel through an interruption method, so as to realize the rapid locking and real-time reporting of abnormal channels, making it easier for operators to locate the fault point as soon as possible.

[0009] Preferably, the dual-source fault self-diagnosis and isolation module includes a board status monitoring unit and a fault tracing unit; The board status monitoring unit is used to monitor the voltage changes of key test points and fault indicator lights on the driver board in real time through the GPIO interface of the DSP control chip or the auxiliary sampling circuit during the power-on test of the driver board, and generate a time-series status dataset to be uploaded to the control system in real time, so as to ensure that the board status is traceable throughout the process and improve the comprehensiveness and accuracy of fault analysis. The fault tracing unit utilizes a self-diagnostic algorithm based on a DSP control chip. When a fault indicator light is detected, it performs logical judgment based on the current test conditions (no load / load) and PWM output status. By analyzing the fault triggering sequence and electrical characteristics, it automatically distinguishes the fault source, namely, hardware damage to the driver board itself or signal abnormality caused by poor IGBT module connection. It then displays a clear fault code on the touch screen to guide maintenance personnel in precise operations, accurately pinpoint the root cause of the fault, and significantly improve the pertinence and efficiency of maintenance operations.

[0010] Preferably, the board status monitoring unit specifically includes: During the initial power-on phase of the driver board, the level status of key test points on the board is periodically scanned through the GPIO port and compared with the preset power-on initial status table to determine whether there is a short circuit or power supply abnormality, effectively preventing board damage caused by power-on abnormality and improving test safety. During the PWM pulse signal injection test, the auxiliary sampling circuit captures the level transition of the corresponding pin of the fault indicator on the board in real time, records the precise timestamp of the transition and the corresponding test conditions, and realizes the accurate capture of fault events, providing reliable data support for subsequent source tracing analysis. The collected state change data is associated and packaged with the current PWM output channel and load access status to form a time-series state dataset, which is transmitted to the control system in real time to assist in subsequent analysis, ensuring the traceability and data integrity of the fault diagnosis process and improving analysis efficiency.

[0011] Preferably, the fault tracing unit specifically includes: Receive the time-series status dataset from the board status monitoring unit, and based on the fault indicator light transition timestamp, trace back the PWM output status and load access flag bit within a few milliseconds before that moment, thereby restoring the working condition at the moment of the fault and ensuring the accuracy and reliability of the diagnostic data source. The built-in self-diagnostic logic algorithm is invoked. When a fault occurs, if the PWM pulse signal output is normal and the device is in an unloaded state, it is determined to be a hardware fault of the driver board itself, which can accurately locate the board-level fault and avoid blindly replacing components. If the device is in a loaded state and accompanied by abnormal current sampling, it is determined to be an abnormal IGBT module connection, which can effectively distinguish external load problems and improve the pertinence of fault diagnosis. Based on the judgment result, the corresponding fault code and fault definition are retrieved from the fault code library and sent to the touch screen display through the communication interface. The intuitive code guides the maintenance, reduces the risk of personnel misjudgment, and locks the current test interface until it is manually reset, forcibly interrupting dangerous operations and ensuring the safety of subsequent tests.

[0012] Preferably, the high-voltage output sampling module specifically includes: It receives voltage setting instructions from the control panel, outputs the analog set value to the high-voltage power supply control circuit through the DAC, adjusts the duty cycle of the DC-DC converter, and establishes a 0-1000VDC programmable high voltage at the output terminal, realizing precise programmable adjustment of the high voltage output to meet the flexible power supply needs of different test scenarios. A high-precision Hall voltage sensor and a current sensor are connected in series in the high-voltage output circuit to isolate and convert the high-voltage signal into a low-voltage analog signal in the range of 0-3V, which is then input to a 16-bit ADC converter to achieve safe isolation between high and low voltage, ensuring that the sampling circuit is not affected by high voltage and that the signal is linear and undistorted. The ADC continuously converts analog voltage and current quantities at a preset sampling rate. The DSP control chip reads the conversion results through DMA (Direct Memory Access) and performs digital filtering and scaling transformation. The results are then updated in real time to the system monitoring variable area, enabling high-speed transmission and real-time processing of sampled data, and providing accurate data support for dynamic protection and control.

[0013] Preferably, the collaborative protection strategy adjustment module specifically includes: The real-time voltage and current data obtained by the high-voltage output sampling module are compared with the preset overcurrent, overvoltage and short-circuit protection thresholds using both hardware comparators and software logic. If any condition is triggered, the hardware-level PWM blocking circuit is immediately activated. Through the dual comparison mechanism of hardware and software, the risk of module damage caused by the failure of a single protection path is effectively avoided. While the PWM output is shut down by hardware, the DSP control chip responds to the protection interrupt, reads the voltage and current waveform data at the moment of the fault and stores it in non-volatile memory. At the same time, it dynamically adjusts the recovery strategy of PWM parameters according to the type of abnormality. The complete recording of waveform data at the moment of the fault and the dynamic adjustment of parameters provide an accurate basis for subsequent fault analysis and improve the safety of the recovery process. After the fault source is eliminated, the system responds to the reset command and gradually restores the PWM output according to the dynamically adjusted soft-start strategy. This avoids secondary impact on the IGBT module caused by direct restoration. The soft-start strategy ensures that the electrical stress borne by the module during the restoration process is within a safe and controllable range, thus extending the module's service life.

[0014] Preferably, the guided human-computer interaction module specifically includes: After power-on, the touch screen loads the graphical test main interface. Based on the test mode selected by the user (board test or module test), the corresponding step guide page is dynamically called and the current operation step is highlighted, making the operation process intuitive and clear, and effectively reducing the risk of misoperation by on-site personnel. During the test execution, the waveform feature data and fault codes uploaded by the DSP control chip are analyzed in real time, and voltage and current waveforms are dynamically drawn in a designated area on the screen. The status of each channel and fault prompts are displayed in text form, realizing the visual monitoring of the test process, which makes it easy to detect and locate abnormal conditions as soon as possible. After the test is completed, the complete data of this test (including parameter settings, waveform records, fault codes and test conclusions) will be automatically saved to local storage, and historical data query and export interfaces will be provided to ensure that the test results are traceable and reproducible, which will facilitate subsequent analysis and quality archiving.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. This inverter power module tester can accurately locate abnormal channels in the drive board by synchronously acquiring and comparing the waveform characteristics of multiple PWM pulses, significantly improving the accuracy and efficiency of fault location, overcoming the limitation of traditional testing that it is difficult to identify specific channel abnormalities based solely on the presence or absence of pulses, and providing a reliable technical means for board-level maintenance.

[0016] 2. This inverter power module tester has intelligent fault tracing capabilities. It can automatically distinguish whether the fault source is from inside the drive board or from an abnormal connection of the IGBT module based on the status of the fault indicator light, the test conditions, and electrical characteristics, and clearly indicate this on the interface. This effectively solves the problem of difficulty in identifying the fault source in traditional testing and improves the scientificity and accuracy of diagnosis.

[0017] 3. This inverter power module tester constructs a dual protection mechanism of hardware and software collaboration in dynamic load testing. It can quickly shut down the output when abnormal voltage or current is detected, while dynamically adjusting the recovery strategy and recording the abnormal waveform. This ensures the safety and controllability of the testing process, avoids secondary damage to the module due to sudden abnormalities, and significantly improves the protection capability of the equipment. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the working process of a frequency converter power module tester according to the present invention; Figure 2 This is a schematic diagram of the test process for the drive board of a frequency converter power module tester according to the present invention; Figure 3 This is a schematic diagram of the IGBT module testing process of a frequency converter power module tester according to the present invention. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0020] Example 1, please refer to Figures 1 to 3 The present invention provides a technical solution: a frequency converter power module tester, including a control panel, the control panel being communicatively connected to the following modules: The multi-channel pulse analysis module is used to send PWM pulse signals to the driver board under test through the DSP control chip, and filter and offset the output pulses in combination with the conditioning circuit. Through synchronous acquisition and waveform feature comparison, the abnormal channel of the driver board can be accurately located, which significantly improves the efficiency and accuracy of fault channel location and shortens the troubleshooting time. The multi-channel pulse analysis module includes a PWM generation and conditioning unit and a multi-channel synchronous comparison unit. The PWM generation and conditioning unit, based on the ePWM module of the DSP control chip (DSP28335), generates three pairs of complementary six-channel PWM pulse signals. Through built-in conditioning circuitry (operational amplifier + filter), the output pulses are offset, amplified, and filtered to maintain signal purity and driving capability before transmission to the board under test, eliminating high-frequency noise interference, effectively suppressing signal distortion, and ensuring stable and reliable transmission of the test signal. In response to the test start command, it calls the ePWM module configuration register of the DSP control chip, sets the carrier frequency to 4kHz and the dead time, and generates three pairs of complementary six-channel original PWM pulse signals. To ensure strict complementarity of the upper and lower bridge arm drive signals and fundamentally eliminate the risk of shoot-through short circuits, the original PWM pulse signal is introduced into an active filter and level offset circuit composed of operational amplifiers. By adjusting the feedback resistor and bias voltage, the signal level is calibrated to the receiving range of the interface of the driver board under test, so that the pulse level is precisely matched with the board input specifications, ensuring that the signal is correctly identified and received. The conditioned PWM pulse signal is output to the test interface through an impedance matching network. At the same time, a high-frequency bypass capacitor is connected in parallel at the output to filter out common-mode and differential-mode high-frequency interference induced during transmission, eliminate signal reflection and interference, and ensure that the pulse transmitted to the board is pure and complete. It should be noted that after the operator issues the test start command via the touchscreen, the DSP control chip responds to the interrupt and immediately calls the ePWM module's register configuration program. The carrier frequency is set to 4kHz according to preset parameters, and the dead time is configured to 2.5μs according to the IGBT module's safe conduction requirements to ensure no shoot-through occurs between the upper and lower bridge arms. After configuration, the ePWM module generates three pairs of complementary six-channel raw PWM pulse signals, corresponding to the upper and lower bridge arm drive channels of the U, V, and W phases respectively. These raw signals are led out from the DSP's dedicated output pins and transmitted to the subsequent conditioning circuit via PCB traces to ensure real-time response to the test command and synchronous generation of the pulse signals. The raw PWM pulse signals enter an active filter and level offset circuit composed of an operational amplifier OPA4350. During on-site operation, the feedback resistor value and bias voltage parameters are automatically adjusted via a digital potentiometer according to the electrical specifications of the interface of the driver board under test, thus adjusting the signal level. Precisely calibrated to the 0~3.3V range to meet the receiving requirements of the board's input, the conditioning circuit simultaneously performs second-order low-pass filtering with a cutoff frequency set to 10kHz, effectively suppressing high-frequency harmonic components. The conditioned PWM signal waveform is smooth and has a steep cutoff, possessing sufficient driving capability and avoiding misdiagnosis caused by signal distortion. The conditioned PWM pulse signal enters the impedance matching network, which is composed of precision resistors with an output impedance designed to be 50Ω, matching the characteristic impedance of the transmission line of the test interface to minimize signal reflection. At each PWM output, a 100pF high-frequency bypass capacitor is connected in parallel to filter out common-mode and differential-mode high-frequency interference induced during long-distance transmission. After processing, the PWM signal is transmitted to the driver board under test through the ribbon cable connector of the test interface. The interface adopts a three-phase independent ribbon cable design (U, V, W), with each phase containing two signals from the upper and lower bridge arms, ensuring the independence of signal transmission and anti-interference capability. The multi-channel synchronous comparison unit is used to synchronously acquire the output pulses returned by the driver board. Utilizing the floating-point arithmetic of the DSP control chip, it performs real-time feature comparison of the input and output waveforms. When the waveform characteristics of a certain channel deviate from a preset threshold, the specific abnormal channel is immediately locked and identified, achieving sub-millisecond-level accurate fault location, significantly improving fault response speed, and ensuring immediate identification and location of abnormal channels. Through multiple parallel ADC sampling channels, it synchronously acquires the output pulses of each phase returned after processing by the driver board under test, converts the analog signals into digital waveform data, and stores them in the buffer memory of the DSP control chip, ensuring the synchronization of multi-channel signal acquisition and complete data storage. This provides a reliable foundation for subsequent accurate analysis. The floating-point arithmetic unit built into the DSP control chip is called to perform point-by-point correlation calculation between the actual waveform data of each channel and the standard waveform template stored in Flash, and extract the amplitude, rise time and pulse width feature values ​​to achieve accurate extraction of waveform features, improve the accuracy and sensitivity of fault identification. The feature values ​​of each channel are compared with the preset tolerance threshold. When the feature value of any channel exceeds the tolerance threshold range, the channel identifier is immediately locked and the abnormal channel information is uploaded to the control panel through interrupt mode, so as to realize the rapid locking and real-time reporting of abnormal channels, which makes it easy for operators to locate the fault point as soon as possible. It should be noted that after the operator initiates the board test process via the touchscreen, the DSP control chip immediately activates its built-in 16-bit ADC module, configuring it to multi-channel synchronous sampling mode. The ADC module performs parallel acquisition of the six output pulses returned from the U, V, and W phases at a sampling rate of 1MHz. Each signal is adjusted to the 0~3.0V range by the front-end conditioning circuit to ensure a sampling accuracy of ±0.5%. The sampling start time is synchronized with the PWM pulse transmission time, and the ADC conversion is triggered by the synchronization signal of the ePWM module to ensure the phase correspondence between the input and output waveforms. The converted digital waveform data is directly transferred to the high-speed buffer memory inside the DSP via the DMA controller. The entire process does not require CPU intervention, minimizing transmission delay. After the waveform data in the buffer memory is ready, the DSP control chip calls the floating-point unit to start the feature extraction program. First, it retrieves the standard waveform template corresponding to the current test model from the Flash memory. This template contains key characteristic parameters such as the nominal amplitude value of 3.3V, the nominal rise time value of 100ns, and the nominal pulse width value of 125μs. The arithmetic unit performs point-by-point correlation calculations on the actual waveform data of each channel and the standard template. Using a sliding window comparison algorithm, it precisely locks the start and end points of each pulse, and then calculates the actual amplitude, the rise time from 10% to 90%, and the pulse width at 50% amplitude. During the calculation process, data overflow and abnormal transitions are monitored in real time to ensure the accuracy of feature value extraction. After feature value extraction, the fault determination stage begins. The DSP control chip compares the actual feature values ​​calculated for each channel with the tolerance thresholds stored in the parameter area. The amplitude tolerance range is set to ±0.2V, the rise time tolerance range to ±20ns, and the pulse tolerance range to ±2μs. When any feature value of a channel exceeds the corresponding tolerance range, the physical identifier of that channel is immediately locked, and the abnormal information is packaged and uploaded via a hardware interrupt mechanism before the start of the next PWM cycle. The uploaded data packet includes the abnormal channel number, the feature item exceeding the threshold, the measured value, and the fault occurrence timestamp. Upon receiving the interrupt signal, the control panel immediately updates the touchscreen display, highlighting the abnormal channel in red to allow operators to quickly locate the fault point. The dual-source fault self-diagnosis isolation module is used to monitor the status of fault indicator lights on the driver board by utilizing the real-time fault diagnosis logic of the DSP control chip. Combined with the self-diagnosis algorithm, it automatically distinguishes the fault source as an abnormality in the driver board or the IGBT module connection and displays the corresponding fault code on the touch screen. This achieves intelligent differentiation of the fault source, reduces misjudgment and repeated troubleshooting. The dual-source fault self-diagnosis isolation module includes a board status monitoring unit and a fault tracing unit. The board status monitoring unit is used to monitor the voltage changes of key test points and fault indicator lights on the driver board in real time during the power-on test of the driver board through the GPIO interface of the DSP control chip or auxiliary sampling circuit. It generates a time-series status dataset and uploads it to the control system in real time, ensuring full traceability of the board status and improving the comprehensiveness and accuracy of fault analysis. In the initial power-on phase of the driver board, it periodically scans the voltage levels of key test points on the board through the GPIO port and compares them with a preset initial power-on status table to determine if there is a short circuit or power supply abnormality, effectively preventing faults caused by abnormal power-on. To prevent common board damage and improve test safety, during PWM pulse signal injection testing, an auxiliary sampling circuit captures the level transitions of the corresponding pins of the fault indicator on the board in real time, records the precise timestamp of the transition and the corresponding test conditions, and achieves accurate capture of fault events. This provides reliable data support for subsequent source analysis. The collected state change data is associated and packaged with the current PWM output channel and load access status to form a time-series state dataset, which is transmitted to the control system in real time to assist in subsequent analysis, ensuring the traceability and data integrity of the fault diagnosis process and improving analysis efficiency. It should be noted that after the operator connects the driver board under test to the test interface of the tester via a dedicated cable, and starts the power-on initialization program, the DSP control chip immediately performs periodic level scans on the preset key test points on the board through the GPIO port group. The test points include the +15V power input terminal, the +3.3V logic power supply terminal, and the signal ground terminal. The scan frequency is set to 10kHz, and each scan lasts for 5 cycles to ensure that any possible transient anomalies are fully captured. The collected level data is compared point by point with the power-on initial state table stored in Flash. The state table contains information on each test point. The pilot test operates within the normal voltage range, with the +15V power supply allowed to range from 14.25V to 15.75V and the +3.3V logic power supply allowed to range from 3.14V to 3.46V. If the voltage level at any test point deviates from the allowed range for more than 20ms, a short circuit or power supply abnormality is detected. The power-on process is immediately terminated, and the corresponding fault code is displayed on the touchscreen, prompting the operator to check the board's power circuit. After completing the power-on initialization and confirming that there are no abnormalities, the operator initiates the PWM pulse injection test via the touchscreen. The DSP control chip outputs six 4kHz channels through the test interface. Simultaneously with the PWM signal, the auxiliary sampling circuit is activated to capture the corresponding pins of the fault indicator lights on the driver board in real time. The auxiliary sampling circuit adopts a high-speed comparator design with a threshold voltage set to 2.0V. When the pin level crosses this threshold, it triggers precise timestamp recording with a time resolution of 1μs. At the same time, it automatically records the current test condition parameters, including the PWM output frequency setting of 1000Hz, the load connection status flag, and the current test phase. The level transition, transition direction, precise timestamp, and corresponding test condition parameters of the fault indicator light pins are combined and encapsulated into a status event record, which is uploaded to the control system buffer in real time via DMA. After receiving multiple status event records from the auxiliary sampling circuit, the control system starts the data association and packaging program, first packaging each fault indicator... The lamp switching event is matched with the current PWM output channel status to determine whether the specific phase at the time of the switching is U phase, V phase, or W phase. Then, combined with the flag information returned by the load access detection circuit, it is determined whether the current test is in no-load mode or load mode. After all associations are completed, the event records are organized into a time-series status dataset according to the time sequence. Each dataset contains the fault indicator number, switching timestamp, switching type, associated PWM channel, load status, and current test step identifier. This dataset is transmitted in real time to the touch screen control unit via the RS485 communication interface at a baud rate of 115200bps to dynamically update the status prompts on the interface. At the same time, it is stored in the local log file for subsequent fault playback and analysis, ensuring the traceability of the fault diagnosis process. The fault tracing unit utilizes a self-diagnostic algorithm based on a DSP control chip. When a fault indicator light illuminates, it performs logical judgment based on the current test conditions (no-load / loaded) and PWM output status. By analyzing the fault trigger timing and electrical characteristics, it automatically distinguishes the fault source: either hardware damage to the driver board itself or signal abnormalities caused by poor IGBT module connections. It displays a clear fault code on the touchscreen to guide maintenance personnel in precise operations, accurately pinpointing the root cause of the fault, and significantly improving the targeting and efficiency of maintenance work. It receives a time-series status dataset from the board status monitoring unit and, based on the fault indicator light's transition timestamp, traces back the PWM output status and load connection flag bit within several milliseconds prior to that moment, thereby... The system identifies the fault condition at the moment of failure, ensuring the accuracy and reliability of the diagnostic data source. It calls the built-in self-diagnostic logic algorithm. When a fault occurs, if the PWM pulse signal output is normal and the system is under no-load conditions, it is determined to be a hardware fault of the driver board itself, achieving precise orientation of board-level faults and avoiding blind replacement of components. If the system is under load conditions and accompanied by abnormal current sampling, it is determined to be an abnormal connection of the IGBT module, effectively distinguishing external load problems and improving the pertinence of fault diagnosis. Based on the diagnosis results, the system retrieves the corresponding fault code and fault definition from the fault code library and sends it to the touch screen display through the communication interface. This provides intuitive code guidance for repair, reduces the risk of personnel misjudgment, and locks the current test interface until it is manually reset, forcibly interrupting dangerous operations and ensuring the safety of subsequent tests. It should be noted that in actual operation, after the board status monitoring unit uploads the time-series dataset containing precise timestamps, the fault tracing unit immediately starts the backtracking analysis program. The DSP control chip uses the fault indicator light transition timestamp as a reference to backtrack the PWM output status register data within 5ms before that moment, accurately reading the pulse output status of the U, V, and W phases within that time window, including the duty cycle setting value of each phase PWM, the actual output channel enable status, and the current test phase. At the same time, it calls the flag information returned by the load access detection circuit within that time window to confirm whether the test is currently in no-load mode or loaded mode. Through the backtracking mechanism, the complete working condition environment at the moment of the fault occurrence is accurately restored, providing accurate data support for logic judgment and ensuring that the fault source analysis is based on reliable field operating data. After completing the working condition backtracking, the DSP control chip calls the built-in self-diagnostic logic algorithm to distinguish the fault source. First, it determines whether the PWM pulse signal output is normal when the fault occurs, that is, whether the output amplitude, frequency, and dead time of each channel are consistent with the set values ​​of 4kHz and 2.5μs. If the PWM output parameters are normal... If the load access flag indicates a normal and traced load condition, the system determines the fault source to be hardware damage to the driver board itself, such as aging of the onboard optocoupler, failure of the driver chip, or abnormality of the isolation power supply. If the traced result indicates a loaded condition, and the current sampling data uploaded by the high-voltage output sampling module shows abnormal fluctuations or exceeds the preset threshold during the same period, the system determines the fault source to be poor IGBT module connection or damage to internal components of the module. Based on the determination result obtained from the self-diagnosis logic, the DSP control chip immediately accesses the fault code library stored in the Flash memory. This fault code library is stored according to fault type, including driver board hardware fault codes and IGBT module connection abnormality codes. After retrieving the corresponding code and fault definition, it is sent to the touch screen control unit at a baud rate of 115200bps through the RS485 communication interface. The touch screen immediately pops up a fault prompt window, highlighting the fault code and specific definition in red. At the same time, the current test interface is automatically locked, prohibiting the continued issuance of PWM pulses or high-voltage output commands until the operator manually presses the reset button and eliminates the fault, ensuring the safety and reliability of subsequent tests. The high-voltage output sampling module provides a programmable high voltage (0-1000VDC) for IGBT module load testing. Simultaneously, it uses a high-precision voltage / current sensor (in conjunction with a 16-bit ADC) to sample the DC bus voltage, output voltage, and current in real time, rapidly converting analog signals into digital signals for processing by the DSP control chip. This ensures precise and controllable high-voltage output, reliable real-time sampling data, and supports dynamic testing requirements. It receives voltage setting commands from the control panel and outputs the analog setpoint to the high-voltage power supply control circuit via the DAC. This adjusts the duty cycle of the DC-DC converter, establishing a programmable high voltage (0-1000VDC) at the output, achieving precise programmable control of the high-voltage output and meeting flexible power supply needs in different testing scenarios. A high-precision Hall voltage sensor and current sensor are connected in series in the high-voltage output circuit to isolate and convert the high-voltage signal into a low-voltage analog signal within the 0-3V range, which is then input to the 16-bit ADC converter. This ensures safe isolation between high and low voltage signals, protecting the sampling circuit from high-voltage impacts and maintaining signal linearity without distortion. The ADC continuously converts analog voltage and current signals at a preset sampling rate. The DSP control chip uses DMA (Direct Memory Access) to... Access (Direct Memory Access) reads the conversion results, performs digital filtering and scaling transformation, and updates them to the system monitoring variable area in real time, realizing high-speed transmission and real-time processing of sampled data, providing accurate data support for dynamic protection and control; It should be noted that after the operator inputs the required high-voltage output value via the touchscreen, the control panel immediately generates a corresponding voltage setting command, which is transmitted to the DSP control chip via the RS485 communication interface. Upon receiving the command, the DSP chip calls its built-in 12-bit DAC module to output an analog setpoint proportional to the set voltage to the high-voltage power supply control circuit. This control circuit uses the setpoint as a reference and combines a PID adjustment algorithm to generate a PWM drive signal, controlling the duty cycle of the power switching transistors in the DC-DC converter. The converter adopts a high-frequency isolation topology, establishing a stable and adjustable high-voltage DC bus at the output. The voltage adjustment range is 0 to 1000VDC, with a resolution of 1V and an accuracy of ±1%. The entire adjustment process is completed within milliseconds, ensuring rapid response of the high-voltage output to the operation command and meeting the real-time requirements of IGBT module dynamic testing for the supply voltage. In the high-voltage output circuit, a high-precision Hall effect voltage sensor and a current sensor are arranged in series to monitor the DC bus voltage and load current in real time, respectively. The voltage sensor linearly isolates and converts the 0 to 1000VDC high-voltage signal into a low-voltage analog signal of 0 to 3V, and the current sensor... The current signal from 0 to 50A is converted into a voltage signal from 0 to 3V. After the two analog signals are filtered by the front-end anti-aliasing filter, they are input to a 16-bit successive approximation ADC converter. The ADC is configured in continuous sampling mode with a sampling rate of 100kSPS to ensure rapid capture of voltage and current changes. During the conversion process, the analog signal is quantized into a digital quantity, and the conversion result is temporarily stored in the ADC's data register, waiting for the DSP control chip to read it. The DSP control chip reads the ADC conversion result through the DMA controller in direct memory access mode, without CPU intervention, which greatly reduces data transmission latency. After each DMA transfer, the DSP calls a digital filtering algorithm to smooth the original sampled data and filter out high-frequency noise interference. The filtered data is scaled and restored to the actual voltage and current values ​​according to the sensor turns ratio and the gain of the conditioning circuit. The processed real-time data is immediately updated to the system monitoring variable area. On the one hand, it is used to dynamically display the current bus voltage and load current waveform on the touch screen. On the other hand, it serves as the input parameter for the collaborative protection strategy adjustment module to compare with the preset overvoltage and overcurrent protection thresholds in real time, ensuring the safety and controllability of the test process. The collaborative protection strategy adjustment module employs a dual protection mechanism based on preset hardware-level rapid shutdown and software dynamic adjustment. When a sudden drop in output voltage, overcurrent, or short circuit is detected, the hardware-level protection can rapidly shut down the PWM output within <1μs. Simultaneously, the DSP control chip dynamically adjusts the PWM parameters based on the abnormal waveform and records the abnormal waveform data, avoiding secondary impacts that may result from direct hard shutdown. This ensures the absolute safety of the IGBT module during dynamic testing, achieving dual protection of instantaneous protection and intelligent recovery. This enhances the safety of the testing process and extends the module's lifespan. The module performs a dual comparison of real-time voltage and current data obtained from the high-voltage output sampling module with preset overcurrent, overvoltage, and short-circuit protection thresholds using both hardware comparators and software logic. Triggering any of these conditions immediately activates the hardware-level PWM blocking circuit. Through a dual comparison mechanism of hardware and software, the risk of module damage caused by the failure of a single protection path is effectively avoided. While the hardware shuts off the PWM output, the DSP control chip responds to the protection interrupt, reads the voltage and current waveform data at the moment of the fault and stores it in non-volatile memory. At the same time, it dynamically adjusts the recovery strategy of PWM parameters according to the type of abnormality. The complete recording of the waveform data at the moment of the fault and the dynamic adjustment of parameters provide an accurate basis for subsequent fault analysis and improve the safety of the recovery process. After the fault source is eliminated, it responds to the reset command and gradually restores the PWM output according to the dynamically adjusted soft start strategy. This avoids the secondary impact on the IGBT module caused by direct recovery. The soft start strategy ensures that the electrical stress borne by the module during the recovery process is within a safe and controllable range, thus extending the module's service life. It should be noted that during the dynamic load test of the IGBT module, the collaborative protection strategy adjustment module receives voltage and current data from the high-voltage output sampling module in real time and performs a dual comparison with the preset protection threshold. The hardware comparator is responsible for comparing the analog signal with the threshold voltage in real time. Once the voltage exceeds 1050V, the current exceeds the set limit, or short-circuit characteristics are detected, the hardware-level PWM blocking circuit is activated immediately within 1μs to cut off the drive pulse output and prevent the IGBT module from being damaged due to overcurrent or overvoltage. At the same time, the software logic performs periodic verification of the sampled data through the DSP control chip to ensure the accuracy and redundancy of the protection action and avoid false triggering or protection failure due to single-point faults. This dual comparison mechanism superimposes software verification on the basis of hardware fast response, which not only ensures the real-time performance of protection but also improves the anti-interference capability and reliability of the system. After the hardware-level PWM blocking is triggered, the DSP control chip immediately responds to the protection interrupt and executes the fault data acquisition and storage program. The chip reads the high-voltage output sampling module data within the previous 5ms based on the moment of the fault, including the DC bus voltage, output voltage, and current. The waveform and PWM output status are fully reproduced to recreate the electrical characteristics at the time of the fault. All data is encapsulated and stored in non-volatile memory via DMA to form a fault log file for fault analysis and diagnosis. At the same time, the DSP dynamically adjusts the recovery strategy of the PWM parameters according to the type of abnormality. If it is an overcurrent fault, the upper limit of the duty cycle is reduced; if it is an overvoltage fault, the voltage rise rate is limited to ensure that the recovery process is adapted to the fault characteristics and avoid secondary faults caused by improper parameters. After the operator eliminates the fault source and manually presses the reset button, the DSP control chip responds to the reset command and starts the soft start recovery process. According to the dynamically adjusted recovery strategy, the PWM duty cycle is gradually increased so that the output voltage and current rise slowly to the set value, ensuring that the electrical stress borne by the IGBT module during the recovery process is within a safe range. During the soft start, the collaborative protection strategy adjustment module continuously monitors the voltage and current data. If the protection threshold is triggered again, the recovery is immediately interrupted and the fault state is locked. This soft start mechanism effectively avoids current surges or voltage overshoots caused by direct recovery, ensuring the absolute safety and long-term reliability of the IGBT module in dynamic testing. The guided human-machine interface module uses an integrated touchscreen display to graphically and step-by-step guide the board and module testing processes. Testers simply need to click "start" and "stop" according to the on-screen prompts to complete the test. Waveforms, data, and fault codes are displayed in real time, reducing training costs and operational error rates, significantly improving operational convenience and testing standardization, and reducing reliance on training and the risk of misoperation. After power-on, the touchscreen loads the graphical test main interface. Based on the user-selected test mode (board or module test), it dynamically calls the corresponding step-by-step guidance page and highlights the current operation step, making the operation process intuitive and clear, effectively reducing the risk of misoperation by on-site personnel. During test execution, it analyzes the waveform characteristic data and fault codes uploaded by the DSP control chip in real time, dynamically draws voltage and current waveforms in a designated area on the screen, and displays the status of each channel and fault prompts in text form, achieving visual monitoring of the test process. This facilitates the immediate detection and location of abnormal conditions. After the test is completed, the complete test data (including parameter settings, waveform records, fault codes, and test conclusions) is automatically saved to local storage, and historical data query and export interfaces are provided to ensure that every test result is traceable and reproducible, facilitating subsequent analysis and quality archiving. It should be noted that after the operator powers on the touchscreen, a graphical test interface is automatically loaded. The interface clearly displays two mode options: board test and module test. When the user selects the board test mode, the touchscreen immediately calls up the corresponding step-by-step guide page, highlighting the operation process sequentially: first, connect the dedicated cable of the driver board to the test interface; then, start the power-on initialization program; and finally, enter the PWM pulse injection test stage. If the module test mode is selected, the guide page dynamically adjusts to the module connection check, high-voltage output setting, and load test steps. The entire guide process uses a combination of graphical symbols and text descriptions, with each step highlighted to ensure that on-site personnel can complete the test preparation step by step without referring to the manual, effectively reducing the risk of misoperation and improving testing efficiency. During the test execution, the touchscreen receives waveform characteristic data and fault codes uploaded by the DSP control chip in real time, and dynamically plots voltage and current waveforms in a coordinate axis format in a designated area of ​​the screen. The waveform refresh frequency is 4kHz, which is the same as the PWM carrier frequency. The system maintains Hz synchronization, ensuring operators can intuitively observe changes in the output of each phase. Simultaneously, the right side of the screen displays the current status in text format for each channel, including measured amplitude values, rise time, and pulse width data for the upper and lower arms of the U, V, and W phases. If a channel's characteristic value exceeds the preset tolerance range, the corresponding channel status immediately turns red and displays a specific fault message. This real-time display mechanism allows operators to grasp the test progress and any abnormalities immediately. After the test is completed, the complete test data is automatically packaged and saved to local non-volatile memory. The data package includes information such as test mode, parameter settings, waveform records, fault codes, and test conclusions. Operators can access the historical data query interface via the touchscreen, filtering and viewing past records by timestamp or test mode. Each record supports waveform playback and fault code parsing. Furthermore, a USB or RS485 export interface is provided for transferring data to external devices for in-depth analysis or archiving. This data storage and traceability function ensures that every test process is traceable and reproducible.

[0021] Example 2, as Figures 1 to 3 As shown, based on Embodiment 1, the present invention provides a technical solution: 1. The mechanical structure of the detector is as follows: The dimensions are 410mm (L) × 350mm (W) × 190mm (H); the material is modified PP alloy engineering plastic; the characteristics are IP54 level shock and drop resistance, waterproof and dustproof, high and low temperature resistance (-40℃ to +125℃), and chemical corrosion resistance, ensuring the safe transportation and use of the equipment in harsh industrial environments.

[0022] II. The hardware platform is as follows: The hardware platform consists of a control panel and a test host (comprising multiple circuit components such as power supply, control, and signal conversion). The test host is installed inside the enclosure, and the panel integrates all key interfaces and operating units in an ergonomic layout. Features include: a main power switch controlling AC220V input with an indicator light; an emergency stop button (red self-locking button to cut off all outputs in emergencies for safety); a system power indicator light showing the main power status; a touchscreen display as the core of the human-machine interface; test signal interfaces providing U, V, and W ribbon cable interfaces for connecting to the driver board and sending PWM drive signals; an auxiliary power output interface providing DC24V output to power the driver board; high-voltage output interfaces with "DC+" and "DC-" high-voltage terminals for providing an adjustable voltage from 0-1000VDC; and a measurement interface reserved for connecting an external oscilloscope probe or multimeter for in-depth monitoring.

[0023] III. The core minimum system design of the hardware circuit is as follows: (1) Power supply circuit: The DSP28335 core requires 1.9V (±0.1V), the I / O port requires 3.3V, and the instrument also needs a circuit with ±15V (op-amp) and +5V (other chips). A two-stage voltage regulation scheme is adopted. The first stage is a DC-DC switching regulator (such as TPS5430) to efficiently reduce the input voltage to +5V or +3.3V to power the subsequent LDO and some peripheral circuits. The second stage is a low dropout linear regulator (LDO). The core voltage is 1.9V: one of the dual LDOs such as TI's TPS767D301 is used. The I / O voltage is 3.3V: the other channel of the same LDO or a separate LDO (AMS1117-3.3) is used. (2) Clock circuit: Provides a stable clock source for the DSP. The DSP28335 supports a maximum operating frequency of 150MHz and uses a 30MHz passive crystal oscillator. The internal PLL of the DSP multiplies this reference clock to 150MHz (set the PLLCR register with a multiplication factor of 10). The crystal should be as close as possible to the X1 / X2 pins of the DSP and surrounded by ground lines to prevent high-frequency signal lines from passing through. (3) Reset circuit: A dedicated power monitoring chip (TPS3823) is used to generate a low-level active reset signal of at least 200ms when power is on, power is off or voltage drops, to ensure reliable DSP reset; (4) JTAG debugging interface: Designed to conform to 14-pin or 20-pin JTAG interface (compliant with IEEE 1149.1 standard) for connecting to emulators (XDS100, XDS510) for program download and online debugging.

[0024] IV. The design of key peripheral interface circuits is as follows: (1) PWM output circuit (drive pulse generation): generates 6 channels (3 pairs of complementary) 4kHz PWM waves to drive the board and IGBT module. The DSP's ePWM1 / 2 / 3 module generates the original 3 pairs of complementary PWM signals (EPWMxA / B); (2) Conditioning circuit: The conditioning circuit composed of operational amplifiers (such as OPA4350) offsets, amplifies and filters the sensor output to precisely adjust it to the DSP voltage input range (0-3.0V). An RC low-pass filter (such as 1kΩ+100pF) is added before the ADC input pin to filter out high-frequency noise. When laying out the PCB, the analog part and the digital part are routed separately, and the strategy of "single-point grounding" or "segmented ground plane, interconnected ferrite beads" is adopted. (3) Human-machine interface: communicates with the touch screen, receives instructions and sends data. Select industrial touch screens that support UART (RS232 / RS485) or Ethernet communication.

[0025] V. Design considerations are as follows: (1) Number of layers: Using a 4-layer board (top layer - signal, inner layer 1 - ground, inner layer 2 - power, bottom layer - signal) is a guarantee of stability and EMC performance; (2) Zone layout: High voltage / low voltage zoning: The high voltage section (sensor front end) and the low voltage section (DSP and peripherals) are strictly separated; Analog / Digital partitioning: The analog section (conditioning circuit, reference source) and the digital section (DSP, crystal oscillator) are laid out separately; (3) Wiring: Signal lines: Key signal lines (such as clock and PWM) should be as short as possible, and 90° right angle routing should be avoided; Decoupling capacitors: Place them as close as possible to the chip power supply pins.

[0026] VI. Basic parameters are shown in Table 1 below.

[0027] Table 1 Basic parameters of the inverter power module tester VII. Output characteristics, as shown in Table 2 below.

[0028] Table 2 Output characteristics of the inverter power module tester 8. Measurement characteristics, as shown in Table 3 below.

[0029] Table 3 Measurement characteristics of the inverter power module tester 8. Protection functions, as shown in Table 4 below.

[0030] Table 4 Protection Functions of the Inverter Power Module Tester

[0031] It should be noted that a simple method for judging driver board testing is as follows: Check the board components for overheating, metal foil detachment, wire burn-out, missing components, solder bridging, component damage, etc. Measure for short circuits. The measurement points are the +15V measurement point between J1 and J2 and the GND measurement point near J11S. Measure the +15V to GND (if the above problems are found, power on test after troubleshooting and resolving the problems). The power-on test method is as follows: (1) After there is no short circuit, connect the J2 port of the driver board to the test signal of the test device; (2) After the test device is powered on, observe whether the power indicator light is constantly on. The test can only be carried out if the three-phase indicator light is constantly off. The indicator light corresponding to the fault in the U-phase, V-phase, and W-phase will light up. (3) Click to enter the board test interface. Observe the D2 and D3 indicator lights of the driver board. If the D66 and D76 indicator lights are lit, it means that the driver board is faulty. Test again after the fault is dealt with. In the lower left corner, modify the frequency to 1000 and confirm. Then click Start at the command button. The waveform will be output on the display interface. If the measured value is abnormal, it can be temporarily determined that there is a fault in this channel of the driver board. Continue to test and check after the fault is found and resolved. (4) If the fault lights D76 and D66 light up during the test, click Stop and then Reset. Wait for the fault lights to go out and then test again. If the fault is still reported after multiple tests, it is determined that there is a hardware fault on the driver board that needs to be checked and resolved. (5) If the fault lights D38, D76 and D66 light up during the test, click Stop first and then Reset. Observe whether the connection between the driver board and the IGBT module is normal. Wait for the fault lights to go out and then perform the test. If the fault is still reported after multiple tests, it is determined that there is a hardware fault in the IGBT module that needs to be investigated and resolved. (6) Click Stop after the test is complete.

[0032] The judgment method for IGBT module testing is as follows: (1) Before testing the IGBT module, it is necessary to confirm that the board is functioning normally; (2) No-load test: After the IGBT module is powered on, turn on the test device, power the drive board, enter the test interface, and input a value between 0 and 255 in the data modification area in the lower left corner. Confirm and check whether the output voltage and output waveform are normal. (3) Load test: After the IGBT module is powered on, turn on the test device, power the drive board, enter the test interface, and enter the data modification area in the lower left corner. The maximum frequency can be 25. Confirm and click Start on the test interface. Use clamp meter, multimeter and other tools to measure whether the current and other values ​​are balanced.

[0033] The following is a detailed explanation of the workflow of this inverter power module tester.

[0034] After the operator selects the test mode and issues the start command via the touch screen, the tester executes the corresponding test process according to the selected mode. In the driver board test mode, the DSP control chip first calls the GPIO port to perform a power-on initialization scan of the key test points of the board to determine whether there is a short circuit or abnormality in the power supply. After confirming that it is normal, the ePWM module is activated to generate three pairs of complementary 6-channel 4kHz PWM pulse signals, which are sent to the board under test after active filtering, level offset and impedance matching conditioning. At the same time, the 16-bit ADC module synchronously acquires the six output pulses returned by the board at a sampling rate of 1MHz, and transmits them to the buffer memory via DMA. The DSP calls the floating-point arithmetic unit to perform point-by-point correlation calculation between the actual waveform and the standard template, extracts the amplitude, rise time and pulse width feature values ​​and compares them with the preset tolerance threshold. If there is an abnormality, the channel identifier is locked and uploaded to the touch screen for highlighting through an interrupt. In module testing mode, after the detector completes the board test and confirms that it is normal, it outputs a simulated given value to the high-voltage power supply control circuit through the DAC according to the set instructions, establishing an adjustable high-voltage DC bus from 0 to 1000VDC. The Hall sensor samples the voltage and current signals in real time and converts them into digital quantities through a 16-bit ADC for monitoring and protection judgment by the DSP. During the test, the collaborative protection strategy adjustment module performs dual comparison of the voltage and current data with the preset threshold using both hardware comparators and software logic. Once overvoltage, overcurrent, or short circuit characteristics are detected, the hardware-level PWM blocking circuit is activated immediately within 1μs to cut off the output. At the same time, the DSP records the electrical data within 5ms before and after the fault and dynamically adjusts the recovery strategy. The guided human-machine interaction module draws waveforms and displays the status of each channel and fault codes in real time throughout the process. After the test is completed, the complete data is automatically saved to the local memory, supporting historical query and export, ensuring that the test process is traceable and reproducible.

[0035] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A frequency converter power module tester, comprising a control panel, characterized in that, The control panel has the following communication connection modules: The multi-channel pulse analysis module is used to send PWM pulse signals to the driver board under test through the DSP control chip, and to filter and offset the output pulses in combination with the conditioning circuit. Through synchronous acquisition and waveform feature comparison, the abnormal channel of the driver board can be accurately located. The dual-source fault self-diagnosis isolation module is used to monitor the status of the fault indicator lights on the driver board by utilizing the real-time fault diagnosis logic of the DSP control chip. Combined with the self-diagnosis algorithm, it automatically distinguishes the fault source as an abnormality in the driver board or the IGBT module connection and displays the corresponding fault code on the touch screen. The high-voltage output sampling module is used to provide a programmable high voltage of 0-1000VDC during IGBT module load testing. At the same time, it samples the DC bus voltage, output voltage and current values ​​in real time through voltage / current sensors, and quickly converts analog quantities into digital quantities for processing by the DSP control chip. The collaborative protection strategy adjustment module is based on a dual protection mechanism of preset hardware-level fast shutdown and software dynamic adjustment. When a sudden drop in output voltage, overcurrent or short circuit is detected, the hardware-level protection can quickly shut down the PWM output within <1μs. At the same time, the DSP control chip dynamically adjusts the PWM parameters according to the abnormal waveform and records the abnormal waveform data. The guided human-machine interaction module is used to graphically and step-by-step guide the board testing process and module testing process through an integrated touch screen, and to display waveforms, data and fault codes in real time.

2. The inverter power module tester according to claim 1, characterized in that: The multi-channel pulse analysis module includes a PWM generation and conditioning unit and a multi-channel synchronous comparison unit; The PWM generation and conditioning unit, based on the ePWM module of the DSP control chip, generates three pairs of complementary six-channel PWM pulse signals. The built-in conditioning circuit offsets, amplifies, and filters the output pulses to eliminate high-frequency noise interference. The multi-channel synchronous comparison unit is used to synchronously acquire the output pulses returned by the driver board, and use the floating-point operation of the DSP control chip to perform real-time feature comparison of the input and output waveforms. When the waveform characteristics of a certain channel deviate from the preset threshold, the specific abnormal channel is immediately locked and identified.

3. The inverter power module tester according to claim 2, characterized in that: The PWM generation and conditioning unit specifically includes: In response to the test start command, the ePWM module configuration register of the DSP control chip is called to set the carrier frequency to 4kHz and the dead time, generating three pairs of complementary six-channel original PWM pulse signals. The original PWM pulse signal is introduced into an active filter and level offset circuit composed of an operational amplifier. By adjusting the feedback resistor and bias voltage, the signal level is calibrated to the receiving range of the interface of the driver board under test. The conditioned PWM pulse signal is output to the test interface through an impedance matching network. At the same time, a high-frequency bypass capacitor is connected in parallel at the output to filter out common-mode and differential-mode high-frequency interference induced during transmission.

4. The inverter power module tester according to claim 2, characterized in that: The multi-channel synchronous comparison unit specifically includes: The multi-channel parallel ADC sampling system synchronously acquires the output pulses of each phase returned after processing by the driver board under test, and converts the analog signal into digital waveform data, which is then stored in the buffer memory of the DSP control chip. The floating-point arithmetic unit built into the DSP control chip is called to perform point-by-point correlation calculation between the actual waveform data of each channel and the standard waveform template stored in Flash, and extract the amplitude, rise time and pulse width feature values. The feature values ​​of each channel are compared with the preset tolerance threshold. When the feature value of any channel exceeds the tolerance threshold range, the channel identifier is immediately locked, and the abnormal channel information is uploaded to the control panel through an interruption.

5. The inverter power module tester according to claim 2, characterized in that: The dual-source fault self-diagnosis and isolation module includes a board status monitoring unit and a fault tracing unit. The board status monitoring unit is used to monitor the voltage and fault indicator status changes of key test points on the driver board in real time through the GPIO interface of the DSP control chip or the auxiliary sampling circuit during the power-on test of the driver board, and generate a time-series status dataset to be uploaded to the control system in real time. The fault tracing unit is used to utilize a self-diagnostic algorithm based on a DSP control chip. When the fault indicator light is detected to be on, it makes a logical judgment based on the current test conditions and PWM output status. By analyzing the fault triggering timing and electrical characteristics, it automatically distinguishes the fault source and displays a clear fault code on the touch screen.

6. The inverter power module tester according to claim 5, characterized in that: The board status monitoring unit specifically includes: During the initial power-on phase of the driver board, the level status of key test points on the board is periodically scanned through the GPIO port and compared with the preset power-on initial status table to determine whether there is a short circuit or power supply abnormality. During the PWM pulse signal injection test, the auxiliary sampling circuit captures the level transition of the corresponding pin of the fault indicator on the board in real time, and records the precise timestamp of the transition and the corresponding test conditions. The collected state change data is associated with and packaged with the current PWM output channel and load connection status to form a time-series state dataset.

7. The inverter power module tester according to claim 5, characterized in that: The fault tracing unit specifically includes: Receive the time-series status dataset from the board status monitoring unit, and based on the fault indicator light transition timestamp, trace back the PWM output status and load access flag bit within a few milliseconds before that moment; The built-in self-diagnostic logic algorithm is invoked. When a fault occurs, if the PWM pulse signal output is normal and the device is in no-load condition, it is determined to be a hardware fault of the driver board itself; if the device is in load condition and accompanied by abnormal current sampling, it is determined to be an abnormal connection of the IGBT module. Based on the judgment result, the corresponding fault code and fault definition are retrieved from the fault code library, sent to the touch screen display via the communication interface, and the current test interface is locked until manually reset.

8. A frequency converter power module tester according to claim 5, characterized in that: The high-voltage output sampling module specifically includes: It receives voltage setting instructions from the control panel, outputs an analog setpoint to the high-voltage power supply control circuit via DAC, adjusts the duty cycle of the DC-DC converter, and establishes a 0-1000VDC programmable high voltage at the output. A high-precision Hall voltage sensor and a current sensor are connected in series in the high-voltage output circuit to isolate and convert the high-voltage signal into a low-voltage analog signal in the range of 0-3V, which is then input to a 16-bit ADC converter. The ADC continuously converts analog voltage and current quantities at a preset sampling rate. The DSP control chip reads the conversion results through DMA and performs digital filtering and scaling transformation, updating the system monitoring variable area in real time.

9. A frequency converter power module tester according to claim 8, characterized in that: The collaborative protection strategy adjustment module specifically includes: The real-time voltage and current data obtained by the high-voltage output sampling module are compared with the preset overcurrent, overvoltage and short-circuit protection thresholds by both hardware comparators and software logic. If any condition is triggered, the hardware-level PWM blocking circuit will be activated immediately. While the hardware shuts down the PWM output, the DSP control chip responds to the protection interrupt, reads the voltage and current waveform data at the moment of the fault and stores it in non-volatile memory, and dynamically adjusts the recovery strategy of the PWM parameters according to the type of abnormality. After the fault source is eliminated, respond to the reset command and gradually restore PWM output according to the dynamically adjusted soft-start strategy.

10. A frequency converter power module tester according to claim 9, characterized in that: The guided human-computer interaction module specifically includes: After power-on, the touchscreen loads the graphical test main interface, dynamically calls the corresponding step guide page and highlights the current operation step according to the test mode selected by the user; During the test execution, the waveform feature data and fault codes uploaded by the DSP control chip are analyzed in real time, and the voltage and current waveforms are dynamically drawn in the specified area of ​​the screen, and the status of each channel and fault prompts are displayed in text form. After the test is completed, the complete data of this test will be automatically saved to local storage, and an interface for querying and exporting historical data will be provided.

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