An artificial short circuit test system, method and apparatus

Abstract

This invention discloses a system, method, and equipment for artificial short-circuit testing, relating to the field of power engineering technology. The system includes a test network circuit, a programmable fault branch, and a processor. By setting up the test network circuit, this invention equivalently maps the short-circuit conditions on the target high-voltage side of an actual power station to the corresponding low-voltage side in the test network circuit. This enables the reproduction of typical power station fault environments in the laboratory and covers both grid-connected and off-grid operation modes, making the test results closer to actual engineering conditions. Through the programmable fault branch and processor, fault initiation and isolation can be transformed from manual operation to automated condition triggering, ensuring the test is implemented stably according to the expected plan and improving the repeatability and comparability of artificial short-circuit tests. Furthermore, by utilizing the programmable impedance capability of the programmable fault branch to achieve progressive fault injection and / or progressive fault exit, it can reduce current surges and decrease the probability of protection malfunctions and equipment stress.

Description

Technical Field

[0001] This invention relates to the field of power engineering technology, and in particular to an artificial short-circuit test system, method and equipment. Background Technology

[0002] With the high proportion of renewable energy integration, the voltage source structure of the power system has undergone significant changes. Energy storage converters and their clusters are taking on increasing responsibilities for voltage support, inertia support, transient stability enhancement, and power quality management under weak grid conditions. Fault ride-through capability and fault process control stability have become common concerns for equipment access, grid connection acceptance, dispatch operation, and project delivery. Artificial short-circuit testing, as a key means of verifying equipment transient support capability, the rationality of current limiting strategies, the effectiveness of protection coordination, and post-fault recovery performance, plays an irreplaceable role in practical engineering.

[0003] However, conducting artificial short-circuit tests in real-world sites typically faces constraints such as long preparation periods, high organizational costs, and significant risks and consequences. Furthermore, existing artificial short-circuit tests largely rely on manual configuration and on-site operation, lacking a unified test script description language and automated execution mechanism, making it difficult to standardize and solidify various indicators. The key to artificial short-circuit testing lies in the determinism of the fault injection process; traditional hard short-circuit methods result in problems such as a large current rise slope, high peak values, and uncontrollable DC components. Therefore, how to conveniently conduct automated artificial short-circuit tests, ensure stable implementation according to the expected plan, and improve the repeatability and comparability of artificial short-circuit tests are urgent problems that need to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide an artificial short-circuit test system, method, and equipment to facilitate automated artificial short-circuit testing, ensure that the test is carried out stably according to the expected plan, and improve the repeatability and comparability of artificial short-circuit tests.

[0005] To solve the above-mentioned technical problems, the present invention provides an artificial short-circuit test system, comprising: a test network circuit, a programmable fault branch, and a processor; The test network circuit includes an energy storage power station converter cluster, a first transformer, a first adjustable impedance, and a power grid simulation source. The energy storage power station converter cluster is connected to the power grid simulation source through the first transformer and the first adjustable impedance connected in series. The test network circuit is used to equivalently map the short-circuit condition of the target high-voltage side in the test site to the low-voltage side at the common coupling point connected to the energy storage power station converter cluster, according to the configuration of the first transformer and the first adjustable impedance. The programmable fault branch includes: a main switching circuit, an impedance network, and an impedance switching device; the main switching circuit and the impedance network are connected in series to the common coupling point; the impedance network includes multiple levels of resistors and reactances; the main switching circuit is used to inject or remove a fault of the target fault type according to the control of the processor; the impedance switching device is connected in parallel with the impedance network and is used to switch the impedance level of the impedance network according to the control of the processor; the target fault type is any preset fault type; the preset fault type includes at least one of three-phase short circuit, two-phase short circuit, and single-phase grounding; The processor is used to acquire three-phase electrical information at the common coupling point; when the three-phase electrical information meets the point wave triggering conditions of the artificial short-circuit script, it sends corresponding fault activation triggering instructions and / or fault clearing triggering instructions to the main switching circuit and the impedance switching device to control the programmable fault branch to achieve progressive fault injection and / or progressive fault exit.

[0006] On the other hand, the energy storage power station converter cluster includes a first number of energy storage subarrays, a second transformer, and a second adjustable impedance; Each of the energy storage subarrays is connected to the common coupling point through its corresponding series-connected second transformer and second adjustable impedance; each of the energy storage subarrays includes a second number of parallel-connected energy storage simulation converter units; each of the energy storage simulation converter units includes a series-connected energy storage battery simulator and an energy storage converter.

[0007] On the other hand, each of the energy storage analog converter units is provided with a first controllable switch at both ends to control the number of energy storage analog converter units activated in the energy storage subarray; the i-th energy storage analog converter unit in each energy storage subarray is connected in parallel with the (i+1)-th energy storage analog converter unit through a second controllable switch; where i is a positive integer greater than or equal to 1 and less than or equal to n-1, and n is the second quantity.

[0008] On the other hand, the energy storage converter adopts an active midpoint clamping topology with a common-mode current loop.

[0009] On the other hand, the first quantity is 3, the second quantity is 16, and the low-voltage side at the common coupling point is the 690V side.

[0010] On the other hand, the point wave triggering conditions include at least one of the following: the specified phase voltage is within the zero-crossing range, the specified phase voltage phase angle reaches a preset angle, the specified line voltage amplitude reaches a preset threshold, and the phase-locked synchronization conditions are met.

[0011] On the other hand, the system also includes: A grid-connected / off-grid switching circuit is used to switch between grid-connected and off-grid operating conditions; wherein, the grid simulation source is connected to the grid bus through the grid-connected / off-grid switching circuit; the energy storage power station converter cluster is connected to the grid bus through a first transformer and a first adjustable impedance connected in series.

[0012] On the other hand, the test network circuit also includes: a power generation and supply unit, a third transformer, and a third adjustable impedance; wherein, the power generation and supply unit includes: a photovoltaic power station inverter cluster, a wind power station converter cluster, and / or a synchronous generator; Each of the power generation and supply units is connected to the power grid bus via its corresponding series-connected third transformer and third adjustable impedance.

[0013] On the other hand, the processor is specifically configured to, when the three-phase electrical information meets the fault activation triggering condition, control the main switch circuit to inject the fault of the target fault type and control the impedance switching device to switch the impedance network to the first impedance level; when the first delay is reached or the voltage drop threshold condition is met, control the impedance switching device to switch the impedance network to the target impedance level; wherein, the impedance of the first impedance level is greater than the impedance of the target impedance level. When the three-phase electrical information meets the fault clearing trigger condition, the impedance switching device is controlled to switch the impedance network to the second impedance level; after the fault current decreases and the system transiently converges, the main switching circuit is controlled to clear the fault.

[0014] On the other hand, the processor is also configured to generate the artificial short-circuit script according to the acquired test script generation instructions; wherein the artificial short-circuit script includes at least one of the following: fault type information, fault location information, equivalent impedance information, fault duration information, fault injection information, fault exit information, and data acquisition window and acceptance index information.

[0015] On the other hand, the processor is also configured to perform executability verification and risk pre-assessment on the artificial short-circuit script before executing the artificial short-circuit script; if the verification and pre-assessment pass, the artificial short-circuit script is executed; if the verification and / or pre-assessment fail, a script problem prompt message is output.

[0016] On the other hand, the processor is also used to control the energy storage power station converter cluster using a conventional steady-state control strategy in the pre-fault stage; to control the energy storage power station converter cluster using a safety and stability priority strategy in the fault stage; and to control the energy storage power station converter cluster using a smooth recovery strategy in the post-fault stage.

[0017] On the other hand, the safety and stability priority strategy includes at least one of fault current limiting, virtual impedance adjustment, and power reference and voltage reference adjustment; the smooth recovery strategy includes at least one of fault exit identification, gradual recovery of control parameters, and power recovery rate limiting.

[0018] The present invention also provides an artificial short-circuit test method, applied to the artificial short-circuit test system as described above, comprising: The processor acquires the three-phase electrical information at the common coupling point; Determine whether the three-phase electrical information meets the point wave triggering conditions of the artificial short circuit script; If so, a corresponding fault activation trigger command and / or fault clearance trigger command are sent to the fault branch in the artificial short-circuit test system to control the programmable fault branch to implement progressive fault injection and / or progressive fault exit.

[0019] Furthermore, the present invention also provides an artificial short-circuit test device, comprising: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the artificial short-circuit test method as described above.

[0020] The present invention provides an artificial short-circuit test system, comprising: a test network circuit, a programmable fault branch, and a processor; wherein, the test network circuit includes an energy storage power station converter cluster, a first transformer, a first adjustable impedance, and a power grid simulation source, the energy storage power station converter cluster being connected to the power grid simulation source via the first transformer and the first adjustable impedance in series, the test network circuit being used to equivalently map the short-circuit conditions of the target high-voltage side in the test site to the low-voltage side at the common coupling point connected to the energy storage power station converter cluster according to the configuration of the first transformer and the first adjustable impedance; the programmable fault branch includes: a main switch circuit, an impedance network, and an impedance switching device; the main switch circuit and the impedance network in series are connected to the common coupling point; the impedance network... The network includes multi-level resistors and reactances; the main switching circuit is used to inject or remove faults of the target fault type according to the control of the processor; the impedance switching device is connected in parallel with the impedance network and is used to switch the impedance level of the impedance network according to the control of the processor; the target fault type is any preset fault type; the preset fault type includes at least one of three-phase phase-to-phase short circuit, two-phase short circuit and single-phase grounding; the processor is used to acquire the three-phase electrical information at the common coupling point; when the three-phase electrical information meets the point wave triggering conditions of the artificial short circuit script, it sends corresponding fault entry triggering instructions and / or fault removal triggering instructions to the main switching circuit and the impedance switching device to control the programmable fault branch to achieve progressive fault injection and / or progressive fault exit.

[0021] As can be seen, this invention, through the setup of the test network circuit, equivalently maps the short-circuit conditions on the target high-voltage side of the actual substation to the corresponding low-voltage side in the test network circuit. This enables the reproduction of typical substation fault environments in the laboratory and covers both grid-connected and off-grid operation modes, making the test results closer to engineering reality and reducing deviations caused by issues such as nonlinear saturation, protection coordination, and discrete implementation that are difficult to cover through simulation alone. By setting up programmable fault branches and processors, fault initiation and isolation can be transformed from manual operation to automated condition triggering, ensuring the stable implementation of the test according to the expected plan and improving the repeatability and comparability of manual short-circuit tests. Furthermore, utilizing the programmable impedance capability of the programmable fault branches to achieve progressive fault injection and / or progressive fault exit can reduce current surges and decrease the probability of protection malfunctions and equipment stress. In addition, this invention also provides a method and equipment for artificial short-circuit testing, which also have the above-mentioned beneficial effects. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0023] Figure 1 This is a structural block diagram of an artificial short-circuit test system provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another artificial short-circuit test system provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a converter cluster for an energy storage power station provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating a short-circuit ratio calculation provided in an embodiment of the present invention; Figure 5 This is a diagram illustrating an artificial short-circuit test location provided in an embodiment of the present invention. Figure 6 A flowchart of an artificial short-circuit test method provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of an artificial short-circuit test device provided in an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Please refer to Figure 1 , Figure 1 This is a structural block diagram of an artificial short-circuit test system provided in an embodiment of the present invention. The system may include: a test network circuit 10, a programmable fault branch 20, and a processor 30; The test network circuit 10 includes an energy storage power station converter cluster 11, a first transformer 12, a first adjustable impedance 13, and a grid simulation source 14. The energy storage power station converter cluster 11 is connected to the grid simulation source 14 through the first transformer 12 and the first adjustable impedance 13 connected in series. The test network circuit 10 is used to map the short-circuit conditions of the target high-voltage side in the test site to the low-voltage side at the common coupling point connected to the energy storage power station converter cluster 11 according to the configuration of the first transformer 12 and the first adjustable impedance 13. The programmable fault branch 20 includes: a main switch circuit 21, an impedance network 22, and an impedance switching device 23; the main switch circuit 21 and the impedance network 22, connected in series, are connected to a common coupling point; the impedance network 22 includes multiple levels of resistors and reactances; the main switch circuit 21 is used to inject or remove faults of the target fault type according to the control of the processor 30; the impedance switching device 23 is connected in parallel with the impedance network 22 and is used to switch the impedance level of the impedance network 22 according to the control of the processor 30; the target fault type is any preset fault type; the preset fault type includes at least one of three-phase short circuit, two-phase short circuit, and single-phase grounding; The processor 30 is used to acquire three-phase electrical information at the common coupling point; when the three-phase electrical information meets the point wave triggering conditions of the artificial short circuit script, it sends corresponding fault entry triggering instructions and / or fault clearing triggering instructions to the main switch circuit 21 and the impedance switching device 23 to control the programmable fault branch 20 to realize progressive fault injection and / or progressive fault exit.

[0026] It is understood that the test network circuit 10 in this embodiment can be a grid structure constructed to be equivalent to the grid structure of the actual energy storage station (i.e., the station under test) for artificial short-circuit testing. This embodiment takes the artificial short-circuit test of the energy storage power station converter cluster 11 corresponding to the actual energy storage station as an example for demonstration. That is, the energy storage power station converter cluster 11 is used as the test object, and the artificial short-circuit test of the energy storage power station converter cluster 11 is used to simulate the artificial short-circuit test of the actual energy storage station.

[0027] Correspondingly, the specific structure of the experimental network circuit 10 in this embodiment can be set by the designer according to the practical scenario and user needs. For example, the power grid simulation source 14 can be directly connected to the power grid bus. Figure 2 The 1140V grid bus is used to simulate a 110kV bus. The grid simulation source 14 can also be connected to the grid bus via a grid-connected / off-grid switching circuit to connect or disconnect the grid simulation source 14 from the grid bus, switching between grid-connected and off-grid operating conditions. In other words, the test network circuit 10 can also include a grid-connected / off-grid switching circuit for switching between grid-connected and off-grid operating conditions; wherein, the grid simulation source 14 is connected to the grid bus via the grid-connected / off-grid switching circuit; the energy storage power station converter cluster 11 is connected to the grid bus via a first transformer 12 and a first adjustable impedance 13 connected in series.

[0028] Correspondingly, such as Figure 2 As shown, the test network circuit 10 provided in this embodiment may also include local load and / or remote load to simulate the load connected to the site under test.

[0029] In order to simulate the short-circuit conditions on the high-voltage side of the test site (such as artificial short-circuit conditions on the 35kV side), for example, an environment where the high-voltage side of the test site experiences artificial short circuits such as three-phase phase-to-phase short circuits, two-phase short circuits, and single-phase grounding, this embodiment can establish an equivalent mapping rule on the low-voltage side (such as the 690V side) at the point of common coupling (PCC) where the energy storage power station converter cluster 11 is connected. The equivalent mapping can include at least the following elements. First, short-circuit ratio matching; by selecting the equivalent voltage source capacity and equivalent impedance of the upstream grid simulation source 14, and combining it with the adjustable line impedance level of the system, the precise setting within the target short-circuit ratio range can be achieved, so that the equivalent short-circuit capacity of the 690V side common coupling point before the fault is consistent with or controllably close to the target scenario on the 35kV side. Secondly, equivalent impedance conversion: Based on the transformer turns ratio and impedance conversion relationship, the equivalent impedance of the target fault on the 35kV side is converted to the 690V side as the target setting for the programmable impedance of the fault branch. The conversion can include not only impedance amplitude but also impedance angle characteristics to simulate resistive faults, reactive faults, and mixed fault conditions when needed. Thirdly, consistent operating modes: Under grid-connected conditions, the energy storage subarray operates with a given power factor or given voltage support strategy, and the grid simulation source 14 provides frequency reference and voltage stiffness. Under off-grid conditions, the energy storage subarray acts as a voltage source and maintains local voltage and frequency. The load model can be configured as resistive load, inductive load, rectifier load, or mixed load to cover operating conditions with different recovery difficulties after faults. Fourthly, consistent measurement and protection boundaries: Based on the characteristics of the measurement link and protection link of the converter under test controller, sampling filtering, limiting links, protection thresholds, action delays, and reclosing strategies are configured to make the triggering boundaries of control and protection traceable and reproducible during the test.

[0030] Correspondingly, the energy storage power station converter cluster 11 may include a first number of energy storage subarrays, a second transformer, and a second adjustable impedance; wherein, each energy storage subarray is connected to a common coupling point through its corresponding series-connected second transformer and second adjustable impedance; each energy storage subarray includes a second number of parallel-connected energy storage simulation converter units; each energy storage simulation converter unit includes a series-connected energy storage battery simulator (such as... Figure 3 (DC source simulation in the laboratory) and power conversion system (PCS). For example, the first number of energy storage subarrays can be set up in a cabinet in the laboratory.

[0031] Accordingly, to facilitate the configuration of the number of energy storage analog converter units activated in the energy storage subarray, such as Figure 3As shown, in this embodiment, each energy storage analog converter unit is provided with a first controllable switch at both ends to control the number of energy storage analog converter units activated in the energy storage subarray; the i-th energy storage analog converter unit in each energy storage subarray is connected in parallel with the (i+1)-th energy storage analog converter unit through a second controllable switch; where i is a positive integer greater than or equal to 1 and less than or equal to n-1, and n is the second quantity.

[0032] Correspondingly, in this embodiment, the energy storage converter in the energy storage analog converter unit can adopt an active neutral point clamp (ANPC) topology with a common-mode current loop. For example... Figure 3 As shown, 1) Energy storage simulation converter unit (×16 / cluster / subarray), each unit can consist of a 20kW energy storage battery simulator + energy storage converter (energy storage PCS), rated voltage level 380V. The energy storage battery simulator can provide a programmable DC source to reproduce the characteristics of battery open circuit voltage, internal resistance, SOC (State of Charge), dynamic power limiting, etc.; the energy storage converter completes DC / AC energy conversion and grid-connected control. 2) Inverter topology and parallel system, the energy storage converter adopts ANPC topology with common mode current loop, 16 grid-connected inverters share AC bus (380V side) and are connected in parallel to the low-voltage side of cluster transformer (first transformer 12) after LCL filtering; the constraint of ANPC + common mode loop can significantly reduce the common mode current and dv / dt of the parallel system. It should be combined with carrier phase stagger / random spread spectrum and zero sequence / circulating current suppression strategies to ensure the stability of multi-machine parallel connection. 3) Cluster transformers and busbars: Each cluster is equipped with a 240kVA, 380 / 690V transformer (first transformer 12) connected to a 690V common busbar; three transformers are connected in parallel throughout the field, forming an equivalent 720kVA 690V busbar capacity (per unit mapped to the 35kV side for system-level calculations). That is to say, the first number can be 3, the second number can be 16, and the low-voltage side at the common coupling point can be the 690V side.

[0033] Furthermore, in this embodiment, the processor can also be used to configure the test network circuit 10 (such as the first transformer 12, the first adjustable impedance 13, the second transformer, the second adjustable impedance, and the controllable switch, etc.) according to user instructions or a manual short-circuit script, so that the short-circuit condition of the target high-voltage side in the test site is equivalently mapped to the low-voltage side at the common coupling point connected to the energy storage power station converter cluster 11. For example, the processor can configure the test network circuit 10 according to the short-circuit condition of the target high-voltage side in the manual short-circuit script, so that it is equivalently mapped to the low-voltage side at the common coupling point connected to the energy storage power station converter cluster 11.

[0034] For example, the calculation of the short-circuit ratio in this embodiment may include the following two calculation processes for short-circuit capacity. For example... Figure 4As shown, the grid-side voltage of the system is 115kV, connected to a 100MW load via overhead line L1, transformer T, and cable L2. The line impedance of L1 is 16Ω, and that of L2 is 0.04Ω. The transformer reduces the voltage from 115kV to 6.3kV; its capacity is 31.5MVA, and its short-circuit impedance is 10.5%. For a specific device or impedance in the line, its short-circuit capacity is: Where U1 represents the voltage of the line where the device is located, and Z1 is its impedance value. Figure 4 The short-circuit capacity of line L1 in the diagram is: The short-circuit capacity corresponding to transformer T is 300MVA. Figure 4 The short-circuit capacity corresponding to line L2 in the diagram is: .

[0035] If in Figure 4 A short circuit occurs at point K. From point K's perspective, L1, transformer T, and L2 are in series. The short-circuit capacity at point K is affected by all three, and its calculation method is similar to the parallel equivalent of admittance. Let its short-circuit capacity be Sk, then... , Let T be the short-circuit capacity of transformer T; we obtain Sk = 180MVA; if point K is connected to a 100MVA load or a new energy power station, then... If the VA is 100MVA, then the short-circuit ratio at point K is: Through the above mapping and configuration, this embodiment can form a repeatable and switchable artificial short-circuit test platform in a laboratory environment, providing consistent preconditions for subsequent controllable fault injection and control strategy verification.

[0036] It should be noted that the programmable fault branch 20 can be set at a common coupling point (e.g., Figure 5Near the test point (in the test), fault types such as three-phase phase-to-phase short circuit, two-phase short circuit, and single-phase grounding can be injected according to test requirements. The programmable fault branch 20 may include a main switch circuit 21, an impedance network 22, and an impedance switching device 23; the main switch circuit 21 can be used to realize the connection and disconnection of the programmable fault branch 20, that is, the main switch circuit 21 can be used to inject or disconnect faults of the target fault type according to the control of the processor 30; the target fault type is any preset fault type; the preset fault type includes at least one of three-phase phase-to-phase short circuit, two-phase short circuit, and single-phase grounding. The main switch circuit 21 may include fault switching switches for realizing the injection and disconnection of the target fault type. For example, the number of fault switching switches can be 9, and each phase line is connected to the impedance network 22 through 3 fault switching switches in series, so that the processor 30 can inject or disconnect faults of the target fault type by controlling the on and off of these 9 fault switching switches. The main switching circuit 21 may also include a main circuit breaker for controlling whether the programmable fault branch 20 is connected to the common coupling point, i.e., the fault switching switch can connect the three-phase line at the common coupling point through the main circuit breaker; the main circuit breaker may preferably be a high-speed controllable switch or a combination switch with consistent opening and closing characteristics, and the processor 30 implements the deterministic operating timing. The switching devices (such as the main circuit breaker) in the main switching circuit 21 may also have status feedback and mechanical or electrical position confirmation functions for closed-loop verification of script execution.

[0037] Correspondingly, the impedance network 22 can include multiple levels of resistors and reactances, forming a discrete set of switchable impedance levels. Each level is determined by the impedance value and allowable energy, satisfying the thermal capacity and short-term electrodynamic constraints during the fault duration. The impedance network 22 can support series and parallel combinations to expand the equivalent impedance range and refine the resolution. The impedance switching device 23 can be used to switch the impedance levels of the impedance network 22 according to the control of the processor 30, such as switching the impedance levels in a predetermined sequence during the fault process; its operating speed and consistency directly determine the controllability of the fault current slope and the fault exit impact suppression capability. The impedance switching device 23 can be used to realize progressive fault injection and progressive fault exit; such as two-stage or multi-stage progressive fault injection and progressive fault exit. For example, when a fault is initiated, a larger impedance is first applied to achieve a slight short circuit to suppress the current rise slope and DC component, and then the target impedance level is switched when the set delay or the set voltage drop threshold condition is met to obtain the target voltage drop depth and the target fault current amplitude. When clearing a fault, the system first switches from the target impedance back to a larger impedance. After the current decreases and the system transiently converges, the main switch is then disconnected, which significantly reduces the impact of fault clearing and reduces the probability of secondary oscillation triggering.

[0038] In other words, the processor 30 can be used to control the main switch circuit 21 to inject a fault of the target fault type and control the impedance switching device 23 to switch the impedance network 22 to the first impedance level when the three-phase electrical information meets the fault input triggering conditions; when the first delay is reached or the voltage drop threshold condition is met, control the impedance switching device 23 to switch the impedance network 22 to the target impedance level; wherein the impedance of the first impedance level is greater than the impedance of the target impedance level; when the three-phase electrical information meets the fault clearing triggering conditions, control the impedance switching device 23 to switch the impedance network 22 to the second impedance level; and after the fault current decreases and the system transiently converges, control the main switch circuit 21 to clear the fault.

[0039] Correspondingly, in this embodiment, the processor 30 can acquire three-phase electrical information at the common coupling point, such as collecting the phase voltage and phase current on the 690V side, calculating the phase angle, zero-crossing time, or the required phase; when the three-phase electrical information meets the point wave triggering conditions of the artificial short-circuit script, it sends corresponding fault entry triggering commands and / or fault exit triggering commands to the main switch circuit 21 and impedance switching device 23 to control the programmable fault branch 20 to achieve progressive fault injection and / or progressive fault exit. The point wave triggering conditions may include at least one of the following: the specified phase voltage is within the zero-crossing range, the specified phase voltage phase angle reaches a preset angle, the specified line voltage amplitude reaches a preset threshold, and the phase-locked synchronization conditions are met; through point wave triggering, the initial phase consistency of fault injection is significantly improved, and the repeatability of fault current peak value and waveform shape is significantly improved. In the above-mentioned programmable fault branch 20 and point wave triggering design, this embodiment transforms short-circuit injection from a hard short-circuit to a programmable impedance short-circuit process, and from manual closing to phase condition triggering, realizing the dual determinism of fault injection amplitude and timing.

[0040] Furthermore, to meet the goals of stable and controllable current limiting during short circuits, no loss of transient voltage support capability, and smooth recovery after a fault, this embodiment can divide the control strategy into three stages: pre-fault, during-fault, and post-fault. This is linked with script triggering and the actions of the programmable fault branch 20 to achieve adaptive parameter switching. For example, the processor 30 can also be used to control the energy storage power station converter cluster 11 using a conventional steady-state control strategy in the pre-fault stage; a safety and stability priority strategy in the during-fault stage; and a smooth recovery strategy in the post-fault stage.

[0041] In the pre-fault phase, the system operates under steady-state conditions, executing conventional control strategies according to grid-connected or off-grid conditions. Under grid-connected conditions, grid-following or grid-connected control can be adopted, selecting steady-state parameter settings based on the short-circuit ratio and line impedance levels, including voltage loop bandwidth, current loop bandwidth, virtual impedance coefficient, power loop slope, and limiting settings. Under off-grid conditions, the energy storage subarray acts as a voltage source, needing to maintain voltage and frequency and possess a certain degree of immunity to load disturbances. The key at this stage is establishing a steady-state operating point that matches the target scenario and obtaining the current equivalent grid strength indicators through online identification or parameter calculation, providing a basis for parameter switching during faults.

[0042] During the fault phase, from fault initiation to fault clearance, the control strategy enters a safety and stability priority mode. Its core is current limiting for stable and controllable operation, while maintaining a certain voltage support capability to avoid voltage collapse or control saturation instability. The following combined measures can be adopted: First, current limiting strategy switching; based on current limiting triggering or voltage drop triggering conditions, switch to fault current limiting mode, clearly defining the current limiting method and priority strategy to ensure that the current does not exceed the safety boundary and that the control command does not undergo undesirable reversals. Second, virtual impedance adjustment; during the fault, appropriately increase the virtual impedance or add a damping term to suppress low-frequency and mid-frequency oscillations and reduce the risk of circulating current in multi-machine parallel connections; this adjustment should be coordinated with the impedance sequence of the fault branch to prevent the superposition of the two from causing excessive voltage drops. Third, transient reconstruction of power and voltage references. During the fault, the power reference can be slope-limited or transiently frozen, and the voltage reference can be droop-characteristically corrected or voltage support prioritized, thereby avoiding current saturation caused by strong power loop drive and triggering controller integral saturation.

[0043] In the post-fault phase, from fault clearing to steady-state recovery, the control strategy enters a smooth recovery mode. The main risks in this phase are secondary power and voltage oscillations, and circulating current amplification under multi-machine parallel conditions. To address this, this embodiment employs the following layered exit and gradual recovery strategies: First, exit criteria. Exit is predicated on the common coupling point voltage recovering above a threshold and the oscillation amplitude decaying below a threshold. Frequency deviation, phase angle change rate, current harmonic content, or circulating current estimation can be used as auxiliary criteria to ensure that the fault parameter range is not prematurely exited while the system is still in a high-energy transient state. Second, gradual parameter adjustment. Damping and virtual impedance coefficients, current limiting parameters, power slope limits, etc., increased during the fault phase are gradually transitioned back to the steady-state range using time constants or state variables to avoid secondary impacts caused by a one-step back. Third, power recovery rate limiting. A slope limiting and segmented recovery strategy is adopted for the recovery of active and reactive power references. Voltage support and reactive power regulation capabilities are restored first, and then active power output is gradually restored to avoid voltage and power coupling oscillations caused by a rapid increase in active power before the voltage is fully stable. By combining a three-stage adaptive strategy with the gradual exit of fault branches, this embodiment reduces system energy fluctuations at the moment of fault clearing, significantly suppresses secondary oscillations, and improves the stability margin of multi-machine parallel operation.

[0044] In other words, the safety and stability priority strategy may include at least one of fault current limiting, virtual impedance adjustment, and power reference and voltage reference adjustment; the smooth recovery strategy may include at least one of fault exit identification, gradual recovery of control parameters, and power recovery rate limiting.

[0045] Correspondingly, in this embodiment, the processor 30 can execute a manual short-circuit script to implement the aforementioned three-stage adaptive strategy and the progressive fault injection and exit of the programmable fault branch 20. The method provided in this embodiment may also include a manual short-circuit script generation process. For example, the processor 30 can also generate a manual short-circuit script based on the acquired test script generation instructions to achieve automatic generation of the manual short-circuit script. The manual short-circuit script includes at least one of the following: fault type information, fault location information, equivalent impedance information, fault duration information, fault injection information, fault exit information, and data acquisition window and acceptance indicator information.

[0046] Furthermore, the processor 30 can also be used to perform executability verification and risk pre-assessment of the artificial short-circuit script before execution; if the verification and pre-assessment pass, the artificial short-circuit script is executed; if the verification and / or pre-assessment fail, a script problem prompt message is output. In other words, before executing a formally describable artificial short-circuit script, the processor 30 can perform executability verification and risk pre-assessment of the artificial short-circuit script based on the parameters of the system under test, protection settings, and equipment capability boundaries, ensuring that the test is carried out stably as expected.

[0047] Furthermore, the test network circuit 10 may also include: a power generation and supply unit, a third transformer, and a third adjustable impedance; each power generation and supply unit is connected to the grid bus via its corresponding series-connected third transformer and third adjustable impedance. The power generation and supply unit includes: a photovoltaic power station inverter cluster, a wind power station converter cluster, and / or a synchronous generator, such as... Figure 2 As shown, the power generation and supply unit may include a photovoltaic power station inverter cluster, a wind power station converter cluster, and a synchronous generator.

[0048] Correspondingly, in this embodiment, the programmable fault branch 20 may also include fault injection and exit for all or part of the target fault types corresponding to the power generation and supply units, according to the control of the processor 30. If the circuit structure connected to the energy storage power station converter cluster 11 is the same or similar as described above, this embodiment does not impose any restrictions on this.

[0049] In this embodiment, the present invention uses the test network circuit 10 to map the short-circuit conditions of the target high-voltage side in the actual site to the corresponding low-voltage side in the test network circuit 10. This enables the reproduction of typical site fault environments in the laboratory and covers both grid-connected and off-grid operation modes, making the test results closer to engineering reality and reducing deviations caused by nonlinear saturation, protection coordination, and discrete implementation issues that are difficult to cover by simulation alone. Through the programmable fault branch 20 and processor 30, fault initiation and isolation can be transformed from manual operation to automated condition triggering, ensuring that the test is stably implemented according to the expected plan and improving the repeatability and comparability of manual short-circuit tests. Furthermore, by utilizing the programmable impedance capability of the programmable fault branch 20 to achieve progressive fault injection and / or progressive fault exit, current surges can be reduced, and the probability of protection malfunction and equipment stress can be reduced.

[0050] Corresponding to the system embodiments above, this invention also provides an artificial short-circuit test method. The artificial short-circuit test method described below and the artificial short-circuit test system described above can be referred to and corresponded to each other.

[0051] Please refer to Figure 6 , Figure 6 A flowchart illustrating an artificial short-circuit test method provided in an embodiment of the present invention. This method, applied to the artificial short-circuit test system provided in the above embodiment, may include: Step 101: The processor acquires the three-phase electrical information at the common coupling point.

[0052] The three-phase electrical information provided in this embodiment may include the common coupling point (e.g., Figure 2The phase voltage and phase current collected from the 690V side may also include the phase angle, zero-crossing time and / or required phase calculated using the collected phase voltage and phase current.

[0053] Step 102: Determine whether the three-phase electrical information meets the point wave triggering conditions of the artificial short circuit script; if so, proceed to step 103.

[0054] In some embodiments, the point wave triggering conditions may include at least one of the following: the specified phase voltage is within the zero-crossing range, the specified phase voltage phase angle reaches a preset angle, the specified line voltage amplitude reaches a preset threshold, and the phase-locked loop synchronization conditions are met.

[0055] Correspondingly, if the three-phase electrical information in this embodiment does not meet the point wave triggering conditions of the artificial short circuit script, the process can be terminated directly, or the process can be returned to step 101 to obtain the three-phase electrical information at the next moment.

[0056] Step 103: Send the corresponding fault activation trigger command and / or fault clearance trigger command to the fault branch in the artificial short-circuit test system to control the programmable fault branch to achieve progressive fault injection and / or progressive fault exit.

[0057] In some embodiments, step 103 may include, when the three-phase electrical information meets the fault activation triggering condition, controlling the impedance switching device to switch the impedance network to the first impedance level and controlling the main switch circuit to inject a fault of the target fault type; when the first delay is reached or the voltage drop threshold condition is met, controlling the impedance switching device to switch the impedance network to the target impedance level; wherein, the impedance of the first impedance level is greater than the impedance of the target impedance level. When the three-phase electrical information meets the fault clearing trigger condition, the control impedance switching device switches the impedance network to the second impedance level; after the fault current decreases and the system transiently converges, the control main switch circuit clears the fault.

[0058] In some embodiments, the method may further include: the processor generating an artificial short-circuit script according to the acquired test script generation instructions; wherein the artificial short-circuit script includes at least one of: fault type information, fault location information, equivalent impedance information, fault duration information, fault injection information, fault exit information, and data acquisition window and acceptance index information.

[0059] In some embodiments, the method may further include: before executing the artificial short-circuit script, the processor performs an executability check and risk pre-assessment on the artificial short-circuit script; if the check and pre-assessment pass, the artificial short-circuit script is executed; if the check and / or pre-assessment fail, a script problem prompt message is output.

[0060] In some embodiments, the method may further include: the processor using a conventional steady-state control strategy to control the energy storage power station converter cluster in the pre-fault stage; using a safety and stability priority strategy to control the energy storage power station converter cluster in the fault stage; and using a smooth recovery strategy to control the energy storage power station converter cluster in the post-fault stage.

[0061] In some embodiments, the safety and stability priority strategy includes at least one of fault current limiting, virtual impedance adjustment, and power reference and voltage reference adjustment; the smooth recovery strategy includes at least one of fault exit identification, gradual recovery of control parameters, and power recovery rate limiting.

[0062] In this embodiment, the present invention, through the setting of the test network circuit in the artificial short-circuit test system, equivalently maps the short-circuit conditions of the target high-voltage side in the actual site to the corresponding low-voltage side in the test network circuit. This enables the reproduction of typical site fault environments in the laboratory and covers both grid-connected and off-grid key operating modes, making the test results closer to engineering reality and reducing deviations caused by nonlinear saturation, protection coordination, and discrete implementation issues that are difficult to cover by simulation alone. By setting the programmable fault branch in the artificial short-circuit test system, the processor can transform fault initiation and removal from manual operation to automated condition triggering, ensuring that the test is stably implemented according to the expected plan and improving the repeatability and comparability of the artificial short-circuit test. Furthermore, by utilizing the programmable impedance capability of the programmable fault branch to achieve progressive fault injection and / or progressive fault exit, current surges can be reduced, and the probability of protection malfunction and equipment stress can be reduced.

[0063] Corresponding to the above method embodiments, this invention also provides an artificial short-circuit test device. The artificial short-circuit test device described below and the artificial short-circuit test method described above can be referred to each other.

[0064] Please refer to Figure 7 , Figure 7 This is a schematic diagram of an artificial short-circuit testing device provided in an embodiment of the present invention. The device may include: Memory D1 is used to store computer programs; The processor D2 is used to execute computer programs to implement the steps of the artificial short-circuit test method provided in the above-described method embodiments.

[0065] The artificial short-circuit test equipment provided in this embodiment can be a host device or a server; it can also be a microcontroller or other embedded device.

[0066] Corresponding to the above method embodiments, this invention also provides a computer program product. The computer program product described below can be referred to in correspondence with the artificial short-circuit test method described above.

[0067] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the artificial short-circuit test method provided in the above-described method embodiments.

[0068] Corresponding to the above method embodiments, this invention also provides a computer-readable storage medium. The computer-readable storage medium described below can be referred to in conjunction with the artificial short-circuit test method described above.

[0069] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the artificial short-circuit test method described in the above-described method embodiments.

[0070] The computer-readable storage medium can specifically be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0071] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods, devices, computer program products, and computer-readable storage media disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the system section.

[0072] The artificial short-circuit test system, method, and equipment provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. An artificial short-circuit test system, characterized in that, include: Experiment with network circuits, programmable fault branches, and processors; The test network circuit includes an energy storage power station converter cluster, a first transformer, a first adjustable impedance, and a power grid simulation source. The energy storage power station converter cluster is connected to the power grid simulation source through the first transformer and the first adjustable impedance connected in series. The test network circuit is used to equivalently map the short-circuit condition of the target high-voltage side in the test site to the low-voltage side at the common coupling point connected to the energy storage power station converter cluster, according to the configuration of the first transformer and the first adjustable impedance. The programmable fault branch includes: a main switching circuit, an impedance network, and an impedance switching device; the main switching circuit and the impedance network are connected in series to the common coupling point; the impedance network includes multiple levels of resistors and reactances; the main switching circuit is used to inject or remove a fault of the target fault type according to the control of the processor; the impedance switching device is connected in parallel with the impedance network and is used to switch the impedance level of the impedance network according to the control of the processor; the target fault type is any preset fault type; the preset fault type includes at least one of three-phase short circuit, two-phase short circuit, and single-phase grounding; The processor is used to acquire three-phase electrical information at the common coupling point; when the three-phase electrical information meets the point wave triggering conditions of the artificial short-circuit script, it sends corresponding fault activation triggering instructions and / or fault clearing triggering instructions to the main switching circuit and the impedance switching device to control the programmable fault branch to achieve progressive fault injection and / or progressive fault exit.

2. The artificial short-circuit test system according to claim 1, characterized in that, The energy storage power station converter cluster includes a first number of energy storage subarrays, a second transformer, and a second adjustable impedance. Each of the energy storage subarrays is connected to the common coupling point through its corresponding series-connected second transformer and second adjustable impedance; each of the energy storage subarrays includes a second number of parallel-connected energy storage simulation converter units; each of the energy storage simulation converter units includes a series-connected energy storage battery simulator and an energy storage converter.

3. The artificial short-circuit test system according to claim 2, characterized in that, Each of the energy storage analog converter units is provided with a first controllable switch at both ends to control the number of energy storage analog converter units activated in the energy storage subarray; the i-th energy storage analog converter unit in each energy storage subarray is connected in parallel with the (i+1)-th energy storage analog converter unit through a second controllable switch; where i is a positive integer greater than or equal to 1 and less than or equal to n-1, and n is the second quantity.

4. The artificial short-circuit test system according to claim 2, characterized in that, The energy storage converter adopts an active midpoint clamping topology with a common-mode current loop.

5. The artificial short-circuit test system according to claim 2, characterized in that, The first quantity is 3, the second quantity is 16, the target high voltage side is the 35kV side, and the low voltage side at the common coupling point is the 690V side.

6. The artificial short-circuit test system according to claim 1, characterized in that, The point wave triggering conditions include at least one of the following: the specified phase voltage is within the zero-crossing range, the specified phase voltage phase angle reaches a preset angle, the specified line voltage amplitude reaches a preset threshold, and the phase-locked synchronization conditions are met.

7. The artificial short-circuit test system according to claim 1, characterized in that, Also includes: A grid-connected / off-grid switching circuit is used to switch between grid-connected and off-grid operating conditions; wherein, the grid simulation source is connected to the grid bus through the grid-connected / off-grid switching circuit; the energy storage power station converter cluster is connected to the grid bus through a first transformer and a first adjustable impedance connected in series.

8. The artificial short-circuit test system according to claim 7, characterized in that, The test network circuit also includes: a power generation and supply unit, a third transformer, and a third adjustable impedance; wherein, the power generation and supply unit includes: a photovoltaic power station inverter cluster, a wind power station converter cluster, and / or a synchronous generator; Each of the power generation and supply units is connected to the power grid bus via its corresponding series-connected third transformer and third adjustable impedance.

9. The artificial short-circuit test system according to claim 1, characterized in that, The processor is specifically used to control the main switch circuit to inject the fault of the target fault type and control the impedance switching device to switch the impedance network to the first impedance level when the three-phase electrical information meets the fault activation triggering condition; and to control the impedance switching device to switch the impedance network to the target impedance level when the first delay is reached or the voltage drop threshold condition is met; wherein the impedance of the first impedance level is greater than the impedance of the target impedance level. When the three-phase electrical information meets the fault clearing trigger condition, the impedance switching device is controlled to switch the impedance network to the second impedance level; after the fault current decreases and the system transiently converges, the main switching circuit is controlled to clear the fault.

10. The artificial short-circuit test system according to claim 1, characterized in that, The processor is further configured to generate the artificial short-circuit script according to the acquired test script generation instructions; wherein the artificial short-circuit script includes at least one of the following: fault type information, fault location information, equivalent impedance information, fault duration information, fault injection information, fault exit information, and data acquisition window and acceptance index information.

11. The artificial short-circuit test system according to claim 1, characterized in that, The processor is further configured to perform executability verification and risk pre-assessment on the artificial short-circuit script before executing the artificial short-circuit script; if the verification and pre-assessment pass, the artificial short-circuit script is executed. If the checksum and / or pre-evaluation fail, a script problem message will be output.

12. The artificial short-circuit test system according to any one of claims 1 to 11, characterized in that, The processor is also used to control the energy storage power station converter cluster using a conventional steady-state control strategy in the pre-fault stage; to control the energy storage power station converter cluster using a safety and stability priority strategy in the fault stage; and to control the energy storage power station converter cluster using a smooth recovery strategy in the post-fault stage.

13. The artificial short-circuit test system according to claim 12, characterized in that, The safety and stability priority strategy includes at least one of fault current limiting, virtual impedance adjustment, and power reference and voltage reference adjustment; the smooth recovery strategy includes at least one of fault exit identification, gradual recovery of control parameters, and power recovery rate limiting.

14. A method for conducting an artificial short-circuit test, characterized in that, The system is applied to the artificial short-circuit test system as described in any one of claims 1 to 13, comprising: The processor acquires the three-phase electrical information at the common coupling point; Determine whether the three-phase electrical information meets the point wave triggering conditions of the artificial short circuit script; If so, a corresponding fault activation trigger command and / or fault clearance trigger command are sent to the fault branch in the artificial short-circuit test system to control the programmable fault branch to implement progressive fault injection and / or progressive fault exit.

15. An artificial short-circuit testing device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the artificial short-circuit test method as described in claim 14 when executing the computer program.

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