A 100-nanometer optical communication chip ridge region super-resolution imaging device

Abstract

This invention discloses a ridge region super-resolution imaging device for a 100nm optical communication chip, comprising: an optical imaging module and an FPGA control system, wherein the FPGA control system is connected to the optical imaging module; the optical imaging module includes a first beam shaper, a second beam shaper, a first linear CCD camera, and a second linear CCD camera, all orthogonally arranged above the chip under test, with the first and second beam shapers projecting one-dimensional line beams along the X-axis and Y-axis directions of the chip under test, respectively. This device effectively overcomes the anisotropic resolution bottleneck of traditional imaging by constructing a dual orthogonal line scanning optical system and a physically constrained GAN network hardware acceleration architecture, and the parallel computing process solves the problem of slow inference speed in generative models, significantly improving image reconstruction efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and specifically discloses a 100-nanometer optical communication chip ridge region super-resolution imaging device. Background Technology

[0002] As the optical communication industry evolves towards ultra-high speed and ultra-large capacity, the manufacturing precision requirements for photonic integrated circuits are becoming increasingly stringent. As the core structure for optical field confinement and transmission in optical chips, the nanometer-level roughness or minute morphological defects of the ridge waveguide on its sidewalls directly affect the performance of optical transmission. Therefore, high-precision non-destructive testing of the ridge region at the 100-nanometer level is crucial to ensuring chip yield.

[0003] However, existing detection methods are insufficient to meet the stringent requirements of high-resolution ridge region images in industrial settings. Traditional optical microscopes are limited by the Abbe diffraction limit, making it difficult to break through the 200-nanometer resolution barrier. While scanning electron microscopes offer extremely high spatial resolution, their operation relies on a high-vacuum environment, making them unsuitable for large-scale online inspections.

[0004] The patent published in CN223320686U employs microlens arrays or high numerical aperture microscope objectives for chip imaging, positioning, and detection. This type of method utilizes a combination of optical lenses to improve resolution while maintaining the field of view. While it has good versatility in microfluidics or conventional chip positioning, it struggles to meet the dual requirements of large depth of field and ultra-high resolution for ridge region detection in optical communication chips. Furthermore, due to the inherent contradiction between the aperture and depth of field in optical systems, the extremely shallow depth of field of high-magnification objectives prevents the simultaneous clear imaging of the three-dimensional top and bottom ridge tops. The complex multi-lens optical path multiplexing structure not only increases hardware size and assembly costs but also easily introduces stray light interference, limiting the imaging signal-to-noise ratio.

[0005] Patent publication number CN117094888A proposes an image super-resolution method based on a generative diffusion model. This method trains a neural network to learn the noise distribution and uses an iterative denoising mechanism to generate high-resolution images. Although it can effectively overcome the physical diffraction limit of hardware and improve image texture details, its inference speed and result fidelity are difficult to match the industrial-grade mass production requirements of optical communication chips. However, the multiple iterative sampling process of the diffusion model leads to excessively long processing time per frame, severely slowing down the online detection cycle. In addition, when reconstructing micro-defects at the hundred-nanometer scale, the generative model has the risk of generating artifacts, which can easily misjudge dust as defects or mask real ridge edge damage, resulting in insufficient detection reliability.

[0006] Therefore, there is an urgent need for a new type of super-resolution imaging device that can break through the diffraction limit and take into account high speed and non-destructive characteristics, so as to overcome the technical problems of insufficient resolution and low imaging efficiency of existing detection technologies. Summary of the Invention

[0007] (a) Technical problems to be solved

[0008] To address the aforementioned issues, this invention provides a 100nm optical communication chip ridge region super-resolution imaging device. By constructing a dual-channel orthogonal line scanning optical system and a physically constrained GAN network based on FPGA hardware acceleration, it effectively solves the anisotropic ambiguity problem in line scanning technology, breaks through the optical diffraction limit, overcomes the shortcomings of insufficient resolution and low imaging efficiency in existing detection technologies, and realizes real-time and reliable super-resolution imaging of the chip ridge region microstructure, providing a reliable solution for high-throughput yield detection of optical chips.

[0009] (II) Technical Solution

[0010] To address the aforementioned technical problems, this invention proposes a 100-nanometer optical communication chip ridge region super-resolution imaging device. The 100-nanometer optical communication chip ridge region super-resolution imaging device is used for high-precision non-destructive testing of 100-nanometer-level chips. The 100-nanometer optical communication chip ridge region super-resolution imaging device includes: an optical imaging module and an FPGA control system, wherein the FPGA control system is connected to the optical imaging module.

[0011] The optical imaging module includes a first beam shaper, a second beam shaper, a first linear CCD camera, and a second linear CCD camera. The first beam shaper, the second beam shaper, the first linear CCD camera, and the second linear CCD camera are all orthogonally arranged above the chip under test. The first beam shaper and the second beam shaper project one-dimensional line beams along the X-axis and Y-axis directions of the chip under test, respectively, and the projection angle between the optical axes of the first beam shaper and the second beam shaper on the horizontal plane is 90°.

[0012] Preferably, both the first beam shaping generator and the second beam shaping generator include a laser, a collimating lens group, a Powell prism, a focusing lens, a plane mirror group, a piezoelectric ceramic control unit, and an output field mirror;

[0013] The Gaussian beam emitted by the laser is shaped into a parallel beam by the collimating lens group and then incident on the Powell prism, which converts the Gaussian beam into a line light source with uniform energy distribution along the axis. The line light source is then initially focused by the focusing lens and directed towards the planar galvanometer. The back of the planar galvanometer is connected to the piezoelectric ceramic control unit to drive the planar galvanometer to deflect at a small angle in response to the control signal of the FPGA control system, thereby achieving precise step scanning of the beam at the micrometer scale. After being folded by the planar reflector, the line light source is irradiated onto the chip under test by the output field mirror, forming a one-dimensional line beam with uniform energy, extremely narrow linewidth, and controllable position at the focal plane of the chip under test.

[0014] Preferably, the 100nm optical communication chip ridge region super-resolution imaging device includes an optical path implementation algorithm, which comprises:

[0015] First, the original Gaussian beam emitted by the laser passes through a collimating lens group, assuming the waist radius of the incident beam is... The focal lengths of the first and second lenses in the collimating lens group are respectively and Then the radius of the emitted light spot after beam expansion The following geometric-optical relationships must be satisfied: ;

[0016] Secondly, the expanded parallel Gaussian beam is incident on the Powell prism and exits through the Powell prism, with an input beam radius of... With output line beam coordinates The following error function mapping relationship exists between them: ;in The total length of the target line spot. The error function is defined as follows: ;

[0017] Subsequently, the light beam is focused by the focusing lens after passing through the Powell prism, and then incident on the plane mirror assembly. Driven by the piezoelectric ceramic control unit, the plane mirror assembly is controlled by the voltage signal output from the FPGA control system. The plane galvanometer is driven to produce a small angular displacement. According to the inverse piezoelectric effect of piezoelectric materials, the relationship between angular displacement and driving voltage is as follows: ;in It is the electromechanical coupling constant; its plane mirror assembly includes a plane galvanometer and a plane reflector;

[0018] Finally, the beam is folded by the plane mirror and passes through the telecentric scanning field mirror. The imaging characteristics of the flat surface of the chip are compensated for the curvature of the image field, and the focal plane is corrected to a strict plane to ensure that the beam is always accurately focused on the chip surface throughout the entire scanning field of view.

[0019] Preferably, the telecentric scanning field mirror compensates for the beam while correcting optical distortion, thus ensuring the position of the line beam on the chip surface is correct. With the galvanometer deflection angle The following linear relationship exists between them: .

[0020] Preferably, the first linear CCD camera corresponds to a first beam shaper to acquire beam information from the first beam shaper along the X-axis direction of the chip under test, and the second linear CCD camera corresponds to a second beam shaper to acquire beam information from the second beam shaper along the Y-axis direction of the chip under test. The imaging logic of the linear CCD camera includes:

[0021] The magnification of the optical system of the line scan CCD camera is set to... The physical size of a single CCD pixel is Then the physical limit resolution of the system It can be represented as: ;

[0022] In the scanning direction, assuming the scanning speed is... The camera's integration time is The single step size of a stepper motor is Then the equivalent resolution in the scanning direction Influenced by both motion fuzziness and step discretization, it can be expressed as: ;

[0023] Under normal engineering conditions This results in a blurred image in a single scan, which in turn allows the obtained image to have high resolution in non-scanning directions. In the scanning direction with low resolution ;

[0024] Therefore, the pixel intensity acquired by the beam shaping generator Representing a real-world scenario With anisotropic point diffusion function Convolution and superimposed noise : ; where the anisotropic point diffusion function The formula is as follows: ,in The parameters satisfy .

[0025] Preferably, the FPGA control system includes a synchronous timing and motion control module, a dual-channel high-speed data acquisition module, a data buffer module, and a data formatting and transmission module;

[0026] The synchronous timing and motion control module is used to generate a global clock and dual-axis stepping commands to drive the planar galvanometer to deflect at a small angle; the dual-channel high-speed data acquisition module is equipped with a CameraLink / CXP decoder and a serial-to-parallel conversion unit to receive the high-speed signal stream from the linear CCD camera in real time and perform dual-channel spatiotemporal alignment; the data caching module includes an asynchronous FIFO buffer pool and a DDR4 read / write controller to manage the throughput of the image data stream; the data formatting and transmission module transports the structured and packaged slice sequences and performs image super-resolution reconstruction.

[0027] Preferably, the synchronization timing and motion control logic module of the FPGA control system is pre-set with the scanning path of the chip under test to calculate the pulse sequence of the X / Y axes on the surface of the chip under test in real time, and the synchronization timing and motion control logic module is equipped with a synchronization trigger signal generator to monitor the accumulated pulse count in real time. When the line light source scans a set step size... Immediately upon activation, a wide-pulse-width trigger signal is generated and sent to the linear CCD camera, with a trigger frequency of [missing information]. With scan speed and sampling step size The relationship must satisfy the following formula: ;

[0028] Secondly, the dual-channel high-speed data acquisition and data caching module together constitute a high-speed image data throughput channel. The dual-channel high-speed data acquisition can receive high-speed beam signals acquired by the two linear CCD cameras in parallel, and enter the serial-to-parallel conversion and pixel recombination unit after decoding the raw data stream to convert the serial signal into the parallel pixel bus data format inside the FPGA.

[0029] Next, the data stream enters the dual-channel spatiotemporal alignment unit, based on the real-time position coordinates fed back by the encoder. ,right and Logical address mapping is performed, and the data is written to the asynchronous FIFO buffer pool. The output of the FIFO buffer pool is connected to the DDR4 read / write controller to store massive amounts of image data into the memory using burst transfer mode. and The scan data are for the X-axis and Y-axis, respectively.

[0030] Finally, the structured packaging unit of the data formatting and transmission module periodically reads the corresponding area from the DDR4 read / write controller. and The data is sliced ​​and encapsulated into fixed-size tensor blocks. To reduce the CPU's intervention load, the data formatting and transmission module uses DMA technology and constructs a dedicated DMA transfer engine.

[0031] The theoretical maximum transfer bandwidth of the DMA transport engine Assume the bus width is... The clock frequency is Then the theoretical maximum transmission bandwidth for: ;in This represents the bus arbitration efficiency coefficient.

[0032] Preferably, the FPGA control system is further provided with a hardware-based super-resolution image processing module based on a physically constrained GAN network, and the hardware-based super-resolution image processing module is connected to the data path through an AXI4 high-speed interconnect bus.

[0033] Preferably, the hardware-based super-resolution image processing module includes a deep learning computing array, a PSF degradation kernel register, and a physical degradation verification unit;

[0034] The deep learning computing array utilizes DSP slicing to achieve convolution acceleration, PRuLU activation, and residual accumulation, ultimately converting the input orthogonal low-resolution data stream... and Reconstructed into a high-resolution image Furthermore, the hardware-based super-resolution image processing module is equipped with a physical confidence marker unit. The physical confidence marker unit performs convolution operation between the reconstructed image and the PSF degradation kernel in the PSF degradation kernel register to simulate the blur degradation process of optical imaging. The physical degradation verification unit compares the degradation result with the original input data to quickly evaluate the confidence of the reconstructed 100-nanometer super-resolution image.

[0035] (III) Beneficial Effects

[0036] Compared with existing technologies, the 100-nanometer optical communication chip ridge region super-resolution imaging device of the present invention has the following advantages:

[0037] 1. This invention constructs a dual-channel line-scanning optical system based on a positive cross-complement strategy. By arranging two sets of line beam shapers and linear CCDs with their optical axes at a 90-degree angle, this invention acquires high-resolution features in the X and Y axes respectively. The high physical pixel resolution of the detector itself is used to compensate for the scanning motion blur in the orthogonal directions. Combined with the uniform flat-top light field constructed by the Powell prism and telecentric field mirror, this invention solves the problem of anisotropic resolution loss from the optical physics level, breaks through the optical diffraction limit, and overcomes the problem of insufficient resolution in existing detection technologies.

[0038] 2. This invention proposes a hardware-accelerated dataflow architecture based on FPGA full integration. This invention breaks through the inefficient mode of traditional PC software processing, deeply integrating multi-axis motion control, high-speed CameraLink / CXP signal decoding, DMA direct memory access, and a DSP convolutional computation array within a single FPGA chip. This architecture, through a pipelined parallel processing mechanism, achieves low-latency transmission from heterogeneous photoelectric signal acquisition to structured slice data transfer, ensuring the millisecond-level synchronous response and gigabit-level real-time data throughput capabilities required for industrial-grade online detection.

[0039] 3. This invention innovatively embeds a deep learning inference network into an FPGA logic circuit, constructing a parallel convolution acceleration array based on DSP slices and a PRuLU activation pipeline. This architecture can directly perform real-time super-resolution image reconstruction on the input orthogonal anisotropic low-resolution data stream, completing isotropic reconstruction of features at the hundred-nanometer level without relying on host computer software computation. This hardware-integrated super-resolution processing scheme effectively overcomes the drawback of slow inference speed of traditional software-based generative models, achieving fast, stable, and real-time imaging capabilities while ensuring breakthrough of the optical diffraction limit.

[0040] In summary, the present invention provides a 100-nanometer optical communication chip ridge region super-resolution imaging device, which integrates an orthogonal line scanning optical system and a physically constrained generative adversarial network hardware accelerator. By directly deploying a convolutional computation array optimized for the ridge region features of the optical chip on the FPGA, it achieves real-time reconstruction from anisotropic low-resolution data sampled by optical physics to isotropic high-resolution images at the hundred-nanometer level. This effectively solves the problem of anisotropic blurring in line scanning technology, breaks through the optical diffraction limit, overcomes the shortcomings of insufficient resolution and low imaging efficiency of existing detection technologies, and realizes real-time and reliable super-resolution imaging of the microstructure of the chip ridge region, providing a reliable solution for high-throughput yield detection of optical chips. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the overall structure of the 100-nanometer optical communication chip ridge region super-resolution imaging device of the present invention.

[0043] Figure 2 This is a schematic diagram of the internal optical path of the beam shaping generator of the 100-nanometer optical communication chip ridge region super-resolution imaging device of the present invention.

[0044] Figure 3 This is a schematic diagram of the internal modules of the FPGA control system of the 100-nanometer optical communication chip ridge region super-resolution imaging device of the present invention.

[0045] Figure 4 This is a schematic diagram of the hardware-based super-resolution image processing module based on a physically constrained GAN network in the 100-nanometer optical communication chip ridge region super-resolution imaging device of the present invention.

[0046] Explanation of reference numerals in the attached figures:

[0047] G1: First beam shaping generator; G2: First linear CCD camera; G3: Second beam shaping generator; G4: Second linear CCD camera;

[0048] L1: First lens; L2: Second lens; L3: Powell prism; L4: Focusing lens; L5: Telecentric scanning field lens;

[0049] M1: Planar galvanometer; M2: Planar reflector; S1: Piezoelectric ceramic control unit. Detailed Implementation

[0050] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0051] The following is in conjunction with the appendix Figure 1-4 The 100-nanometer optical communication chip ridge region super-resolution imaging device of the present invention will be further described.

[0052] Please refer to this carefully. Figure 1-2This invention discloses a 100nm optical communication chip ridge region super-resolution imaging device. This device is used for high-precision non-destructive testing of 100nm-level chips. The device includes an optical imaging module and an FPGA control system, with the FPGA control system connected to the optical imaging module. The optical imaging module includes a first beam shaper G1, a second beam shaper G3, a first linear CCD camera G2, and a second linear CCD camera G4. The first beam shaper G1, the second beam shaper G3, the first linear CCD camera G2, and the second linear CCD camera G4 are all orthogonally arranged above the chip under test. The first beam shaper G1 and the second beam shaper G3 project one-dimensional line beams along the X-axis and Y-axis directions of the chip under test, respectively, and the projection angle between the optical axes of the first beam shaper G1 and the second beam shaper G3 on the horizontal plane is 90°.

[0053] In this embodiment, the super-resolution imaging device constructs a dual-channel line-scanning optical system based on a positive cross-complement strategy using a first beam shaper G1 and a second beam shaper G3. Addressing the physical bottleneck of motion axis resolution limitations in line-scanning imaging, it acquires high-resolution features in the X and Y axes by arranging two sets of line beam shapers with their optical axes at a 90-degree angle to a linear CCD array. Furthermore, it utilizes the high physical pixel resolution of the detector itself to compensate for scanning motion blur in orthogonal directions. Combined with the uniform flat-top light field constructed by the Powell prism L3 and the telecentric field mirror, it solves the anisotropic resolution loss problem from an optical physics perspective, breaks through the optical diffraction limit, overcomes the insufficient resolution of existing detection technologies, and provides a complete high signal-to-noise ratio complementary data source for the full reconstruction of 100-nanometer-level features.

[0054] like Figure 2 As shown, both the first beam shaping generator G1 and the second beam shaping generator G3 include a laser, a collimating lens group, a Powell prism L3, a focusing lens L4, a plane mirror group, a piezoelectric ceramic control unit S1, and an output field mirror. The Gaussian beam emitted by the laser is shaped into a parallel beam by the collimating lens group and then incident on the Powell prism L3, which converts the Gaussian beam into a line light source with uniform energy distribution along the axis. The line light source is then initially focused by the focusing lens L4 and directed towards the plane galvanometer M1. The back of the plane galvanometer M1 is connected to the piezoelectric ceramic control unit S1 to drive the plane galvanometer M1 to deflect at a small angle in response to the control signal of the FPGA control system, thereby realizing precise step scanning of the beam at the micrometer scale. After being folded by the plane mirror M2, the line light source is irradiated onto the chip under test through the output field mirror and forms a one-dimensional line beam with uniform energy, extremely narrow linewidth, and controllable position at the focal plane of the chip under test.

[0055] To further address the anisotropic resolution loss problem and overcome the optical diffraction limit, a light path implementation algorithm is incorporated into the ridge region super-resolution imaging device of the 100nm optical communication chip. This algorithm includes:

[0056] First, the original Gaussian beam emitted by the laser passes through a collimating lens group, assuming the waist radius of the incident beam is... The focal lengths of the first lens L1 and the second lens L2 in the collimating lens group are respectively and Then the radius of the emitted light spot after beam expansion The following geometric-optical relationships must be satisfied: ;

[0057] Secondly, the expanded parallel Gaussian beam is incident on Powell prism L3, exits through Powell prism L3, and the input beam radius is... With output line beam coordinates The following error function mapping relationship exists between them: ;in The total length of the target line spot. The error function is defined as follows: This formula physically guarantees the output light field after passing through the Powell prism L3. It remains constant across the entire linewidth range, thus achieving a uniformity greater than [value missing]. Flat-top light field illumination.

[0058] Subsequently, the light beam passes through the Powell prism L3 and is focused by the focusing lens L4 before entering the plane mirror assembly. Driven by the piezoelectric ceramic control unit S1, the plane mirror assembly is controlled by the voltage signal output from the FPGA control system. This causes a small angular displacement in the plane mirror assembly. According to the inverse piezoelectric effect of piezoelectric materials, the relationship between angular displacement and driving voltage is as follows: ;in It is the electromechanical coupling constant, which enables the beam to produce sub-micron level controlled motion in the scanning direction;

[0059] Finally, the beam passes through the telecentric scanning field lens L5, which compensates for the curvature of the image field to suit the imaging characteristics of the flat surface of the chip, and corrects the focal plane to a strictly flat plane to ensure that the beam is always accurately focused on the chip surface throughout the entire scanning field of view.

[0060] Furthermore, the telecentric scanning field lens L5 corrects optical distortion while compensating for the beam, thus ensuring the correct position of the line beam on the chip surface. With the galvanometer deflection angle The following linear relationship exists between them: Through the aforementioned precision optical path, high-quality line beam illumination with a linewidth of less than one micrometer and a uniformity of greater than one micrometer was achieved.

[0061] like Figure 2 As shown, in order to further acquire beam information from the surface of the chip under test, the first linear CCD camera G2 corresponds to the first beam shaping generator G1 to acquire beam information from the first beam shaping generator G1 along the X-axis direction of the chip under test, and the second linear CCD camera G4 corresponds to the second beam shaping generator G3 to acquire beam information from the second beam shaping generator G3 along the Y-axis direction of the chip under test. The imaging logic of the linear CCD camera includes:

[0062] The orthogonal layout of the aforementioned linear CCD camera aims to utilize the inherent anisotropic resolution characteristics of linear CCDs: linear CCDs have extremely high physical resolution in non-scanning directions. In the direction of scanning motion, its resolution This is constrained by the motor stepping accuracy, integration time, and motion blur. Therefore, the magnification of the linear CCD camera's optical system is set to... The physical size of a single CCD pixel is Then the physical limit resolution of the system It can be represented as: ;

[0063] In the scanning direction, assuming the scanning speed is... The camera's integration time is The single step size of a stepper motor is Then the equivalent resolution in the scanning direction Influenced by both motion fuzziness and step discretization, it can be expressed as: ;

[0064] Under normal engineering conditions This results in a blurred image in a single scan, which in turn allows the obtained image to have high resolution in non-scanning directions. In the scanning direction with low resolution ;

[0065] Therefore, the pixel intensity acquired by the beam shaping generator Representing a real-world scenario With anisotropic point diffusion function Convolution and superimposed noise : ; where the anisotropic point diffusion function The formula is as follows: ,in The parameters satisfy .

[0066] In this embodiment, based on this physical degradation model, the device strategically utilizes and By extracting complementary high-frequency information from the intrinsic high-resolution characteristics in the non-scanning dimension to avoid motion blur, a complete set of physical feature inputs is provided for subsequent FPGA super-resolution reconstruction. Furthermore, in the degradation module, if the numerical aperture of the imaging system is known... and wavelength The diffraction-limited resolution scale of the imaging system is then determined. Initial estimation can be performed using the Rayleigh criterion, as shown in the following formula: This paper uses it as the initial estimate of the parameters in the point spread function for initialization. , .

[0067] See Figure 3 The FPGA control system includes a synchronous timing and motion control module, a dual-channel high-speed data acquisition module, a data buffer module, and a data formatting and transmission module. The synchronous timing and motion control module includes a global clock, a dual-axis stepping instruction generator, and a synchronous trigger signal generator to drive the planar galvanometer M1 to deflect at a small angle. The dual-channel high-speed data acquisition module is equipped with a CameraLink / CXP decoder, a serial-to-parallel conversion unit, and a dual-channel spatiotemporal alignment unit for receiving high-speed signal streams from the linear CCD camera in real time and performing dual-channel spatiotemporal alignment. The data buffer module includes an asynchronous FIFO buffer pool and a DDR4 read / write controller to manage the throughput of the image data stream. The data formatting and transmission module transports the structured and packaged slice sequences and performs image super-resolution reconstruction.

[0068] Furthermore, the functional logic and collaborative working mechanism of each module within the FPGA control system are as follows: Firstly, a synchronous timing and motion control logic module is constructed within the FPGA. This module is driven by a global clock management unit, providing a unified time reference for the entire system and driving the dual-axis stepping instruction generator. The synchronous timing and motion control logic module of the FPGA control system has a preset scanning path for the chip under test to calculate the X / Y axis pulse sequence on the surface of the chip under test in real time. Furthermore, a synchronous trigger signal generator is set within the synchronous timing and motion control logic module to monitor the accumulated pulse count in real time. Each time the line light source scans a set step size... At that moment, a wide-pulse-width trigger signal is immediately generated and sent to the linear CCD camera, with a trigger frequency of [missing information]. With scan speed and sampling step size The relationship must satisfy the following formula: ;

[0069] Secondly, the dual-channel high-speed data acquisition and data caching module together form a high-speed image data throughput channel. The dual-channel high-speed data acquisition can receive high-speed beam signals acquired by two linear CCD cameras in parallel, and enter the serial-to-parallel conversion and pixel recombination unit after decoding the raw data stream to convert the serial signal into the parallel pixel bus data format inside the FPGA.

[0070] Next, the data stream enters the dual-channel spatiotemporal alignment unit, based on the real-time position coordinates fed back by the encoder. ,right and Logical address mapping is performed, and the data is written to an asynchronous FIFO buffer. The output of the FIFO buffer is connected to a DDR4 read / write controller to store massive amounts of image data into memory using burst transfer mode. and The scan data are for the X-axis and Y-axis, respectively.

[0071] Finally, the structured packaging unit of the data formatting and transmission module periodically reads the corresponding area from the DDR4 read / write controller. and Data is sliced ​​and encapsulated into fixed-size tensor blocks. To reduce the CPU's intervention load, the data formatting and transmission module uses DMA technology and builds a dedicated DMA transfer engine. This engine bypasses the main processor and directly transfers structured data packets to the on-chip computing core at high speed via the AXI bus.

[0072] The theoretical maximum transfer bandwidth of the DMA transfer engine Assume the bus width is... The clock frequency is Then the theoretical maximum transmission bandwidth for: ;in This represents the bus arbitration efficiency coefficient. Through the pipelined collaboration of the above four modules, the FPGA achieves a fully hardware-accelerated process from photoelectric signal conversion to structured data output.

[0073] like Figure 4 As shown, the FPGA control system also includes a hardware-based super-resolution image processing module based on a physically constrained GAN network. This module is connected to the data path via an AXI4 high-speed interconnect bus. The hardware-based super-resolution image processing module includes a deep learning computing array, a PSF degradation kernel register, and a physical degradation verification unit. The deep learning computing array utilizes DSP slicing to achieve convolution acceleration, PRuLU activation, and residual accumulation, ultimately processing the input orthogonal low-resolution data stream. and Reconstructed into a high-resolution image Furthermore, the hardware-based super-resolution image processing module is equipped with a physical confidence labeling unit. The physical confidence labeling unit performs convolution operations between the reconstructed image and the PSF degradation kernel in the PSF degradation kernel register to simulate the blur degradation process of optical imaging. The physical degradation verification unit compares the degradation result with the original input data to quickly evaluate the confidence of the reconstructed 100-nanometer super-resolution image.

[0074] In a preferred embodiment, the internal architecture and processing flow of the super-resolution image reconstruction module integrated on the FPGA chip include:

[0075] This module integrates the deep learning inference network and optical physical model verification into the hardware logic circuit, and interacts with the storage module through the AXI4 high-speed interconnect bus, realizing real-time super-resolution imaging without CPU intervention.

[0076] The processing begins with the data loading phase. Once enough orthogonal image slices are cached in the DDR4, the storage module sends a transfer request to the reconstruction module via the AXI4 bus. The module's internal DMA transfer engine responds to the request, transferring the anisotropic low-resolution slice sequence to be processed. The data is moved to the on-chip line cache. Simultaneously, the pre-trained GAN model weight parameters stored in Flash are pre-loaded into a dedicated on-chip distributed memory for rapid access by the computational core.

[0077] Next, the data stream enters the core super-resolution reconstruction stage. Data is fed from the row buffer into the deep learning computing array, which consists of a large number of DSP slices arranged in parallel within the FPGA, forming a hardware-based convolution accelerator. The input data first passes through the DSP convolution acceleration array to complete the core feature extraction. Unlike software computation, each DSP unit in the FPGA completes one multiply-accumulate operation within one clock cycle. For the... The first layer of the network With one output channel, the DSP array performs the following discrete convolution operation formula:

[0078] ;

[0079] in, The first input of the previous layer Channel feature map Preload the convolutional kernel weights into the registers for the current layer. For bias terms, For spatial coordinate index, The kernel size is the convolution kernel size. The convolution stride is... This represents the total number of input channels. This formula is mapped to parallel pipelined logic in hardware, achieving high-speed throughput at the pixel level.

[0080] Convolution output results The system then enters the PReLU activation logic unit. To introduce nonlinear characteristics and address the vanishing gradient problem along the negative half-axis, this unit utilizes comparator and multiplier circuits in hardware to perform PReLU activation in real time. Its hardware logic is described below:

[0081] ;

[0082] in, For the first The learnable slope parameter of the channel is also stored in an on-chip register. A hardware comparator determines the sign of the value and dynamically selects whether to pass through or multiply by a coefficient. This allows for nonlinear mapping with low latency. The processed data then flows through a residual accumulator module, which utilizes the FPGA's carry chain resources to bitwise accumulate the current deep features with the shallow input features, ultimately outputting an isotropic high-resolution prediction image. .

[0083] To ensure the authenticity of the generated images, the process ultimately enters the confidence verification stage. (Image reconstruction) It is fed into the physical degradation unit, which reads the optical point spread function pre-stored in the PSF degradation core register. In hardware, the physical degradation process is implemented as a fast Gaussian convolution operation, simulating the optical blurring effect of the imaging system to generate a regressed image. : ;

[0084] Subsequently, the confidence labeling unit uses a hardware comparator to compute the backtracking image in parallel. Compared with the original input data The mean square error between them. If the error value Less than the preset physical consistency threshold If the image passes the initial test, it is considered valid; otherwise, a marker signal is triggered. The error calculation formula is as follows:

[0085] ,in .

[0086] The verified image data is finally written into the image register and transmitted back via the AXI4 bus, completing a full 100-nanometer-level super-resolution reconstruction that conforms to physical laws.

[0087] In this embodiment, the present invention innovatively embeds the deep learning inference network into the FPGA logic circuit, constructing a parallel convolution acceleration array based on DSP slices and a PRuLU activation pipeline. This architecture can directly perform real-time super-resolution image reconstruction on the input orthogonal anisotropic low-resolution data stream, completing isotropic reconstruction of features at the hundred-nanometer level without relying on host computer software computation. This hardware-integrated super-resolution processing scheme effectively overcomes the drawback of slow inference speed of traditional software-based generative models, achieving fast, stable, and real-time imaging capabilities while ensuring breakthrough of the optical diffraction limit.

[0088] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can also refer to a "transmission connection," that is, a power connection through various suitable methods such as belt drive, gear drive, or sprocket drive. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

Claims

1. A 100nm optical communication chip ridge region super-resolution imaging device, wherein the 100nm optical communication chip ridge region super-resolution imaging device is used for high-precision non-destructive testing of 100nm-level chips, characterized in that, The 100-nanometer optical communication chip ridge region super-resolution imaging device includes: an optical imaging module and an FPGA control system, wherein the FPGA control system is connected to the optical imaging module; The optical imaging module includes a first beam shaper, a second beam shaper, a first linear CCD camera, and a second linear CCD camera. The first beam shaper, the second beam shaper, the first linear CCD camera, and the second linear CCD camera are all orthogonally arranged above the chip under test. The first beam shaper and the second beam shaper project one-dimensional line beams along the X-axis and Y-axis directions of the chip under test, respectively, and the projection angle between the optical axes of the first beam shaper and the second beam shaper on the horizontal plane is 90°.

2. The ridge region super-resolution imaging device for a 100-nanometer optical communication chip according to claim 1, characterized in that, Both the first and second beam shaping generators include a laser, a collimating lens group, a Powell prism, a focusing lens, a plane mirror group, a piezoelectric ceramic control unit, and an output field mirror; the plane mirror group includes a plane galvanometer and a plane reflector. The Gaussian beam emitted by the laser is shaped into a parallel beam by the collimating lens group and then incident on the Powell prism, which converts the Gaussian beam into a line light source with uniform energy distribution along the axis. The line light source is then initially focused by the focusing lens and directed towards the planar galvanometer. The back of the planar galvanometer is connected to the piezoelectric ceramic control unit to drive the planar galvanometer to deflect at a small angle in response to the control signal of the FPGA control system, thereby achieving precise step scanning of the beam at the micrometer scale. After being folded by the planar reflector, the line light source is irradiated onto the chip under test by the output field mirror, forming a one-dimensional line beam with uniform energy, extremely narrow linewidth, and controllable position at the focal plane of the chip under test.

3. The 100-nanometer optical communication chip ridge region super-resolution imaging device according to claim 2, characterized in that, The 100nm optical communication chip ridge region super-resolution imaging device incorporates an optical path implementation algorithm, which includes: First, the original Gaussian beam emitted by the laser passes through a collimating lens group, assuming the waist radius of the incident beam is... The focal lengths of the first and second lenses in the collimating lens group are respectively and Then the radius of the emitted light spot after beam expansion The following geometric-optical relationships must be satisfied: ; Secondly, the expanded parallel Gaussian beam is incident on the Powell prism and exits through the Powell prism, with an input beam radius of... With output line beam coordinates The following error function mapping relationship exists between them: ;in The total length of the target line spot. The error function is defined as follows: ; Subsequently, the light beam is focused by the focusing lens after passing through the Powell prism, and then incident on the plane mirror assembly. Driven by the piezoelectric ceramic control unit, the plane mirror assembly is controlled by the voltage signal output from the FPGA control system. This causes a small angular displacement in the plane mirror assembly. According to the inverse piezoelectric effect of piezoelectric materials, the relationship between angular displacement and driving voltage is as follows: ;in It is the electromechanical coupling constant; Finally, the beam passes through the telecentric scanning field lens, which compensates for the field curvature due to the imaging characteristics of the flat chip surface, and corrects the focal plane to a strictly flat plane to ensure that the beam is always accurately focused on the chip surface throughout the entire scanning field of view.

4. The 100-nanometer optical communication chip ridge region super-resolution imaging device according to claim 3, characterized in that, The telecentric scanning field mirror compensates for the beam while correcting optical distortion, thus improving the position of the line beam on the chip surface. With the galvanometer deflection angle The following linear relationship exists between them: ,in is the focal length of the telecentric scanning field mirror.

5. The 100-nanometer optical communication chip ridge region super-resolution imaging device according to claim 4, characterized in that, The first linear CCD camera corresponds to a first beam shaper to acquire beam information from the first beam shaper along the X-axis direction of the chip under test; the second linear CCD camera corresponds to a second beam shaper to acquire beam information from the second beam shaper along the Y-axis direction of the chip under test; the imaging logic of the linear CCD camera includes: The magnification of the optical system of the line scan CCD camera is set to... The physical size of a single CCD pixel is Then the physical limit resolution of the system It can be represented as: ; In the scanning direction, assuming the scanning speed is... The camera's integration time is The single step size of a stepper motor is Then the equivalent resolution in the scanning direction Influenced by both motion fuzziness and step discretization, it can be expressed as: ; Under normal engineering conditions This results in a blurred image in a single scan, which in turn allows the obtained image to have high resolution in non-scanning directions. In the scanning direction with low resolution ; Therefore, the pixel intensity acquired by the beam shaping generator Representing a real-world scenario With anisotropic point diffusion function Convolution and superimposed noise : ; where the anisotropic point diffusion function The formula is as follows: ,in The parameters satisfy .

6. The ridge region super-resolution imaging device for a 100-nanometer optical communication chip according to claim 5, characterized in that, The FPGA control system includes a synchronous timing and motion control module, a dual-channel high-speed data acquisition module, a data buffer module, and a data formatting and transmission module. The synchronous timing and motion control module is used to generate a global clock and dual-axis stepping commands to drive the planar galvanometer to deflect at a small angle; the dual-channel high-speed data acquisition module is equipped with a CameraLink / CXP decoder and a serial-to-parallel conversion unit to receive the high-speed signal stream from the linear CCD camera in real time and perform dual-channel spatiotemporal alignment; the data caching module includes an asynchronous FIFO buffer pool and a DDR4 read / write controller to manage the throughput of the image data stream; the data formatting and transmission module transports the structured and packaged slice sequences and performs image super-resolution reconstruction.

7. The ridge region super-resolution imaging device for a 100-nanometer optical communication chip according to claim 6, characterized in that, The synchronous timing and motion control logic module of the FPGA control system is pre-programmed with the scanning path of the chip under test to calculate the pulse sequence of the X / Y axes on the surface of the chip under test in real time. Furthermore, the synchronous timing and motion control logic module includes a synchronous trigger signal generator to monitor the accumulated pulse count in real time. Each time the line light source scans a set step size... Immediately upon activation, a wide-pulse-width trigger signal is generated and sent to the linear CCD camera, with a trigger frequency of [missing information]. With scan speed and sampling step size The relationship must satisfy the following formula: ; Secondly, the dual-channel high-speed data acquisition and data caching module together constitute a high-speed image data throughput channel. The dual-channel high-speed data acquisition can receive high-speed beam signals acquired by the two linear CCD cameras in parallel, and enter the serial-to-parallel conversion and pixel recombination unit after decoding the raw data stream to convert the serial signal into the parallel pixel bus data format inside the FPGA. Next, the data stream enters the dual-channel spatiotemporal alignment unit, based on the real-time position coordinates fed back by the encoder. ,right and Logical address mapping is performed, and the data is written to the asynchronous FIFO buffer pool. The output of the FIFO buffer pool is connected to the DDR4 read / write controller to store massive amounts of image data into the memory using burst transfer mode. and The scan data are for the X-axis and Y-axis, respectively. Finally, the structured packaging unit of the data formatting and transmission module periodically reads the corresponding area from the DDR4 read / write controller. and The data is sliced ​​and encapsulated into fixed-size tensor blocks. To reduce the CPU's intervention load, the data formatting and transmission module uses DMA technology and constructs a dedicated DMA transfer engine. The theoretical maximum transfer bandwidth of the DMA transport engine Assume the bus width is... The clock frequency is Then the theoretical maximum transmission bandwidth for: ;in This represents the bus arbitration efficiency coefficient.

8. The ridge region super-resolution imaging device for a 100-nanometer optical communication chip according to claim 7, characterized in that, The FPGA control system also includes a hardware-based super-resolution image processing module based on a physically constrained GAN network. This hardware-based super-resolution image processing module is connected to the data path via an AXI4 high-speed interconnect bus.

9. The 100-nanometer optical communication chip ridge region super-resolution imaging device according to claim 8, characterized in that, The hardware-based super-resolution image processing module includes a deep learning computing array, a PSF degradation kernel register, and a physical degradation verification unit. The deep learning computing array utilizes DSP slicing to achieve convolution acceleration, PRuLU activation, and residual accumulation, ultimately converting the input orthogonal low-resolution data stream... and Reconstructed into a high-resolution image Furthermore, the hardware-based super-resolution image processing module is equipped with a physical confidence marker unit. The physical confidence marker unit performs convolution operation between the reconstructed image and the PSF degradation kernel in the PSF degradation kernel register to simulate the blur degradation process of optical imaging. The physical degradation verification unit compares the degradation result with the original input data to quickly evaluate the confidence of the reconstructed 100-nanometer super-resolution image.

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