Computing device protection in low power mode

Abstract

This disclosure relates to the protection of computing devices in low-power mode. Methods, apparatus, systems, and articles of manufacture for protecting computing devices in low-power mode are described. An example system includes: a temperature monitoring circuit system (134) capable of generating a first temperature sample and a second temperature sample; and a control circuit system (136) coupled to the temperature monitoring circuit system (134) and capable of: incrementing a count in response to the first temperature sample satisfying a first temperature threshold; increasing the first temperature threshold to a second temperature threshold in response to the first temperature sample satisfying the first temperature threshold; comparing the second temperature sample with the second temperature threshold after increasing the first temperature threshold to the second temperature threshold; and incrementing the count in response to the second temperature sample satisfying the second temperature threshold.

Description

[0001] Related applications

[0002] This application relates to U.S. Patent No. 11,847,466, filed November 30, 2021, entitled “Controlled Thermal Shutdown and Recovery,” and U.S. Patent No. 12,146,801, filed June 23, 2021, entitled “Temperature-Based Tamper Detection.” U.S. Patent Nos. 11,847,466 and 12,146,801 are hereby incorporated herein by reference in their entirety. Technical Field

[0003] This specification generally relates to circuits, and more specifically, to the protection of computing devices in low-power modes. Background Technology

[0004] Microcontrollers and / or other computing devices contain processing circuitry (e.g., a central processing unit, graphics processing unit, and / or any other type of processing unit) that performs one or more operations to perform workloads, tasks, and / or functions. To conserve power, such computing devices can enter low-power modes, such as standby mode, hibernation mode, etc. In low-power mode, some components are powered down to save power. Other components remain active to perform secondary tasks and / or periodically, intermittently, or based on triggers, quickly wake up to enter full-power mode. Summary of the Invention

[0005] To provide computing device protection in low-power mode, the example system includes a temperature monitoring circuitry that can generate a first temperature sample and a second temperature sample. The system also includes a control circuitry coupled to the temperature monitoring circuitry and configured to: increment a count in response to the first temperature sample meeting a first temperature threshold; increase the first temperature threshold to a second temperature threshold in response to the first temperature sample meeting the first temperature threshold; compare the second temperature sample with the second temperature threshold after increasing the first temperature threshold to the second temperature threshold; and increment the count in response to the second temperature sample meeting the second temperature threshold. Other examples are described.

[0006] To provide device protection in low-power mode, an example device includes a first comparator for comparing a temperature measurement with a temperature threshold. The device also includes a state machine that can: increment a count in response to the temperature measurement meeting the temperature threshold; and increment the temperature threshold in response to the temperature measurement meeting the temperature threshold. The device further includes a second comparator for inducing a device reset based on the count exceeding a count threshold. Other examples are described.

[0007] To provide computing device protection in low-power mode, an example system device includes: a power management circuit that can generate charging pulses to supply current to peripheral devices during low-power mode; and a digital ammeter coupled to the power management circuit and used to determine the current based on the charging pulses during low-power mode. The device also includes a comparator coupled to the digital ammeter and used to trigger a device reset when the current exceeds a threshold during low-power mode. Other examples are described. Attached Figure Description

[0008] Figure 1 This is an example computing device described in conjunction with the examples described herein.

[0009] Figure 2 yes Figure 1 The circuit diagram is an example of a leakage current control circuit system and a temperature monitoring circuit system.

[0010] Figure 3 It indicates that it can be executed to be implemented. Figure 1-2 A flowchart of the methods, instructions and / or operations of a computing device.

[0011] Figure 4 It is a combination Figure 2 Timing diagram describing the leakage current control circuit system.

[0012] Figure 5 It is a combination Figure 2 Additional timing diagrams describing the leakage current control circuit system.

[0013] The same reference numerals or other reference indicators are used in the accompanying drawings to indicate (functionally and / or structurally) the same or similar features. Detailed Implementation

[0014] The accompanying drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to the same or similar parts. Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0015] Computing devices, such as computers, servers, IoT devices, automotive end devices, laptops, smartphones, smart TVs, microcontrollers, and / or other computing devices / electronics, are implemented in various electronic devices to perform operations and / or tasks. Such computing devices can be divided into a Standard Voltage Threshold (SVT) section / domain and an Ultra-Low Leakage (ULL) Always-On (AON) section / domain. The SVT section may include processing circuitry systems (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.), memory circuitry systems, high-performance peripherals, digital radio circuitry systems, etc., implemented using high-speed SVT transistors with higher leakage current than ULL transistors. The ULL AON section includes low-speed peripherals and other always-on functions implemented using lower-speed ULL transistors with lower leakage current than SVT transistors.

[0016] Leakage current is any non-functional current flowing when the ideal current is zero. Leakage current can cause safety hazards, deplete battery power, shorten battery life, damage equipment, cause interference, and interfere with signals. When a device is programmed into a low-power mode, such as standby mode, deep low-power mode, or hibernation mode, the SVT domain will be disabled, and only the ULL domain will be operational.

[0017] In such computing devices, it is desirable to track and adjust the current drawn from the battery in different operating modes (e.g., active mode, low-power mode, etc.) to ensure the lifespan and reliability of the battery and the desired product. As temperature increases, the leakage current of the device increases, but this does not cause any damage, failure, or unreliable operation of the computing device.

[0018] In the active modes of a computing device, some technologies are available for thermal management and load balancing, controlling the peak and average current drawn from the battery by cutting off necessary circuitry to ensure the safe / reliable operation of the computing device. However, if the computing device is operating in low-power modes, such as standby mode, deep low-power mode, hibernation mode, etc., there are no technologies that can monitor the leakage current drawn from the battery and take appropriate measures.

[0019] During low-power mode, leakage current depends on operating temperature, voltage, and clock frequency. Temperature and voltage affect the static portion and clock frequency, while associated peripheral operations affect the dynamic portion of the leakage current. Temperature has a greater impact on leakage current in the ULL domain, increasing exponentially with increasing temperature, especially at smaller technology nodes (e.g., 28 nanometers (nm)).

[0020] While some technologies monitor temperature to take steps to prevent increased leakage current during active or normal modes, such technologies may be unavailable during low-power modes due to the limited resources in the ULL AON domain. For example, software-based methods may not be able to handle leakage current monitoring because most processing components in the SVT domain are off in low-power modes, and processing power is limited in the ULL AON domain. The examples described herein provide a low-resource-consumption, hardware-based temperature / current monitoring circuitry system in the ULL AON domain to protect computing devices in low-power modes. The examples described herein use hardware to dynamically monitor temperature changes and / or trends over time when operating in low-power modes.

[0021] If leakage current increases consistently and exponentially, the computing device can be reset or shut down completely to prevent damage to the device and / or overload of the battery. To ensure reliable device operation, it needs to be placed in a reset state for cooling. The examples described herein ensure that current caused by high temperatures does not reach alarming or unacceptable levels, thus avoiding shortened battery life due to delayed safety measures. Timely intervention is crucial for battery-powered devices and can even extend battery life before safety precautions are taken. Therefore, the examples described herein provide a low-cost, simple, low-power circuit that protects the computing device from high leakage current during low-power modes by triggering a device reset based on temperature changes and / or trends.

[0022] Furthermore, as described above, the ULL domain voltage level (e.g., 1.1V, 1.3V, etc.), the number of ULL domain peripherals that can operate simultaneously, and the operating frequency (e.g., 32kHz, 2MHz, 16MHz, etc.) affect standby current consumption (also known as low-power current) and / or leakage current. Leakage current is equal to the sum of (a) quiescent current (based on temperature and voltage) and (b) dynamic steady-state current (based on clock frequency and peripheral operation). Therefore, the example described herein ensures that the current drawn from ULL peripherals during low-power mode does not reach a potentially damaging stage and / or shorten battery life by measuring the total current drawn, and triggers a device reset when the total current exceeds a threshold.

[0023] As described above, the examples described herein trigger device resets based on temperature changes and / or standby current to protect the device and ensure reliable operation, preventing further battery depletion. Therefore, the examples described herein can extend battery life in battery-powered products at higher temperatures. Furthermore, in some of the examples described herein, parameters such as temperature and / or current thresholds can be configured or customized based on user and / or manufacturer preferences, thus providing flexibility for a variety of use cases.

[0024] Figure 1 An example computing device 100 is shown. The example computing device 100 includes an example voltage regulator 102, an example SVT domain 104, and an example ULL AON domain 106. The SVT domain 104 includes an example general-purpose timer (GPT) 108, an example UART 110, an example SPI 112, an example inter-integrated circuit (I2C) 114, an example digital radio device 116, an example CPU 118, an example static random access memory (SRAM) 120, and an example general-purpose instruction memory system (VIMS) 122. Example ULL AON domain 106 includes example power management unit (PMU) 124, example clock module (CKM) 126, example input / output controller (IOC) 128, example SPI follower (FLLR) 130, example memory-mapped register (MMR) 132, example temperature monitoring circuitry (TMP MONCKT) 134, example leakage current (Ilkg) control circuitry (CNTR) 136, and example reset controller (RST CNTR) 138.

[0025] Figure 1 The voltage regulator 102 regulates the voltage from a power source (e.g., a battery, external power supply, etc.) to one or more voltages (e.g., supply voltages) suitable for components in the SVT domain 104 and / or the ULL AON domain 106. For example, the voltage regulator 102 may include one or more directional current (DC) to DC converters, low-dropout regulators (LDOs), etc. During normal operation, the voltage regulator 102 provides one or more supply voltages to the SVT domain 104 and the ULL AON domain 106. However, during low-power mode, the supply voltage is not provided to the SVT domain 104 to conserve power. Instead, during the low-power mode of the computing device 100, only the ULL AON domain 106 is operational.

[0026] Figure 1The SVT domain 104 contains one or more devices that can be implemented using higher power standard threshold voltage (SVT) transistors. For example, GPT 108, UART 110, SPI 112, I2C 114, digital radio device 116, CPU 118, SRAM 120, and / or VIMS 122 are high-power, high-performance components that can implement one or more SVT transistors. However, as described above, in low-power mode, the components in SVT domain 104 are not powered to conserve energy. After a reset is performed by the reset controller 138 in ULL AON domain 106, computing device 100 resets and restarts after several clock cycles, using CPU 118 to execute the user application again. After a reset, while in active mode before re-entering low-power mode, CPU 118 can check the cause of the reset and perform thermal management. In some examples, CPU 118 can be configured to keep computing device 100 in shutdown mode for a specified duration. In some examples, CPU 118 can increase the duration of the shutdown mode based on the number of resets within the duration.

[0027] ULL AON domain 106 contains components that utilize ULL transistors. Compared to SVT transistors, ULL transistors are more efficient and consume less power, but have lower performance. For example, PMU 124, CKM 126, IOC 128, SPI FLLR 130, MMR 132, temperature monitoring circuitry 134, leakage current control circuitry 136, and reset controller 138 are components that can implement one or more ULL transistors with lower power consumption and lower performance. PMU 124 may be an application-specific integrated circuit (ASIC) for controlling and powering various components / devices and / or peripheral devices / components. PMU 124 may contain transistors for supplying current to various components and / or peripheral components. As further described below, leakage current control circuitry 136 may use charging pulses (also known as inductor charging pulses) to drive and / or control the transistors of PMU 124 to determine the amount of standby current consumed by peripheral components.

[0028] Figure 2 The CKM 126 generates one or more clock signals that can be used by various components of the ULL AON domain 106. The CKM 126 may include one or more oscillators (e.g., clock oscillators, crystal oscillators, etc.) to generate the one or more clock signals. An oscillator is a device for generating clock signals (e.g., clock signals with different frequencies). For example, the oscillator generates a periodic signal for the leakage current control circuitry system 136, which can be used to monitor temperature and / or leakage current.

[0029] Figure 1The MMR 132 contains various registers that can store information. For example, during normal operation, the user can provide preferences for monitoring temperature and / or current via the CPU 118. The CPU 118 can then input values ​​corresponding to these preferences into one or more of the MMR 132 for use during low-power modes. (See below for further details.) Figure 2 Further, MMR 132 can store one or more of the following: a baseline lower temperature limit, a baseline upper temperature limit, a temperature step size, a temperature sensing trigger rate, a temperature rise sample count, and a standby current limit (e.g., a maximum current threshold). For example, a user can program the temperature monitoring circuitry 134 to trigger temperature measurements at a user-defined rate (e.g., every 256 milliseconds (ms), every 512 ms, per second, etc.) by storing values ​​corresponding to the trigger rate in MMR 132. In another example, a user can encode a base temperature value, a temperature upper limit, and a temperature step size into one or more of the MMR 132. If the measured temperature is higher than the base temperature value, then temperature change tracking is initialized. If a user wants to start temperature tracking from 70 degrees Celsius (°C) in 1°C steps (e.g., where the temperature upper limit increases by 1°C after each comparison), then the user can program a 70°C baseline value into one MMR 132 and a 1°C step size into another MMR 132. Users can also program temperature rise sample counts into an MMR 132 to determine how many consecutive temperature measurements are needed above the upper temperature limit before the trigger device resets. The MMR 132 is discussed below. Figure 2 Further description.

[0030] Figure 1 The temperature monitoring circuit system 134 includes circuitry for acquiring temperature samples that can be compared with one or more thresholds. For example, the temperature monitoring circuit system 134 may include a temperature sensor for generating analog-based temperature measurements, an analog-to-digital converter (ADC) for converting the analog-based temperature measurements into digital temperature measurements, and timing circuitry for triggering the ADC to generate digital temperature samples based on the temperature measurements from the temperature sensor. The temperature monitoring circuit system 134 is described below in conjunction with... Figure 2 Further description.

[0031] Figure 1The leakage current control circuitry 136 triggers a reset of the computing device 100 based on monitored temperature trends and / or total standby current consumption to protect the computing device 100 and / or the battery. As described above, leakage current increases exponentially with increasing temperature. Therefore, the leakage current control circuitry 136 monitors temperature changes and total standby current to prevent excessive battery power consumption during low-power modes. Because software use is limited in the ULL AON domain 106, the leakage current control circuitry 136 provides a hardware-based temperature monitoring circuitry to identify a steady increase in temperature over a user-defined duration, which can be used to trigger a device reset. Figure 1 The reset controller 138 triggers the reset of the computing device 100 based on a reset signal from the leakage current control circuit system 136. The leakage current control circuit system 136 is described below in conjunction with... Figure 2 Further description.

[0032] Figure 2 yes Figure 1 Block diagrams of example PMU 124, example leakage current control circuit system 136, and example temperature monitoring circuit system 134. Figure 2 The temperature monitoring circuit system 134 includes an example temperature sensor 200, an example timer trigger circuit system 202, and an example analog-to-digital converter (ADC) 204. The leakage current control circuit system 136 includes an example temperature-to-ADC code conversion circuit system 206, an example digital window comparator 208 including two example comparators 210 and 212, an example finite state machine 214, an example counter 216, an example comparator 218, an example digital ammeter 220, an example comparator 222, and an example logic gate 224. Figure 2 It further includes example memory-mapped registers 225, 226, 228, 230, and 232, which are... Figure 1 The part of MMR 132.

[0033] Figure 2 Temperature sensor 200 senses temperature (e.g., silicon junction temperature) and provides the sensed temperature to ADC 204. Temperature sensor 200 provides the sensed temperature as an analog signal corresponding to the sensed temperature. Temperature sensor 200 is coupled to ADC 204.

[0034] Figure 2The timer trigger circuit system 202 generates a trigger or pulse at predefined time points based on a trigger rate (e.g., every 256 ms, 512 ms, 1 second, etc.) stored in the trigger rate MMR 225. As further described below, the trigger rate MMR 225 stores a value corresponding to a user- and / or manufacturer-selected frequency of the pulse to be applied to the ADC 204. Therefore, the timer trigger circuit system 202 accesses the trigger rate value from the trigger rate MMR 225 to determine the frequency of the pulse signal to be provided to the ADC 204. As further described below, the ADC 204 converts the temperature measurement value at each pulse of the pulse signal. The timer trigger circuit system 202 generates the pulse signal using a clock signal generated by the CKM 126. The timer trigger circuit system 202 is coupled to the CKM 126, the ADC 204, and the trigger rate MMR 225.

[0035] Figure 2 The ADC 204 converts an analog-based temperature measurement (e.g., a signal) from the temperature sensor 200 into a digital-based temperature measurement (e.g., a signal) corresponding to the sensed temperature. Although the temperature sensor 200 can continuously send analog temperature signals to the ADC 204, the ADC 204 converts the analog signal at specific points in time based on a trigger (e.g., a pulse) from the timer-triggered circuitry 202. Therefore, based on a trigger (e.g., a pulse) from the timer-triggered circuitry 202, the ADC 204 samples the analog temperature signal from the temperature sensor 200 and converts the sample into a digital value representing the sensed temperature. The ADC 204 provides the digital temperature sample to the digital window comparator 208. The ADC 204 is coupled to the temperature sensor 200, the timer-triggered circuitry 202, and the digital window comparator 208.

[0036] Figure 2The temperature-to-ADC code circuitry 206 converts a user- and / or manufacturer-selected temperature value from a first format to a second format corresponding to the format of the output signal of the ADC 204. The user can select at least one of a minimum temperature threshold (e.g., a baseline temperature) or a maximum temperature threshold (e.g., a user / manufacturer-defined initial maximum temperature threshold or a baseline temperature threshold plus a temperature step) and a temperature step, storing the threshold in a baseline temperature MMR 226 and the temperature step in a temperature step MMR 228. However, the format of the output of the ADC 204 can differ from the format of the values ​​stored in MMRs 226 and 228. Therefore, the temperature-to-ADC code circuitry 206 can convert the values ​​in MMRs 226 and 228 into a format usable by the ADC 204. The temperature-to-ADC code circuitry 206 may include a lookup table that associates a user / manufacturer-selected value in the first format with an ADC value in the second format. In some examples, the temperature-to-ADC code circuitry 206 can convert a baseline temperature value or step size based on a pre-stored temperature sensor slope and offset coefficient, and provide a lower limit value to the window comparator 208. Furthermore, based on a trigger or instruction from the finite state machine 214, the temperature-to-ADC code 206 increments a user / manufacturer-selected maximum temperature threshold in temperature steps stored in the MMR 228. The temperature-to-ADC code circuitry 206 provides the ADC value corresponding to the maximum temperature threshold to a first comparator 210 of the digital window comparator 208, and provides the ADC value corresponding to the minimum temperature threshold to a second comparator 212 of the digital window comparator 208. The temperature-to-ADC code 206 is coupled to the digital window comparator 208, the finite state machine 214, and the MMRs 226 and 228.

[0037] Figure 2The digital window comparator 208 compares the sensed temperature with a minimum temperature threshold and a maximum temperature threshold. For example, a first comparator 210 compares the upper temperature limit from the temperature-to-ADC code circuitry 206 with the sensed temperature data from the ADC 204, and a second comparator 212 compares the lower temperature limit from the temperature-to-ADC code circuitry 206 with the sensed temperature from the ADC 204. If the sensed temperature signal is below the maximum temperature threshold, comparator 210 provides a first voltage (e.g., logic low or 0 V) ​​to the finite state machine 214. If the sensed temperature signal is above the maximum temperature threshold, comparator 210 provides a second voltage (e.g., logic high or 1.3 V) to the finite state machine 214. Comparator 210 is coupled to the temperature-to-ADC code circuitry 206, the ADC 204, and the finite state machine 214. If the sensed temperature signal is below the minimum temperature threshold, comparator 212 provides a first voltage (e.g., logic low or 0 V) ​​to the finite state machine 214. If the sensed temperature signal is higher than a minimum temperature threshold, then comparator 212 provides a second voltage (e.g., a logic high voltage or 1.3 V) to finite state machine 214. Comparator 212 is coupled to temperature-to-ADC code circuitry 206, ADC 204, and finite state machine 214.

[0038] Figure 2 Finite state machine 214 is a hardware-based state machine that adjusts the tracking count and / or the maximum temperature threshold based on the output signal of digital window comparator 208. For example, finite state machine 214 initiates operation after the output of second comparator 212 is a voltage corresponding to a temperature exceeding a minimum threshold voltage. After initiation, if the output of first comparator 210 is a voltage corresponding to a temperature exceeding the maximum temperature threshold, then finite state machine 214 provides a first signal to tracking counter 216 to increment tracking counter 216 by one, and provides a second signal to temperature-to-ADC code circuitry 206 to adjust the maximum temperature threshold according to temperature steps stored in MMR 228, as further described above. If the output of first comparator 210 is a voltage corresponding to a temperature below the maximum temperature threshold, then finite state machine 214 provides a first signal to tracking counter 216 to reset the tracking count, and provides a second signal to temperature-to-ADC code circuitry 206 to reset the maximum temperature threshold to a baseline maximum temperature threshold stored in MMR 226. Furthermore, finite state machine 214 can output a signal to reset the tracking counter and reset the highest temperature threshold after receiving a signal from comparator 218 indicating that a reset will be performed. Finite state machine 214 is coupled to temperature-to-ADC code circuitry 206, digital window comparator 208, tracking counter 216, and comparator 218.

[0039] Figure 2 A trace counter 216 (e.g., a 5-bit trace counter) stores the count (also referred to as the counter value). Furthermore, the trace counter 216 increments and / or resets the count based on output signals from the finite state machine 214. Initially, the count is zero. The trace counter 216 increments the count each time the finite state machine 215 provides a signal corresponding to an increment instruction / command. If the finite state machine 214 provides a reset signal to the trace counter 216, then the trace counter 216 resets the count to zero. The trace counter 216 provides the counter value to the comparator 218. The trace counter 216 is coupled to the finite state machine 214 and the comparator 218. Although... Figure 2 The example includes a tracking counter 216, but in some examples, a timer can be implemented. In such examples, the timer can be initiated based on a measured temperature exceeding a temperature limit. If a subsequent measured temperature falls below the temperature limit, the timer can be reset. If the timer reaches a specific value, comparator 218 can trigger a reset, as further described below.

[0040] Figure 2 Comparator 218 compares the counter value with a user / manufacturer-selected temperature rise sample count stored in MMR 230. As further described below, the user and / or manufacturer can select the temperature rise sample count and store it in MMR 230. The temperature rise sample count corresponds to the number of consecutive high-temperature readings allowed before triggering a reset. For example, if the temperature rise sample count is four, then comparator 218 provides a first voltage (e.g., logic low or 0 V) ​​to logic gate 224 and finite state machine 214 until the counter value from track counter 216 reaches four. After comparator 218 determines that the counter value has reached the temperature rise temperature count, comparator 218 provides a second voltage (e.g., logic high or 1.3 V) to finite state machine 214 and logic gate 224 to trigger a reset and to trigger finite state machine 214 to reset the track count. Comparator 218 is coupled to track counter 216, MMR 230, finite state machine 214, and logic gate 224.

[0041] Figure 2The digital ammeter 220 generates a digital signal corresponding to the total standby current (also known as low-power current) based on inductor charging pulses from the PMU 124. The PMU 124 controls a DC-DC buck converter, which is used to reduce low-power current consumption (e.g., to absorb and supply inductors and / or peripheral devices). The ammeter 220 counts the number of charging pulses delivered to the inductors and / or peripheral devices (e.g., based on the signal from the PMU 124) and accumulates the counts over a certain period of time (e.g., based on a clock signal from the CKM 126) to represent the standby current consumption. The standby current may increase due to multiple peripheral operations at different clock frequencies. For example, a UART in follower mode may receive data at 1 megabaud, an SPI follower 130 may operate at 4 Mbps, and an I2C follower may receive data at 400 kHz. The ammeter 220 may periodically, irregularly, or based on triggers, based on the number of charging pulses within the time period, output a measured standby current value to comparator 222. As described above, standby current may increase due to multiple peripheral operations at different clock frequencies. Digital ammeter 220 is coupled to CKM 126, PMU 124 and comparator 222.

[0042] Figure 2 Comparator 222 compares the measured standby current value from digital ammeter 220 with a user / manufacturer-selected maximum current threshold stored in MMR 232. As further described below, the user and / or manufacturer can select the standby current threshold and store the count in MMR 232. The standby current threshold corresponds to the maximum allowable standby current before triggering a reset. For example, if the measured standby current is below the threshold, comparator 222 provides a first voltage (e.g., logic low or 0 V) ​​to logic gate 224. If the measured standby current is above the threshold, comparator 222 provides a second voltage (e.g., logic high or 1.3 V) to logic gate 224 to trigger a reset. Comparator 222 is coupled to digital ammeter 220, MMR 232, and logic gate 224.

[0043] Figure 2Logic gate 224 is an OR gate. If either comparator 218 or 222 provides a voltage corresponding to a counter value higher than the temperature rise sample count or a measured standby current higher than the standby current threshold, then logic gate 224 compares the outputs of the two comparators 218 and 222 to trigger a reset. In this way, if the counter value does not exceed the temperature rise sample count and the measured standby current does not exceed the standby current threshold, then logic gate 224 provides a first voltage (e.g., logic low or 0 V) ​​to the reset controller 138 to indicate that a reset is not required. If the counter value exceeds the temperature rise sample count or the measured standby current exceeds the standby current threshold, then logic gate 224 provides a second voltage (e.g., logic high or 1.3 V) to the reset controller 138. After receiving the second voltage from logic gate 224, the reset controller 138 resets the computing device 100. Logic gate 224 is coupled to finite state machine 214, comparators 218 and 222, and reset controller 138.

[0044] Figure 3 It means that it can be passed. Figure 1-2 The flowchart illustrates the method and / or example operation 300 executed and / or instantiated by the computing device 100, CPU 118, PMU 124, leakage current control circuitry system 136, and / or temperature monitoring circuitry system 135. Operation 300 can be performed by... Figure 1-2 Any one or a combination of the circuit systems shown may be executed. Although Figure 3 The instructions and / or operations are combined Figure 1 and 2 The computing device 100 and / or the ULL AON domain 106 are described, but the instructions and / or operations can be described in combination with any type of implementation of the processing circuitry system. Figure 3 Some of the processes shown can be executed in a different order than described, and many processes can be executed simultaneously in parallel. Furthermore, in some examples of this specification, Figure 3 The process shown can be omitted or replaced.

[0045] Figure 3 Machine-readable instructions and / or operations 300 begin at box 302, where CPU 118 stores user / manufacturer-defined configurations. Figure 1 and 2The configuration is stored in memory register 132. For example, a user or manufacturer can define the configuration by instructing the CPU 118 to store configuration information in register 132 in the ULL AON domain 106. The user / manufacturer can store the baseline temperature (e.g., minimum temperature threshold) in the baseline temperature MMR 226, the temperature step size in the temperature step size MMR 228, the temperature sensor trigger rate in the trigger rate MMR 225, the temperature rise sample count in the temperature rise sample count MMR 230, and the low power current limit in the standby current limit MMR 232.

[0046] At box 304, CPU 118 determines whether to enter a low-power mode. CPU 118 may enter a low-power mode based on the duration of limited or no activity, user instructions, triggers, etc. If CPU 118 determines not to enter a low-power mode (box 304: No), control returns to box 304. If CPU 118 determines to enter a low-power mode (box 304: Yes), control continues to boxes 306 and 324. Figure 3 In example operation 300, boxes 306-322 and boxes 324-326 are performed in parallel. However, in some examples, the instructions can be executed sequentially.

[0047] At block 306, example timer-triggered circuitry 202 triggers ADC 204 to convert analog temperature measurements into digital temperature measurements. As further described above, timer-triggered circuitry 202 uses a clock signal from CKM 126 and a user / manufacturer-defined trigger rate stored in trigger rate MMR 225 to trigger ADC 204 to generate temperature samples based on the trigger rate. ADC 204 provides the digital temperature measurements to digital window comparator 208. At block 308, a second comparator 212 determines whether the digital temperature measurement is below a first threshold (e.g., a baseline temperature threshold corresponding to a user / manufacturer-selected value stored in baseline temperature MMR 226). If comparator 212 provides a voltage corresponding to the temperature measurement being below the first threshold (block 308: yes), then hardware-based finite state machine 214 resets temperature tracking (e.g., disconnects temperature tracking) and, in incrementing cases, resets the tracking counter (block 310), and control returns to block 306. If comparator 212 provides a voltage corresponding to a temperature measurement value that is not lower than a first threshold (box 308: No), then the hardware-based finite state machine 214 initiates or continues temperature tracking (box 312).

[0048] At block 314, the first comparator 210 determines whether the temperature measurement is below a second temperature threshold (e.g., an upper temperature limit). Initially, the initial second temperature threshold may be defined by the user / manufacturer and stored in a baseline temperature MMR 226. Alternatively, the initial second temperature threshold may correspond to a baseline temperature threshold (e.g., stored in baseline temperature threshold MMR 226) plus a temperature step (e.g., stored in temperature step MMR 228). After the temperature measurement is above the second threshold, the second threshold is incremented by the temperature step, as further described below. If the first comparator 210 determines that the temperature measurement is below the second temperature threshold (block 314: yes), then the finite state machine 214 resets the tracking counter 216 and / or the second temperature threshold back to the initial second temperature threshold (block 316) if the tracking counter and the second temperature threshold have previously been incremented, and control returns to block 306.

[0049] If the first comparator 210 determines that the measured temperature value is not lower than the second temperature threshold (box 314: No), then the finite state machine 214 increments the tracking counter 216 and the second temperature threshold (box 318). The finite state machine 214 increments the tracking count of the tracking counter 216 by '1' and increments the second threshold by the temperature step value stored in the temperature step MMR 228.

[0050] At block 320, comparator 218 determines whether the tracking count monitored by tracking counter 216 is greater than or equal to the temperature rise sample count stored in temperature rise sample count MMR 230. The tracking count can be used as an indicator or measure of the amount of time the temperature exceeds a first threshold. As described above, the temperature rise sample count can be the number of consecutive temperature measurements that exceed the increased temperature limit before triggering a reset, as defined by the user / manufacturer. If comparator 218 determines that the tracking count is not at or above the temperature rise sample count (block 320: No), then control returns to block 306. If comparator 218 determines that the tracking count is at or above the temperature rise sample count (block 320: Yes), then comparator 218 signals to finite state machine 214 to reset the tracking count monitored by tracking counter 216 to its initial value (e.g., 0) and reset the second temperature threshold to its initial second temperature threshold (block 322).

[0051] At block 324, digital ammeter 220 measures the low-power current. As described above, ammeter 220 counts the number of charging pulses delivered to the external inductor (e.g., based on a signal from PMU 124) and accumulates the counts over a period of time (e.g., tracked based on a clock signal from CKM 126) to represent standby current consumption. At block 326, comparator 222 determines whether the low-power current is higher than a low-power current threshold (e.g., defined by the user / manufacturer and stored in the standby current limit MMR 232). If comparator 222 determines that the low-power current is not higher than the low-power current threshold (block 326: No), then control returns to block 324 to continue measuring / monitoring the low-power current. If comparator 222 determines that the low-power current is higher than the low-power current threshold (block 326: Yes), then control proceeds to block 328.

[0052] At block 328 (e.g., if the tracking count is higher than a count threshold or if the standby current is higher than a standby current threshold), logic gate 224 signals reset controller 138 to trigger a device reset. The device reset restarts and executes the user application. In some examples, the reset can be configured by the application to remain in shutdown mode for a sufficient amount of time to allow computing device 100 to cool down, thereby protecting computing device 100 from damage or further battery depletion.

[0053] Figure 4 Is with Figure 2 Example timing diagram 400 corresponding to the example temperature monitoring of the leakage current control circuit system 136. Figure 4 This includes an example temperature measurement cycle signal 402, an example ADC temperature data signal 404, an example lower limit signal 406, an example upper limit signal 408, an example track counter reset signal 410, an example track counter increment signal 412, an example temperature rise sample count signal 414, an example track counter value signal 416, and an example device reset request signal 418. The example temperature measurement cycle signal 402 corresponds to the output of the timer trigger circuit system 202. The ADC temperature data signal 404 corresponds to the output of ADC 204. The lower limit signal 406 corresponds to the lower limit output of the temperature-to-ADC code circuit system 206. The upper limit signal 408 corresponds to the upper limit output of the temperature-to-ADC code circuit system 206. The track counter reset signal 410 corresponds to the reset signal output by the finite state machine 214. The track counter increment signal 412 corresponds to the increment signal output by the finite state machine 214. The temperature rise sample count signal 414 corresponds to the value stored in the temperature rise sample count MMR 230. The tracking counter value signal 416 corresponds to the tracking count output by tracking counter 216. The device reset request signal 418 corresponds to the output of comparator 218 or logic gate 224.

[0054] exist Figure 4 In the example, the baseline temperature lower limit is 0x500 (which can correspond to 70 degrees Celsius), the baseline temperature upper limit is 0x550 (which can correspond to 75 degrees Celsius), the temperature step size is 0x010 (which can correspond to 1 degree Celsius), and the temperature rise sample count is 0x4 (which corresponds to the count of 4 consecutive samples before triggering the reset). At time t1, the temperature measurement cycle signal 402 generates a pulse, which triggers the ADC 204 to convert the analog temperature measurement value from the temperature sensor 200 into a digital value of 0x482, as shown in the ADC temperature data 404. Because the ADC temperature data 404 is less than the window comparator upper limit 408 0x500, the FSM machine 214 provides a high voltage for the track counter reset signal 410 to hold the track counter value 416 at 0x0.

[0055] At time t2, ADC 204 generates an ADC temperature data signal 404 0x524, which is still less than the upper limit 0x550. At time t3, the ADC temperature signal 404 0x556 is higher than the upper limit 0x560. Therefore, finite state machine 214 increments the upper limit signal 408 to 0x560 (e.g., the temperature upper limit is increased by a temperature step). Furthermore, finite state machine 214 decreases the track counter reset signal 410 to a low voltage and increases the track counter increment signal 412 to a high voltage, causing the track counter 216 to increment the track counter value 416 from 0x0 to 0x1. However, because the track count value 416 0x1 is below the 0x4 threshold of the temperature rise sample count signal 414, the device reset request signal 418 is not triggered. Instead, the device reset request signal 418 remains low (e.g., 0 V). By delaying the device reset request signal 418 until the track count value 416 reaches the 0x4 threshold, the device avoids a reset for a temporary temperature rise. This method is similar to image stabilization technology; it delays the response until the stimulus duration exceeds the duration associated with transience. In other words, the device resets due to sustained (rather than temporary) high temperatures. For these reasons, using a tracking count value of 416 reduces false positives and associated reset events caused by transient temperature increases.

[0056] At time t4, the ADC temperature signal 404 0x564 is higher than the upper limit 0x560. Therefore, finite state machine 214 increases the upper limit signal 408 to 0x570 (e.g., the temperature upper limit is increased by a temperature step). Furthermore, finite state machine 214 maintains a high voltage for the tracking counter increment signal 412, causing the tracking counter 216 to increment the tracking counter value 416 from 0x1 to 0x2. However, because the tracking count value 416 0x2 is lower than the 0x4 threshold of the temperature rise sample count signal 414, the device reset request signal 418 is not triggered.

[0057] At time t5, the ADC temperature signal 404 0x542 is below the upper limit 0x570. Therefore, finite state machine 214 resets the upper limit signal 408 to 0x550. Furthermore, finite state machine 214 lowers the tracking counter increment signal 412 to a low voltage and increases the tracking counter reset signal 410 to a high voltage, thereby resetting the tracking counter 216 to 0x0.

[0058] During times t6-t8, the ADC temperature signal 404 is higher than the increased upper limit signal 408 (e.g., 0x558>0x500, 0x564>0x560, 0x576>0x570). Therefore, finite state machine 214 increases the upper limit signal 408 from time t6 to after time t8. Furthermore, finite state machine 214 maintains a high voltage for the tracking counter increment signal 412 and a low voltage for the tracking counter reset signal 410, thereby causing the tracking counter 216 to increase the tracking counter value 416 from 0x0 to 0x3 from time t6 to after time t8.

[0059] At time t9, the ADC temperature signal 404 is higher than the temperature upper limit 408 (e.g., 0x585 > 0x580). Therefore, the finite state machine 214 maintains a high voltage for the tracking counter increment signal 412 and a low voltage for the tracking counter reset signal 410, causing the tracking counter 216 to increment the tracking counter value 416 from 0x3 to 0x4 after time t9. Because the tracking counter value 416 is at the temperature rise sample count value 0x4 after time t9, the device reset request signal 418 increases to a high voltage to trigger a device reset. Furthermore, after time t9, the window comparator upper limit signal 408 resets to the baseline upper limit, and the tracking counter value 416 resets to the initial value 0x0.

[0060] Figure 5 Is with Figure 2 Example timing diagram 500 corresponding to the standby current monitoring of the leakage current control circuit system 136. Figure 5 This includes an example ammeter measurement cycle signal 502, an example ammeter standby current data signal 504, an example standby current limit 506, and an example device reset request 508. The example ammeter measurement cycle signal 502 and... Figure 2 The digital ammeter 220 corresponds to the duration of the inductor charging pulse sampling. Example ammeter standby current data signal 504 corresponds to the standby current measurement value output by digital ammeter 220. Example standby current limit 506 corresponds to the value used to trigger a reset and is... Figure 2 The standby current limit corresponds to the standby current threshold of the MMR 232 storage / output. Example device reset request 508 and... Figure 2 The outputs of comparator 222 or logic gate 224 correspond to each other.

[0061] At time t1, the digital ammeter 220 uses the inductor charging pulse to generate and measure the standby current value, as described above. Figure 2 Further description. For example, at time t1, the ammeter standby current data 504 is adjusted to a value of 0x200. Because the standby current limit 506 corresponds to the maximum threshold 0x300, at time t1, the value of the ammeter standby current data 504 is lower than the standby current limit (e.g., the maximum current threshold). For each pulse of the ammeter loop signal 502, the digital ammeter 220 generates a new standby current measurement value based on the clock signal and the number of inductor charging pulses. However, for each current measurement value before time t2, the ammeter standby current data value is lower than the standby current limit. Therefore, the device reset request signal 508 remains at a low voltage. At time t2, the digital ammeter 220 provides a value of 0x310 for the ammeter standby current data 504, which is higher than the standby current limit 0x300. Therefore, after time t2, the comparator 222 and the logic gate 224 increase the device reset request signal 508 from a low voltage to a high voltage, thereby triggering a device reset. For example, logic gate 224 provides a high voltage to reset controller 138, thereby triggering reset controller 138 to initiate device reset.

[0062] Implementation Figure 1 Example mode of computing device 100 in Figure 1-2 As shown in the image. However... Figure 1-2 One or more of the elements, processes and / or devices shown may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other way.

[0063] also, Figure 1-2 The PMU 124, CKM 126, leakage current control circuit system 136, reset controller 138, temperature sensor 200, ADC 204, timer trigger circuit system 202, digital window comparator 208, comparators 210, 212, 218, 222, finite state machine 214, tracking counter 216, digital ammeter 220, and / or logic gate 224 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Therefore, for example, Figure 1-2The PMU 124, CKM 126, leakage current control circuit system 136, reset controller 138, temperature sensor 200, ADC 204, timer trigger circuit system 202, digital window comparator 208, comparators 210, 212, 218, 222, finite state machine 214, tracking counter 216, digital ammeter 220 and / or logic gate 224 can be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and / or field-programmable logic devices (FPLDs).

[0064] When reading any of the device or system claims in this patent to cover only software and / or firmware implementations... Figure 1-2 At least one of the following is specifically defined as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, a digital universal optical disc (DVD), an optical disc (CD), a Blu-ray disc, etc., containing software and / or firmware: PMU 124, CKM 126, leakage current control circuit system 136, reset controller 138, temperature sensor 200, ADC 204, timer trigger circuit system 202, digital window comparator 208, comparators 210, 212, 218, 222, finite state machine 214, tracking counter 216, digital ammeter 222, and / or logic gate 224. Figure 1-2 The PMU 124, CKM 126, leakage current control circuit system 136, reset controller 138, temperature sensor 200, ADC 204, timer trigger circuit system 202, digital window comparator 208, comparators 210, 212, 218, 222, finite state machine 214, tracking counter 216, digital ammeter 222, and / or logic gate 224 may contain one or more elements, processes, and / or devices as... Figure 1-2 The elements, processes, and apparatus shown may be supplements or alternatives to those shown, and / or may include more than one of any or all of the shown elements, processes, and apparatuses. As used herein, the phrase “communication” includes variations thereof that cover direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-off events.

[0065] Indicates for implementation Figure 1-2 Example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof flowcharts of computing device 100 are shown in Figure 3As shown in the diagram. Machine-readable instructions can be one or more executable programs or portions of an executable program for execution by a computer processor. The program can be implemented in software, which is stored on a non-transitory computer-readable storage medium, such as a CD-ROM, floppy disk, hard disk drive, DVD, Blu-ray disc, or processor-associated memory, but the entire program and / or portions thereof may alternatively be executed by a device outside the processor, and / or implemented in firmware or dedicated hardware.

[0066] Furthermore, although the example program is a reference Figure 3 The flowcharts shown illustrate, but many other methods of implementing the computing device 100 may be used alternatively. For example, the execution order of the blocks may be changed, and / or some of the blocks described may be altered, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0067] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and packaged format. The machine-readable instructions described herein can be stored as data (e.g., portions of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). Machine-readable instructions may require one or more of the following processes: installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, depackage, allocation, reassignment, compilation, etc., so that they can be directly read, interpreted, and / or executed by computing devices and / or other machines. For example, machine-readable instructions can be stored in multiple parts, which are respectively compressed, encrypted, and stored on separate computing devices, wherein said parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as the program described herein.

[0068] In another example, machine-readable instructions may be stored in a computer-readable state, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the instructions on a specific computing device or another device. In another example, the machine-readable instructions and / or their corresponding programs may be configured (e.g., storage settings, input data, recording network addresses, etc.) before they can be fully or partially executed. Therefore, the described machine-readable instructions and / or corresponding programs encompass these machine-readable instructions and / or programs regardless of their specific format or state at storage or otherwise at rest or in transmission.

[0069] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C-sharp, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0070] As mentioned above, Figure 3 The example process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on a non-transitory computer and / or machine-readable medium, such as a hard disk drive, flash memory, read-only memory, optical disk, digital universal optical disk, cache, random access memory, and / or any other storage device or disk in which information is stored for any duration (e.g., extended time period, permanent, short time period, temporary buffering of information, and / or cache). As used herein, the term non-transitory computer-readable medium is explicitly defined as including any type of computer-readable storage device and / or disk, excluding propagation signals and transmission media.

[0071] While certain example methods, apparatuses, and articles of manufacture have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles of manufacture that fall within the scope of the claims of this patent.

[0072] When identifying multiple elements or components that can be individually mentioned, this document uses descriptive terms such as "first," "second," "third," etc. Unless otherwise specified or known from the context of their use, these descriptive terms do not imply any priority, physical order, or arrangement or chronological order in a list, but are merely labels to refer to multiple elements or components separately to facilitate understanding of the described examples. In some examples, the descriptive term "first" may be used to refer to an element in a detailed description, while the same element may be referred to in the claims by different descriptive terms such as "second" or "third." In such cases, these descriptive terms are used solely for ease of reference to multiple elements or components.

[0073] In this specification and claims, unless otherwise stated, the terms "comprising" and "having," and their variations similar to the term "including," are inclusive. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means a difference of + / -10% from the stated value. In another example, "about," "approximately," or "substantially" preceding a value means a difference of + / -5% from the stated value. In yet another example, "about," "approximately," or "substantially" preceding a value means a difference of + / -1% from the stated value.

[0074] As used herein, the terms “coupled,” “coupled,” “couples,” and variations thereof may cover connections, communication, or signaling paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: in a first example, device A is coupled to device B; or in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A. Furthermore, the terms “coupled,” “coupled,” “couples,” or variations thereof include indirect or direct electrical or mechanical connections.

[0075] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or through a combination thereof.

[0076] Although not in Figure 1-2All are individually labeled, but the components or elements of the systems and circuits shown herein have one or more conductors or ends that allow signals to enter and / or exit the component or element. Conductors or ends (or portions thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0077] As used herein, a “terminal” of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component is typically a conductor, such as a wire, trace, pin, pad, or other connector or interconnect that enables the component, device, system, etc., to be electrically and / or mechanically connected to another component, device, system, etc. For example, a terminal may be used to receive or provide analog or digital electrical signals (or simply signals) or to be electrically connected to a common or ground reference. Thus, an input terminal or input is used to receive signals from another component, device, system, etc. An output terminal or output is used to provide signals to another component, device, system, etc. Other terminals may be used to connect to a common, ground, or voltage reference, such as a reference terminal or ground terminal. Terminals on an IC or PCB may also be referred to as pins (longitudinal conductors) or pads (planar conductors). A node is a connection point or interconnect of two or more terminals. An example number of terminals and nodes may have been shown. However, depending on the specific circuit or system topology, there may be more or fewer terminals and nodes. However, in some cases, the terms “terminal,” “node,” “interconnect,” “pad,” and “pin” are used interchangeably.

[0078] For example, the terms “or” and “and / or” when used in the form of, for example, A, B or C or A, B and / or C, refer to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C.

[0079] This document describes example methods, apparatus, systems, and articles of manufacture for protecting computing devices in low-power modes. Other examples and combinations thereof include the following: Example 1 is a system comprising: a temperature monitoring circuit system configured to generate a first temperature sample and a second temperature sample; and a control circuit system coupled to the temperature monitoring circuit system and configured to increment a count in response to the first temperature sample satisfying a first temperature threshold, increase the first temperature threshold to a second temperature threshold in response to the first temperature sample satisfying the first temperature threshold, compare the second temperature sample with the second temperature threshold after increasing the first temperature threshold to the second temperature threshold, and increment the count in response to the second temperature sample satisfying the second temperature threshold.

[0080] Example 2 includes the system according to Example 1, wherein the control circuitry is configured to increment the count during a low-power mode, wherein the control circuitry is configured to increase the first temperature threshold to the second temperature threshold during the low-power mode, and wherein the control circuitry is configured to compare the second temperature sample with the second temperature threshold during the low-power mode.

[0081] Example 3 includes the system according to Example 1, wherein the control circuitry can be used to compare the second temperature sample with the second temperature threshold in response to the count not meeting the count threshold.

[0082] Example 4 includes a system according to Example 1, wherein the control circuitry can be used to cause a device reset based on the count meeting a count threshold.

[0083] Example 5 includes the system described in Example 4, wherein the first temperature threshold and the counting threshold are user-defined.

[0084] Example 6 includes the system described in Example 1, wherein the step size between the first temperature threshold and the second temperature threshold is user-defined.

[0085] Example 7 includes a system according to Example 1, wherein the temperature monitoring circuitry is configured to generate a third temperature sample before generating the first temperature sample and the second temperature sample, and the control circuitry is configured to reset the count and reduce the second temperature threshold to the first temperature threshold during a low-power mode after the third temperature sample fails to meet the second temperature threshold.

[0086] Example 8 includes the system according to Example 1, further including power management circuitry that can be used to generate charging pulses to provide current to peripheral devices, wherein the control circuitry can be used to determine the current based on the charging pulses and to cause a device reset based on the current being higher than a threshold.

[0087] Example 9 includes a system according to Example 1, wherein the control circuitry can be used to reset the count and reduce the second temperature threshold to the first temperature threshold based on the count meeting a count threshold.

[0088] Example 10 includes a device comprising: a first comparator for comparing a temperature measurement with a temperature threshold; a state machine for incrementing a count in response to the temperature measurement satisfying the temperature threshold, and for increasing the temperature threshold in response to the temperature measurement satisfying the temperature threshold; and a second comparator for causing a device reset based on the count being higher than a count threshold.

[0089] Example 11 includes a device according to Example 10, wherein the first comparator is available for comparing the temperature measurement with the temperature threshold during a low power mode, wherein the state machine is available for incrementing the count and the temperature threshold during the low power mode, and wherein the second comparator is available for causing the device to reset during the low power mode.

[0090] Example 12 includes the device according to Example 10, wherein the state machine can be used to reduce the temperature threshold based on the temperature measurement being lower than the temperature threshold.

[0091] Example 13 includes the device according to Example 10, wherein the temperature measurement is a first measurement, wherein the first comparator is available to compare a second temperature measurement with the temperature threshold, and wherein the state machine is available to reset the count based on the second temperature measurement being lower than the temperature threshold.

[0092] Example 14 includes the device according to Example 13, wherein the first comparator can be used to compare the second temperature measurement with the temperature threshold in response to the count not meeting the count threshold.

[0093] Example 15 includes the device according to Example 10, further comprising: an ammeter for determining the current supplied to a load based on a charging pulse from a power management unit; and a third comparator for causing the device to reset based on the current being higher than a current threshold.

[0094] Example 16 includes the device according to Example 10, wherein the temperature measurement is a digital-based temperature measurement, and the device further includes an analog-to-digital converter that can be used to convert the analog temperature measurement into the digital-based temperature measurement.

[0095] Example 17 includes the device according to Example 16, wherein the analog-to-digital converter can be used to sample analog-based temperature measurements at a user-defined rate.

[0096] Example 18 includes the device according to Example 17, wherein the analog-to-digital converter generates the temperature measurement in a first format, and the device further includes a lookup table that converts the temperature threshold from a second format to the first format.

[0097] Example 19 includes a device comprising: a power management circuit that can be used to generate a charging pulse during a low-power mode to provide current to an external device; a digital ammeter coupled to the power management circuit and used to determine a current based on the charging pulse during the low-power mode; and a comparator coupled to the digital ammeter and used to cause a device reset when the current is above a threshold during the low-power mode.

[0098] Example 20 includes the device according to Example 19, wherein the power management circuitry is used to generate the charging pulses to drive transistors to supply or absorb current for the peripheral device.

[0099] Within the scope of the claims, the described embodiments may be modified, and other embodiments are possible.

Claims

1. A system comprising: A temperature monitoring circuit system that can be used to generate a first temperature sample and a second temperature sample. as well as A control circuit system, coupled to the temperature monitoring circuit system, is capable of: In response to the first temperature sample meeting the first temperature threshold, the count is incremented; In response to the first temperature sample satisfying the first temperature threshold, the first temperature threshold is increased to the second temperature threshold; After increasing the first temperature threshold to the second temperature threshold, compare the second temperature sample with the second temperature threshold; as well as In response to the second temperature sample meeting the second temperature threshold, the count is incremented.

2. The system according to claim 1, The control circuitry described therein is capable of incrementing the count during low-power mode. The control circuitry is configured to increase the first temperature threshold to the second temperature threshold during the low-power mode, and The control circuitry system is capable of comparing the second temperature sample with the second temperature threshold during the low-power mode.

3. The system of claim 1, wherein the control circuitry is configured to compare the second temperature sample with the second temperature threshold in response to the count not meeting the count threshold.

4. The system of claim 1, wherein the control circuitry is configured to cause a device reset based on the count meeting a count threshold.

5. The system of claim 4, wherein the first temperature threshold and the counting threshold are user-defined.

6. The system of claim 1, wherein the step size between the first temperature threshold and the second temperature threshold is user-defined.

7. The system according to claim 1, wherein: The temperature monitoring circuit system is capable of generating a third temperature sample before generating the first and second temperature samples; and The control circuitry system is capable of resetting the count and reducing the second temperature threshold to the first temperature threshold during low-power mode after the third temperature sample fails to meet the second temperature threshold.

8. The system of claim 1, further comprising a power management circuit capable of generating charging pulses to provide current to peripheral devices, wherein the control circuit system is capable of: Based on the charging pulse, the current is determined; and The device is reset because the current is higher than the threshold.

9. The system of claim 1, wherein the control circuitry is configured to reset the count and reduce the second temperature threshold to the first temperature threshold based on the count satisfying a count threshold.

10. An apparatus comprising: The first comparator is used to compare the temperature measurement value with the temperature threshold. State machines can be used for: In response to the temperature measurement value satisfying the temperature threshold, the count is incremented; as well as In response to the temperature measurement value satisfying the temperature threshold, the temperature threshold is increased; and A second comparator is used to trigger a device reset based on the count being higher than a count threshold.

11. The device according to claim 10, The first comparator can be used to compare the temperature measurement with the temperature threshold during low-power mode. The state machine is configured to increment the count and the temperature threshold during the low-power mode, and The second comparator can be used to cause the device to reset during the low power mode.

12. The device of claim 10, wherein the state machine is configured to reduce the temperature threshold based on the temperature measurement being lower than the temperature threshold.

13. The device according to claim 10, wherein the temperature measurement value is a first measurement value, wherein: The first comparator can be used to compare the second temperature measurement value with the temperature threshold; and The state machine can be used to reset the count based on the second temperature measurement value being lower than the temperature threshold.

14. The device of claim 13, wherein the first comparator is configured to compare the second temperature measurement with the temperature threshold in response to the count not meeting the count threshold.

15. The device of claim 10, further comprising: An ammeter capable of determining the current supplied to the load based on charging pulses from the power management unit; and A third comparator is used to cause the device to reset based on the current being higher than a current threshold.

16. The device of claim 10, wherein the temperature measurement is a digital temperature measurement, and the device further comprises an analog-to-digital converter capable of converting the analog temperature measurement into the digital temperature measurement.

17. The device of claim 16, wherein the analog-to-digital converter is capable of sampling analog-based temperature measurements at a user-defined rate.

18. The device of claim 17, wherein the analog-to-digital converter generates the temperature measurement in a first format, the device further comprising a lookup table that converts the temperature threshold from a second format to the first format.

19. An apparatus comprising: A power management circuit that can generate charging pulses to supply current to peripheral devices during low-power modes; A digital ammeter, coupled to the power management circuit and capable of determining the current based on the charging pulse during the low-power mode; as well as A comparator, coupled to the digital ammeter, is used to cause a device reset when the current exceeds a threshold during the low-power mode.

20. The device of claim 19, wherein the power management circuitry is configured to generate the charging pulses to drive the transistors to supply or absorb current to the peripheral device.

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