PMBus-based power supply digital controller implemented on FPGA hardware
By implementing a PMBus power digital controller based on FPGA hardware, the problems of insufficient flexibility and real-time performance in existing PMBus protocol implementation methods are solved, achieving efficient and flexible power control, which is suitable for power management systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU GST INFOMATION TECH CO LTD
- Filing Date
- 2026-04-23
- Publication Date
- 2026-07-31
AI Technical Summary
In existing PMBus protocol implementations, dedicated PMBus interface chips have fixed functions and limited flexibility, increasing system complexity. Meanwhile, general-purpose microcontrollers have limited real-time performance and multi-slave management efficiency, failing to meet the high real-time and high flexibility requirements of power control systems.
A power digital controller based on FPGA hardware is used to implement PMBus, including PMBus interface protocol implementation circuit, power status parsing circuit and power status monitoring platform. By leveraging the parallelism and determinism of FPGA, the state machine drives the IO pins to achieve efficient read and write operations and real-time data parsing, and issues warnings through UART.
It improves the real-time performance and flexibility of the power control system, reduces system complexity, enables high-speed access to multiple slave devices and deterministic data processing, and reduces scheduling delays and resource contention issues.
Smart Images
Figure CN122488918A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrical communication technology, and in particular to a power digital controller based on FPGA hardware implementation of PMBus. Background Technology
[0002] PMBus (Power Management Bus) is an open standard digital power management protocol designed to achieve digital power management. It is a variant of System Management Bus (SMBus), based on I... 2 Built using the C protocol, it is primarily used for power control and management.
[0003] Common PMBus protocol implementations include dedicated PMBus interface chips and general-purpose microcontrollers. Dedicated PMBus interface chips embed the PMBus protocol stack (physical layer, data link layer, and core command set) into hardware. The controller (such as a microcontroller unit (MCU) communicates with this chip via parallel or SPI (Serial Peripheral Interface) buses, and the chip handles low-level tasks such as SMBus timing generation, PEC (Packet Error Checking), and command implementation. General-purpose microcontrollers utilize the MCU's built-in hardware... 2 C peripherals or GPIO (General Purpose Input Quotation) can be used to simulate SMBus timing as the physical layer, with the complete PMBus protocol stack implemented in software.
[0004] However, among the two existing PMBus protocol implementations, dedicated PMBus interface chips hardware-enable complex protocol processing, simplifying the main control design, but with fixed functions, limited flexibility, and increased overall system complexity. Using general-purpose microcontrollers is low-cost and more flexible, but real-time performance, processing power, and multi-slave management efficiency are limited by the MCU core performance and software architecture. These limitations do not meet the high real-time performance and high flexibility requirements of power control systems. Summary of the Invention
[0005] Therefore, it is necessary to provide a power digital controller based on FPGA hardware implementation of PMBus to address the above-mentioned technical problems, and to provide a power control solution with high real-time performance and high flexibility.
[0006] A power digital controller based on FPGA hardware implementation of PMBus includes: an FPGA-based PMBus interface protocol implementation circuit, a power status parsing circuit, and a power status monitoring platform, with the FPGA connected to the power module.
[0007] The PMBus interface protocol implementation circuit is used to perform read and write operations on the power module.
[0008] The power status analysis circuit is used to read the status data of the power module in real time;
[0009] The power status monitoring platform is used to receive status data and issue warnings.
[0010] In one embodiment, when the power module is a single power supply, the PMBus interface protocol implementation circuit completes a read / write operation on the power module in the order of address writing, read / write command writing, read / write content interaction, and triggering the end of communication.
[0011] In one embodiment, when the power module consists of multiple power supplies, the PMBus interface protocol implementation circuit performs read and write operations on the multiple power supplies in a fixed order. After each read and write operation on a power supply is completed, a communication restart is triggered to start the read and write operation on the next power supply. After all read and write operations on all power supplies are completed, the communication ends, thus completing one read and write operation on the power module.
[0012] For each power supply, read and write operations are completed in the order of address writing, read and write command writing, and read and write content interaction.
[0013] In one embodiment, the PMBus interface protocol completes a read / write process of a power module through a three-stage state machine.
[0014] In one embodiment, the power status analysis circuit reads the status data in real time by combining FPGA DSP slices with logic circuits.
[0015] In one embodiment, the power status analysis circuit also performs base conversion on the status data by combining FPGA DSP slices with logic circuits.
[0016] In one embodiment, the power status monitoring platform compares the status data with preset parameter values, and issues a warning via UART when the status data exceeds the corresponding preset parameter value.
[0017] In one embodiment, the power status monitoring platform is connected to a host computer via UART, and the host computer displays status data and warnings.
[0018] In one embodiment, the power status monitoring platform configures preset parameter values via UART.
[0019] In one embodiment, the power status monitoring platform is also used to employ external hard shutdown or internal soft shutdown.
[0020] The aforementioned power digital controller based on FPGA hardware implementation of PMBus includes: an FPGA-based PMBus interface protocol implementation circuit, a power status parsing circuit, and a power status monitoring platform. The FPGA is connected to the power module. The PMBus interface protocol implementation circuit is used to perform read and write operations on the power module; the power status parsing circuit is used to read the power module's status data in real time; and the power status monitoring platform is used to receive status data and issue warnings. This power digital controller design implements PMBus using an FPGA, leveraging the parallelism and determinism of FPGA hardware to eliminate scheduling delays and resource contention issues in traditional software architectures, improving real-time performance. Furthermore, it offers greater flexibility compared to dedicated PMBus interface chips. Attached Figure Description
[0021] Figure 1 This is a block diagram of a power digital controller for PMBus implemented based on FPGA hardware in one embodiment.
[0022] Figure 2 This is a state flowchart of the PMBus interface protocol implementation in one embodiment. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0024] This application provides a power digital controller based on FPGA hardware implementation of PMBus, such as... Figure 1 As shown, it includes: a PMBus interface protocol implementation circuit, a power status parsing circuit, and a power status monitoring platform. All of these circuits or platforms are implemented based on an FPGA (Field Programmable Gate Array) digital platform. The FPGA connects to I... 2 The C bus connects to the power module.
[0025] The PMBus interface protocol implementation circuit is used to perform read and write operations on the power module, the power status parsing circuit is used to read the status data of the power module in real time, and the power status monitoring platform is used to receive status data and issue warnings.
[0026] In this embodiment, the PMBus interface protocol implementation circuit uses FPGA logic circuitry to perform low-level tasks such as PMBus timing generation, PEC verification, and command parsing. PMBus is based on I... 2The physical layer is C, therefore, the FPGA and power module need to be connected via SCL and SDA signal lines. SCL is the clock line, providing a precise and stable clock pulse signal to the FPGA as an output segment and controlling the timing of data transmission between the two sides. SDA is the data line, providing a bidirectional transmission channel between the FPGA and the power module, capable of transmitting control commands and data.
[0027] Typically, the FPGA acts as the master, and the power module as the slave. The FPGA, as the master controller, directly reads and writes the power module's registers. In other modes, the FPGA itself is a PMBus slave device, and external devices read and write the FPGA's internal PMBus registers.
[0028] In the first mode, when the power module is a single power supply, the PMBus interface protocol implementation circuit completes a read / write operation on the power module in the order of address writing, read / write command writing, read / write content interaction, and triggering the end of communication.
[0029] In one embodiment, when the power module consists of multiple power supplies, the PMBus interface protocol implementation circuit performs read and write operations on the multiple power supplies in a fixed order. After completing the read and write operation on each power supply, a communication restart is triggered to start the read and write operation on the next power supply. After completing the read and write operation on all power supplies, a communication termination is triggered, thus completing one read and write operation on the power module. Specifically, for each power supply, the read and write operation is completed in the order of address writing, read and write command writing, and read and write content interaction.
[0030] The PMBus interface protocol implementation circuit achieves time-division multiplexing through precise timing scheduling, efficiently completing simultaneous read and write operations on multiple power supplies (such as parallel power supply groups). Figure 1 Taking the power supply module with power supply A and power supply B connected in parallel as an example, the FPGA performs a read and write operation on the parallel power supply group in the following order: power address A is written, read and write command A is written, read and write content A is interacted, communication is triggered to restart, power address B is written, read and write command B is written, read and write content B is interacted, and communication is triggered to end.
[0031] In one embodiment, the PMBus interface protocol completes a read / write process of a power module through a three-stage state machine, and the communication clock is flexibly adjustable.
[0032] The first stage of the state machine updates the current state based on the "next state" at the rising edge of the clock, ensuring strict synchronization of all state transitions and eliminating glitches, which is the foundation of stability. The second stage determines and specifies the "next state" based on the "current state" and external inputs (such as power module response and counter completion signals). The third stage outputs precise bus control signals (such as SCL and SDA enable), internal counter enable, data shift / load signals, etc., based on the "current state".
[0033] In one embodiment, such as Figure 2 The diagram shows the state diagram of the state machine, including the following states: Saddr (send device number), command_8 (send 8-bit command instruction), Saddr_rd (read device number), Rdate_8 (read 8-bit data), Rdate_16 (read 16-bit data), date_8 (write 8-bit data), date_16 (write 16-bit data), SRaddr (send device number), stop (communication ends), and Idle (idle). It includes the following control signals: mux_wr (write enable), en (communication enable), and done (operation complete), as well as the byte_num, r_byte_num, and group_num signals to control the number of bytes and groups of data transmitted, enabling multi-byte register access.
[0034] In one embodiment, the power status analysis circuit reads the status data in real time by combining FPGA DSP slices with logic circuits.
[0035] Status data includes output current, output voltage, input voltage, temperature, and fan speed.
[0036] FPGA via I 2 The C-bus interface and PMBus interface protocol enable the circuit to read and write power module registers. The logic circuit continuously reads data and sends the data stream to the DSP slice. The DSP slice processes the read data to obtain status data.
[0037] For example, the DSP slice is configured in accumulator mode to calculate the average value of several samples read: the DSP slice completes the accumulation operation in a single cycle without occupying logic units. After the accumulation is completed, the logic circuit controls the DSP slice to shift to the right (division) to obtain the average current / voltage value.
[0038] For example, the DSP slice is configured in multiplier mode to multiply the instantaneous voltage and instantaneous current to obtain the instantaneous power. Then, the instantaneous power is accumulated. After the accumulation is completed, the logic circuit controls the DSP slice to shift to the right (division) to obtain the average power.
[0039] In this embodiment, the logic circuit is responsible for controlling the clock enable and operation mode of the DSP slice, and the DSP slice is responsible for completing the corresponding calculation of the operation mode within a number of clock cycles.
[0040] By combining DSP slicing with logic circuits, the DSP slices can perform tasks that truly require hard-core arithmetic acceleration, such as multiplication, accumulation, and filtering, while the logic circuits are responsible for control-intensive operations such as state machines, protocol parsing, format conversion, and condition judgment, thereby maximizing resource utilization efficiency.
[0041] In one embodiment, the power status analysis circuit also performs base conversion on the status data by combining FPGA DSP slices with logic circuits.
[0042] This embodiment performs number system conversion according to the different ranges of each parameter, converting binary fixed-point fractions of different bit widths into decimal floating-point numbers. This operation is preferably implemented using logic circuits.
[0043] In one embodiment, the power status monitoring platform compares the status data with preset parameter values, and issues a warning via UART when the status data exceeds the corresponding preset parameter value.
[0044] In this embodiment, the power status monitoring platform compares the status data with preset parameter values using a comparator. These preset values are safety thresholds. When the status data exceeds the upper or lower limit of the threshold, it indicates a potential anomaly in the power module, triggering the power status monitoring platform to immediately issue an anomaly warning.
[0045] A UART (Universal Asynchronous Receiver / Transmitter) is responsible for converting data between parallel and serial modes, enabling low-speed, simple, asynchronous serial communication between devices. In this embodiment, the UART is responsible for packaging parallel data into serial data within the FPGA and sending it out; or for unpacking serial data received from the outside into parallel data for use by internal logic.
[0046] The power status monitoring platform connects to the host computer via UART. The UART packages and sends status data, warning signals, and other data to the host computer, which then displays the status data and warning information.
[0047] In one embodiment, the power status monitoring platform configures preset parameter values via UART.
[0048] The host computer sets the preset parameter values and sends them to the FPGA. The UART unpacks them into parallel data and stores them in a register for the power status monitoring platform to call. The platform then compares the updated preset parameter values with the data to determine whether to issue a warning.
[0049] In one embodiment, the power status monitoring platform is also used to employ external hard shutdown or internal soft shutdown.
[0050] External hard shutdown involves the FPGA outputting a GPIO signal to control an external MOSFET or power enable pin, directly cutting off the main power supply. This method is characterized by fast response and thorough power-off. Internal soft shutdown involves the FPGA sending an interrupt signal to the power module, with software saving the data before power-off. This method is characterized by protecting data integrity.
[0051] In one embodiment, the host computer can also send PMBus operation commands to the PMBus interface protocol implementation circuit via UART, including system control (power-on / off control, write protection, fault clearing), configuration and setting (output voltage / current / temperature protection thresholds, timing parameters), telemetry monitoring (reading voltage, current, temperature, power), status and fault (reading fault status, clearing fault flags), identification information (reading device ID, manufacturer, version number), and NVM management (storing / restoring configuration to non-volatile memory), etc. The PMBus interface protocol implementation circuit performs corresponding read and write operations on the power module according to the received operation commands.
[0052] The beneficial effects of this invention are as follows:
[0053] 1. The hardware state machine can switch tasks without delay, enabling high-speed, deterministic access to multiple slave devices.
[0054] Traditional MCUs suffer from low real-time performance, processing power, and efficiency in managing multiple slave devices when communicating via software simulation or internal peripherals. FPGAs, on the other hand, directly drive the level changes of I / O pins (such as the clock line SCL and data line SDA of the PMBus) through state machines. State machine transitions are entirely determined by hardware logic gate delays, not instruction cycles. This is because the state machines operate within the same clock domain, with each state transition occurring on the rising edge of the clock. When task switching is required, the state machine can complete the process within one clock cycle (e.g., 10ns). There is no software overhead associated with task switching. Furthermore, within the FPGA, the hardware state machines can operate completely independently and simultaneously, effectively reducing switching latency.
[0055] 2. It can parse and process the returned data simultaneously.
[0056] Internally, FPGAs can design the receiving and parsing of data in a pipelined structure. For example, while the PMBus protocol stack is receiving the 8th bit (data bit), the logic circuits are already calculating the CRC (Cyclic Redundancy Check) value of the first 7 bits in parallel. When the byte transmission is complete, the hardware comparator has already compared the data with a preset threshold within the same clock cycle and directly generated a hardware flag. In other words, data reception and parsing are physically performed simultaneously through different logic gates, without any serial calls in software.
[0057] 3. The entire control system has low dependence on external components and high integration.
[0058] Traditional solutions typically require a combination of an MCU, crystal oscillator, external watchdog timer, level shifter chip, and complex RC reset circuitry to achieve power control. This invention utilizes an FPGA to achieve a single-chip solution. Specifically, the FPGA not only implements the PMBus protocol controller internally, but can also integrate the following functions that originally required external chips:
[0059] Logic control unit: The timing coordination that originally required external CPLD or logic gate circuits is now directly integrated into the FPGA logic.
[0060] Hardware watchdog and monitoring: By utilizing the internal timer core of the FPGA, a hardware watchdog independent of the logic operation can be built. Even if the PMBus state machine deadlocks, the hardware timer can still independently trigger a global reset, eliminating the need for an external dedicated power monitoring chip.
[0061] Level conversion adaptation: Supports multi-voltage domain IO banks. You can configure Bank1 to 1.8V (for connecting PMBus slave devices) and Bank2 to 3.3V (for connecting to a host computer or backplane). Level matching is completed internally by logic, eliminating the need for external level converters (such as TXS0108).
[0062] Clock source: Many FPGAs have built-in high-precision on-chip oscillators (such as the internal oscillator of the Intel MAX 10, with an accuracy of ±1% to ±2%). For protocols like PMBus, which typically have a maximum speed of 1MHz, the on-chip oscillator fully meets the timing requirements, eliminating the need for an external crystal oscillator.
[0063] Decoupling and Reset: FPGA configuration logic typically incorporates power-on reset (POR) circuitry and delay circuitry, reducing the need for external RC (resistor-capacitor) reset circuitry.
[0064] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0066] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A power digital controller based on FPGA hardware implementation of PMBus, characterized in that, include: The system includes a PMBus interface protocol implementation circuit, a power status parsing circuit, and a power status monitoring platform based on an FPGA, wherein the FPGA is connected to the power module. The PMBus interface protocol implementation circuit is used to perform read and write operations on the power module. The power status analysis circuit is used to read the status data of the power module in real time. The power status monitoring platform is used to receive the status data and issue warnings.
2. The power digital controller according to claim 1, characterized in that: When the power module is a single power supply, the PMBus interface protocol implementation circuit completes a read / write operation on the power module in the order of address writing, read / write command writing, read / write content interaction, and triggering the end of communication.
3. The power digital controller according to claim 1, characterized in that: When the power module consists of multiple power supplies, the PMBus interface protocol implementation circuit performs read and write operations on the multiple power supplies in a fixed order. After each read and write operation on a power supply is completed, a communication restart is triggered to start the read and write operation on the next power supply. After all read and write operations on all power supplies are completed, a communication termination is triggered, thus completing one read and write operation on the power module. For each power supply, read and write operations are completed in the order of address writing, read and write command writing, and read and write content interaction.
4. The power digital controller according to claim 3 or 4, characterized in that: The PMBus interface protocol completes one read / write process of the power module through a three-stage state machine.
5. The power digital controller according to claim 1, characterized in that: The power status analysis circuit reads the status data in real time through FPGA DSP slicing combined with logic circuits.
6. The power digital controller according to claim 5, characterized in that, The power status analysis circuit also performs base conversion on the status data by combining FPGA DSP slicing with logic circuits.
7. The power digital controller according to claim 1, characterized in that: The power status monitoring platform compares the status data with preset parameter values. When the status data exceeds the corresponding preset parameter value, a warning is issued via UART.
8. The power digital controller according to claim 7, characterized in that: The power status monitoring platform is connected to a host computer via UART, and the host computer displays the status data and warnings.
9. The power digital controller according to claim 7, characterized in that: The power status monitoring platform configures the preset values of the parameters via UART.
10. The power digital controller according to claim 1, characterized in that: The power status monitoring platform is also used to perform external hard shutdown or internal soft shutdown.