Fast comparison and fast indexing circuit of floating point data in artificial intelligence chip

Abstract

This invention, entitled "A Fast Comparison and Fast Indexing Circuit for Floating-Point Data in an Artificial Intelligence Chip," belongs to the field of computing chip design technology. The technical problems it addresses include excessively high comparison latency for floating-point data, lack of special value handling, the need for additional hardware circuitry for index output, and poor scalability and resource waste in handling non-power-of-two data. The key technical solution includes a comparator, special value handling, a tree-structured comparison mechanism, non-power-of-two adaptation, and an index passing and concatenation module. A pipelined processing module can be added. The comparator outputs the maximum / minimum value and the initial index based on the control signal. The special value module handles NaN and Inf in hardware. The tree structure enables parallel comparison of power-of-two data at each level. The non-power-of-two module completes data adaptation. The index module passes and concatenates data at each level to form a complete original index. All modules work together to achieve synchronous output of the result and index.

Description

Technical Field

[0001] This invention belongs to the field of computing chip design technology, specifically relating to a fast comparison and fast indexing circuit for floating-point data in an artificial intelligence chip. Background Technology

[0002] In the actual operation of artificial intelligence chips, when performing key operations such as pooling, reduce, and Top-K selection, multiple floating-point data need to be processed in parallel. The rapid comparison of floating-point data and the accurate acquisition of the corresponding original sequence number are the core links to ensure the efficient execution of the above operations, which directly affect the real-time inference performance and computing efficiency of artificial intelligence chips.

[0003] Relevant patent documents retrieved: Country of Origin: China; Publication Number: CN107301031B; Publication Date: No explicit publication (based on search information). This document discloses a normalized floating-point data filtering circuit, including a normalized floating-point data comparator, a rising edge monitoring circuit, an input circuit, and an output circuit. The floating-point data stream Ain and its corresponding address stream Bin are input through the input circuit. After passing through the normalized floating-point data comparator, the output result R is sent to the output circuit, which outputs the obtained maximum / minimum value data. The address corresponding to the data Enable signal Threshold comparison results and the current threshold comparison valid signal This circuit can filter a large amount of normalized floating-point data in a data stream manner, and provide data or corresponding addresses that meet the specified conditions. It can simplify software program design, reduce processor execution power consumption, and make up for the shortcomings of ordinary data comparison instructions that can only compare a few numbers.

[0004] The prior art represented by the aforementioned documents has at least the following unresolved technical problems or defects: (1) The latency is too high. The relevant evidence is that when the traditional solution (including the prior art represented by the aforementioned patent documents) processes 64 floating-point data, the comparison latency is >20ns@7nm process, which cannot meet the real-time inference requirements of AI chips. (2) There are defects in the handling of special values. The relevant evidence is that the aforementioned patent documents do not disclose the hardware handling mechanism for floating-point special values. The existing technology has errors in comparison due to the lack of handling of floating-point special values, and additional overhead is required through software preprocessing. (3) Index output requires additional hardware resources. The relevant evidence is that although the aforementioned patent documents can output the address corresponding to the data, they do not disclose the index generation architecture that is synchronized with the data comparison path. The existing technology requires an additional sorting circuit to realize the index output, which increases the hardware area by 35%. (4) Poor scalability. The relevant evidence is that the aforementioned patent documents do not involve an adaptation scheme for non-power-of-2 data. When processing non-power-of-2 data, the existing technology needs to fill in redundant values, resulting in a waste of hardware resources.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] To address the aforementioned technical problems in the prior art, this invention provides a fast comparison and fast indexing circuit for floating-point data in an artificial intelligence chip, which solves the technical problems of excessively high floating-point data comparison latency, lack of floating-point special value processing, the need for additional hardware circuits for index output, and poor scalability and resource waste in processing non-power-of-2 data.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows: A fast comparison and fast indexing circuit for floating-point data in an artificial intelligence chip includes: The comparator module is used to select the maximum or minimum value to output based on the control signal, and to bypass the output of the initial index corresponding to the maximum or minimum value; The special value processing module is used to process and convert input non-numeric NaN and infinite Inf type floating-point data; The tree-structured comparison module, connected to the comparator module and the special value processing module, is used to receive floating-point data processed by special values ​​up to the power of 2, and to achieve parallel comparison through multi-level comparators. The non-power-2 adaptation module is connected to the tree comparison structure module and is used to adapt the input data that is not aligned to the power of 2. The comparator input terminal corresponding to the non-power-2 aligned data is configured to a preset fixed maximum or minimum value without affecting the final comparison result. The index passing and splicing module, connected to the tree comparison structure module, is used to pass and splice the indexes output by each level comparator step by step, and finally output the complete original index corresponding to the comparison result.

[0008] Furthermore, the special value processing module performs hardware processing and conversion of non-Number NaN and Infinity Inf through a dedicated conversion circuit, without the need for software preprocessing intervention.

[0009] Furthermore, the preset fixed value configuration rule for the non-power-2 adaptation module is as follows: When comparing the maximum value, the useless comparator input is configured to negative infinity; when comparing the minimum value, the useless comparator input is configured to positive infinity.

[0010] Furthermore, the two input terminals of the comparator module are defined as input a and input b, respectively, where the initial index of input a is 0 and the initial index of input b is 1.

[0011] Furthermore, the control signal for the comparator module is: Its control logic is: when When, the comparator module outputs the maximum value; when When the minimum value is reached, the comparator module outputs the minimum value.

[0012] Furthermore, the multi-level comparators of the tree comparison structure module are connected step by step in a binary search manner. When the number of input floating-point data is N=2^k, the total number of levels of the tree comparison structure module is k. Furthermore, the tree-structured comparison module supports circuit reuse, grouping a large amount of input data, comparing it at lower levels, and then performing a final comparison on the grouping results.

[0013] Furthermore, the index passing and concatenation logic of the index passing and concatenation module is as follows: Using the leftmost comparator in the tree comparison structure as level 1 and the rightmost comparator as level 3, the index value is passed from left to right. The first-level comparator outputs a 1-bit initial index, and the number of bits increases by 1 bit for each level passed down. The final output of the complete original index has a total of 1 bit. Where N is the total number of input floating-point data and N is a power of 2; and when concatenating, the index value of the current level is placed in the low bit and the index value of the next level is placed in the high bit.

[0014] Furthermore, the specific splicing process of the index passing and splicing module is as follows: each level comparator splices the index output by this level with the index passed by the next level to form the intermediate index corresponding to this level. After being passed and spliced ​​level by level, the last level comparator of the tree comparison structure module outputs the complete original index.

[0015] Furthermore, the complete original index is a unique identifier of the original sequence number of the input floating-point data, and the number of bits in the complete original index increases with the number of input floating-point data N. The index grows in a regular pattern; the encoding method of the index reduces the number of bits required for signal flipping, thereby reducing circuit power consumption and increasing transmission speed.

[0016] Furthermore, it also includes a pipeline processing module, which is used to implement periodic updates of input data and output the corresponding comparison results and complete original indexes in each period.

[0017] The beneficial effects of this invention are as follows: (1) The comparison result and the original index are output synchronously in the same period. No additional index-related circuits are required. The index transmission and data comparison path are strictly synchronized, ensuring the accurate correspondence between the index and the result, which greatly simplifies the hardware design. (2) The lightweight index-level encoding splicing method is adopted, which saves a lot of encoding bit width and reduces the number of signal flips compared with the traditional full encoding method, thereby improving the index transmission speed and effectively reducing circuit power consumption. (3) The processing and conversion of floating-point special values ​​are completed by dedicated hardware circuits without the need for software preprocessing intervention, which fundamentally avoids comparison errors caused by special values ​​and reduces the additional processing overhead caused by software intervention. (4) It can adapt to input data that is not a power of 2, without filling in redundant values. The comparison results can be guaranteed to be unaffected by extreme value configuration alone. The tree comparison structure supports circuit reuse, which improves the scalability of the circuit while avoiding the waste of hardware resources. (5) The tree-shaped parallel comparison structure combined with pipeline timing control design greatly reduces the floating-point data comparison delay, realizes the periodic update of input data and the continuous output of comparison results, and meets the real-time inference requirements of artificial intelligence chips. Attached Figure Description

[0018] Figure 1 An architecture diagram of a fast comparison and fast indexing circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram illustrating the working principle of the comparator module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the multi-level cascading and index passing splicing of the tree comparison structure module provided in the embodiment of the present invention. Detailed Implementation

[0019] The technical solution of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are not all embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0020] It should be noted that, unless otherwise specifically stated, the relative arrangement and numerical expressions of the components and steps described in these embodiments should not be construed as limiting the scope of the invention.

[0021] The following description of exemplary embodiments is merely illustrative and is not intended to limit the invention or its application or use in any way. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail herein, but where applicable, such techniques, methods, and apparatus should be considered part of this specification.

[0022] Example 1 See Figure 1 , Figure 1 This invention presents an architecture diagram of a fast comparison and fast indexing circuit for floating-point data in an artificial intelligence chip. It is suitable for parallel comparison operations of floating-point data in artificial intelligence accelerators and can be directly applied to scenarios requiring parallel comparison of multiple floating-point data streams, such as neural network pooling layers, reinforcement learning decision-making, pooling, reduce, and Top-K selection in artificial intelligence chips. Specifically, it includes: M1, comparator module, is used to select the maximum or minimum value to output according to the control signal, and bypass the output of the initial index corresponding to the maximum or minimum value; Specifically, see Figure 2 This module is the fundamental comparison unit of the entire circuit. All cascaded comparators in the tree-structured comparison module are composed of this module. Its core function is to select the maximum or minimum value from two input floating-point data based on the externally input control signal, and to synchronously output the 1-bit initial index corresponding to the maximum / minimum value. Specifically, it includes: M11, Input Terminal Definition: The module sets two floating-point data input terminals, namely input a and input b. In order to realize the standardized generation of index, the initial index corresponding to input a is preset to 0, and the initial index corresponding to input b is preset to 1. M12, Control Signal Logic: The module's control signals are... ,when When the module selects to output the maximum value of the two inputs, it also outputs the initial index (0 or 1) corresponding to the maximum value via a bypass. when When the module selects to output the minimum value of the two inputs, it also outputs the initial index (0 or 1) corresponding to the minimum value via a bypass. M13. Connection Relationship: The input terminals of this module are electrically connected to the output terminals of the special value processing module and the non-power-2 adaptation module, respectively, to receive preprocessed floating-point data; the output terminals are electrically connected to the primary comparator input terminal of the tree comparison structure module and the primary input terminal of the index transfer and splicing module, to synchronously output the comparison result value and the initial index.

[0023] M2, the special value processing module, is used to process and convert input non-numeric and infinite floating-point data; Specifically, this module is a floating-point data preprocessing unit. Its core function is to perform hardware-level processing and conversion on special values ​​in the raw floating-point data input from external sources, solving the problems of comparison errors caused by NaN (Not a Number) / Inf (Infinity) and the increased overhead of software preprocessing in existing technologies; specifically including: M21. Processing objects: NaN and Inf type special values ​​in single-precision floating-point data. Based on the classification rules of single-precision floating-point values, the data type of floating-point data (normalized, denormalized, Inf, NaN) is determined by the exponent value. M22. Processing method: The module has a built-in dedicated conversion circuit that directly processes and converts NaN and Inf through hardware circuitry without the need for software intervention. The processed floating-point data can be directly used in subsequent comparisons to ensure the accuracy of the comparison results. M23. Connection Relationship: The module's input terminal is connected to the external floating-point data input port, and its output terminal is electrically connected to the input terminal of the tree comparison structure module and the input terminal of the non-power-2 adapter module, transmitting the processed normalized / denormalized floating-point data to subsequent modules.

[0024] M3, a tree-structured comparison module, is connected to the comparator module and the special value processing module. It is used to receive floating-point data of 2 powers of 2 after special value processing and to achieve parallel comparison through multi-level comparators. Specifically, see Figure 3 This module is the core parallel comparison unit of the entire circuit. Its core function is to receive a power of 2 number of floating-point data points processed with special values. Through a multi-stage comparator connected in a binary search manner, it achieves high-speed parallel comparison of floating-point data, which is the key structure of this invention for reducing comparison latency; specifically, it includes: M31, Structural Rules: The module is composed of the above comparator modules cascaded together. All comparators are connected in a binary search manner. If the total number of input floating-point data is N, and N is a power of 2 (i.e. N=2k, k is a positive integer), then the total number of levels of the module is k. M32, Circuit Multiplexing Feature: The module supports hardware circuit multiplexing and is suitable for comparison processing of a large number of floating-point data. Specifically, it splits a large number of floating-point data that are not multiples of 2^k into multiple groups of power of 2 data. Each group of data is compared through the original level of the comparator module. Finally, the comparison results of each group are compared again through the comparator module to obtain the overall maximum / minimum value. For example, comparing 32 floating-point data requires 5 levels of comparators. When comparing 64 floating-point data, the same 5-level circuit can be reused. The 64 data are divided into two groups of 32 data to complete the 5-level comparison respectively. Then, the comparison results of the two groups are passed through a 1-level comparator to complete the final comparison. M33, Core Synchronization Feature: The floating-point data comparison path and index transmission path within the module are strictly synchronized, ensuring that the comparison result at each level and the transmission of the corresponding index have no delay deviation, providing a foundation for the accurate splicing of subsequent indexes; M34, Connection Relationship: The input terminal of the module is electrically connected to the output terminal of the special value processing module and the non-power-2 adapter module, and receives preprocessed power-2 floating-point data; The outputs of the multi-stage comparators in the module are all electrically connected to the corresponding inputs of the index transmission and splicing module, synchronously transmitting the comparison result value and corresponding index of each stage; the output of the last stage comparator in the module is the pre-output terminal of the result value of the entire circuit, and is electrically connected to the pipeline processing module.

[0025] M4, a non-power-2 adaptation module, is used to adapt input data that is not aligned to a power of 2, configuring the comparator input corresponding to the non-power-2 aligned data to the maximum or minimum value without affecting the final comparison result. Specifically, this module is a data adaptation unit. Its core function is to perform hardware adaptation processing on input floating-point data that is not aligned to powers of 2, solving the problem in existing technologies where processing data that is not aligned to powers of 2 requires filling in redundant values, resulting in wasted hardware resources, and achieving high scalability of the circuit; specifically including: M41, Adaptation Rules: The module configures the useless comparator inputs in non-power-of-2 data to preset fixed values. These fixed values ​​are extreme values ​​that do not affect the final comparison result. Specifically, when the entire circuit needs to compare the maximum output value, the useless input is configured to negative infinity (-inf); when the circuit needs to compare the minimum output value, the useless input is configured to positive infinity (+inf). M42, Adaptation method: The useless input terminal is directly tied to the above extreme value through hardware circuit, without the need to fill redundant floating-point data, and does not occupy hardware storage resources. The adapted floating-point data is a power of 2, which can be directly input into the tree comparison structure module for parallel comparison. M43, Connection Relationship: The input terminal of the module is electrically connected to the output terminal of the special value processing module to receive the raw floating-point data after special value processing; the output terminal is electrically connected to the input terminal of the tree comparison structure module to transmit the adapted power of 2 floating-point data to the parallel comparison unit.

[0026] M5, the index passing and splicing module, is used to pass and splice the indexes output by each level of the comparator, and finally output the complete original index corresponding to the comparison result. Specifically, this module is an index generation unit. Its core function is to pass and concatenate the indices output by each comparator in the tree comparison structure module, ultimately generating and outputting the complete original index corresponding to the comparison result value. This index is a unique identifier of the original sequence number of the input floating-point data. Furthermore, the index encoding method used in this module effectively reduces the number of signal flip bits, lowers circuit power consumption, and improves index transmission speed. Specifically, it includes: M51, Definition of hierarchy and transmission direction: The leftmost comparator of the tree comparison structure module is the first level, and the rightmost comparator is the last level. The index value is passed level by level along the data comparison process from left to right. M52, Index Concatenation Logic: (1) Bit growth rule: The first-stage comparator outputs a 1-bit initial index. For each stage passed down to the next stage, the number of bits in the index increases by 1 bit. The total number of bits in the final output complete original index is log2(N) (N is the total number of input floating-point data, and N is a power of 2). (2) Concatenation position rule: For each level passed down, the index value of the current level is placed in the low bit and the index value of the next level is placed in the high bit, thus completing the concatenation of the two levels of indexes; for example, the current level comparator outputs an index value of 0, the next level passes an index value of 1, and the concatenated intermediate index is {10}. M53, Index Concatenation Process: Each comparator concatenates its own 1-bit output index with the intermediate index passed from the next level to form a new intermediate index corresponding to that level. After being passed and concatenated level by level through all levels of the tree comparison structure module, the final complete original index is output by the last level comparator. M54, Encoding Advantages: Compared with the full encoding index method, the index encoding method of this module can significantly save the number of encoding bits, and the number of signal flipping bits is small, which improves the transmission speed while reducing power consumption; for example, to encode 16 floating-point data, 4 bits of complete index are required. If the full encoding method is used, the comparator of the 4-level connection structure needs to output 4×4=16 bits. This solution only requires 1+2+3+4=10 bits, which reduces the encoding amount by 6 bits. M55, Core Features: The number of bits in the index increases according to the log2(N) rule as the number of input floating-point data N increases, and the index passing and splicing process is strictly synchronized with the data comparison process of the tree comparison structure module, ensuring a one-to-one correspondence between the comparison result value and the complete original index; M56, Connection Relationship: The input terminal of the module is electrically connected to the output terminals of each level of the comparator in the tree comparison structure module, synchronously receiving the 1-bit initial index / intermediate index of each level; the output terminal of the module is the index output terminal of the entire circuit, electrically connected to the pipeline processing module, and outputs the complete original index.

[0027] M6, the pipeline processing module, is used to implement the periodic update of input data, and output the corresponding comparison result and the complete original index in each period; Specifically, see Figure 1 This module is the timing control unit of the circuit. Its core function is to realize the periodic update of input data and ensure that the circuit synchronously outputs the floating-point data comparison result value and the corresponding complete original index in each cycle, thereby improving the real-time processing capability of the circuit and meeting the real-time inference requirements of artificial intelligence chips. Specifically, it includes: M61, Working Logic: The pipeline stages of the module correspond one-to-one with the hierarchy of the tree comparison structure module. The timing of the pipeline is configured according to the hierarchy of the tree comparison structure to realize the update of the input floating-point data in each clock cycle. In each clock cycle, a set of comparison result values ​​and the complete original index can be obtained from the circuit output. M62, Connection Relationship: The module is electrically connected to the comparator module, special value processing module, tree comparison structure module, non-power-2 adapter module, and index passing and splicing module, and the working timing of all modules is uniformly controlled; the output of the module is the final output of the entire circuit, and synchronously outputs the floating-point data comparison result (maximum value / minimum value) and the corresponding complete original index.

[0028] In summary, the fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip of this invention, with each module working collaboratively, has the following overall workflow: S1. When external floating-point data is input to the circuit, it first enters the special value processing module, where a dedicated conversion circuit completes the hardware processing and conversion of special values ​​such as NaN and Inf to obtain directly comparable floating-point data. S2. The floating-point data after special value processing is input to the non-power-2 adaptation module. If the data is not a power of 2, the module will configure the useless input terminal as -inf / +inf to adapt it to power-2 data; if the data is a power of 2, it will directly enter the subsequent module. S3. The adapted power-of-2 floating-point data is input to the tree-structured comparison module, where it is compared in parallel at each level by a multi-level comparator using a binary search approach. Each level of the comparator module... The control signal outputs the comparison result value of this stage and synchronously bypasses and outputs a 1-bit initial index; S4. The 1-bit index output from each level of the tree comparison structure module is synchronously input to the index passing and splicing module, and is passed level by level from left to right. Each time it is passed to the next level, 1 bit is added and spliced ​​(lower bit of the current level, higher bit of the next level). Finally, the last level comparator outputs the value corresponding to the comparison result. Complete original index; S5, the pipeline processing module updates the input data every clock cycle according to the hierarchical configuration timing of the tree comparison structure, and synchronously outputs the comparison result value (maximum / minimum value) of the floating-point data and the corresponding complete original index from the final output terminal of the circuit every clock cycle.

[0029] The above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fast comparison and fast indexing circuit for floating-point data in an artificial intelligence chip, characterized in that, include: The comparator module is used to select the maximum or minimum value to output based on the control signal, and to bypass the output of the initial index corresponding to the maximum or minimum value; The special value processing module is used to process and convert input non-numeric NaN and infinite Inf type floating-point data; The tree-structured comparison module, connected to the comparator module and the special value processing module, is used to receive floating-point data processed by special values ​​up to the power of 2, and to achieve parallel comparison through multi-level comparators. The non-power-2 adaptation module is connected to the tree comparison structure module and is used to adapt the input data that is not aligned to the power of 2. The comparator input terminal corresponding to the non-power-2 aligned data is configured to a preset fixed maximum or minimum value without affecting the final comparison result. The index passing and splicing module, connected to the tree comparison structure module, is used to pass and splice the indexes output by each level comparator step by step, and finally output the complete original index corresponding to the comparison result.

2. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The special value processing module uses a dedicated conversion circuit to perform hardware processing and conversion of non-Number NaN and Infinity Inf, without the need for software preprocessing intervention.

3. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The preset fixed value configuration rule for the non-power-2 adaptation module is as follows: When comparing the maximum value, the useless comparator input is configured to negative infinity; when comparing the minimum value, the useless comparator input is configured to positive infinity.

4. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The two input terminals of the comparator module are defined as input a and input b, respectively, where the initial index of input a is 0 and the initial index of input b is 1.

5. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The control signal for the comparator module is: Its control logic is: when When, the comparator module outputs the maximum value; when When the minimum value is reached, the comparator module outputs the minimum value.

6. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The multi-level comparators of the tree comparison structure module are connected in a binary search manner. When the number of input floating-point data is N=2^k, the total number of levels of the tree comparison structure module is k. Furthermore, the tree-structured comparison module supports circuit reuse, grouping a large amount of input data, comparing it at lower levels, and then performing a final comparison on the grouping results.

7. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The index passing and concatenation logic of the index passing and concatenation module is as follows: Using the leftmost comparator in the tree comparison structure as level 1 and the rightmost comparator as level 3, the index value is passed from left to right. The first-level comparator outputs a 1-bit initial index, and the number of bits increases by 1 bit for each level passed down. The final output of the complete original index has a total of 1 bit. Where N is the total number of input floating-point data and N is a power of 2; and when concatenating, the index value of the current level is placed in the low bit and the index value of the next level is placed in the high bit.

8. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The specific splicing process of the index passing and splicing module is as follows: each level comparator splices the index output by this level with the index passed by the next level to form the intermediate index corresponding to this level. After being passed and spliced ​​level by level, the last level comparator of the tree comparison structure module outputs the complete original index.

9. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, The complete original index is a unique identifier for the original sequence number of the input floating-point data, and the number of bits in the complete original index increases with the number of input floating-point data N. The index grows in a regular pattern; the encoding method of the index reduces the number of bits required for signal flipping, thereby reducing circuit power consumption and increasing transmission speed.

10. The fast comparison and fast indexing circuit for floating-point data in the artificial intelligence chip according to claim 1, characterized in that, It also includes a pipeline processing module, which is used to implement periodic updates of input data and output the corresponding comparison results and complete original indexes for each period.

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