Dense algorithm execution method and device, electronic equipment, storage medium and vehicle

Abstract

This disclosure relates to a method, apparatus, electronic device, storage medium, and vehicle for executing intensive algorithms. In response to a lookup operation on a target data table in an intensive algorithm to be executed, the target lookup table is loaded into on-chip static random access memory (SRAM) via direct memory access. The number of loop unrolling iterations is determined based on the size parameter of the target lookup table. For at least one query value to be searched, an iterative operation is performed based on the number of loop unrolling iterations to obtain the index result corresponding to each of the at least one query value. Compared to existing technologies, this disclosure eliminates the unpredictable latency of off-chip DDR random access by preloading the lookup table into on-chip SRAM. By using a statically determined number of loop unrolling iterations, the runtime dynamic loop is transformed into a fixed number of iterations, eliminating runtime loop control logic and avoiding runtime loop control overhead. This solves the problems of memory bloat and bandwidth waste, and improves execution efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of algorithm processing technology, and in particular to a method, apparatus, electronic device, storage medium and vehicle for intensive algorithm execution. Background Technology

[0002] When executing control-intensive algorithms (such as binary search, piecewise function evaluation, irregular indexing, etc.) on a neural network processing unit in a dataflow architecture, a naive vectorization scheme is usually adopted, that is, all control flow logic is expanded into tensor operations through a broadcast mechanism to eliminate branches and loops.

[0003] However, this approach requires a large number of random memory accesses and conditional selection operations, which will cause a sharp consumption of off-chip main memory bandwidth, turning the computing task from computationally intensive to memory intensive, resulting in memory bloat and bandwidth waste, and severely reducing execution efficiency. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a method, apparatus, electronic device, storage medium, and vehicle for intensive algorithm execution.

[0005] In a first aspect, embodiments of this disclosure provide a method for executing intensive algorithms, the method comprising: In response to a lookup operation on a target data table in a dense algorithm to be executed, the target lookup table is loaded into on-chip static random access memory via direct memory access. The number of loop unrolling times is determined based on the size parameter of the target lookup table in the on-chip static random access memory; For at least one query value to be searched, perform an iterative operation based on the number of loop expansions to obtain the index result corresponding to each of the at least one query value.

[0006] In some embodiments, the step of performing an iterative operation based on the number of loop unrolls to obtain the index result corresponding to each of the at least one query value includes: For each query value, in each iteration, the intermediate index of the current iteration is calculated based on the current left boundary index and right boundary index of each query value; Read the intermediate value corresponding to the intermediate index from the on-chip static random access memory; The intermediate value is compared with each query value in a vectorized manner to generate a Boolean mask vector; Based on the Boolean mask vector, the left and right boundary indices of each query value are simultaneously updated using the target selection instruction; After the iteration is complete, the index result corresponding to each query value is output according to the updated left boundary index or right boundary index.

[0007] In some embodiments, updating the left boundary index and the right boundary index simultaneously according to the Boolean mask vector via a target selection instruction includes: Using the target selection instruction, for positions in the Boolean mask vector that are true, the left boundary index is updated to the middle index plus one, while the right boundary index remains unchanged; Using the target selection instruction, for positions in the Boolean mask vector that are false, the left boundary index remains unchanged, and the right boundary index is updated to the middle index.

[0008] In some embodiments, calculating the intermediate index of the current iteration based on the current left and right boundary indices of each query value includes: Add the left boundary index to the right boundary index to obtain the summation result; The summation result is shifted right by one bit to obtain the intermediate index of the current iteration.

[0009] In some embodiments, reading the intermediate value corresponding to the intermediate index from the on-chip static random access memory includes: Through vector aggregation operations, the intermediate values ​​corresponding to the intermediate indices of each query value are read in parallel from the non-contiguous addresses of the on-chip static random access memory.

[0010] In some embodiments, before performing the iteration operation based on the number of loop unrolls, the method further includes: Initialize the left and right boundary indices; Specifically, the left boundary index is initialized as the starting index of the target lookup table, and the right boundary index is initialized as the ending index of the target lookup table.

[0011] In some embodiments, after obtaining the index result corresponding to each of the at least one query value, the method further includes: Post-processing operations are performed based on the index results to obtain the query results corresponding to each query value. The post-processing operations include retrieving two adjacent values ​​from the target lookup table based on the index results and performing linear interpolation, coordinate mapping, or numerical transformation.

[0012] In some embodiments, loading the target lookup table into on-chip static random access memory via direct memory access includes: If the size parameter of the target lookup table is less than or equal to the capacity threshold of the on-chip static random access memory, the target lookup table is loaded into the on-chip static random access memory via direct memory access.

[0013] In some embodiments, loading the target lookup table into on-chip static random access memory via direct memory access includes: If the size parameter of the target lookup table is greater than the capacity threshold of the on-chip static random access memory, the target lookup table is divided into multiple blocks based on the capacity threshold. Each block is loaded sequentially into the on-chip static random access memory via direct memory access; The step of performing iterative operations based on the number of loop unrolls to obtain the index result corresponding to each of the at least one query value includes: The iterative operation is performed within each block to generate a local index result corresponding to each block; After each block has been iterated, the local index results corresponding to each block are merged to obtain the index result corresponding to each query value.

[0014] Secondly, embodiments of this disclosure provide a high-intensity algorithm execution apparatus, comprising: A loading module is used to load the target lookup table into on-chip static random access memory via direct memory access in response to a lookup operation of the target data table in an intensive algorithm to be executed. The determining module is used to determine the number of loop unrolling times based on the size parameter of the target lookup table in the on-chip static random access memory; The module is used to perform an iterative operation based on the number of loop expansions for at least one query value to be searched, and obtain the index result corresponding to each query value among the at least one query value.

[0015] Thirdly, embodiments of this disclosure provide an electronic device, including: Memory; Processor; and Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in the first aspect.

[0016] Fourthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the method as described in the first aspect.

[0017] Fifthly, embodiments of this disclosure also provide a computer program product, which includes a computer program or instructions that, when executed by a processor, implement the intensive algorithm execution method described above.

[0018] The intensive algorithm execution method, apparatus, electronic device, storage medium, and vehicle provided in this disclosure, in response to a lookup operation on a target data table in an intensive algorithm to be executed, load the target lookup table into on-chip static random access memory (SRAM) via direct memory access. Based on the size parameter of the target lookup table in the SRAM, the number of loop unrolling operations is determined. For at least one query value to be searched, an iterative operation is performed based on the number of loop unrolling operations to obtain the index result corresponding to each of the at least one query value. Compared to the prior art, this disclosure eliminates the unpredictable latency of off-chip DDR random access by preloading the lookup table into on-chip SRAM. By using a statically determined number of loop unrolling operations, the runtime dynamic loop is transformed into a fixed number of iterations, eliminating runtime loop control logic and avoiding runtime loop control overhead. This solves the problems of memory bloat and bandwidth waste, and improves execution efficiency. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart of a intensive algorithm execution method provided in this embodiment of the disclosure; Figure 2 A flowchart of a intensive algorithm execution method provided in another embodiment of this disclosure; Figure 3 A flowchart of a intensive algorithm execution method provided in another embodiment of this disclosure; Figure 4 This is a schematic diagram of the overall process of the intensive algorithm execution method provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the structure of the intensive algorithm execution device provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0022] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0023] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0024] This disclosure provides a method for intensive algorithm execution, which will be described below with reference to specific embodiments.

[0025] Figure 1 This is a flowchart illustrating a method for executing intensive algorithms according to an embodiment of this disclosure. This method can be applied to electronic devices, specifically portable mobile devices such as tablets, laptops, in-vehicle navigation devices, and smart sports equipment; it can also be fixed devices such as personal computers, smart home appliances, and servers. The server can be a single server, a server cluster, or a distributed or centralized cluster. This method can be applied to scenarios involving the execution of intensive algorithms. It is understood that the intensive algorithm execution method provided in this disclosure can also be applied to other scenarios.

[0026] This embodiment uses search-sorted array as an example to describe the basic implementation of the present invention in detail. Assume the target search table has a size parameter M=241, containing 241 monotonically increasing floating-point numbers; the number of query values ​​to be queried is N=60, containing 60 values ​​whose insertion positions need to be determined. It runs on a dataflow architecture neural network processing unit.

[0027] The following is about Figure 1 The intensive algorithm execution method shown is introduced below, and the specific steps of the method are as follows: S101. In response to the lookup operation of the target data table in the intensive algorithm to be executed, the target lookup table is loaded into the on-chip static random access memory via direct memory access.

[0028] The target data table LUT can be an ordered array. In this step, before the algorithm executes, it is identified that the current task is an ordered array search, which requires frequent random index accesses on a fixed target data table. For example... Figure 4As shown, the target data table is moved entirely from off-chip main memory (DDR) to the unified buffer area of ​​on-chip static random access memory (SRAM) using a direct memory access (DMA) engine and resides there. This movement process can overlap with the final computation of the previous operator, hiding the overhead of direct memory access. After the movement is complete, all subsequent aggregation operations read data from the on-chip SRAM, completely bypassing the random access path of off-chip main memory and improving access efficiency.

[0029] S102. Determine the number of loop unrolling steps based on the size parameter of the target lookup table in the on-chip static random access memory.

[0030] The number of iterations is a value obtained by rounding up the logarithm of the scale parameter to base 2.

[0031] In this step, the size parameter M=241 of the target lookup table is obtained, and the base-2 logarithm is calculated and rounded up: .like Figure 4 As shown, the value K, representing the loop unrolling count, is determined as a constant at compile time. This means that subsequent iterations will be statically unrolled into an instruction sequence repeated 8 times, eliminating the need for runtime loop control. By determining the loop unrolling count, runtime loop control logic is eliminated, ensuring that the entire computation graph no longer contains any loop nodes. This avoids runtime loop control overhead and fully adapts to the static scheduling constraints of the Neural Processing Unit (NPU).

[0032] S103. For at least one query value to be searched, perform an iterative operation based on the number of loop expansions to obtain the index result corresponding to each query value among the at least one query value.

[0033] In this step, N=60 query values ​​are processed in parallel, performing a fixed number of K=8 iterations. In each iteration, each query value independently maintains its own left and right boundaries (initial left boundary = 0, right boundary = 240). After 8 iterations, the left and right boundaries of each query value converge to the adjacent index (right boundary = left boundary + 1), and the left or right boundary is output as the insertion position index of the query value in the candidate array.

[0034] In some embodiments, before performing the iteration operation based on the number of loop unrolls, the method further includes: initializing a left boundary index and a right boundary index; wherein, the initialized left boundary index is the starting index of the target lookup table, and the initialized right boundary index is the ending index of the target lookup table. This can be referred to as Embodiment 1.

[0035] For example, when M=241, before entering the iteration loop, L=0 and R=M-1 (i.e., 241-1=240) are set for each query value. This is the standard initial condition for binary search. The left boundary index is initialized to the starting index 0 of the target search table, and the right boundary index is initialized to the ending index 240 of the target search table. Correct initialization ensures that the search interval covers the entire candidate array, guaranteeing the correctness of the search results.

[0036] This embodiment of the disclosure, in response to a lookup operation on a target data table in a dense algorithm to be executed, loads the target lookup table into on-chip static random access memory (SRAM) via direct memory access. Based on the size parameter of the target lookup table in the SRAM, the number of loop unrolling iterations is determined. For at least one query value to be searched, an iterative operation is performed based on the number of loop unrolling iterations to obtain the index result corresponding to each of the at least one query value. Compared to the prior art, this embodiment of the disclosure eliminates the unpredictable latency of off-chip DDR random access by preloading the lookup table into on-chip SRAM. By using a statically determined number of loop unrolling iterations, the runtime dynamic loop is transformed into a fixed number of iterations, eliminating runtime loop control logic and avoiding runtime loop control overhead. This solves the problems of memory bloat and bandwidth waste, improving execution efficiency. This can be referred to as Embodiment 2.

[0037] Figure 2 A flowchart of a intensive algorithm execution method provided in another embodiment of this disclosure is shown below. Figure 2 As shown, the method includes the following steps: S201. In response to a lookup operation on a target data table in a dense algorithm to be executed, the target lookup table is loaded into an on-chip static random access memory via direct memory access.

[0038] Specifically, the implementation process and principle of S201 and S101 are the same, and will not be repeated here.

[0039] S202. Determine the number of loop unrolling steps based on the size parameter of the target lookup table in the on-chip static random access memory.

[0040] Specifically, the implementation process and principle of S202 and S102 are the same, and will not be repeated here.

[0041] S203. For each query value, in each iteration, calculate the intermediate index of the current iteration based on the current left boundary index and right boundary index of each query value.

[0042] In this step, let the left boundary of the current query value be L, the right boundary be R, and the middle index mid = (L + R)>>1, which means shifting the integer one bit to the right, which is equivalent to the average value of rounding down.

[0043] In some embodiments, calculating the intermediate index of the current iteration based on the current left boundary index and right boundary index of each query value includes: adding the left boundary index and the right boundary index to obtain a summation result; and performing an integer right shift operation on the summation result by one bit to obtain the intermediate index of the current iteration.

[0044] Specifically, add L and R, then right-shift the sum by one bit: mid = (L + R) >> 1. Right-shifting by one bit is equivalent to dividing by 2 and rounding down, avoiding the overhead of division instructions and resulting in high computational efficiency. For example, if the current L=0 and R=240 for the i-th query, then mid=(0+240) >> 1 = 120.

[0045] S204. Read the intermediate value corresponding to the intermediate index from the on-chip static random access memory.

[0046] In this step, using mid as the address, the intermediate value mid_val corresponding to each of the N query values ​​is read concurrently from the on-chip static random access memory.

[0047] In some embodiments, reading the intermediate value corresponding to the intermediate index from the on-chip static random access memory includes: reading the intermediate value corresponding to the intermediate index of each query value in parallel from non-contiguous addresses of the on-chip static random access memory through a vector aggregation operation.

[0048] The vector gather operation, using `mid` as the address, concurrently reads the intermediate value `mid_val` corresponding to each of the N lookup values ​​from the on-chip static random access memory (SRAM). Since the lookup table resides on-chip, the read latency is fixed and extremely low. Specifically, the Vector Gather Unit receives a vector `mid[0..N-1]` containing N indices, reads data from N different addresses in the on-chip SRAM within a single instruction cycle, and returns a vector composed of N intermediate values. This operation compresses what would otherwise require N independent memory accesses into a single parallel memory access, which is key to achieving high throughput. Combined with multi-bank interleaving of the on-chip SRAM, memory bank conflicts can be avoided. For example, if `mid = [120, 85, 200, …]`, the gather operation reads N floating-point values ​​from SRAM address offsets of 120, 85, 200, etc., at once to obtain `mid_val`.

[0049] S205. Vectorize the comparison between the intermediate value and each query value to generate a boolean mask vector.

[0050] Further, for each query value, compare mid_val with the query value query to generate a boolean mask mask = (mid_val < query). mask is a boolean vector of length N, where each element corresponds to the comparison result of a query value. For example, in a binary search, determine whether mid_val < query holds. Generate a boolean mask vector mask with the same length as the query vector, and each element is true or false. If the i-th query value is 100 and mid_val = 120, then the comparison result 120 < 100 is false, and mask[i] = false. If the (i + 1)-th query value is 150 and mid_val = 120, then 120 < 150 is true, and mask[i + 1] = true.

[0051] S206. According to the boolean mask vector, simultaneously update the left boundary index and the right boundary index of each query value through a target selection instruction.

[0052] In this step, according to the boolean mask vector, combined with a target selection instruction (such as where or select), simultaneously update the left and right boundaries of all query values.

[0053] In some embodiments, S206 includes S2061 and S2062: S2061. Using the target selection instruction, for the positions in the boolean mask vector that are true, update the left boundary index to the middle index plus one, and keep the right boundary index unchanged; Optionally, it can be implemented through the following algorithm: [[ID=ID=17]] left = where(mask, mid + 1, left); right = where(mask, right, mid).

[0054] For the positions in mask that are true, that is, when mid_val < query (mask = True), it means the target is in the right half region, and the left boundary is updated to mid + 1, while the right boundary remains unchanged.

[0055] S2062. Using the target selection instruction, for the positions in the boolean mask vector that are false, keep the left boundary index unchanged and update the right boundary index to the middle index.

[0056] For the positions in mask that are false, that is, when mid_val ≥ query (mask = False), it means the target is in the left half region or is hit, and the right boundary is updated to mid, while the left boundary remains unchanged.

[0057] For example, if L=0 and R=240, then mid=120. If the mask of the i-th query is false, then L... i R remains unchanged (e.g., still 0). i Update to mid=120; if the j-th query mask is true, then L j Update to mid+1 (e.g., L=0 becomes 121), R j Remain unchanged (still 240).

[0058] The target selection instruction provided in this embodiment is precisely equivalent to the conditional branching logic in a traditional binary search, but it is implemented entirely through a data flow approach. Since all query value updates are completed simultaneously, there is no situation where any channel waits for other channels, eliminating thread divergence. This can be referred to as Embodiment 3.

[0059] S207. After the iteration is completed, output the index result corresponding to each query value according to the updated left boundary index or right boundary index.

[0060] In this step, after 8 iterations, the L and R of each query value satisfy R = L+1, at which point L is the index of the position where the query value should be inserted.

[0061] In this embodiment, the operation sequence is completely fixed in each iteration, with no branch jumps. All single-instruction multiple-data channels execute the same instruction, achieving 100% pipeline utilization. Vectorized comparison and mask selection avoid the overhead of traditional branches, and the mask vector length is only N, resulting in minimal storage overhead. This can be referred to as Embodiment 4.

[0062] S208. Perform post-processing operations based on the index results to obtain the query results corresponding to each query value.

[0063] The post-processing operation includes retrieving two adjacent values ​​from the target lookup table based on the index result and performing linear interpolation, coordinate mapping, or numerical transformation.

[0064] In this step, in practical applications, the index obtained from the lookup is often not the final output. For example, in evaluating piecewise linear functions, after obtaining index i, it is necessary to extract the i-th and (i+1)-th values ​​from the candidate array and perform linear interpolation between the two endpoints based on the query value. Figure 4As shown, since the entire computation graph (lookup phase + post-processing phase) is a well-structured sequence of static operators, the AI ​​compiler can cross the boundary between lookup and post-processing, unifying the operators of both phases into a single kernel for execution. This means that in the complete computation path from input query to final interpolation result, intermediate tensors (index results) can flow directly in registers or on-chip static random access memory buffers without needing to be written to off-chip main memory. Post-processing fusion further reduces off-chip main memory bandwidth consumption and avoids kernel startup overhead. This can be referred to as Example 5.

[0065] This embodiment of the disclosure, in response to a lookup operation on a target data table in a dense algorithm to be executed, loads the target lookup table into on-chip static random access memory (SRAM) via direct memory access. The number of iterations is determined based on the size parameter of the target lookup table in the SRAM. Then, for each query value, in each iteration, an intermediate index for the current iteration is calculated based on the current left and right boundary indices of each query value. The intermediate value corresponding to the intermediate index is read from the SRAM, and the intermediate value is compared with each query value using vectorization to generate a Boolean mask vector. Further, based on the Boolean mask vector, the left and right boundary indices of each query value are simultaneously updated using a target selection instruction. After iteration, the index result corresponding to each query value is output based on the updated left or right boundary index. Post-processing operations are then performed based on the index result to obtain the query result corresponding to each query value. Through this method, this embodiment of the disclosure achieves 100% pipeline utilization by completely fixing the operation sequence in each iteration, without any branch jumps, and ensuring that all single-instruction multiple-data channels execute the same instruction. Using vectorized comparison and mask selection avoids the overhead of traditional branches, and the mask vector length is only N, resulting in minimal storage overhead.

[0066] Figure 3 A flowchart of a intensive algorithm execution method provided in another embodiment of this disclosure is shown below. Figure 3 As shown, the method includes the following steps: S301. If the size parameter of the target lookup table is less than or equal to the capacity threshold of the on-chip static random access memory, the target lookup table is loaded into the on-chip static random access memory via direct memory access.

[0067] Before execution, it is first determined whether the lookup table size is compatible with the on-chip static random access memory (SRAM) capacity. For example, if the on-chip SRAM capacity is 256KB and the target lookup table contains 500 floating-point numbers (approximately 2KB), it is loaded directly. This determination avoids invalid loading attempts and ensures the applicability of the solution. This can be referred to as Example 6.

[0068] S302. Determine the number of loop unrolling steps based on the size parameter of the target lookup table in the on-chip static random access memory.

[0069] Specifically, the implementation process and principle of S302 and S102 are the same, and will not be repeated here.

[0070] S303. For at least one query value to be searched, perform an iterative operation based on the number of loop expansions to obtain the index result corresponding to each query value among the at least one query value.

[0071] Specifically, the implementation process and principle of S303 and S103 are the same, and will not be repeated here.

[0072] S304. If the size parameter of the target lookup table is greater than the capacity threshold of the on-chip static random access memory, the target lookup table is divided into multiple blocks based on the capacity threshold.

[0073] For example, if the size of the target lookup table is M=50000, and the on-chip static random access memory can only hold 5000 elements, then the target lookup table is divided into 10 blocks, each with 5000 elements.

[0074] S305. Load each block sequentially into the on-chip static random access memory via direct memory access, perform the iterative operation within each block, and generate the local index result corresponding to each block.

[0075] In this step, for each block, the following steps are performed sequentially: the block is loaded into the on-chip static random access memory, and an iterative operation is performed within the block (the local index of each query value relative to the block) to obtain whether each query value is hit or the position to be inserted in the block, which is the local index result corresponding to each block.

[0076] S306. After each block has been iterated, the local index results corresponding to each block are merged to obtain the index result corresponding to each query value.

[0077] In this step, after all blocks have been processed, the results of each query value in all blocks are merged to determine the global index, which is the index result corresponding to each query value.

[0078] By decomposing the large lookup table problem into multiple on-chip resident subproblems using a block-based strategy, although the number of block operations increases, random access to off-chip main memory is avoided, and overall performance is still significantly improved. This can be referred to as Example 7.

[0079] In this embodiment, when the size parameter of the target lookup table is less than or equal to the capacity threshold of the on-chip static random access memory (SRAM), the target lookup table is loaded into the SRAM via direct memory access (DMA). The number of iterations is determined based on the size parameter of the target lookup table in the SRAM. Further, for at least one query value to be searched, an iterative operation is performed based on the number of iterations to obtain an index result corresponding to each of the at least one query value. Alternatively, when the size parameter of the target lookup table is greater than the capacity threshold of the SRAM, the target lookup table is divided into multiple blocks based on the capacity threshold. Each block is sequentially loaded into the SRAM via DMA. The iterative operation is performed within each block to generate a local index result corresponding to each block. After all iterations for each block are completed, the local index results corresponding to each block are merged to obtain the index result corresponding to each query value. By means of this method, the present invention can still run effectively when the lookup table exceeds the SRAM capacity by using a strategy of block loading, block-by-block lookup, and result merging. It exchanges a small amount of block switching overhead for support for large-capacity lookup tables, which has a significant advantage over traditional solutions that cannot run at all due to memory explosion.

[0080] It should be noted that the vehicle control method involved in the above embodiments may include at least one of Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, Embodiment 5, Embodiment 6, and Embodiment 7. For example, Embodiment 1 can be implemented as an independent embodiment, Embodiment 1+2 can be implemented as an independent embodiment, Embodiment 1+2+3 can be implemented as an independent embodiment, Embodiment 1+2+3+4 can be implemented as an independent embodiment, Embodiment 1+2+3+4+5 can be implemented as an independent embodiment, Embodiment 1+2+3+4+5+6 can be implemented as an independent embodiment, Embodiment 1+2+3+4+5+6+7 can be implemented as an independent embodiment, Embodiment 1+4 can be implemented as an independent embodiment, Embodiment 1+2+4 can be implemented as an independent embodiment, Embodiment 1+5 can be implemented as an independent embodiment, Embodiment 1+2+5 can be implemented as an independent embodiment, Embodiment 1+4+5 can be implemented as an independent embodiment, and Embodiment 1+2+3+5 can be implemented as an independent embodiment. Examples 1, 5, and 6 can be implemented as independent embodiments, as can examples 1, 2, 5, and 6, as well as examples 1, 4, 5, and 6, and examples 1, 2, 3, 5, and 6, and examples 1, 5, and 7 can be implemented as independent embodiments. These examples are merely illustrative and not exhaustive; further examples will not be provided here.

[0081] Figure 5 This is a schematic diagram of the structure of a dense algorithm execution device provided in an embodiment of this disclosure. The dense algorithm execution device can be an electronic device as described in the above embodiment, or it can be a component or assembly within that electronic device. The dense algorithm execution device provided in this disclosure can execute the processing flow provided in the embodiments of the dense algorithm execution method, such as... Figure 5As shown, the intensive algorithm execution device 40 includes: a loading module 41, a determining module 42, and a obtaining module 43; wherein, the loading module 41 is used to load the target lookup table into the on-chip static random access memory via direct memory access in response to a lookup operation of the target data table in the intensive algorithm to be executed; the determining module 42 is used to determine the number of loop unrolling operations based on the size parameter of the target lookup table in the on-chip static random access memory; the obtaining module 43 is used to perform an iterative operation based on the number of loop unrolling operations for at least one query value to be searched, and obtain the index result corresponding to each query value among the at least one query value.

[0082] Optionally, when the obtaining module 43 performs an iterative operation based on the number of loop unrolls to obtain the index result corresponding to each of the at least one query value, it is specifically used to: for each query value, in each iteration, calculate the intermediate index of the current iteration based on the current left boundary index and right boundary index of each query value; read the intermediate value corresponding to the intermediate index from the on-chip static random access memory; perform a vectorized comparison between the intermediate value and each query value to generate a Boolean mask vector; update the left boundary index and right boundary index of each query value simultaneously through a target selection instruction based on the Boolean mask vector; after the iteration is completed, output the index result corresponding to each query value based on the updated left boundary index or right boundary index.

[0083] Optionally, when the obtaining module 43 updates the left boundary index and the right boundary index simultaneously according to the Boolean mask vector through the target selection instruction, it is specifically used to: using the target selection instruction, for positions in the Boolean mask vector that are true, update the left boundary index to the middle index plus one, and keep the right boundary index unchanged; using the target selection instruction, for positions in the Boolean mask vector that are false, keep the left boundary index unchanged, and update the right boundary index to the middle index.

[0084] Optionally, when the obtaining module 43 calculates the intermediate index of the current iteration based on the current left boundary index and right boundary index of each query value, it is specifically used to: add the left boundary index and the right boundary index to obtain a summation result; and perform an integer right shift operation on the summation result to obtain the intermediate index of the current iteration.

[0085] Optionally, when the obtaining module 43 reads the intermediate value corresponding to the intermediate index from the on-chip static random access memory, it is specifically used to: read the intermediate value corresponding to the intermediate index of each query value in parallel from the non-contiguous addresses of the on-chip static random access memory through vector aggregation operation.

[0086] Optionally, before performing the iteration operation based on the number of loop unrolls, the obtaining module 43 is further configured to: initialize the left boundary index and the right boundary index; wherein, the initialization of the left boundary index is the starting index of the target lookup table, and the initialization of the right boundary index is the ending index of the target lookup table.

[0087] Optionally, after obtaining the index result corresponding to each of the at least one query value, the device 40 further includes: a processing module 44, configured to perform post-processing operations based on the index result to obtain the query result corresponding to each query value, wherein the post-processing operations include retrieving two adjacent values ​​from the target lookup table according to the index result and performing linear interpolation, coordinate mapping, or numerical transformation.

[0088] Optionally, when the loading module 41 loads the target lookup table into the on-chip static random access memory via direct memory access, it is specifically used to: load the target lookup table into the on-chip static random access memory via direct memory access when the size parameter of the target lookup table is less than or equal to the capacity threshold of the on-chip static random access memory.

[0089] Optionally, the loading module 41 is further configured to, when the size parameter of the target lookup table is greater than the capacity threshold of the on-chip static random access memory, divide the target lookup table into multiple blocks based on the capacity threshold; and load each block into the on-chip static random access memory in sequence via direct memory access. The obtaining module 43 is further configured to perform the iteration operation within each block to generate a local index result corresponding to each block; after each block has been iterated, the local index results corresponding to each block are merged to obtain the index result corresponding to each query value.

[0090] Figure 5 The intensive algorithm execution device shown in the embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.

[0091] Figure 6 This is a schematic diagram of the structure of an electronic device according to an embodiment of this disclosure. See below for details. Figure 6 It shows a schematic diagram of a structure suitable for implementing the electronic device 600 in the embodiments of this disclosure. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0092] like Figure 6As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 608 into random access memory (RAM) 603 to implement the intensive algorithm execution method as described in the embodiments of this disclosure. Various programs and data required for the operation of electronic device 600 are also stored in RAM 603. Processing device 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0093] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0094] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts, thereby implementing the intensive algorithm execution method as described above. In such embodiments, the computer program can be downloaded and installed from a network via communication device 609, or installed from storage device 608, or installed from ROM 602. When the computer program is executed by processing device 601, it performs the functions defined in the methods of embodiments of this disclosure.

[0095] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0096] Additionally, this disclosure also provides a vehicle, including: a memory; a processor; and a computer program; wherein the computer program is stored in the memory and configured to be executed by the processor to implement the intensive algorithm execution method described above.

[0097] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0098] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0099] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to: In response to a lookup operation on a target data table in a dense algorithm to be executed, the target lookup table is loaded into on-chip static random access memory via direct memory access. The number of loop unrolling times is determined based on the size parameter of the target lookup table in the on-chip static random access memory; For at least one query value to be searched, perform an iterative operation based on the number of loop expansions to obtain the index result corresponding to each of the at least one query value.

[0100] Optionally, when one or more of the above-described procedures are executed by the electronic device, the electronic device may also execute other steps described in the above embodiments.

[0101] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0103] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0104] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0105] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0106] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0107] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0108] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method of performing a dense algorithm, the method comprising: The method includes: In response to a lookup operation on a target data table in a dense algorithm to be executed, the target lookup table is loaded into on-chip static random access memory via direct memory access. The number of loop unrolling times is determined based on the size parameter of the target lookup table in the on-chip static random access memory; For at least one query value to be searched, perform an iterative operation based on the number of loop expansions to obtain the index result corresponding to each of the at least one query value.

2. The method according to claim 1, characterized in that, The step of performing iterative operations based on the number of loop unrolls to obtain the index result corresponding to each of the at least one query value includes: For each query value, in each iteration, the intermediate index of the current iteration is calculated based on the current left boundary index and right boundary index of each query value; Read the intermediate value corresponding to the intermediate index from the on-chip static random access memory; The intermediate value is compared with each query value in a vectorized manner to generate a Boolean mask vector; Based on the Boolean mask vector, the left and right boundary indices of each query value are simultaneously updated using the target selection instruction; After the iteration is complete, the index result corresponding to each query value is output according to the updated left boundary index or right boundary index.

3. The method according to claim 2, characterized in that, The step of simultaneously updating the left and right boundary indices based on the Boolean mask vector and the target selection instruction includes: Using the target selection instruction, for positions in the Boolean mask vector that are true, the left boundary index is updated to the middle index plus one, while the right boundary index remains unchanged; Using the target selection instruction, for positions in the Boolean mask vector that are false, the left boundary index remains unchanged, and the right boundary index is updated to the middle index.

4. The method according to any one of claims 2 or 3, characterized in that, The step of calculating the intermediate index for the current iteration based on the current left and right boundary indices of each query value includes: Add the left boundary index to the right boundary index to obtain the summation result; The summation result is shifted right by one bit to obtain the intermediate index of the current iteration.

5. The method according to any one of claims 2-4, characterized in that, The step of reading the intermediate value corresponding to the intermediate index from the on-chip static random access memory includes: Through vector aggregation operations, the intermediate values ​​corresponding to the intermediate indices of each query value are read in parallel from the non-contiguous addresses of the on-chip static random access memory.

6. The method according to any one of claims 1-5, characterized in that, Before performing the iteration operation based on the number of loop unrolls, the method further includes: Initialize the left and right boundary indices; Specifically, the left boundary index is initialized as the starting index of the target lookup table, and the right boundary index is initialized as the ending index of the target lookup table.

7. The method according to any one of claims 1-6, characterized in that, After obtaining the index result corresponding to each of the at least one query value, the method further includes: Post-processing operations are performed based on the index results to obtain the query results corresponding to each query value. The post-processing operations include retrieving two adjacent values ​​from the target lookup table based on the index results and performing linear interpolation, coordinate mapping, or numerical transformation.

8. The method according to any one of claims 1-7, characterized in that, The step of loading the target lookup table into the on-chip static random access memory via direct memory access includes: If the size parameter of the target lookup table is less than or equal to the capacity threshold of the on-chip static random access memory, the target lookup table is loaded into the on-chip static random access memory via direct memory access.

9. The method according to any one of claims 1-8, characterized in that, The step of loading the target lookup table into the on-chip static random access memory via direct memory access includes: If the size parameter of the target lookup table is greater than the capacity threshold of the on-chip static random access memory, the target lookup table is divided into multiple blocks based on the capacity threshold. Each block is loaded sequentially into the on-chip static random access memory via direct memory access; The step of performing iterative operations based on the number of loop unrolls to obtain the index result corresponding to each of the at least one query value includes: The iterative operation is performed within each block to generate a local index result corresponding to each block; After each block has been iterated, the local index results corresponding to each block are merged to obtain the index result corresponding to each query value.

10. A high-intensity algorithm execution device, characterized in that, The device includes: A loading module is used to load the target lookup table into on-chip static random access memory via direct memory access in response to a lookup operation of the target data table in an intensive algorithm to be executed. The determining module is used to determine the number of loop unrolling times based on the size parameter of the target lookup table in the on-chip static random access memory; The module is used to perform an iterative operation based on the number of loop expansions for at least one query value to be searched, and obtain the index result corresponding to each query value among the at least one query value.

11. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in any one of claims 1-9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-9.

13. A vehicle, characterized in that, Includes the intensive algorithm execution device as described in claim 10.

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