Vector data rearrangement execution method based on load storage lane multiplexing and processor

Abstract

The application discloses a vector data rearrangement execution method based on load storage channel multiplexing and a processor, and relates to the technical field of computers. The method comprises the following steps: analyzing a vector data rearrangement instruction and generating a control signal; switching an input end of a load storage channel from a memory interface to an output port of a source vector register according to the control signal, so that register data enters the load storage channel; switching an address generation unit to an index generation mode to generate a data flow index sequence; completing vector data rearrangement according to the data flow index sequence by using a data distribution path and a multi-stage data selection node in the load storage channel; and writing back data after rearrangement to a target vector register. According to the application, register-level vector data rearrangement is realized without adding a special permutation network, so that the hardware complexity is reduced and the hardware resource utilization is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a vector data rearrangement execution method and processor based on load storage path multiplexing. Background Technology

[0002] In processor architectures based on the vector extension of the fifth-generation Reduced Instruction Set Computer (RISC-V), vector data rearrangement is one of the fundamental operations supporting multimedia processing, signal processing, and artificial intelligence computing. Vector interleaving / deinterleaving operations are used to interleave and deinterleave multiple data streams, and have wide applications in data layout transformation, single-instruction multiple-data-stream parallel computing, and memory access alignment optimization. With the development of RISC-V vector extensions, the frequency of use of vector interleaving / deinterleaving data rearrangement operations in vectorized computing is gradually increasing.

[0003] In related technologies, vector interleaving / deinterleaving operations mainly rely on general permutation networks, vector permutation instruction combinations, or dedicated data rearrangement units. Using general permutation networks for vector interleaving / deinterleaving typically requires complex data exchange structures, leading to high hardware complexity and significant hardware resource overhead. While implementations based on vector permutation instruction combinations offer the advantage of reusing existing instruction units, they suffer from high execution latency due to the need to execute multiple instructions and place high demands on instruction scheduling and register bandwidth. Implementations based on dedicated data rearrangement units usually require the introduction of additional dedicated hardware modules, further increasing design complexity and hardware overhead. Furthermore, existing solutions typically implement vector data rearrangement functionality independently from the load storage path, failing to fully utilize the existing data organization capabilities within the data distribution path.

[0004] Therefore, how to improve the execution efficiency of vector data rearrangement while reducing hardware complexity has become a problem that needs to be solved in related technologies. Summary of the Invention

[0005] This application provides a vector data rearrangement execution method and processor based on load storage path multiplexing to solve the problems of high hardware complexity, large resource overhead and insufficient execution efficiency in vector data rearrangement operations in related technologies.

[0006] In a first aspect, embodiments of this application provide a vector data rearrangement execution method based on load storage path multiplexing. The method includes: acquiring a vector data rearrangement instruction, parsing the vector data rearrangement instruction, generating a control signal corresponding to the vector data rearrangement instruction, wherein the vector data rearrangement instruction is used to rearrange vector data in a source vector register; according to the control signal, switching the input end of the load storage path from a memory interface to the output port of the source vector register, so that the vector data to be processed enters the load storage path without initiating an external storage system access request; and according to the control signal, moving the address generation unit from the memory access location... The address generation mode is switched to the index generation mode. In the index generation mode, physical address generation is disabled, and a data flow index sequence for controlling the data distribution path is generated. The data flow index sequence is used to describe the target position mapping relationship of each vector data in the multi-level data selection network in the load storage path. Using the multi-level data selection network in the load storage path, according to the data flow index sequence, the vector data in the source vector register is selected and distributed at the lane level to complete the rearrangement operation. The rearranged vector data is written to the target vector register through the write-back path of the load storage path.

[0007] This application provides a vector data rearrangement execution scheme. By reusing the multi-level data selection network in the load storage path, the vector data rearrangement operation can be realized without adding a dedicated cross switch network, permutation network or data exchange network, thereby reducing hardware complexity and improving hardware resource utilization.

[0008] One possible implementation is that generating the data flow direction index sequence for controlling the data distribution path includes: generating the data flow direction index sequence according to vector configuration parameters, wherein each index value in the data flow direction index sequence corresponds to a target data channel (lane) or path selection relationship, so as to drive the multi-level data selection network to adjust the data flow direction.

[0009] One possible implementation of the above-mentioned vector data rearrangement execution method based on load storage path multiplexing further includes: when the vector data rearrangement instruction involves multiple source vector registers, decomposing the vector data rearrangement instruction into multiple micro-operations, wherein the multiple micro-operations time-division multiplex the load storage path, and each micro-operation processes a portion of the vector data in the source vector registers; the step of performing data channel-level path selection and distribution on the vector data in the source vector registers according to the data flow direction index sequence to complete the rearrangement operation includes: according to the data flow direction index sequence, sequentially performing path selection and distribution on the vector data in the source vector registers in the load storage path through multiple execution cycles to complete the rearrangement operation. By decomposing the vector data rearrangement instruction into multiple micro-operations, a smaller-scale multi-level data selection network in the load storage path can be reused. This means that there is no need to introduce a dedicated, large, fully interconnected data exchange unit to support complex wide vector rearrangements, which helps to reduce hardware overhead and design complexity.

[0010] In one possible implementation, the load storage path is further configured to receive segment load data from the memory interface and distribute the segment load data through the multi-level data selection network.

[0011] One possible implementation further includes: during the execution of the vector data rearrangement instruction using the load storage path, clock-gated logic circuits in the load storage path related to external bus protocol control, cache tag comparison, and virtual-to-physical address translation are disabled, leaving only the multi-level data selection network and the write-back path active. By disabling some control logic related to memory access, dynamic power consumption during vector data rearrangement execution can be reduced.

[0012] One possible implementation is that the rearrangement operation includes an interleaving operation; the step of selecting and distributing the vector data in the source vector register according to the data flow direction index sequence includes: when the rearrangement operation is an interleaving operation, according to the data flow direction index sequence, interleaving the vector data from different source vector registers according to a preset data channel (lane) mapping relationship and outputting them to the corresponding target position.

[0013] One possible implementation is that the rearrangement operation includes a deinterleaving operation; the step of selecting and distributing the vector data in the source vector register according to the data flow direction index sequence includes: when the rearrangement operation is a deinterleaving operation, distributing and outputting the vector data from the source vector register according to the preset data channel (lane) mapping relationship according to the data flow direction index sequence, and outputting it to the corresponding position.

[0014] Secondly, embodiments of this application provide a vector data rearrangement processor, the processor comprising: an instruction decoding unit, a load storage unit, an address generation unit, a data distribution unit, and a write-back unit.

[0015] The instruction decoding unit is used to acquire vector data rearrangement instructions, parse the vector data rearrangement instructions, and generate corresponding control signals.

[0016] The load storage unit is used to switch the input terminal of the load storage path from the memory interface to the output port of the source vector register according to the control signal, so that the vector data to be processed enters the load storage path.

[0017] The address generation unit is used to switch from memory access address generation mode to index generation mode according to the control signal. In the index generation mode, physical address generation is disabled, and a data flow index sequence for controlling the data distribution path is generated.

[0018] The data distribution unit is used to utilize the multi-level data selection network in the load storage path to perform data channel-level path selection and distribution on the vector data in the source vector register according to the data flow direction index sequence, and complete the rearrangement operation.

[0019] The write-back unit is used to write the rearranged vector data into the target vector register through the write-back path of the load storage path.

[0020] Thirdly, embodiments of this application provide a chip including the vector data rearrangement processor described in the second aspect above, wherein the chip implements the method described in any possible implementation of the first aspect through the vector data rearrangement processor.

[0021] It should be noted that any of the possible implementation methods in the above aspects can be combined with each other as long as the solutions do not conflict. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the architecture of a computing system provided in an exemplary embodiment of this application; Figure 2 This is a flowchart of a vector data rearrangement execution method based on load storage path multiplexing provided in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of a vector data rearrangement execution system architecture provided in an exemplary embodiment of this application; Figure 4 This is a schematic diagram illustrating the execution logic of each component in a data rearrangement execution system architecture provided in an exemplary embodiment of this application; Figure 5 This is a flowchart of a data rearrangement execution method based on load storage path multiplexing provided in an exemplary embodiment of this application; Figure 6 This is a schematic diagram of a data rearrangement mechanism provided in an exemplary embodiment of this application; Figure 7 This is a schematic diagram of the structure of a vector data rearrangement processor provided in an exemplary embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application; Figure 9 This is a schematic diagram of the structure of a chip system provided in an exemplary embodiment of this application. Detailed Implementation

[0024] In the embodiments of this application, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different. The technical features described by "first" and "second" have no sequential or size order.

[0025] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0026] In the embodiments of this application, at least one can also be described as one or more, and multiple can be two, three, four or more, and this application does not impose any restrictions.

[0027] Furthermore, the network architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0028] It should be noted that the information (including but not limited to device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the subject or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0029] In the RISC-V vector extension processor architecture, vector data rearrangement is one of the fundamental operations supporting multimedia processing, signal processing, and artificial intelligence computing. Vector interleaving / deinterleaving operations are used to interleave and deinterleave multiple data streams, and have wide applications in data layout transformation, single-instruction multiple-data-stream parallel computing, and memory access alignment optimization. For example, in an audio clip, the audio data is typically stored interleaved between the left and right channels. However, during computation, it may be necessary to process the right channel data separately. This requires deinterleaving to separate the left and right channel data, and then recombining the left and right channel data through interleaving after processing the right channel data.

[0030] With the development of RISC-V vector extensions, the frequency of use of vector interleaving / deinterleaving data rearrangement operations in vectorized computing has gradually increased. For vector interleaving / deinterleaving operations, existing technologies mainly employ general permutation networks, combinations of vector permutation instructions, or dedicated data rearrangement units. The implementation methods described below are explained in detail.

[0031] Method 1: Implementation scheme based on general vector permutation unit.

[0032] This scheme supports arbitrary rearrangement of data elements in the vector register across different data lanes by setting up a general permutation network (such as a crossbar network or a shuffle network) within the vector execution unit. Specifically, each lane corresponds to an input / output port, and arbitrary element position mapping is achieved through a fully or partially interconnected switching network. The control unit generates corresponding permutation control signals according to the instruction semantics to drive the rearrangement of vector data across lanes. Interleaving / deinterleaving operations are achieved by configuring specific permutation modes to interleave / deinterleave vector data.

[0033] This scheme utilizes fully or partially interconnected networks to construct highly flexible data pathways. Each data channel acts as an independent port, and the network topology is configured via control signals to achieve arbitrary data location mapping.

[0034] However, such solutions typically require the construction of large-scale data exchange networks. As the vector width or the number of data channels increases, the number of interconnects and the complexity of control logic in the exchange network will increase significantly, leading to increased chip area and power consumption. Furthermore, such solutions usually require the independent construction of a dedicated data rearrangement network, independent of the existing data distribution paths in the load storage unit, resulting in low hardware resource reuse.

[0035] Method 2: Implementation scheme based on vector permutation instruction combination.

[0036] This scheme replaces the dedicated hardware rearrangement structure with a software-level instruction sequence, achieving interleaving or deinterleaving functions through the combination of multiple basic vector instructions. Specifically, basic instructions such as vector gathering, vector sliding, and vector compression can be used to gradually adjust the data positions according to a pre-constructed index vector to achieve the target data arrangement relationship. For example, in implementing interleaving operations, the target data can first be extracted using the gathering instruction, then the element positions can be adjusted using the sliding instruction, and finally the interleaving result can be formed by multiple register write-backs. In implementing deinterleaving operations, the index vector can be used to extract and reorganize data elements at different positions.

[0037] This approach can reuse existing vector execution units and instruction architectures without requiring additional dedicated rearrangement hardware, thus resulting in lower implementation costs.

[0038] However, since interleaving or deinterleaving operations typically require multiple vector instructions to work together, they introduce additional instruction execution overhead and pipeline scheduling overhead. Furthermore, multiple write-backs and re-reads of intermediate results increase the number of accesses to the vector register file, exacerbating resource pressure on register read / write ports and placing higher demands on the processor's register bandwidth and instruction scheduling capabilities, resulting in lower overall execution efficiency.

[0039] Method 3: Implementation scheme based on dedicated data rearrangement unit.

[0040] This solution introduces a dedicated data rearrangement unit to accelerate data arrangement operations in specific patterns. For interleaving / deinterleaving operations, this type of solution may adopt the following approaches: designing a fixed-pattern data interleaving network to achieve interleaved output of data from adjacent lanes; adding dedicated data buffers and rearrangement logic to the execution unit to support the merging and splitting of multiple input data; and improving data rearrangement throughput through pipelined design.

[0041] Because the hardware architecture is optimized for specific rearrangement patterns, this approach typically achieves high execution efficiency.

[0042] However, such solutions typically require additional dedicated data exchange logic, control logic, and buffer structures, resulting in additional chip area overhead and design complexity. Furthermore, the dedicated data rearrangement unit is independent of the processor's existing memory access paths and data distribution structures, leading to low hardware resource reuse. When supporting new data rearrangement patterns is needed, it often requires expanding or redesigning the dedicated hardware, resulting in relatively insufficient flexibility.

[0043] In summary, the industry has not yet developed a solution that can effectively balance low hardware overhead and high execution efficiency when performing data rearrangement in vector registers during interleaving / deinterleaving operations.

[0044] Based on this, this application provides a vector data rearrangement execution scheme. It obtains vector data rearrangement instructions, parses these instructions, and generates corresponding control signals. According to the control signals, the input of the load storage path is switched from the memory interface to the output port of the source vector register, allowing the vector data to be processed to enter the load storage path without initiating an external storage system access request. According to the control signals, the address generation unit is switched from memory access address generation mode to index generation mode. In index generation mode, physical address generation is disabled, and a data flow index sequence is generated to control the data distribution path. Utilizing a multi-level data selection network in the load storage path, the vector data in the source vector register is path-selected and distributed according to the data flow index sequence, completing the rearrangement operation. The rearranged vector data is then written to the target vector register through the write-back path of the load storage path. By reusing the multi-level data selection network in the load storage path, the vector data rearrangement operation is achieved without the need for a dedicated crossbar switch network, permutation network, or data exchange network, thereby reducing hardware complexity and improving hardware resource utilization.

[0045] The solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0046] The solution provided in this application can be applied to Figure 1 An illustrated computing system. (e.g.) Figure 1 As shown, the computing system includes: processor 100.

[0047] Alternatively, the processor 100 may be a processor that supports RISC-V vector extensions, such as a central processing unit (CPU), an artificial intelligence processor, a digital signal processor (DSP), or another vector processor.

[0048] Specifically, the processor 100 obtains a vector data rearrangement instruction and rearranges the vector data in the source vector register based on the instruction to obtain the rearranged vector data. The specific implementation can be found in the description of the following embodiments.

[0049] It should be noted that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0050] Figure 2 A flowchart illustrating a vector data rearrangement execution method based on load storage path multiplexing provided in an exemplary embodiment of this application is shown. This embodiment exemplifies the method being executed by a processor. The processor can be... Figure 1 The processor 100 is shown in the diagram.

[0051] like Figure 2 As shown, the vector data rearrangement execution method based on load storage path multiplexing includes the following steps.

[0052] Step 201: Obtain the vector data rearrangement instruction, parse the vector data rearrangement instruction, and generate the corresponding control signal.

[0053] The vector data rearrangement instruction is used to rearrange the vector data in the source vector register.

[0054] Optionally, the vector data rearrangement instruction can be an instruction involving a single source vector register or an instruction involving multiple source vector registers.

[0055] Specifically, the processor acquires a vector data rearrangement instruction. The instruction decoding unit in the processor parses the input vector data rearrangement instruction, and when the instruction is recognized, it generates a corresponding control signal. In some embodiments, the vector data rearrangement instruction can be a Zip instruction or an Unzip instruction from the RISC-V Zvzip extension. For vector data rearrangement instructions involving multiple source vector registers, the instruction decoding unit generates control information for time-multiplexing the load storage path based on the vector register read port constraints to support subsequent staged execution.

[0056] Control signals are used to control the processor to perform vector data rearrangement operations.

[0057] Optionally, the control signals include data source selection signals, operation type identification signals, and data flow direction index-related control information for driving the data distribution path, but are not limited thereto, and the embodiments of this application do not specifically limit them.

[0058] The data source selection signal is used to select the source vector register. The operation type identifier signal is used to distinguish the operation type of the vector data rearrangement instruction.

[0059] Step 202: According to the control signal, switch the input of the load storage path from the memory interface to the output port of the source vector register, so that the vector data to be processed can enter the load storage path without initiating an access request to the external storage system.

[0060] The load storage path, also known as the memory access data path, is the hardware execution path responsible for executing read / load and write / store instructions.

[0061] Before receiving the vector data rearrangement instruction, the load storage path receives segment load data from the memory interface and distributes the segment load data through a multi-level data selection network. After receiving the vector data rearrangement instruction, the load storage path receives data from the source vector register and distributes it through the multi-level data selection network.

[0062] Optionally, during the execution of vector data rearrangement instructions using the load storage path, the logic circuits related to external bus protocol control, cache tag comparison, and virtual-to-physical address translation in the load storage path are shut down by clock gating, keeping only the multi-level data selection network and the write-back path active.

[0063] The source vector register is used to store vector data.

[0064] Specifically, without reordering, the input of the load storage path is connected to the memory interface, and the load storage path is used to read data from memory or write data to memory.

[0065] During a rearrangement operation, the processor switches the input of the load storage path from the memory interface to the output port of the source vector register according to the control signal, so that the vector data in the source vector register can enter the load storage path.

[0066] Step 203: According to the control signal, switch the address generation unit from memory access address generation mode to index generation mode. In index generation mode, physical address generation is disabled, and a data flow index sequence for controlling the data distribution path is generated.

[0067] Among them, the data flow index sequence is used to describe the target location mapping relationship of each vector data in the multi-level data selection network in the load storage path.

[0068] The memory address generation mode is used to generate the address information required to access main memory or cache.

[0069] The index generation mode is used to generate a data flow index sequence that controls data rearrangement. In index generation mode, the output of the Address Generation Unit (AGU) in the processor is no longer used to represent physical addresses, but instead to generate a data flow index sequence that controls the multi-level data selection network. These indices describe the target location mapping relationship of each vector data in the multi-level data selection network within the load storage path.

[0070] The data distribution path is the data transmission path in the load storage path used to organize segmented loading data, including multi-level data selection nodes and their connection relationships.

[0071] In some embodiments, when generating a data flow direction index sequence for controlling data distribution paths, the processor generates the data flow direction index sequence according to vector configuration parameters. Each index value in the data flow direction index sequence corresponds to a target data channel or path selection relationship to drive a multi-level data selection network to adjust the data flow direction.

[0072] Optionally, the vector configuration parameters include at least one of the following: the width of the vector element (EffectiveElement Width, EEW), the vector length (Vector Length, VL), or the rearrangement operation type.

[0073] For example, in index generation mode, a data flow to index sequence is generated based on EEW, VL, and rearrangement operation type.

[0074] For example, when the vector data rearrangement instruction is a Zip instruction, the address generation unit can generate an index sequence of data flow direction for controlling the interleaving arrangement; when the vector data rearrangement instruction is an Unzip instruction, the address generation unit can generate an index sequence of data flow direction for controlling the deinterleaving arrangement.

[0075] The vector data rearrangement execution method based on load storage path multiplexing provided in this application generates an index sequence based on the width and length of vector elements or the rearrangement operation type, which can flexibly adapt to different vector configuration parameters. This mechanism can support data rearrangement operations of different scales without modifying the hardware structure, and has good versatility and scalability.

[0076] Step 204: Utilize the multi-level data selection network in the load storage path to perform data channel-level path selection and distribution on the vector data in the source vector register according to the data flow index sequence, and complete the rearrangement operation.

[0077] The multi-level data selection network is a data organization network used by the load storage unit to organize and distribute data within a segment when executing segment load instructions. When executing vector data rearrangement instructions, the processor reuses this data organization network to complete vector data rearrangement without adding a separate data exchange network. Specifically, the multi-level data selection network includes multiple data selection nodes. Each data selection node determines the corresponding data transmission direction based on the data flow direction index sequence, thereby realizing the data transmission from the input data to the target output location.

[0078] In some embodiments, when a vector data rearrangement instruction involves multiple source vector registers, the instruction is decomposed into multiple micro-operations. These micro-operations time-multiplex the load storage path, and each micro-operation processes a portion of the vector data in the source vector registers. Based on the data flow index sequence, the processor sequentially selects and distributes the vector data in the source vector registers through the load storage path over multiple execution cycles to complete the rearrangement operation.

[0079] Specifically, when a vector data rearrangement instruction involves multiple source vector registers, and the load storage path can only read a portion of the source vector register data at a time, the processor can break down the corresponding vector data rearrangement instruction into multiple micro-operations and complete data reading, path selection, and data distribution sequentially within multiple execution cycles, thereby completing the overall rearrangement operation.

[0080] The vector data rearrangement execution method based on load storage path reuse provided in this application decomposes vector data rearrangement instructions into micro-operations, which can reuse the original, smaller-scale multi-level data selection network in the load storage path. This means that there is no need to introduce a dedicated, large, fully interconnected data exchange unit to support complex wide vector rearrangements, which helps to reduce hardware overhead and design complexity.

[0081] The rearrangement operation (vector data rearrangement operation) is implemented by reusing a multi-level data selection network in the load storage path, without adding a new cross-connect network, permutation network or data exchange network dedicated to vector data rearrangement.

[0082] In some embodiments, the rearrangement operation includes an interleaving operation. When the rearrangement operation is an interleaving operation, vector data from different source vector registers are interleaved and output according to a preset data channel lane mapping relationship based on the data flow direction index sequence, and then output to the corresponding target position, so that the vector data are arranged in an interleaved manner.

[0083] Specifically, when the rearrangement operation is an interleaving operation, the vector data from different source vector registers are cross-multiplexed according to the data flow index sequence, and the interleaving arrangement result of the vector data from different source vector registers is output.

[0084] The vector data rearrangement execution method based on load storage path multiplexing provided in this application reuses the load storage path, which was originally only used for memory access data processing, in the data interleaving process, allowing the same hardware path to perform different functions in different modes. By directly supporting interleaving operations at the hardware level, the data interleaving process, which originally required a combination of multiple vector instructions, is transformed into execution completed by dedicated rearrangement instructions and corresponding micro-operations. This reduces the number of instructions and intermediate data movement processes, lowers the number of register accesses and pipeline scheduling pressure, thereby improving overall execution efficiency.

[0085] In some embodiments, the rearrangement operation includes a deinterleaving operation. When the rearrangement operation is a deinterleaving operation, the vector data from the source vector register is distributed and output to the corresponding positions according to the data flow direction index sequence and a preset data channel lane mapping relationship.

[0086] Specifically, when the rearrangement operation is a deinterleaving operation, the vector data in the source vector register is selected and distributed at the lane level according to the data flow index sequence, and the vector data in the source vector register is mapped to different target data locations.

[0087] The vector data rearrangement execution method based on load storage path multiplexing provided in this application directly supports deinterleaving operations at the hardware level. This transforms the data deinterleaving process, which originally required multiple vector instructions, into execution completed through dedicated rearrangement instructions and corresponding micro-operations. This reduces the number of instructions and intermediate data movement, lowers register access frequency and pipeline scheduling pressure, thereby improving overall execution efficiency.

[0088] Step 205: Write the rearranged vector data to the target vector register through the write-back path of the load storage path.

[0089] The write-back path is used to transfer and submit the rearranged vector data to the target vector register. The write-back path is also used to write the rearrangement result to the target vector register.

[0090] In summary, the technical solution provided by the embodiments of this application realizes the interleaving or deinterleaving operation of vector data by reusing the multi-level data selection network in the load storage path. In the implementation process, there is no need to introduce a general permutation network or additional data exchange structure, avoiding the introduction of highly complex interconnection structures. This helps to reduce hardware area overhead, reduce wiring complexity, and improve the execution efficiency of vector data rearrangement.

[0091] Furthermore, by reusing the load storage path for memory access data processing in the register-level data rearrangement process, the same hardware path can perform different functions in different modes. Through data source path switching and control signal configuration, unified support for memory access mode and vector data rearrangement mode can be achieved, thereby avoiding resource redundancy caused by independent data rearrangement and improving the reuse rate of existing load storage hardware resources.

[0092] The above embodiments mainly describe in detail the vector data rearrangement execution method based on load storage path multiplexing. The following will describe in detail the system architecture of the processor that implements the vector data rearrangement execution method based on load storage path multiplexing.

[0093] like Figure 3 The diagram shows a schematic of the vector data rearrangement execution system architecture. This architecture includes: an instruction decoder, a vector register file (VRF), a load / store unit (LSU), an address generation unit (AGU), a data distribution path (also called a data distribution path), a write-back unit, and a memory interface.

[0094] The load storage unit connects the vector register file and the memory interface, and includes a data distribution path for organizing and distributing segment load instruction data. In memory access mode, this data distribution path distributes the data returned by the segment load according to the target register layout; in rearrangement mode, it is reused for vector data rearrangement operations. The write-back unit writes the processing results back to the vector register file. The address generation unit generates a data flow index that controls the data distribution path. In memory access mode, the address generation unit generates the memory access address; in rearrangement mode, the address generation unit switches to index generation mode and generates a data flow index sequence based on the vector configuration parameters to drive the data distribution path to complete vector data rearrangement.

[0095] In memory access mode, the loaded data output by the memory interface enters the data distribution path through the load storage unit and is distributed to the target vector register according to the data organization method corresponding to the segment load instruction.

[0096] In rearrangement mode, the input of the load storage path switches from the memory interface to the source vector register output port, allowing the vector data to be processed to enter the load storage path. The address generation unit outputs a data flow direction index sequence, and the data distribution path selects and distributes the input vector data according to the data flow direction index sequence, thereby completing the interleaving or deinterleaving operation, and writing it to the target vector register through the write-back unit. During the rearrangement process, no access to the external storage system is triggered; the vector data only flows between the vector register file, the load storage unit, and the write-back unit.

[0097] The above provides a brief description of the overall architecture of the vector data rearrangement execution system. The execution logic within the vector data rearrangement execution system architecture will be described below.

[0098] like Figure 4 The diagram shows the execution logic of each component in the data rearrangement execution system architecture.

[0099] A data source selection logic is set at the input of the load storage path. The input of the load storage path includes source vector data from the vector register file and memory access data from the memory interface. The data source selection logic switches between two modes based on control signals: Mode 1. Memory Access Mode: Selects memory access data output from the memory interface as input, performing regular segment load or store operations. Mode 2. Vector Data Reordering Mode: Selects source data from the vector register file (source vector register 1 and source vector register 2), allowing the source vector register data to enter the load storage path, thereby reusing the memory access data processing path to perform data reordering. Through this switching mechanism, the data path originally used for processing memory access data is used for data reordering between source vector registers without actual memory access occurring.

[0100] The load storage unit contains a data distribution path for segment loading instructions. This path includes a multi-level data selection network for allocating, combining, and mapping the input data. In this embodiment, no new dedicated permutation network is added in the rearrangement mode. Instead, the interleaving and deinterleaving of vector data are achieved by controlling the selection relationships of the existing multi-level data selection network. As data flows through each selection node, it completes position mapping according to the data flow direction index sequence, thereby achieving data rearrangement. In the interleaving operation mode, the data distribution path outputs data from multiple source vector registers alternately in a preset order according to the data flow direction index sequence. In the deinterleaving operation mode, the data distribution path splits the input data according to preset rules and maps it to different output positions according to the data flow direction index sequence. Thus, the existing segment loading data organization structure can be used to achieve interleaving and deinterleaving operations without adding a dedicated crossbar switch network, permutation network, or data exchange network.

[0101] The address generation unit (AGU) is connected to the load storage unit and operates in different modes. For example, in memory access address generation mode, the AGU generates the physical address for load or storage operations; in index generation mode, the AGU masks the memory access address output when executing vector data rearrangement instructions and generates a data flow index sequence based on the width of the vector elements, the vector length, or the rearrangement operation type. The data flow index sequence describes the target location mapping relationship of each vector data in the multi-level data selection network of the load storage path.

[0102] In vector data rearrangement mode, the execution of vector data rearrangement instructions does not depend on the actual storage access process. The data flow is as follows: the vector data to be rearranged is output from the source vector register file, enters the load storage unit via the data source selection logic, completes data rearrangement in the data distribution path, and is then written to the target vector register via the write-back path. Throughout the entire execution process: no access requests to the external storage system are initiated, no cache access path is used, and vector data flows only within the load storage path between the source vector register file and the load storage unit. Thus, register-level data rearrangement execution is achieved.

[0103] Optionally, when a vector data rearrangement instruction involves multiple source vector registers, the instruction decoding unit can decompose it into multiple micro-operations. Each micro-operation time-multiplexes the load storage path, and each micro-operation processes only a portion of the vector data each time, completing the full data rearrangement within multiple execution cycles.

[0104] The above method enables the rearrangement of multi-source data without increasing the number of vector register stack read ports, thereby avoiding the need to increase the number of vector register stack read ports and dedicated data exchange networks, and reducing hardware implementation complexity and area overhead.

[0105] The above provides a brief description of the overall architecture of the vector data rearrangement execution system. The execution logic within this architecture will be described below. Figure 5 The flowchart shown illustrates the data rearrangement execution method. This embodiment uses the example of the method being executed by a processor. The processor can be... Figure 1 The processor 100 is shown in the diagram.

[0106] Step 501: Decode and recognize the instruction, and generate control signals.

[0107] Specifically, during the instruction decoding stage, the instruction decoding unit in the processor parses the input instruction, and when it is identified as a vector data rearrangement instruction, it generates the corresponding control signal for the vector data rearrangement instruction.

[0108] The control signals include data source selection signals, operation type identification signals, and data flow direction index-related control information used to drive the data distribution path. For vector data rearrangement instructions involving multiple source vector registers, the decoding unit generates control signals for time-multiplexed load storage paths based on vector register read port constraints to support subsequent phased execution.

[0109] Step 502: Switch the input of the load storage path from the memory interface to the output port of the source vector register.

[0110] Specifically, based on the control signal, the input of the load storage path is switched to the output of the vector register file, allowing the vector data to be processed to enter the load storage path. At this time, the input path originally used to receive data returned from the memory interface is reused as the vector register data input path, thus allowing the data in the vector register to enter the data distribution path without initiating an actual memory access request.

[0111] Step 503: Switch from memory address generation mode to index generation mode.

[0112] Specifically, during the execution of vector data rearrangement instructions, the address generation unit (AGU) switches from memory access address generation mode to index generation mode according to control signals, thus masking the physical address generation path. In index generation mode, the AGU generates a data flow index sequence based on the vector element width, vector length, and operation type.

[0113] Step 504: Data enters the data distribution path in the load storage path.

[0114] Specifically, after the data source path is switched and a data flow index sequence is generated, the vector data from the source vector register file enters the data distribution path in the load storage path. During this process, the data enters the data distribution path in the same data format as the memory access return data, thereby reusing the existing data processing structure, so there is no need to modify the original data distribution path structure.

[0115] Step 505: Select the data rearrangement path.

[0116] Specifically, the corresponding data rearrangement path is selected based on the operation type identifier signal. After the data enters the data distribution path, the corresponding data rearrangement execution path is selected based on the operation type identifier signal generated in step 501. If the rearrangement operation type of the vector data rearrangement instruction is interleaving, step 506 is executed. If the rearrangement operation type of the vector data rearrangement instruction is deinterleaving, step 507 is executed.

[0117] Step 506: Perform interleaving mapping output using a multi-level data selection network.

[0118] Specifically, when the rearrangement operation type of the vector data rearrangement instruction is interleaving, the multi-level data selection network controls the connection relationship of each level of selection node according to the data flow direction index sequence, and interleaves the data from different source vector registers according to the preset lane mapping relationship, so that the data forms an interleaved arrangement at the output end.

[0119] Step 507: Perform deinterleaving mapping output using a multi-level data selection network.

[0120] Specifically, when the rearrangement operation type of the vector data rearrangement instruction is deinterleaving, the multi-level data selection network controls the connection relationship of each level of selection node according to the data flow direction index sequence, separates and redirects the input data by lane, and outputs it to the corresponding target position.

[0121] Step 508: Write to the target vector register.

[0122] Specifically, after the data rearrangement is completed, the rearrangement result is written to the target vector register through the write-back path of the load storage unit, thereby completing the submission of the result corresponding to the vector data rearrangement instruction. This completes one vector data rearrangement operation.

[0123] In summary, through the above steps, this embodiment utilizes the data distribution path originally used for segment loading instructions in the load storage path to complete vector data rearrangement, and generates a data flow index sequence in index generation mode through the address generation unit to drive a multi-level data selection network to complete data location mapping. Without adding a dedicated replacement network or relying on actual memory access operations, it achieves vector data interleaving and deinterleaving, thereby improving hardware resource utilization and reducing implementation complexity.

[0124] like Figure 6 The diagram shows a data rearrangement mechanism.

[0125] In this application, vector data is rearranged using lanes as the basic processing unit. The input vector data is arranged element-wise in multiple lanes, with each lane corresponding to a data processing channel in the load storage path. The data distribution path includes multi-level data selection nodes to control the distribution and output of data between lanes. Therefore, the data rearrangement process can be abstracted as follows: under the control of multi-level selection nodes, the input vector data is allocated to the target location according to the path selection relationship corresponding to a predetermined rearrangement pattern.

[0126] The purpose of performing an interleaving operation is to arrange vector data from multiple source vector registers into an interleaved arrangement at the output.

[0127] Specifically, vector data from multiple source vector registers are sequentially input into the load storage path and then into the data distribution path. The address generation unit generates a corresponding data flow direction index sequence, which describes the target position mapping relationship of each vector data in the multi-level data selection network within the load storage path. Data path selection is controlled according to the data flow direction index sequence, causing vector data from different source vector registers to be alternately distributed between different lanes. After processing by the multi-level selection nodes, the output data forms an interleaved arrangement by lane in the target vector register. In this process, data interleaving is not achieved through a general permutation network, but rather by controlling the selection relationship within the existing data distribution path, thereby reducing hardware complexity.

[0128] For example, during the interleaving operation, the input data includes vector data in source vector register 1 and vector data in source vector register 2. The vector data in source vector register 1 is (A0, A1, A2, A3), and the vector data in source vector register 2 is (B0, B1, B2, B3). The address generation unit generates the corresponding data flow direction index sequence and controls the data path selection so that the vector data from different source vector registers are output in an alternating order. The resulting interleaved output is: (A0, B0, A1, B1, A2, B2, A3, B3).

[0129] The purpose of performing deinterleaving is to split and reorganize the interleaved data in the input vector according to its source or location.

[0130] Specifically, the input vector data is fed into the data distribution path as a whole. The address generation unit generates a corresponding data flow direction index sequence. At each level of data selection node, the input data is selected and distributed at the lane level according to the data flow direction index sequence, separating the originally interleaved data into different output paths. After processing by the data distribution path, data from different sources or locations are reassembled into the corresponding positions in the target vector register, achieving deinterleaving. Similarly, this process is completed by controlling the existing data distribution path, without introducing additional data exchange structures.

[0131] For example, suppose the input vector data is "(A0, B0, A1, B1, A2, B2, A3, B3)". The address generation unit generates the corresponding data flow direction index sequence and controls the data path selection, so that the interleaved data is reorganized according to its source. The final deinterleaved output is: First target vector register: (A0, A1, A2, A3); Second target vector register: (B0, B1, B2, B3).

[0132] In summary, both interleaving and deinterleaving operations share the core principle of driving multi-level data selection nodes through a data flow direction index sequence to achieve path selection and mapping of data between different lanes. Specifically, the data flow direction index sequence is dynamically generated by the address generation unit based on vector configuration parameters. Each index value corresponds to a path selection relationship in the data distribution path. The multi-level data selection nodes adjust the data flow direction step by step according to the data flow direction index sequence, thereby forming the target arrangement at the output end.

[0133] In some embodiments, the data flow index sequence is not used to generate memory access addresses, but rather as control information for a multi-level data selection network to control the flow of data in the data distribution path.

[0134] This mechanism transforms the data rearrangement problem, which originally required a complex permutation network, into a data distribution problem under index control. In the embodiments of this application, the data rearrangement process has the following characteristics: data rearrangement is completed by controlling multi-level data selection nodes, rather than relying on a general permutation network; all vector data flows within the register and load storage path; the data flow index sequence can be dynamically generated according to the vector length and element width; it supports interleaving and deinterleaving operations, and can be combined with a micro-operation decomposition mechanism to complete multi-source vector data rearrangement.

[0135] The foregoing mainly describes the method provided in this application. Accordingly, this application also provides a vector data rearrangement processor for implementing the above-described method embodiments.

[0136] In some embodiments, the vector data rearrangement processor includes hardware structures and / or software modules corresponding to the execution of each function in order to achieve the above-described functions. Those skilled in the art will readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0137] This application embodiment can divide the vector data rearrangement processor into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0138] In some embodiments, this application provides a vector data rearrangement processor. For example... Figure 7 The diagram shows the structure of a vector data rearrangement processor. The vector data rearrangement processor may include: an instruction decoding unit 701, a load storage unit 702, an address generation unit 703, a data distribution unit 704, and a write-back unit 705.

[0139] The instruction decoding unit 701 is used to obtain the vector data rearrangement instruction, parse the vector data rearrangement instruction, and generate the control signal corresponding to the vector data rearrangement instruction. The vector data rearrangement instruction is used to rearrange the vector data in the source vector register.

[0140] The load storage unit 702 is used to switch the input terminal of the load storage path from the memory interface to the source vector register output port according to the control signal, so that the vector data to be processed can enter the load storage path without initiating an external storage system access request.

[0141] Address generation unit 703 is used to switch from memory access address generation mode to index generation mode according to the control signal. In the index generation mode, physical address generation is disabled, and a data flow index sequence for controlling the data distribution path is generated. The data flow index sequence is used to describe the target location mapping relationship of each vector data in the multi-level data selection network in the load storage path.

[0142] The data distribution unit 704 is used to utilize the multi-level data selection network in the load storage path to perform data channel-level path selection and distribution on the vector data in the source vector register according to the data flow direction index sequence, thereby completing the rearrangement operation.

[0143] The write-back unit 705 is used to write the rearranged vector data into the target vector register through the write-back path of the load storage path.

[0144] In one possible implementation, the address generation unit 703 is specifically used to: generate the data flow direction index sequence according to the vector configuration parameters, wherein each index value in the data flow direction index sequence corresponds to a target data channel or path selection relationship, so as to drive the multi-level data selection network to adjust the data flow direction; wherein the vector configuration parameters include at least one of the following: the width of the vector element, the vector length, or the rearrangement operation type.

[0145] In one possible implementation, the instruction decoding unit 701 is further configured to: when the vector data rearrangement instruction involves multiple source vector registers, decompose the vector data rearrangement instruction into multiple micro-operations and generate control information for time-division multiplexing of the load storage path. Correspondingly, the data distribution unit 704 is specifically configured to: according to the data flow direction index sequence, sequentially complete the data channel-level path selection and distribution corresponding to the multiple micro-operations within multiple execution cycles, thereby completing the rearrangement operation.

[0146] In another possible implementation, the load storage path is used in memory access mode to receive segment load data from the memory interface and to complete data distribution in the multi-level data selection network.

[0147] Another possible implementation is that the rearrangement operation is achieved by reusing the multi-level data selection network in the load storage path, without adding a new data exchange network dedicated to vector data rearrangement.

[0148] Another possible implementation is that the data distribution unit 704 described above is specifically used to: when the rearrangement operation is an interleaving operation, according to the data flow direction index sequence, interleave vector data from different source vector registers according to a preset data channel mapping relationship and output them to the corresponding target position.

[0149] Another possible implementation is that the data distribution unit 704 is specifically used to: when the rearrangement operation is the deinterleaving operation, distribute the vector data from the source vector register according to the data flow direction index sequence, according to the preset data channel lane mapping relationship, and output it to the corresponding target position.

[0150] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8 As shown, the electronic device may include a processor 810, a communications interface 820, a memory 830, and a communication bus 840. The processor 810, communications interface 820, and memory 830 communicate with each other via the communication bus 840. The processor 810 can call logical instructions from the memory 830 to execute a vector data rearrangement execution method based on load storage path multiplexing.

[0151] Furthermore, the logical instructions in the aforementioned memory 830 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0152] In some embodiments, this application also provides a chip including at least one processor, the processor being configured to execute program instructions to perform the methods provided in the above embodiments.

[0153] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory and / or non-volatile memory. Non-volatile memory can be ROM, Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), or flash memory. Volatile memory can be RAM. For example, RAM can be used as an external cache. By way of example and not limitation, RAM includes various forms such as: Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchlink Dynamic Random Access Memory (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) can be integrated into the processor.

[0154] like Figure 9 This application provides a chip system 900. The chip system 900 (or processing system) includes logic circuitry 910 and an input / output interface 920. The logic circuitry 910 can be a processing circuit or an interface circuit within the chip system 900. The logic circuitry 910 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 900 to implement the methods and functions of the embodiments of this application. The input / output interface 920 can be an input / output circuit within the chip system 900, outputting processed information or inputting data or signaling information to be processed into the chip system 900 for processing.

[0155] As one approach, the chip system 900 is used to implement the operations described in the various method embodiments above. For example, the logic circuit 910 is used to implement the relevant operations performed by each execution entity in the method embodiments above; the input / output interface 920 is used to implement the sending and / or receiving related operations performed by each execution entity in the method embodiments above.

[0156] The processor embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0157] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vector data rearrangement execution method based on load storage path multiplexing, characterized in that, The method includes: Obtain the vector data rearrangement instruction, parse the vector data rearrangement instruction, and generate the corresponding control signal. The vector data rearrangement instruction is used to rearrange the vector data in the source vector register. According to the control signal, the input of the load storage path is switched from the memory interface to the source vector register output port, so that the vector data to be processed can enter the load storage path without initiating an external storage system access request. According to the control signal, the address generation unit is switched from memory access address generation mode to index generation mode. In the index generation mode, physical address generation is blocked, and a data flow index sequence for controlling the data distribution path is generated. The data flow index sequence is used to describe the target location mapping relationship of each vector data in the multi-level data selection network in the load storage path. Using the multi-level data selection network in the load storage path, the vector data in the source vector register is selected and distributed at the lane level according to the data flow index sequence to complete the rearrangement operation; The rearranged vector data is written to the target vector register through the write-back path of the load storage path.

2. The method according to claim 1, characterized in that, The generation of the data flow index sequence for controlling the data distribution path includes: The data flow direction index sequence is generated based on the vector configuration parameters. Each index value in the data flow direction index sequence corresponds to a target data channel lane or path selection relationship to drive the multi-level data selection network to adjust the data flow direction.

3. The method according to claim 1, characterized in that, The method further includes: When the vector data rearrangement instruction involves multiple source vector registers, the vector data rearrangement instruction is decomposed into multiple micro-operations. The multiple micro-operations time-multiplex the load storage path, and each micro-operation processes a portion of the vector data in the source vector registers. The step of performing lane-level path selection and distribution on the vector data in the source vector register according to the data flow direction index sequence to complete the rearrangement operation includes: Based on the data flow index sequence, the vector data in the source vector register is sequentially selected and distributed in the load storage path through multiple execution cycles to complete the rearrangement operation.

4. The method according to claim 1, characterized in that, The load storage path is also used to receive segment load data from the memory interface and distribute the segment load data through the multi-level data selection network.

5. The method according to any one of claims 1 to 4, characterized in that, The rearrangement operation is implemented by reusing the multi-level data selection network in the load storage path, without adding a new cross-connect network, permutation network or data exchange network dedicated to vector data rearrangement.

6. The method according to any one of claims 1 to 4, characterized in that, The rearrangement operation includes: interleaving operation; The step of selecting and distributing data channel-level paths for the vector data in the source vector register based on the data flow direction index sequence includes: When the rearrangement operation is an interleaving operation, vector data from different source vector registers are interleaved and output according to the data flow direction index sequence, and output to the corresponding target position.

7. The method according to any one of claims 1 to 4, characterized in that, The rearrangement operation includes: deinterleaving operation; The step of selecting and distributing data channel-level paths for the vector data in the source vector register based on the data flow direction index sequence includes: When the rearrangement operation is the deinterleaving operation, the vector data from the source vector register is distributed and output to the corresponding position according to the data flow direction index sequence and the preset data channel lane mapping relationship.

8. The method according to claim 2, characterized in that, The step of generating the data flow direction index sequence based on the vector configuration parameters includes: The data flow index sequence is generated based on the vector element width EEW, the vector length VL, and the rearrangement operation type.

9. A vector data rearrangement processor, characterized in that, The processor includes: The instruction decoding unit is used to acquire vector data rearrangement instructions, parse the vector data rearrangement instructions, and generate corresponding control signals; The load storage unit is used to switch the input terminal of the load storage path from the memory interface to the source vector register output port according to the control signal, so that the vector data to be processed can enter the load storage path without initiating an external storage system access request. The address generation unit is used to switch from memory access address generation mode to index generation mode according to the control signal. In the index generation mode, physical address generation is blocked, and a data flow index sequence for controlling the data distribution path is generated. The data distribution unit is used to utilize the multi-level data selection network in the load storage path to perform lane-level path selection and distribution on the vector data in the source vector register according to the data flow direction index sequence, and complete the rearrangement operation. The write-back unit is used to write the rearranged vector data into the target vector register through the write-back path of the load storage path.

10. A chip, characterized in that, Includes the vector data rearrangement processor as described in claim 9.

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