An automatic monitoring and adaptation method for multiple configurations on the same board

Abstract

This invention discloses an automatic monitoring and adaptation method for multiple configurations on the same board, belonging to the technical field of server hardware design and board configuration management. This invention detects the level states of the logic outputs and logic inputs of the general-purpose input / output signals associated with high-speed connectors to determine whether the loopback cable is in place. Based on the combination of loopback cable presence states corresponding to different high-speed connectors, the board hardware configuration type is determined. A corresponding preset configuration identifier is written to a designated storage area of ​​the field-replaceable unit. Then, a multiplexer switches the access permissions of the field-replaceable unit. The board management controller reads the configuration identifier to complete board configuration adaptation and cable alarm processing. This invention achieves a unified design of board hardware and firmware, reduces overall production and maintenance costs, avoids data conflicts caused by multiple accesses, and improves the deployment efficiency and operational stability of hardware configuration adjustments.

Description

Technical Field

[0001] This invention relates to the field of server hardware design and single-board configuration management technology, and in particular to a method for automatic monitoring and adaptation of multiple configurations on the same single board. Background Technology

[0002] With the rapid development of cloud computing and artificial intelligence technologies, the application requirements of general-purpose servers are gradually shifting towards AI / GPU servers, and the application scale of multi-GPU parallel computing hardware configurations in the server field continues to expand. In server hardware architecture design, the single-board unit, as the core carrier of hardware resources and signal transmission, directly determines the allocation capability and configuration flexibility of server hardware resources. Currently, in the industry, server hardware management generally adopts a board management controller to realize hardware status monitoring, resource configuration, and fault alarm functions. By reading the single-board hardware information stored in the field replaceable unit, it completes single-board resource topology identification, IO capability configuration, and cable connection status management. At the same time, in response to the diverse hardware configuration requirements of servers, the industry is also continuously exploring standardized and compatible solutions for single-board hardware design to adapt to the combination configuration requirements of different numbers of GPUs, NVMe storage components, and other hardware, and to match the server hardware deployment requirements under different application scenarios.

[0003] Current server multi-configuration adaptation technologies require the design and production of different PCBA boards for different hardware configurations, assigning independent material codes to each board. This prevents the standardization of board hardware design, resulting in high overall costs for board manufacturing, bill of materials management, and subsequent maintenance. Different configurations require different field-replaceable unit information and firmware programs to be burned, hindering firmware and storage information standardization. This increases manufacturing complexity and the manpower and time costs of firmware iteration and version maintenance. Hardware configuration changes necessitate re-application for board codes, firmware burning, and software adaptation, hindering automatic hardware configuration identification and adaptation. Furthermore, simultaneous handling of cable connection status alarms is difficult, making server hardware configuration adjustments cumbersome and inefficient. Additionally, the lack of an orderly switching control mechanism for field-replaceable unit access permissions leads to data conflicts caused by multiple users operating simultaneously, impacting the stability and reliability of configuration information storage. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an automatic monitoring and adaptation method for multiple configurations on the same board.

[0005] The objective of this invention is achieved through the following technical solution: A method for automatic detection and adaptation of multiple configurations on the same board is provided, which includes the following steps: S1. After power-on, the level status of the logic output general input / output signal and logic input general input / output signal associated with each high-speed connector is detected to determine whether the loopback cable is in place. The loopback cable connects the logic output general input / output signal and logic input general input / output signal of the same high-speed connector. S2. Determine the hardware configuration type of the board based on the combination of the in-situ states of the loopback cables corresponding to different high-speed connectors; S3. Write the preset configuration identifier corresponding to the hardware configuration type of the single board into the designated storage area of ​​the field replaceable unit to complete the update of the configuration identifier in the field replaceable unit; S4. Switch the access permissions of the field replaceable unit through a multiplexer, establish a communication connection between the baseboard management controller and the field replaceable unit, read the configuration identifier in the field replaceable unit, and complete the single board configuration adaptation and cable alarm processing according to the configuration identifier.

[0006] Furthermore, step S1 includes the following sub-steps: S1.1. After power-on, initialize the working mode of all general-purpose input / output ports, set the push-pull output mode of the ports corresponding to the logic output general-purpose input / output signals, set the pull-up input mode of the ports corresponding to the logic input general-purpose input / output signals, and output fixed-level logic output general-purpose input / output signals to the signal ports corresponding to each high-speed connector according to the preset timing. S1.2. After outputting the general logic input / output signal, wait for a preset level stabilization time, sequentially collect the level state of the general logic input / output signal corresponding to each high-speed connector, and store the collected level state in the temporary storage area. S1.3. Compare bit by bit the output level of the logic output general input / output signal and the acquisition level of the logic input general input / output signal corresponding to each high-speed connector. If the two levels are consistent, it is determined that the corresponding high-speed connector is connected to the loopback cable. If the two levels are inconsistent, it is determined that the corresponding high-speed connector is not connected to the loopback cable.

[0007] Furthermore, step S2 includes the following sub-steps: S2.1. A mapping table between loopback cable in-situ state combinations and board hardware configuration types is pre-stored in a non-volatile storage area. Each loopback cable in-situ state combination in the mapping table corresponds to a unique board hardware configuration type. The mapping table is written during the board production stage and cannot be modified after being written. S2.2. Read the loopback cable presence status of all high-speed connectors from the temporary storage area, combine them into loopback cable presence status combinations according to the preset arrangement order, match the combined loopback cable presence status combinations with all entries in the mapping table one by one, and obtain the single-board hardware configuration type corresponding to the successfully matched entries.

[0008] Furthermore, step S3 includes the following sub-steps: S3.1. Based on the determined single-board hardware configuration type, read the pre-stored preset configuration identifiers that correspond one-to-one with the single-board hardware configuration type from the non-volatile storage area. The preset configuration identifiers are written during the single-board production stage and correspond one-to-one with the single-board hardware configuration types in the mapping table. S3.2. Generate a first control signal for the multiplexer, send the first control signal to the control port of the multiplexer, switch the internal channel of the multiplexer according to the first control signal, disconnect the communication channel between the substrate management controller and the field replaceable unit, and establish a communication channel between the complex programmable logic device and the field replaceable unit. S3.3. Through the established communication channel, the read preset configuration identifier is written into the designated storage area of ​​the field replaceable unit. After writing is completed, the written content is verified bit by bit to confirm that the written content is consistent with the preset configuration identifier.

[0009] Furthermore, step S4 includes the following sub-steps: S4.1. After completing the writing and verification of the preset configuration identifier, generate the second control signal of the multiplexer, send the second control signal to the control port of the multiplexer, and switch the internal channel of the multiplexer according to the second control signal; S4.2. Disconnect the communication channel between the complex programmable logic device and the field replaceable unit, establish a communication channel between the baseboard management controller and the field replaceable unit, and maintain the connection status of the communication channel between the baseboard management controller and the field replaceable unit until the board is powered off; S4.3. Read the configuration identifier in the designated storage area of ​​the field replaceable unit through the established communication channel, load the corresponding board configuration parameters according to the read configuration identifier, and perform board hardware resource allocation operation and cable connection status alarm detection operation.

[0010] Furthermore, in step S1, the loopback cable is manufactured using a uniform type of cable, and all loopback cables have the same electrical parameters and physical structure. The loopback cable only contains conductors for signal connection and physical structures for fixed connection, and does not contain any active electronic components. Both ends of the loopback cable are provided with physical interfaces that match the high-speed connector. The physical interfaces are only connected to the logic output general input / output signal pins and logic input general input / output signal pins corresponding to the same high-speed connector, and are not connected to any other pins of the high-speed connector.

[0011] Furthermore, in step S3, the designated storage area of ​​the field-replaceable unit is an independent storage area pre-divided within the field-replaceable unit. The address allocation of the designated storage area of ​​the field-replaceable unit is completed during the production stage of the field-replaceable unit, and the address allocation cannot be modified afterward. The designated storage area is only used to store the configuration identifier corresponding to the hardware configuration type of the board, and does not store any other information of the field-replaceable unit. The length of the configuration identifier matches the capacity of the designated storage area. Each configuration identifier corresponds to a unique board hardware configuration type, and there are no duplicate configuration identifiers.

[0012] Furthermore, in step S3.2, after sending the first control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit, and a handshake response signal is received from the field replaceable unit. Based on the handshake response signal, it is confirmed that the communication channel between the complex programmable logic device and the field replaceable unit has been successfully established. Before the configuration identifier writing operation and the write content verification operation are completed, the control port level of the multiplexer remains unchanged, the communication channel connection between the complex programmable logic device and the field replaceable unit is maintained, and switching of the internal channel of the multiplexer is prohibited.

[0013] Furthermore, in step S4, the multiplexer is a two-to-one analog switch device. The multiplexer includes two input channels, one output channel, and a control port. The two input channels are respectively connected to the communication port of the complex programmable logic device and the communication port of the board management controller. The output channel is connected to the communication port of the field replaceable unit. According to the control signal received by the control port, one of the input channels is selected to be connected to the output channel to realize the switching of the field replaceable unit access subject. Only one input channel can be connected to the output channel at the same time.

[0014] Furthermore, in step S4.1, after sending the second control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit, and a handshake response signal is received from the field replaceable unit. Based on the handshake response signal, it is confirmed that the communication channel between the board management controller and the field replaceable unit has been successfully established. After confirming that the communication channel has been successfully established, the control port level of the multiplexer is locked. During the remaining time of the board's current power-on operation, the control port level of the multiplexer remains unchanged, and it no longer responds to any multiplexer control signals from the complex programmable logic device.

[0015] The beneficial effects of this invention are: (1) Through the complete process of loopback cable presence detection, hardware configuration type identification and configuration identifier dynamic update, the same board can automatically adapt to multiple hardware configurations and handle alarms. There is no need to design and produce boards separately for different configurations, which reduces the overall cost of production and maintenance. (2) By using a multiplexer to control the time-sharing of access permissions for field replaceable units, the orderly execution of configuration identifier writing and reading operations is achieved, avoiding data conflicts and writing anomalies caused by simultaneous operations by multiple access subjects; (3) The standardized single-board hardware design and standardized loopback cable scheme simplify the whole life cycle management process of hardware materials, improve system deployment efficiency and operation stability, and reduce the workload of manual configuration and troubleshooting. Attached Figure Description

[0016] Figure 1 A flowchart illustrating the steps of an automatic monitoring and adaptation method for multiple configurations on the same board. Figure 2 The flowchart illustrates the specific steps of an automatic monitoring and adaptation method for multiple configurations on the same board, as provided in this embodiment. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1 See Figure 1 This embodiment provides an automatic monitoring and adaptation method for multiple configurations on the same board, which includes the following steps: S1. After power-on, the level status of the logic output general input / output signal and logic input general input / output signal associated with each high-speed connector is detected to determine whether the loopback cable is in place. The loopback cable connects the logic output general input / output signal and logic input general input / output signal of the same high-speed connector. S2. Determine the hardware configuration type of the board based on the combination of the in-situ states of the loopback cables corresponding to different high-speed connectors; S3. Write the preset configuration identifier corresponding to the hardware configuration type of the single board into the designated storage area of ​​the field replaceable unit to complete the update of the configuration identifier in the field replaceable unit; S4. Switch the access permissions of the field replaceable unit through a multiplexer, establish a communication connection between the baseboard management controller and the field replaceable unit, read the configuration identifier in the field replaceable unit, and complete the single board configuration adaptation and cable alarm processing according to the configuration identifier.

[0019] In some embodiments, step S1 includes the following sub-steps: S1.1. After power-on, initialize the working mode of all general-purpose input / output ports, set the push-pull output mode of the ports corresponding to the logic output general-purpose input / output signals, set the pull-up input mode of the ports corresponding to the logic input general-purpose input / output signals, and output fixed-level logic output general-purpose input / output signals to the signal ports corresponding to each high-speed connector according to the preset timing. S1.2. After outputting the general logic input / output signal, wait for a preset level stabilization time, sequentially collect the level state of the general logic input / output signal corresponding to each high-speed connector, and store the collected level state in the temporary storage area. S1.3. Compare bit by bit the output level of the logic output general input / output signal and the acquisition level of the logic input general input / output signal corresponding to each high-speed connector. If the two levels are consistent, it is determined that the corresponding high-speed connector is connected to the loopback cable. If the two levels are inconsistent, it is determined that the corresponding high-speed connector is not connected to the loopback cable.

[0020] In some embodiments, step S2 includes the following sub-steps: S2.1. A mapping table between loopback cable in-situ state combinations and board hardware configuration types is pre-stored in a non-volatile storage area. Each loopback cable in-situ state combination in the mapping table corresponds to a unique board hardware configuration type. The mapping table is written during the board production stage and cannot be modified after being written. S2.2. Read the loopback cable presence status of all high-speed connectors from the temporary storage area, combine them into loopback cable presence status combinations according to the preset arrangement order, match the combined loopback cable presence status combinations with all entries in the mapping table one by one, and obtain the single-board hardware configuration type corresponding to the successfully matched entries.

[0021] In some embodiments, step S3 includes the following sub-steps: S3.1. Based on the determined single-board hardware configuration type, read the pre-stored preset configuration identifiers that correspond one-to-one with the single-board hardware configuration type from the non-volatile storage area. The preset configuration identifiers are written during the single-board production stage and correspond one-to-one with the single-board hardware configuration types in the mapping table. S3.2. Generate a first control signal for the multiplexer, send the first control signal to the control port of the multiplexer, switch the internal channel of the multiplexer according to the first control signal, disconnect the communication channel between the substrate management controller and the field replaceable unit, and establish a communication channel between the complex programmable logic device and the field replaceable unit. S3.3. Through the established communication channel, the read preset configuration identifier is written into the designated storage area of ​​the field replaceable unit. After writing is completed, the written content is verified bit by bit to confirm that the written content is consistent with the preset configuration identifier.

[0022] In some embodiments, step S4 includes the following sub-steps: S4.1. After completing the writing and verification of the preset configuration identifier, generate the second control signal of the multiplexer, send the second control signal to the control port of the multiplexer, and switch the internal channel of the multiplexer according to the second control signal; S4.2. Disconnect the communication channel between the complex programmable logic device and the field replaceable unit, establish a communication channel between the baseboard management controller and the field replaceable unit, and maintain the connection status of the communication channel between the baseboard management controller and the field replaceable unit until the board is powered off; S4.3. Read the configuration identifier in the designated storage area of ​​the field replaceable unit through the established communication channel, load the corresponding board configuration parameters according to the read configuration identifier, and perform board hardware resource allocation operation and cable connection status alarm detection operation.

[0023] In some embodiments, in step S1, the loopback cable is manufactured using a cable of the same model, and all loopback cables have the same electrical parameters and physical structure. The loopback cable only contains conductors for signal connection and physical structures for fixed connection, and does not contain any active electronic components. Both ends of the loopback cable are provided with physical interfaces that match the high-speed connector. The physical interfaces are only connected to the logic output general input / output signal pins and logic input general input / output signal pins corresponding to the same high-speed connector, and are not connected to any other pins of the high-speed connector.

[0024] In some embodiments, in step S3, the designated storage area of ​​the field-replaceable unit is an independent storage area pre-divided in the field-replaceable unit. The designated storage area of ​​the field-replaceable unit completes address allocation during the production stage of the field-replaceable unit, and the address allocation cannot be modified after allocation. The designated storage area is only used to store the configuration identifier corresponding to the hardware configuration type of the board, and does not store any other information of the field-replaceable unit. The length of the configuration identifier matches the capacity of the designated storage area. Each configuration identifier corresponds to a unique board hardware configuration type, and there are no duplicate configuration identifiers.

[0025] In some embodiments, in step S3.2, after sending the first control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit, and a handshake response signal returned by the field replaceable unit is received. Based on the handshake response signal, it is confirmed that the communication channel between the complex programmable logic device and the field replaceable unit has been successfully established. Before the configuration identifier writing operation and the write content verification operation are completed, the control port level of the multiplexer remains unchanged, the communication channel connection between the complex programmable logic device and the field replaceable unit is maintained, and switching of the internal channel of the multiplexer is prohibited.

[0026] In some embodiments, in step S4, the multiplexer is a two-to-one analog switch device. The multiplexer includes two input channels, one output channel, and a control port. The two input channels are respectively connected to the communication port of the complex programmable logic device and the communication port of the board management controller. The output channel is connected to the communication port of the field-replaceable unit. According to the control signal received by the control port, one of the input channels is selected to be connected to the output channel to realize the switching of the field-replaceable unit access subject. Only one input channel can be connected to the output channel at the same time.

[0027] In some embodiments, in step S4.1, after sending the second control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit, and a handshake response signal returned by the field replaceable unit is received. Based on the handshake response signal, it is confirmed that the communication channel between the board management controller and the field replaceable unit has been successfully established. After confirming that the communication channel has been successfully established, the control port level state of the multiplexer is locked. During the remaining time of the board's current power-on operation, the control port level state of the multiplexer remains unchanged, and it no longer responds to any multiplexer control signals from complex programmable logic devices.

[0028] Example 2 This embodiment provides a specific implementation process for an automatic monitoring and adaptation method for multiple configurations on the same board. This method is designed for application scenarios with multiple hardware configurations on a single board. Through a complete execution process involving loopback cable presence detection, dynamic writing of configuration identifiers, and switching of access permissions for field-replaceable units, it achieves automatic identification and adaptation of the board's hardware configuration. Figure 2 As shown, the specific implementation process is as follows: Step 1. Loopback cable in-situ detection: Step 1.1. General Purpose Input / Output Port Initialization and Signal Output: A general purpose input / output port (GPIO) is a programmable digital interface that can be configured as an input or output mode via registers to achieve digital signal transmission and detection. After power-on, the operating modes of all GPIO ports are initialized. The ports corresponding to the logic output GPIO signals are set to push-pull output mode. In push-pull output mode, two complementary MOSFETs drive high and low levels respectively, enabling the port to output stable high and low level signals with strong driving capability, capable of driving long transmission lines and multiple loads. The ports corresponding to the logic input GPIO signals are set to pull-up input mode. In pull-up input mode, internal pull-up resistors pull the port level to a high level. When there is no external signal input, the port level is stabilized at a high level to avoid uncertain level values ​​and prevent false triggering.

[0029] According to the preset timing, the logic output general-purpose input / output signals with fixed levels are output to the corresponding signal ports of each high-speed connector. The preset timing controls the time interval and duration of the signal output through a timer to ensure the stability and synchronization of the signal output and avoid errors in the detection results due to signal timing disorder.

[0030] In some specific implementations, the initialization process of the general-purpose input / output ports is completed by writing the control bits of the corresponding registers. The control bits of the registers corresponding to the push-pull output mode are set to binary values ​​0 and 1, and the control bits of the registers corresponding to the pull-up input mode are set to binary values ​​10. The preset timing is set to a signal output duration of 10 milliseconds, a signal output interval of 50 milliseconds, and three consecutive outputs of fixed-level signals, with a 20-millisecond wait after each output before the next output. The fixed level of the logic output general-purpose input / output signals is set to low, with a corresponding voltage range of 0 volts to 0.8 volts, while the high-level voltage range in pull-up input mode is 2.0 volts to 3.3 volts.

[0031] Step 1.2. Input signal acquisition and storage: After the general input / output signal is output from the output logic, wait for a preset level stabilization time. The preset level stabilization time is used to ensure that the output signal reaches a stable state on the transmission line and avoid acquiring incorrect level values ​​due to signal transmission delay.

[0032] The logic input and general-purpose input / output (GPIO) signals corresponding to each high-speed connector are sequentially acquired, and the acquired logic input and general-purpose input / output (GPIO) signals are stored in a temporary storage area. The temporary storage area is a volatile storage medium used to temporarily store data generated during operation. It features fast read / write speeds and, in this embodiment, is used to store the acquired logic input and output data, providing data support for subsequent comparison and judgment. The logic input and output data acquisition is accomplished by reading the input data registers of the GPIO ports. After each acquisition, the acquired logic input and output data is converted into binary values, where 0 represents a low level and 1 represents a high level. These binary values ​​are then stored at the corresponding address in the temporary storage area.

[0033] Step 1.3. Level Comparison and Presence Judgment: Compare bit by bit the output level of the general logic input / output signal corresponding to each high-speed connector with the acquisition level of the general logic input / output signal. If the two levels are consistent, it is determined that the corresponding high-speed connector is connected to the loopback cable. If the two levels are inconsistent, it is determined that the corresponding high-speed connector is not connected to the loopback cable.

[0034] A loopback cable is a connection cable used to transmit signals back. In this embodiment, it is used to transmit the logic output general-purpose input / output (GPIO) signal of a high-speed connector back to the logic input GPIO signal port, thereby detecting the presence status of the loopback cable. The level comparison process is completed through logical operations. The binary value of the output level is XORed with the binary value of the acquired level. If the result is 0, it indicates that the two level states are the same; if the result is 1, it indicates that the two level states are not the same.

[0035] In some specific implementations, a signal filtering process is added to the detection of the loopback cable's presence status. The level status of the acquired logic input and general-purpose input / output signals is continuously acquired multiple times. The acquired level statuses are statistically processed, and the level status that appears most frequently is taken as the final acquisition result. At the same time, edge jitter filtering is applied to the acquired level statuses. Only when the level status remains stable within a preset time is the level status considered a valid acquisition result. This avoids misjudgment of the level status due to transient interference on the line and improves the accuracy of the loopback cable's presence status detection results.

[0036] In some embodiments, pulse signal detection can be used instead of fixed-level detection. By outputting a pulse signal with a specific frequency and duty cycle, the system detects whether the input port receives a pulse signal with the same frequency and duty cycle, thereby determining whether the loopback cable is in place. Pulse signal detection effectively avoids the problem of misjudgment caused by fixed-level signals due to external interference, improving the accuracy of the detection results.

[0037] Step 1.4. Description of Loopback Cable Structure and Characteristics: Loopback cables are manufactured using cables of the same model. All loopback cables have the same electrical parameters and physical structure. Loopback cables only contain conductors for signal connection and physical structures for fixed connection, and do not contain any active electronic components.

[0038] The loopback cable has physical interfaces at both ends that match the high-speed connector. These interfaces connect only to the corresponding logic output / general-purpose input / output (GPIO) pins and logic input / general-purpose input / output (GPIO) pins of the same high-speed connector, and not to any other pins of the high-speed connector. This design ensures that the loopback cable only performs signal return functionality and does not interfere with other signal transmissions of the high-speed connector. Furthermore, a standardized design simplifies material management and reduces material procurement and inventory costs. The loopback cable's conductors are made of copper, providing excellent conductivity, and the physical structure is encased in insulating material to prevent signal interference and short circuits.

[0039] Step 2. Determine the hardware configuration type: Step 2.1. Mapping table storage: A mapping table between the loopback cable in-situ status combination and the single-board hardware configuration type is pre-stored in the non-volatile storage area. The non-volatile storage area is a storage medium that can retain data after power failure. In this embodiment, it is used to store data that needs to be stored for a long time, such as the mapping table and preset configuration identifiers.

[0040] Each combination of loopback cable in-situ states in the mapping table corresponds to a unique board hardware configuration type. The mapping table is written during the board production phase and cannot be modified afterward. This design ensures the stability and consistency of the mapping table, preventing configuration identification errors due to accidental modifications. The mapping table is stored as a two-dimensional array. The first dimension stores the loopback cable in-situ state combinations, and the second dimension stores the corresponding board hardware configuration type. The array index corresponds to the binary value of the loopback cable in-situ state combination.

[0041] In some specific implementations, the non-volatile storage area is implemented using flash memory chips. The mapping table is stored in the address range of 0x00001000 to 0x00001FFF of the flash memory chip. This address range is locked during the production stage to prevent subsequent write and erase operations. The mapping table contains the correspondence between three sets of loopback cable presence status combinations and single-board hardware configuration types. The first set of loopback cable presence status combinations is a binary value of 00, corresponding to a single-board hardware configuration type of full high-speed resource allocation. The second set of loopback cable presence status combinations is a binary value of 01, corresponding to a single-board hardware configuration type of the first part of high-speed resource allocation. The third set of loopback cable presence status combinations is a binary value of 10, corresponding to a single-board hardware configuration type of the second part of high-speed resource allocation.

[0042] In some embodiments, the mapping table can be configured to be modifiable, allowing authorized personnel to update and modify it during single-board operation via a specific permission verification mechanism to accommodate subsequently added hardware configuration types. This design improves the flexibility and scalability of the method, meeting the needs of different application scenarios.

[0043] Step 2.2. State Combination Matching and Configuration Type Determination: Read the loopback cable in-situ status of all high-speed connectors from the temporary storage area, and combine them according to the preset arrangement order to form a loopback cable in-situ status combination. The preset arrangement order is used to ensure the uniqueness and consistency of the status combination and avoid different status combinations corresponding to the same hardware configuration due to different arrangement orders.

[0044] The combined loopback cable in-situ status combination is matched one by one with all entries in the mapping table to obtain the single-board hardware configuration type corresponding to the successfully matched entry. The status combination formation process is arranged according to the physical location order of the high-speed connectors. From left to right and from top to bottom, the in-situ status of each high-speed connector is converted into a binary value. Then, all binary values ​​are concatenated to form a complete binary number, which is used as the loopback cable in-situ status combination.

[0045] The matching process involves traversing all entries in the mapping table, comparing the current loopback cable status combination with the status combinations in the entries, and then reading the corresponding board hardware configuration type after finding a matching entry.

[0046] In some specific implementations, a fault-tolerant mechanism is incorporated into the matching process between the loopback cable presence status combination and the board hardware configuration type. A primary and backup copy of the mapping table are stored simultaneously in a non-volatile storage area. When an anomaly occurs during the reading or matching process of the primary copy, the system automatically switches to the backup copy to complete the matching operation. When the loopback cable presence status combination cannot match all entries in the mapping table, the default board hardware configuration type is automatically loaded, and relevant information about the matching anomaly is recorded. This provides data support for subsequent troubleshooting and prevents the board from failing to complete initialization and configuration adaptation due to matching anomalies.

[0047] Step 3. Write the configuration identifier: Step 3.1. Reading Preset Configuration Identifiers: Based on the determined single-board hardware configuration type, read the pre-stored preset configuration identifiers, which correspond one-to-one with the single-board hardware configuration type, from the non-volatile storage area. The preset configuration identifier is a digital code used to identify the single-board hardware configuration type; in this embodiment, it is used to implement software identification of the single-board hardware configuration type. The preset configuration identifiers are written during the single-board production stage and correspond one-to-one with the single-board hardware configuration types in the mapping table.

[0048] The default configuration identifier uses a fixed-length binary code, the length of which is determined by the number of hardware configuration types, ensuring that each hardware configuration type has a unique code. The reading process is completed by accessing the corresponding address in the non-volatile memory area, and the address corresponds to the number of the single-board hardware configuration type.

[0049] Step 3.2. Multiplexer Channel Switching: Generate the first control signal for the multiplexer and send the first control signal to the control port of the multiplexer. A multiplexer is an electronic device used to switch signal channels. It can select to connect different input channels and output channels according to the control signal. In this embodiment, it is used to switch the access subject of the field replaceable unit.

[0050] The internal channels of the multiplexer are switched according to the first control signal, disconnecting the communication channel between the board management controller and the field-replaceable unit, and establishing a communication channel between the complex programmable logic device (CPLD) and the field-replaceable unit. The CPLD is a programmable logic device that can implement various logic functions through programming. In this embodiment, it is used to implement functions such as loopback cable presence detection, configuration identifier writing, and multiplexer control. The field-replaceable unit is a storage device that stores board hardware information and can be read and written via a communication interface. In this embodiment, it is used to store the board's hardware configuration identifier. The internal channel switching of the multiplexer is achieved by changing the level state of the control port; different level states correspond to different channel connection methods.

[0051] Step 3.3. Configuration Identifier Writing and Verification: Through the established communication channel, the read preset configuration identifier is written to the designated storage area of ​​the field replaceable unit. After writing, the written content is verified bit by bit to confirm that the written content is consistent with the preset configuration identifier.

[0052] Bit-by-bit verification is a method used to verify the correctness of data writing. It compares the written data bit-by-bit with the original data to determine if any writing errors exist. The writing process follows the communication protocol requirements: first, a write command is sent, then the write address is sent, and finally the write data is sent. The verification process first reads the data from the designated storage area of ​​the field replaceable unit, then compares the read data bit-by-bit with the original preset configuration identifier. If all bits match, the write is successful; if any bits are inconsistent, the write has failed and needs to be re-entered.

[0053] In some specific implementations, an abnormal interruption recovery mechanism is incorporated into the configuration identifier writing process. Before the write operation begins, a status flag for the write operation is written to an independent storage area of ​​the field-replaceable unit. This status flag indicates the progress and completion status of the write operation. If an abnormal interruption occurs during the write process, the completion status can be determined by reading the status flag upon power-on. If the write operation is incomplete, the configuration identifier writing and verification operations are automatically re-executed to prevent incomplete configuration identifier writing due to abnormal interruption, thus ensuring the integrity and validity of the configuration identifier stored in the field-replaceable unit.

[0054] In some embodiments, cyclic redundancy check (CR) can be used instead of bit-by-bit verification. The CR value of the written data is calculated and compared with the CR value of the original data to determine if the data writing is correct. CR has the advantages of fast verification speed and strong error detection capability, effectively improving the efficiency and accuracy of data writing verification.

[0055] Step 3.4. Description of the designated storage area for the field-replaceable unit: The designated storage area for the field-replaceable unit is an independent storage area pre-divided within the field-replaceable unit. The address allocation for the designated storage area of ​​the field-replaceable unit is completed during the production stage of the field-replaceable unit, and the address allocation cannot be modified afterward.

[0056] The designated storage area is used solely for storing configuration identifiers corresponding to the hardware configuration type of the single board. It does not store any other information about the field-replaceable units. The length of the configuration identifier matches the capacity of the designated storage area. Each configuration identifier corresponds to a unique single-board hardware configuration type, and there are no duplicate configuration identifiers. This design ensures the security and stability of configuration identifier storage, preventing the configuration identifiers from being overwritten or damaged due to the writing of other data. The field-replaceable units are implemented using electrically erasable programmable read-only memory, which features fast read / write speeds and the ability to be erased and rewritten multiple times.

[0057] In some specific implementations, the designated storage area address range of the field-replaceable unit is 0x00000080 to 0x0000008F, with a total capacity of 16 bytes. The first 8 bytes are used to store the configuration identifier, and the last 8 bytes are reserved for future expansion. The configuration identifier uses 8 bytes of binary encoding, where the first 2 bytes identify the basic type of the board, the middle 4 bytes identify the hardware configuration type of the board, and the last 2 bytes store the checksum. The checksum is obtained by summing the first 6 bytes of the configuration identifier and is used to verify the integrity of the configuration identifier.

[0058] Step 3.5. Communication Channel Establishment Confirmation and Maintenance: After sending the first control signal to the multiplexer, a communication handshake signal is sent to the field-replaceable unit. A handshake response signal is received from the field-replaceable unit. Based on the handshake response signal, the successful establishment of the communication channel between the complex programmable logic device (CPLD) and the field-replaceable unit is confirmed. Communication handshake is a mechanism used to confirm whether two communicating parties are properly connected. By sending and receiving specific handshake signals, it is determined whether the communication channel has been properly established.

[0059] Before the configuration identifier writing operation and the written content verification operation are completed, the control port level of the multiplexer remains unchanged to maintain the communication channel connection between the complex programmable logic device and the field-replaceable unit, and switching of the multiplexer's internal channels is prohibited. This design ensures the continuity and integrity of the configuration identifier writing process and avoids interruption due to channel switching. The communication handshake signal uses a fixed-format data packet, including start bit, command bit, data bit, and stop bit. After receiving the handshake signal, the field-replaceable unit returns a response signal of the same format, indicating that the communication channel has been successfully established.

[0060] In some specific implementations, the communication handshake signal data packet is 8 bytes long, with a start bit of 1 byte (value 0xAA), a command bit of 1 byte (value 0x01), a data bit of 4 bytes (value 0x12345678), and a stop bit of 2 bytes (value 0x55AA). After receiving the handshake signal, the field-replaceable unit returns an acknowledgment signal within 10 milliseconds. The start, command, and stop bits of the acknowledgment signal are the same as the handshake signal, and the data bit is 0x87654321. If no acknowledgment signal is received within 50 milliseconds, the communication channel establishment is considered to have failed, and the handshake signal is retransmitted. If no acknowledgment signal is received after three consecutive retransmissions, a communication fault alarm is generated.

[0061] Step 4. Configure adaptation and alarm handling: Step 4.1. Multiplexer Channel Switching Again: After completing the writing and verification of the preset configuration identifier, a second control signal for the multiplexer is generated and sent to the control port of the multiplexer. The internal channels of the multiplexer are switched according to the second control signal. The level state of the second control signal is opposite to that of the first control signal, and it is used to switch the channel connection mode of the multiplexer, changing the access subject of the field-replaceable unit from the complex programmable logic device to the board management controller.

[0062] Step 4.2. Communication Channel Switching and Maintenance: Disconnect the communication channel between the complex programmable logic device and the field replaceable unit, establish a communication channel between the board management controller and the field replaceable unit, and maintain the connection status of the communication channel between the board management controller and the field replaceable unit until the board is powered off.

[0063] The baseboard management controller is a controller used to manage and monitor server hardware. It can perform functions such as hardware status monitoring, remote control, and fault alarms. In this embodiment, it is used to read the configuration identifier in the field replaceable unit and complete single-board configuration adaptation and cable alarm processing based on the configuration identifier. After the communication channel is established, the baseboard management controller can access the field replaceable unit at any time to read its hardware information and configuration identifier.

[0064] Step 4.3. Configuration Identifier Reading and Configuration Adaptation: Read the configuration identifier in the designated storage area of ​​the field replaceable unit through the established communication channel, load the corresponding board configuration parameters according to the read configuration identifier, and perform board hardware resource allocation operation and cable connection status alarm detection operation.

[0065] Single-board configuration parameters are a set of parameters used to configure the hardware resources and functions of a single-board unit, including hardware resource allocation parameters and cable connection detection parameters. Hardware resource allocation refers to the reasonable allocation of high-speed resources on the single-board unit according to its hardware configuration type, ensuring the normal operation of each hardware component. Cable connection status alarm detection refers to detecting the cable connection status according to the single-board unit's hardware configuration type; when the cable connection status does not meet the configuration requirements, corresponding alarm information is generated. The configuration identifier reading process follows the requirements of the communication protocol: first, a read command is sent, then the read address is sent, and finally, the read data is received.

[0066] In some embodiments, the alarm detection operation for cable connection status can adopt a hierarchical alarm approach, generating different levels of alarm information and taking different handling measures according to the severity of the cable connection error. For example, a prompt-level alarm is generated for cable connection errors that do not affect the basic operation of the system; a warning-level alarm is generated for cable connection errors that affect some functions of the system; and a severe alarm is generated for cable connection errors that cause the system to malfunction, and corresponding protective measures are taken.

[0067] Step 4.4. Explanation of the structure and working principle of the multiplexer: The multiplexer is a two-to-one analog switch device. The multiplexer includes two input channels, one output channel and one control port. The two input channels are respectively connected to the communication port of the complex programmable logic device and the communication port of the board management controller. The output channel is connected to the communication port of the field replaceable unit.

[0068] Based on the control signal received from the control port, one input channel is selected to connect to the output channel, enabling the switching of the access subject for the field-replaceable unit. Only one input channel can be connected to the output channel at a time. This design ensures that the field-replaceable unit is accessed by only one access subject at a time, avoiding data conflicts and write errors caused by multiple access subjects accessing it simultaneously. The multiplexer internally uses a MOSFET switching structure, controlling the conduction and cutoff of the MOSFET to achieve channel switching, featuring low on-resistance and fast switching speed.

[0069] In some specific implementations, a hardware interlock protection mechanism is incorporated into the channel switching process of the multiplexer. Hardware logic circuits interlock the conduction states of the two input channels of the multiplexer, ensuring that only one input channel and output channel can be active at a time. This prevents simultaneous conduction of two input channels due to abnormal control signals, which could lead to communication port conflicts and device damage. Furthermore, during channel switching, the currently active input channel is first disconnected, and after a preset time, the target input channel is then activated. This avoids momentary short circuits during channel switching, improving the stability and reliability of the multiplexer.

[0070] In some implementations, the control port locking of the multiplexer is achieved through hardware circuitry. After the communication channel between the baseboard management controller and the field-replaceable unit is successfully established, the baseboard management controller outputs a high-level signal to the locking circuit. The locking circuit clamps the control port level of the multiplexer to a fixed state, preventing any change in the channel connection mode of the multiplexer regardless of the control signal output by the complex programmable logic device. The locking circuit uses a clamping circuit composed of diodes and resistors, featuring simple structure and high reliability.

[0071] Step 4.5. Communication Channel Establishment Confirmation and Locking: After sending the second control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit. The handshake response signal returned by the field replaceable unit is received, and the successful establishment of the communication channel between the baseboard management controller and the field replaceable unit is confirmed based on the handshake response signal. After confirming the successful establishment of the communication channel, the control port level of the multiplexer is locked. For the remaining time of the board's current power-on operation, the control port level of the multiplexer remains unchanged, and it no longer responds to any multiplexer control signals from the complex programmable logic device (CPL). This design ensures that the baseboard management controller always has access to the field replaceable unit during board operation, preventing channel switching due to misoperation and affecting the normal operation of the system. Locking the multiplexer's control port is achieved by setting the corresponding register of the CPL. After setting the lock bit of the register to 1, the CPL will no longer output any control signals to the multiplexer's control port.

[0072] This embodiment achieves automatic adaptation of a single board to multiple hardware configurations through loopback cable presence detection and dynamic writing of configuration identifiers. This eliminates the need for separately designing and manufacturing different boards for different configurations, effectively reducing board production and maintenance costs. By switching access permissions for field-replaceable units using a multiplexer, the security and reliability of the configuration identifier writing process are ensured, avoiding data conflicts caused by multiple accessing entities simultaneously. A unified loopback cable design and standardized board design simplify hardware material management processes, reducing material procurement and inventory costs. Automatic configuration adaptation and cable alarm handling improve system deployment efficiency and operational stability, reducing the workload of manual configuration and troubleshooting. The technical solution adopted in this embodiment is highly feasible and practical, and can be widely applied to various board designs requiring multi-configuration adaptation.

[0073] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A same single board multi-configuration automatic monitoring and adaptation method, characterized in that, Includes the following steps: S1. After power-on, the level status of the logic output general input / output signal and logic input general input / output signal associated with each high-speed connector is detected to determine whether the loopback cable is in place. The loopback cable connects the logic output general input / output signal and logic input general input / output signal of the same high-speed connector. S2. Determine the hardware configuration type of the board based on the combination of the in-situ states of the loopback cables corresponding to different high-speed connectors; S3. Write the preset configuration identifier corresponding to the hardware configuration type of the single board into the designated storage area of ​​the field replaceable unit to complete the update of the configuration identifier in the field replaceable unit; S4. Switch the access permissions of the field replaceable unit through a multiplexer, establish a communication connection between the baseboard management controller and the field replaceable unit, read the configuration identifier in the field replaceable unit, and complete the single board configuration adaptation and cable alarm processing according to the configuration identifier.

2. The method of claim 1, wherein, Step S1 includes the following sub-steps: S1.

1. After power-on, initialize the working mode of all general-purpose input / output ports, set the push-pull output mode of the ports corresponding to the logic output general-purpose input / output signals, set the pull-up input mode of the ports corresponding to the logic input general-purpose input / output signals, and output fixed-level logic output general-purpose input / output signals to the signal ports corresponding to each high-speed connector according to the preset timing. S1.

2. After outputting the general logic input / output signal, wait for a preset level stabilization time, sequentially collect the level state of the general logic input / output signal corresponding to each high-speed connector, and store the collected level state in the temporary storage area. S1.

3. Compare bit by bit the output level of the logic output general input / output signal and the acquisition level of the logic input general input / output signal corresponding to each high-speed connector. If the two levels are consistent, it is determined that the corresponding high-speed connector is connected to the loopback cable. If the two levels are inconsistent, it is determined that the corresponding high-speed connector is not connected to the loopback cable.

3. The method of claim 1, wherein, Step S2 includes the following sub-steps: S2.

1. A mapping table between loopback cable in-situ state combinations and board hardware configuration types is pre-stored in a non-volatile storage area. Each loopback cable in-situ state combination in the mapping table corresponds to a unique board hardware configuration type. The mapping table is written during the board production stage and cannot be modified after being written. S2.

2. Read the loopback cable presence status of all high-speed connectors from the temporary storage area, combine them into loopback cable presence status combinations according to the preset arrangement order, match the combined loopback cable presence status combinations with all entries in the mapping table one by one, and obtain the single-board hardware configuration type corresponding to the successfully matched entries.

4. The method of claim 1, wherein, Step S3 includes the following sub-steps: S3.

1. Based on the determined single-board hardware configuration type, read the pre-stored preset configuration identifiers that correspond one-to-one with the single-board hardware configuration type from the non-volatile storage area. The preset configuration identifiers are written during the single-board production stage and correspond one-to-one with the single-board hardware configuration types in the mapping table. S3.

2. Generate a first control signal for the multiplexer, send the first control signal to the control port of the multiplexer, switch the internal channel of the multiplexer according to the first control signal, disconnect the communication channel between the substrate management controller and the field replaceable unit, and establish a communication channel between the complex programmable logic device and the field replaceable unit. S3.

3. Through the established communication channel, the read preset configuration identifier is written into the designated storage area of ​​the field replaceable unit. After writing is completed, the written content is verified bit by bit to confirm that the written content is consistent with the preset configuration identifier.

5. The method of claim 1, wherein, Step S4 includes the following sub-steps: S4.

1. After completing the writing and verification of the preset configuration identifier, generate the second control signal of the multiplexer, send the second control signal to the control port of the multiplexer, and switch the internal channel of the multiplexer according to the second control signal; S4.

2. Disconnect the communication channel between the complex programmable logic device and the field replaceable unit, establish a communication channel between the baseboard management controller and the field replaceable unit, and maintain the connection status of the communication channel between the baseboard management controller and the field replaceable unit until the board is powered off; S4.

3. Read the configuration identifier in the designated storage area of ​​the field replaceable unit through the established communication channel, load the corresponding board configuration parameters according to the read configuration identifier, and perform board hardware resource allocation operation and cable connection status alarm detection operation.

6. The method of claim 1, wherein, In step S1, the loopback cable is manufactured using a uniform cable model. All loopback cables have the same electrical parameters and physical structure. The loopback cable only contains conductors for signal connection and physical structures for fixed connection, and does not contain any active electronic components. Both ends of the loopback cable are provided with physical interfaces that match the high-speed connector. The physical interfaces are only connected to the logic output general-purpose input / output signal pins and logic input general-purpose input / output signal pins corresponding to the same high-speed connector, and are not connected to any other pins of the high-speed connector.

7. The method of claim 1, wherein, In step S3, the designated storage area of ​​the field-replaceable unit is an independent storage area pre-divided within the field-replaceable unit. The address allocation of the designated storage area of ​​the field-replaceable unit is completed during the production stage of the field-replaceable unit, and the address allocation cannot be modified afterward. The designated storage area is only used to store the configuration identifier corresponding to the hardware configuration type of the board, and does not store any other information of the field-replaceable unit. The length of the configuration identifier matches the capacity of the designated storage area. Each configuration identifier corresponds to a unique board hardware configuration type, and there are no duplicate configuration identifiers.

8. The method of claim 4, wherein, In step S3.2, after sending the first control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit, and a handshake response signal is received from the field replaceable unit. Based on the handshake response signal, it is confirmed that the communication channel between the complex programmable logic device and the field replaceable unit has been successfully established. Before the configuration identifier writing operation and the write content verification operation are completed, the control port level of the multiplexer remains unchanged, the communication channel connection between the complex programmable logic device and the field replaceable unit is maintained, and switching of the internal channel of the multiplexer is prohibited.

9. The method of claim 1, wherein, In step S4, the multiplexer is a two-to-one analog switch device. The multiplexer includes two input channels, one output channel, and a control port. The two input channels are respectively connected to the communication port of the complex programmable logic device and the communication port of the board management controller. The output channel is connected to the communication port of the field replaceable unit. According to the control signal received by the control port, one of the input channels is selected to be connected to the output channel to realize the switching of the field replaceable unit access subject. Only one input channel can be connected to the output channel at the same time.

10. The method of claim 5, wherein, In step S4.1, after sending the second control signal to the multiplexer, a communication handshake signal is sent to the field replaceable unit, and a handshake response signal is received from the field replaceable unit. Based on the handshake response signal, it is confirmed that the communication channel between the board management controller and the field replaceable unit has been successfully established. After confirming that the communication channel has been successfully established, the control port level of the multiplexer is locked. During the remaining time of the board's current power-on operation, the control port level of the multiplexer remains unchanged, and it no longer responds to any multiplexer control signals from the complex programmable logic device.

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