Heterogeneous processor cooperative pipeline scheduling method and system for atom-level computing

Abstract

This application discloses a heterogeneous processor cooperative pipeline scheduling method and system for atomic-level computing. The method includes: preprocessing the current atomic-level computing task by the main processor to obtain a data packet to be computed; sending the data packet to be computed to the coprocessor and simultaneously receiving the previous atomic-level computing result returned by the coprocessor; computing the data packet to be computed by the coprocessor to obtain the current atomic-level computing result, and then sending the current atomic-level computing result back to the main processor; and preprocessing the next atomic-level computing task by the main processor. The preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor. This application balances the flexibility of the main processor and the efficiency of the coprocessor, improving the overall performance of atomic-level computing, maximizing the computational efficiency of heterogeneous processors, and can be widely applied in the field of atomic-level computing technology.

Description

Technical Field

[0001] This application relates to the field of atomic-level computing technology, and in particular to a heterogeneous processor cooperative pipeline scheduling method and system for atomic-level computing. Background Technology

[0002] Atomic-level computing (such as molecular dynamics simulations and density functional theory calculations) is a key research tool in fields such as materials science, biomedicine, and new energy. These calculations are characterized by high computational intensity, large data throughput, and complex algorithm structures. Traditionally, atomic-level computing relies on general-purpose processors (such as CPUs and GPUs). However, general-purpose processors employ the von Neumann architecture, which separates storage from computation, resulting in enormous data transfer overhead and limiting computational efficiency and scalability.

[0003] In the few attempts at heterogeneous collaboration, simple task-level parallelism is typically employed, where the main processor distributes the entire computational task to the coprocessor and waits for the coprocessor to complete before proceeding to the next step. This serial execution mode results in the main processor being idle and waiting during the coprocessor's computation, and communication overhead is exposed on the critical path, failing to fully utilize the parallel potential of heterogeneous processors. Summary of the Invention

[0004] The main objective of this application is to propose a heterogeneous processor collaborative pipeline scheduling method and system for atomic-level computing, which can maximize the computing efficiency of heterogeneous processors.

[0005] To achieve the above objectives, one aspect of this application proposes a heterogeneous processor cooperative pipeline scheduling method for atomic-level computing, applied to heterogeneous processors, wherein the heterogeneous processors include a main processor and a coprocessor, and the method includes the following steps: The main processor preprocesses the current atomic-level computation task to obtain the data packet to be computed; The data packet to be computed is sent to the coprocessor, and the previous atomic-level computation result is received from the coprocessor. The coprocessor performs calculations on the data packet to be calculated to obtain the current atomic-level calculation result, and then sends the current atomic-level calculation result back to the main processor, which then preprocesses the next atomic-level calculation task. The preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

[0006] In some embodiments, the preprocessing of the current atomic-level computation task to obtain the data packet to be computed specifically includes: Based on the current atomic-level computation task, read the corresponding atomic coordinates, atomic type, and at least one additional attribute parameter determined according to the computation type of the current atomic-level computation task from memory; According to the interface protocol of the coprocessor, the current atomic-level computation task, the atomic coordinates, the atomic type, and the additional attribute parameters are packaged to obtain the data package to be computed.

[0007] In some embodiments, sending the data packet to be computed to the coprocessor specifically includes: When there is only one coprocessor, the data packet to be computed is sent to the coprocessor based on the direct distribution strategy; When there are multiple coprocessors, the data packets to be computed are sent to the corresponding coprocessors according to a preset distribution order based on a round-robin scheduling strategy.

[0008] In some embodiments, the method further includes: During the computation of the current atomic-level computation task performed by the coprocessor, the main processor performs state update and / or feedback control processing based on the returned results of the previous atomic-level computation.

[0009] In some embodiments, the method further includes: The single-atom preprocessing time of the main processor, the single-atom computation time of the coprocessor, and the single-atom bidirectional communication time between the main processor and the coprocessor are obtained. When the number of coprocessors is one, a first optimization target is determined based on the single-atom preprocessing time, the single-atom computation time, and the single-atom bidirectional communication time, so that the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor. When there are multiple coprocessors, a second optimization objective is determined based on the single-atom preprocessing time, the single-atom computation time, and the single-atom bidirectional communication time, so that the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

[0010] In some embodiments, the first optimization objective is: The single-atom preprocessing time is less than or equal to the single-atom computation time, and the single-atom bidirectional communication time is less than or equal to the single-atom computation time.

[0011] In some embodiments, the second optimization objective is: The product of the number of coprocessors multiplied by the single-atom preprocessing time is less than or equal to the single-atom computation time, and the product of the number of coprocessors multiplied by the single-atom bidirectional communication time is less than or equal to the single-atom computation time.

[0012] To achieve the above objectives, another aspect of this application proposes a heterogeneous processor cooperative pipeline scheduling system for atomic-level computing, the system comprising: The first task processing module is used to preprocess the current atomic-level computing task through the main processor to obtain the data packet to be computed; The task transmission module is used to send the data packet to be calculated to the coprocessor and receive the previous atomic-level calculation result returned by the coprocessor. The second task processing module is used to perform calculations on the data packet to be calculated through the coprocessor to obtain the current atomic-level calculation result, and then send the current atomic-level calculation result back to the main processor. The first task processing module is further configured to preprocess the next atomic-level computation task through the main processor during the computation of the second task processing module, and the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

[0013] To achieve the above objectives, another aspect of the embodiments of this application proposes an electronic device, which includes a memory, a main processor, and at least one coprocessor. The memory stores a computer program, and when the main processor executes the computer program, it controls the coprocessor to collaboratively implement the method described above.

[0014] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer program product, including a computer program that, when executed by a main processor, controls at least one coprocessor to collaboratively implement the aforementioned method.

[0015] The embodiments of this application include at least the following beneficial effects: The heterogeneous processor cooperative pipeline scheduling method and system for atomic-level computing of this application are applied to heterogeneous processors, which include a main processor and a coprocessor. By combining the main processor and the coprocessor, the flexibility of the main processor and the efficiency of the coprocessor can be balanced, thereby improving the overall performance of atomic-level computing. Based on a three-stage pipeline design, the main processor performs data preprocessing for the current atomic-level computing task, sends the preprocessed current data to the coprocessor, and simultaneously receives the result of the previous atomic-level computing. Then, the coprocessor executes the current atomic-level computing process, and the main processor executes the next atomic-level preprocessing process. The preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor. This application ensures that the computational overhead of the main processor and the communication overhead between the main and coprocessors are completely covered by the computation time of the coprocessor, thereby maximizing the computational efficiency of heterogeneous processors for atomic-level computing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the architecture of a heterogeneous processor provided in one embodiment of this application; Figure 2 A flowchart illustrating the steps of a heterogeneous processor cooperative pipeline scheduling method for atomic-level computing provided in one embodiment of this application; Figure 3 This is a single pipeline scheduling timing diagram provided in one embodiment of the present application; Figure 4 This is a schematic diagram of multi-pipeline polling scheduling provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of a heterogeneous processor cooperative pipeline scheduling system for atomic-level computing provided in one embodiment of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] Atomic-level computing (such as molecular dynamics simulations and density functional theory calculations) is a key research tool in materials science, biomedicine, and new energy fields. These calculations are characterized by high computational intensity, large data throughput, and complex algorithm structures. Traditionally, atomic-level computing relies on general-purpose processors (such as CPUs and GPUs). However, general-purpose processors employ the von Neumann architecture, separating storage and computation, resulting in enormous data transfer overhead and creating "memory walls" and "power walls" that limit computational efficiency and scalability. To overcome this bottleneck, the use of application-specific integrated circuit (ASIC) chips with non-von Neumann architectures has become an important direction. ASIC chips are hardware-optimized for specific computational tasks (such as potential energy surface solving and Hamiltonian matrix solving), achieving extremely high computational efficiency and energy efficiency. However, ASIC chips have poor flexibility and are difficult to adapt to the diverse post-processing and ensemble control requirements of atomic-level computing.

[0021] In summary, existing atomic-level computing acceleration solutions mainly fall into two categories: pure general-purpose processor solutions and pure application-specific chip solutions. Pure general-purpose processor solutions, such as CPU / GPU clusters, offer flexible programming but suffer from low computational efficiency and high power consumption, making them unsuitable for large-scale, long-term simulations. Pure application-specific chip solutions, such as ASIC accelerators for specific potential functions, offer fast computation speeds but cannot flexibly handle user-defined post-processing, ensemble control, and other tasks, and are difficult to adapt to algorithm updates.

[0022] In the few attempts at heterogeneous collaboration, simple task-level parallelism is typically employed, where the main processor distributes the entire computational task to the coprocessor and waits for the coprocessor to complete before proceeding to the next step. This serial execution mode results in the main processor being idle and waiting during the coprocessor's computation, and communication overhead is exposed on the critical path, failing to fully realize the parallel potential of heterogeneous systems.

[0023] In view of this, this application proposes a heterogeneous processor cooperative pipeline scheduling method for atomic-level computing, applied to heterogeneous processors including a main processor and coprocessors. By combining the main processor and coprocessors, the flexibility of the main processor and the efficiency of the coprocessors can be balanced, improving the overall performance of atomic-level computing. Based on a three-stage pipeline design, the main processor performs data preprocessing for the current atomic-level computing task, sending the preprocessed data to the coprocessors while simultaneously receiving the results of the previous atomic-level computation. The coprocessors then execute the current atomic-level computation process, and the main processor executes the next atomic-level preprocessing process. The preprocessing time of the main processor and the communication time between the main processor and coprocessors overlap with the computation time window of the coprocessors. This application ensures that the computational overhead of the main processor and the communication overhead between the main and coprocessors are completely covered by the computation time of the coprocessors, maximizing the computational efficiency of heterogeneous processors for atomic-level computing.

[0024] like Figure 1 This is a schematic diagram of the architecture of a heterogeneous processor provided in one embodiment of this application. The heterogeneous processor cooperative pipeline scheduling method for atomic-level computing in this embodiment is applied to a heterogeneous parallel system (i.e., a heterogeneous processor), which includes M main processors (MPUs). m (m=1,2,…,M) and S coprocessors (SPUs) s (s=1,2,…,S). In some embodiments, the main processor (MPU) employs a general-purpose processor (such as a CPU) based on a von Neumann architecture to handle tasks requiring high flexibility in atomic-level computations, such as particle position updates, ensemble control, and data post-processing. The coprocessor (SPU) employs a dedicated computing chip based on a non-von Neumann architecture to accelerate the most computationally intensive and time-consuming core tasks, such as potential energy surface inference in molecular dynamics and Hamiltonian solving in density functional theory. The main processor (MPU) and the coprocessor (SPU) are connected via a high-speed communication interface (such as PCIe), and the main processor (MPU) can schedule multiple coprocessor (SPU) through polling or other methods.

[0025] Reference Figure 2 , Figure 2 This is a flowchart illustrating the steps of a heterogeneous processor cooperative pipeline scheduling method for atomic-level computing provided in one embodiment of this application. This application proposes a heterogeneous processor cooperative pipeline scheduling method for atomic-level computing, which may include, but is not limited to, the following steps S101 to S103: Step S101: The main processor preprocesses the current atomic-level computation task to obtain the data packet to be computed; Step S102: Send the data packet to be calculated to the coprocessor, and at the same time receive the previous atomic-level calculation result returned by the coprocessor; Step S103: The coprocessor performs calculations on the data packet to be calculated to obtain the current atomic-level calculation result, and then sends the current atomic-level calculation result back to the main processor, which then preprocesses the next atomic-level calculation task. The preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

[0026] It should be noted that this application embodiment divides atomic-level computing tasks into two categories: flexible tasks and core computing tasks. Flexible tasks are executed by the main processor (MPU), such as particle position updates, ensemble control, and data post-processing; core computing tasks are executed by the coprocessor (SPU), such as computationally intensive parts like potential energy surface inference and Hamiltonian solving, thus balancing the flexibility of the main processor and the efficiency of the coprocessor, improving the overall performance of atomic-level computing. For the collaborative scheduling between the main processor (MPU) and the coprocessor (SPU), this application embodiment adopts a three-stage pipeline design, ensuring that the preprocessing overhead of the main processor (MPU) and the communication overhead between the main processor (MPU) and the coprocessor (SPU) are completely covered by the computation time of the coprocessor (SPU), thereby maximizing the computational efficiency of heterogeneous processors. Furthermore, the pipeline design hides communication latency, eliminating the impact of the slower main processor (MPU) speed on overall performance.

[0027] Specifically, the three-stage pipeline scheduling design includes MPU preprocessing, MPU-SPU communication, and SPU computation: Stage A (MPU Preprocessing): The main processor (MPU) performs data preprocessing for the current atomic-level computation task and encodes and packages the data according to the format required by the coprocessor (SPU) to form a data packet to be computed; Stage B (MPU-SPU communication): The main processor MPU sends the packaged data packet to be computed to the coprocessor SPU through a high-speed interface, while simultaneously receiving the computation results of the previous atomic-level computation task. StageC (SPU Calculation): After receiving the packaged data packet to be calculated, the coprocessor SPU performs core calculations and outputs the current atomic-level calculation results such as atomic energy, force, and virial.

[0028] In terms of time, consecutive tasks are numbered as Task. i-1 Task i Task i+1 ...Task i+n When the coprocessor SPU is executing a task iDuring computation (Stage C), the main processor MPU executes tasks simultaneously. i+1 Data preprocessing (Stage A) is underway, while the communication interface is performing a Task. i-1 Result return and Task i+1 Data transmission (Stage B); by adjusting task granularity, optimizing hardware performance and / or optimizing system parameters, Stage A, Stage B and Stage C are made to completely overlap in time, so that the total system time is determined only by the efficient coprocessor SPU, thereby maximizing the computing efficiency of heterogeneous processors and keeping the coprocessor SPU at full load at all times.

[0029] As an optional implementation, the step of preprocessing the current atomic-level computation task to obtain the data packet to be computed can be further divided into the following steps S1011 to S1012: Step S1011: Based on the current atomic-level computation task, read the corresponding atomic coordinates, atomic type, and at least one additional attribute parameter determined according to the computation type of the current atomic-level computation task from memory. Specifically, after the main processor (MPU) acquires the current atomic-level computation task, it parses the task to determine the range of atoms to be processed. First, based on the current simulation time step and task queue status, it determines the atomic batch number corresponding to this atomic-level computation task and the number of atoms contained in that batch. Then, based on the atomic batch number, it calculates the starting and ending index positions of the atoms in that batch in the global atomic array. Subsequently, the main processor (MPU) locates the memory storage address of the atomic basic attribute data according to the calculated index range. The atomic basic attribute data includes the three-dimensional spatial coordinates (i.e., atomic coordinates) of each atom at the current moment and the atom type identifier; the additional attribute parameters are extra physical quantities or state parameters related to each atom read from the corresponding location in memory according to the computation type of the current atomic-level computation task (molecular dynamics simulation, density functional theory, etc.).

[0030] Step S1012: According to the interface protocol of the coprocessor, the current atomic-level calculation task, atomic coordinates, atomic type and additional attribute parameters are packaged to obtain the data package to be calculated.

[0031] Specifically, after determining the addresses of the atomic basic attribute data and the nearest neighbor list in memory, the above data is read from the main memory into its internal cache or temporary register. Then, according to the interface protocol corresponding to the coprocessor SPU, the read data is organized into a data packet to be computed, which includes a data packet header and a data packet payload. The data packet header contains the task type and time step, and the data packet payload contains the coordinates, type, and additional attribute parameters of the atoms in this batch.

[0032] As an optional implementation, the step of sending the data packet to be computed to the coprocessor can be further divided into the following steps S1021 to S1022: Step S1021: When there is only one coprocessor, the data packet to be computed is sent to the coprocessor based on the direct distribution strategy; Step S1022: When there are multiple coprocessors, based on the round-robin scheduling strategy, the data packets to be computed are sent to the corresponding coprocessors according to the preset distribution order.

[0033] Specifically, the main processor (MPU) sends the data packets to be computed to the designated coprocessor (SPU) via a high-speed interface. For a single-SPU system, point-to-point sequential transmission is used; for a multi-SPU system, a round-robin method is used to distribute tasks, ensuring balanced load across all coprocessors (SPUs).

[0034] In some optional embodiments, when a main processor (MPU) and a coprocessor (SPU) (S=1) work together in the system, a direct distribution strategy is adopted, and the data to be computed is directly sent to the coprocessor (SPU). The corresponding single pipeline scheduling timing is as follows: Figure 3 As shown. When a main processor (MPU) and multiple coprocessors (SPUs) (S>1) work together in the system, a round-robin scheduling strategy is adopted to distribute tasks in a cyclical manner according to a preset distribution order. Each coprocessor (SPU) runs its internal pipeline independently, forming a multi-pipeline parallelism.

[0035] For example, such as Figure 4 The diagram illustrates a multi-pipeline polling scheduling method, using one main processor (MPU) and four coprocessors (SPUs) as an example. The MPU maintains a task queue and distributes tasks to the coprocessors in a preset order (e.g., SPU1→SPU2→SPU3→SPU4→SPU1…). Each coprocessor (SPU) independently maintains its internal single pipeline (e.g., ...). Figure 3 (As shown).

[0036] After receiving the data packet to be computed, the SPU parses the data packet and then, based on the obtained atomic data, initiates internal computing units to perform core calculations (such as neural network potential inference and Hamiltonian matrix solving). Once the calculations for all atoms in the batch are completed, the SPU summarizes and packages the calculation results to form the current atomic-level calculation result (such as atomic energy, forces, etc.) and sends this current atomic-level calculation result back to the MPU.

[0037] As an optional implementation, the heterogeneous processor cooperative pipeline scheduling method for atomic-level computing may further include the following step S104: Step S104: During the computation of the current atomic-level computation task performed by the coprocessor, the main processor performs state update and / or feedback control processing based on the returned results of the previous atomic-level computation.

[0038] Specifically, during the computation of the current atomic-level computation task performed by the coprocessor, the main processor (MPU) performs operations such as particle position updates, ensemble control, and / or data post-processing based on the previous atomic-level computation results returned by the coprocessor (SPU).

[0039] It is understandable that the process of the main processor MPU performing data preprocessing, encoding, packaging, and sending the data packets to be computed is concurrent with the process of the coprocessor SPU executing the core computing tasks. That is, while the coprocessor SPU is computing the Kth batch of atomic tasks, the main processor MPU may be performing at least one of the following operations: updating the state of the computation results of the (K-1)th batch of atoms, preprocessing and encoding the data of the K+1th batch of atomic tasks, or distributing the data packets to be computed for the K+1th batch of atomic tasks to the coprocessor SPU.

[0040] As an optional implementation, the heterogeneous processor cooperative pipeline scheduling method for atomic-level computing may further include the following steps S105 to S107: Step S105: Obtain the single-atom preprocessing time of the main processor, the single-atom computation time of the coprocessor, and the single-atom bidirectional communication time between the main processor and the coprocessor; Step S106: When there is only one coprocessor, determine the first optimization objective based on the single-atom preprocessing time, single-atom computation time, and single-atom bidirectional communication time, so that the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor. Step S107: When there are multiple coprocessors, determine the second optimization objective based on the single-atom preprocessing time, single-atom computation time, and single-atom bidirectional communication time, so that the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

[0041] As a further optional implementation method, the first optimization objective is: The single-atom preprocessing time is less than or equal to the single-atom computation time, and the single-atom bidirectional communication time is less than or equal to the single-atom computation time.

[0042] Specifically, when a main processor (MPU) and a coprocessor (SPU) (S=1) work together in the system, their single pipeline scheduling timing is as follows: Figure 3 As shown, Figure 3The graph, with time as the horizontal axis, illustrates the pipeline overlap of three consecutive tasks across the MPU preprocessing, MPU-SPU communication, and SPU computation stages. Figure 3 It is evident that the coprocessor SPU is always busy, with the main processor MPU and communication interface working in parallel with the coprocessor SPU.

[0043] Let t be the data preprocessing time of the main processor (MPU) for executing a single atomic task. MPU The bidirectional communication time between the main processor (MPU) and the coprocessor (SPU) is t. comm The computation time for a single atomic task executed by the coprocessor SPU is t. SPU To ensure the production line operates at full capacity, the first optimization objective that needs to be satisfied is: t MPU ≤t SPU , and t comm ≤t SPU At this point, the throughput of the entire production line changes from t SPU The decision was made to completely hide the computational and communication overhead of the main processor MPU.

[0044] In some alternative embodiments, this first optimization objective can be achieved by adjusting the task granularity or optimizing hardware performance. First, the three variables of the three-stage pipeline are modeled as follows regarding task granularity: Linear functions: ; ; ; in, This represents the average time taken by the main processor (MPU) to preprocess an atomic task. This indicates other overhead of the main processor MPU (such as system interrupt response and function calls). Indicates the reciprocal of the bus bandwidth. Indicates the DMA descriptor configuration latency. This represents the average time taken by the coprocessor SPU to compute an atomic task. This represents the instruction startup overhead of the coprocessor SPU, i.e., pipeline drain time.

[0045] To ensure that the preprocessing and communication time of the main processor overlaps with the computation time window of the coprocessor, the following conditions must be met: ; Substitute the previously constructed linear function into the above equation and perform rearrangement to solve the task at a granular level. Then we can get: ; Because the coprocessor in this embodiment uses a dedicated computing chip based on a non-Von Neumann architecture, its pipeline drain delay is... Typically at the nanosecond level, accurate measurement is extremely difficult and unstable. Therefore, the granularity of the solution task... When Negligible, although the final task granularity is... It will be on the larger side, but it can provide a more granular approach to tasks. Leave a safety margin. This means ultimately adjusting the task granularity using the following formula. The time for MPU preprocessing, MPU-SPU communication, and SPU computation is linearly scaled: .

[0046] Furthermore, if the task granularity of the calculation... Larger than the processor's maximum acceptable task granularity This allows for optimization of the processor's hardware parameters, such as configuring the hardware interrupt controller, shared memory, and compressed data representation.

[0047] As an optional implementation method, the second optimization objective is: The product of the number of coprocessors multiplied by the single-atom preprocessing time is less than or equal to the single-atom computation time, and the product of the number of coprocessors multiplied by the single-atom bidirectional communication time is less than or equal to the single-atom computation time.

[0048] Specifically, when a main processor (MPU) works collaboratively with multiple coprocessor processors (S>1) in a system, the main processor MPU needs to handle communication and preprocessing tasks with all coprocessor processors simultaneously due to the parallel operation of the multiple coprocessor processors. In this case, the second optimization objective that the main processor MPU's computing power and communication bandwidth must satisfy is: The main processor (MPU) needs to have the data preprocessing capability to simultaneously supply all coprocessor (SPU) units, i.e., S×t MPU ≤t SPU It should be noted that the t here... MPU This refers to the preprocessing time of a single atomic-level task. In practice, it's necessary to consider that the main processor MPU can process multiple tasks in parallel, but typically the main processor MPU operates serially, therefore the main processor MPU's processing speed needs to be fast enough. The communication bandwidth needs to be able to support data exchange with all coprocessor SPUs simultaneously, i.e., S×t. comm ≤t SPU Here it is assumed that communication can be parallel or time-division multiplexed.

[0049] In some alternative embodiments, this second optimization objective can be achieved by adjusting the task granularity, appropriately selecting M and S (e.g., M=1, S=4), and optimizing hardware performance, thereby enabling all coprocessor SPUs to operate at full load and improving the overall system efficiency. The task granularity... Adjust and optimize according to the following formula: .

[0050] It is understandable that the above-described heterogeneous processor collaborative pipeline scheduling method for atomic-level computing is applicable not only to one MPU corresponding to one or more SPUs, but also to complex topologies where multiple MPUs correspond to one or more SPUs, and corresponding load balancing strategies can be designed.

[0051] In summary, the processing flow of the heterogeneous processor cooperative pipeline scheduling method for atomic-level computing in this application embodiment is as follows: S1. Task Division: Atomic-level computing tasks are divided into two categories: flexible tasks and core computing tasks. Flexible tasks are executed by the MPU, such as particle position updates, ensemble control, and data post-processing; core computing tasks are executed by the SPU, such as computationally intensive parts like potential energy surface inference and Hamiltonian solving.

[0052] S2. Data Preprocessing and Packaging: Based on the atomic-level computation task, the MPU reads the required data (such as atomic coordinates, types, and additional attribute parameters) from memory, encodes and packages it according to the SPU's interface protocol, and forms a data packet to be computed.

[0053] S3. Task Distribution and Communication: The MPU sends the data packets to be computed to the designated SPU via a high-speed interface. For a single-SPU system, point-to-point sequential transmission is used; for a multi-SPU system, a round-robin scheduling method is used to distribute tasks, ensuring load balancing across all SPUs.

[0054] S4, SPU Core Calculation: After receiving the data packet to be calculated, the SPU starts the internal computing unit to perform core calculations (such as neural network potential inference) and obtains atomic-level calculation results (atomic energy, force, etc.).

[0055] S5. Result Feedback and Reception: After the SPU completes the calculation, it sends the atomic-level calculation result back to the MPU through a high-speed interface. The MPU sends new atomic-level tasks while simultaneously receiving the results of completed tasks.

[0056] S6. Overlapping Pipeline Execution: Through the parallel design of steps S2-S5, the MPU's preprocessing (S2), communication (S3+S5), and SPU's computation (S4) overlap in time, forming a pipeline. For a single SPU system, by adjusting the task granularity and optimizing hardware performance, t MPU≤t SPU And t comm ≤t SPU This hides the preprocessing and communication overhead of the MPU, allowing the SPU to run at full capacity. For multi-SPU systems, system parameter optimization, task granularity adjustment, and hardware performance optimization enable S×t... MPU ≤t SPU And S×t comm ≤t SPU This will improve the overall throughput.

[0057] S7. Iteration: Repeat steps S2 to S6 until all atomic-level computational tasks are completed.

[0058] The above describes the heterogeneous processor cooperative pipeline scheduling method for atomic-level computing according to embodiments of this application. It can be recognized that, compared with existing atomic-level computing acceleration schemes, the embodiments of this application have the following advantages: First, atomic-level computing tasks are divided into flexible tasks and core computing tasks. Flexible tasks are executed by the main processor (MPU), while core computing tasks are executed by the coprocessor (SPU). This approach can balance the flexibility of the main processor with the efficiency of the coprocessor, thereby improving the overall performance of atomic-level computing.

[0059] Second, the three-stage pipeline design ensures that the computational overhead of the main processor MPU and the communication overhead between the main-coprocessor MPU and the SPU are completely covered by the computation time of the coprocessor SPU. This maximizes the computational efficiency of heterogeneous processors and hides communication latency through pipeline design, eliminating the impact of the slow speed of the main processor MPU on overall performance.

[0060] Third, for cases with multiple coprocessors (SPUs), a multi-pipeline architecture is implemented through polling scheduling to improve overall computing efficiency.

[0061] Reference Figure 5 This application also provides a heterogeneous processor cooperative pipeline scheduling system for atomic-level computing, the system comprising: The first task processing module is used to preprocess the current atomic-level computing task through the main processor to obtain the data packet to be computed; The task transmission module is used to send the data packet to be computed to the coprocessor and receive the previous atomic-level computation result returned by the coprocessor. The second task processing module is used to perform calculations on the data packet to be calculated through the coprocessor, obtain the current atomic-level calculation result, and then send the current atomic-level calculation result back to the main processor. The first task processing module is also used to preprocess the next atomic-level computation task through the main processor during the computation of the second task processing module, and the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

[0062] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0063] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0064] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0065] Please see Figure 6 , Figure 6 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The main processor 1001 can be implemented using general-purpose computing units such as a general-purpose central processing unit (CPU) or a microprocessor. It is used to execute computer programs and implement the steps executed by the main processor in the embodiments of this application, including data preprocessing, task scheduling, status updating and feedback control.

[0066] The coprocessor 1002 can be implemented using a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other hardware accelerators. It is used to execute dedicated computing tasks performed by the coprocessor in the embodiments of this application, including performing core calculations on the data packets to be calculated and returning the calculation results. The memory 1003 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1003 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1003 and is called and executed by the main processor 1001 using the methods described in the embodiments of this application. Input / output interface 1004 is used to implement information input and output; The communication interface 1005 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 1006 transmits information between various components of the device (e.g., main processor 1001, coprocessor 1002, memory 1003, input / output interface 1004, and communication interface 1005); The main processor 1001, coprocessor 1002, memory 1003, input / output interface 1004, and communication interface 1005 are connected to each other within the device via bus 1006.

[0067] This application also provides a computer-readable storage medium storing a computer program that, when executed by a main processor, controls the main processor and a coprocessor to collaboratively implement the above-described method.

[0068] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0069] This application also provides a computer program product, including a computer program that, when executed by a main processor, controls at least one coprocessor to collaboratively implement the above-described method.

[0070] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0071] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0072] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0073] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0074] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0075] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0076] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0077] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0078] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0079] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0080] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0082] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A heterogeneous processor cooperative pipeline scheduling method for atomic-level computing, characterized in that, Applied to heterogeneous processors, wherein the heterogeneous processor includes a main processor and a coprocessor, the method includes the following steps: The main processor preprocesses the current atomic-level computation task to obtain the data packet to be computed; The data packet to be computed is sent to the coprocessor, and the previous atomic-level computation result is received from the coprocessor. The coprocessor performs calculations on the data packet to be calculated to obtain the current atomic-level calculation result, and then sends the current atomic-level calculation result back to the main processor, which then preprocesses the next atomic-level calculation task. The preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

2. The method according to claim 1, characterized in that, The preprocessing of the current atomic-level computation task to obtain the data packet to be computed specifically includes: Based on the current atomic-level computation task, read the corresponding atomic coordinates, atomic type, and at least one additional attribute parameter determined according to the computation type of the current atomic-level computation task from memory; According to the interface protocol of the coprocessor, the current atomic-level computation task, the atomic coordinates, the atomic type, and the additional attribute parameters are packaged to obtain the data package to be computed.

3. The method according to claim 1, characterized in that, Sending the data packet to be computed to the coprocessor specifically includes: When there is only one coprocessor, the data packet to be computed is sent to the coprocessor based on the direct distribution strategy; When there are multiple coprocessors, the data packets to be computed are sent to the corresponding coprocessors according to a preset distribution order based on a round-robin scheduling strategy.

4. The method according to claim 1, characterized in that, The method further includes: During the computation of the current atomic-level computation task performed by the coprocessor, the main processor performs state update and / or feedback control processing based on the returned results of the previous atomic-level computation.

5. The method according to claim 1, characterized in that, The method further includes: The single-atom preprocessing time of the main processor, the single-atom computation time of the coprocessor, and the single-atom bidirectional communication time between the main processor and the coprocessor are obtained. When the number of coprocessors is one, a first optimization target is determined based on the single-atom preprocessing time, the single-atom computation time, and the single-atom bidirectional communication time, so that the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor. When there are multiple coprocessors, a second optimization objective is determined based on the single-atom preprocessing time, the single-atom computation time, and the single-atom bidirectional communication time, so that the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

6. The method according to claim 5, characterized in that, The first optimization objective is: The single-atom preprocessing time is less than or equal to the single-atom computation time, and the single-atom bidirectional communication time is less than or equal to the single-atom computation time.

7. The method according to claim 5, characterized in that, The second optimization objective is: The product of the number of coprocessors multiplied by the single-atom preprocessing time is less than or equal to the single-atom computation time, and the product of the number of coprocessors multiplied by the single-atom bidirectional communication time is less than or equal to the single-atom computation time.

8. A heterogeneous processor cooperative pipeline scheduling system for atomic-level computing, characterized in that, Applied to heterogeneous processors, the heterogeneous processors including a main processor and a coprocessor, the system includes: The first task processing module is used to preprocess the current atomic-level computing task through the main processor to obtain the data packet to be computed; The task transmission module is used to send the data packet to be calculated to the coprocessor and receive the previous atomic-level calculation result returned by the coprocessor. The second task processing module is used to perform calculations on the data packet to be calculated through the coprocessor to obtain the current atomic-level calculation result, and then send the current atomic-level calculation result back to the main processor. The first task processing module is further configured to preprocess the next atomic-level computation task through the main processor during the computation of the second task processing module, and the preprocessing time of the main processor and the communication time between the main processor and the coprocessor are both within the computation time window of the coprocessor.

9. An electronic device, characterized in that, The electronic device includes a memory, a main processor, and at least one coprocessor. The memory stores a computer program, and when the main processor executes the computer program, it controls the coprocessor to collaboratively implement the method of any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the main processor, it controls at least one coprocessor to collaboratively implement the method of any one of claims 1 to 7.

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