A CPU-FPGA heterogeneous collaborative processing method and device based on dynamic load sensing

Abstract

This invention discloses a CPU-FPGA heterogeneous collaborative processing method and apparatus based on dynamic load awareness. The method includes: a CPU selecting hardware acceleration reconfiguration resources according to configuration information and loading the hardware acceleration reconfiguration resources into the FPGA; the CPU performing a self-test on the FPGA to verify the hardware acceleration reconfiguration resources loaded in the FPGA; when the FPGA passes the self-test, the CPU receives data to be processed; the CPU acquires its own load information in real time and compares the load information with a dynamically set load threshold; when the load information is greater than the load threshold, the data to be processed is split into first split data and second split data; the CPU processes the first split data and obtains a first processing result; the FPGA processes the second split data and obtains a second processing result; the CPU integrates the first processing result and the second processing result and outputs the integrated processing result.

Description

Technical Field

[0001] This invention relates to the field of computer network communication technology, and more specifically, to a CPU-FPGA heterogeneous collaborative processing method and apparatus based on dynamic load awareness. Background Technology

[0002] In existing technologies, relying solely on the CPU (Central Processing Unit) to process large-scale parallel computing tasks is inefficient, and memory bandwidth bottlenecks limit performance in high-throughput scenarios.

[0003] In existing technologies, relying solely on FPGA (Field-Programmable Gate Array) for large-scale parallel computing tasks lacks flexibility and struggles to handle complex control logic, resulting in high performance but limited applicability. Summary of the Invention

[0004] The present invention provides a CPU-FPGA heterogeneous collaborative processing method and apparatus based on dynamic load awareness, in order to solve the problem of how to achieve CPU-FPGA heterogeneous collaborative processing based on dynamic load awareness through the collaboration of FPGA and CPU.

[0005] To address the aforementioned problems, this invention provides a CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness, the method comprising: The CPU selects hardware-accelerated reconfiguration resources according to the configuration information and loads the hardware-accelerated reconfiguration resources into the FPGA; The CPU performs a self-test on the FPGA to verify the hardware-accelerated reconfiguration resources loaded in the FPGA. When the FPGA passes the self-test, the CPU receives the data to be processed; the CPU obtains its own load information in real time and compares the load information with the dynamically set load threshold. When the load information exceeds the load threshold, the data to be processed is split into a first split data and a second split data. The CPU processes the first split data and obtains a first processing result. The FPGA processes the second split data and obtains a second processing result. The CPU integrates the first processing result and the second processing result and outputs the integrated processing result.

[0006] Preferably, the method further includes: When the FPGA fails the self-test, the CPU updates the hardware acceleration reconfiguration resources based on the configuration information and loads the updated hardware acceleration reconfiguration resources into the FPGA.

[0007] Preferably, the method further includes: When the CPU load information is less than or equal to the load threshold, the CPU processes the data to be processed and outputs the processing result.

[0008] Preferably, it further includes: A zero-copy data area is provided between the CPU and the FPGA; The CPU stores the second split data in a zero-copy data area; The FPGA reads the second split data from the zero-copy data area and processes it, storing the second processing result in the zero-copy data area.

[0009] Preferably, the zero-copy data area is connected to the CPU and the FPGA via the address bus and data bus of the dual-port RAM, respectively.

[0010] Preferably, when the FPGA does not receive a computing start instruction from the CPU, or receives a computing stop instruction, it clears the data in the zero-copy data area.

[0011] Preferably, the hardware-accelerated reconfiguration resources are stored in FLASH, and the CPU selects the hardware-accelerated reconfiguration resources in the FLASH.

[0012] Preferably, the load threshold is dynamically set based on CPU utilization, data processing throughput, and memory bandwidth utilization.

[0013] Preferably, the initialization of the CPU and FPGA after power-on reset includes: After power-on reset, the CPU and FPGA are initialized using double data rate memory (DDR), including setting up zero-copy data areas, dynamic load sensing, data splitting, and data aggregation.

[0014] Based on another aspect of the present invention, the present invention provides a CPU-FPGA heterogeneous collaborative processing device based on dynamic load awareness, the device comprising: An initial unit is used for the CPU to select hardware-accelerated reconfiguration resources according to configuration information and load the hardware-accelerated reconfiguration resources into the FPGA; the CPU performs a self-test on the FPGA to verify the hardware-accelerated reconfiguration resources loaded in the FPGA; The judgment unit is used to receive the data to be processed by the CPU when the FPGA passes the self-test; the CPU obtains its own load information in real time and compares the load information with a dynamically set load threshold. An execution unit is configured to split the data to be processed into a first split data and a second split data when the load information is greater than the load threshold. The CPU processes the first split data and obtains a first processing result, the FPGA processes the second split data and obtains a second processing result, and the CPU integrates the first processing result and the second processing result to output the integrated processing result.

[0015] This invention provides a CPU-FPGA heterogeneous collaborative processing method and apparatus based on dynamic load awareness. The method includes: the CPU selecting hardware acceleration reconfiguration resources according to configuration information and loading these resources onto the FPGA; the CPU performing a self-test on the FPGA to verify the loaded hardware acceleration reconfiguration resources; when the FPGA passes the self-test, the CPU receives the data to be processed; the CPU acquires its own load information in real time and compares it with a dynamically set load threshold; when the load information exceeds the load threshold, the data to be processed is split into first split data and second split data; the CPU processes the first split data and obtains a first processing result, the FPGA processes the second split data and obtains a second processing result, and the CPU integrates the first and second processing results to output the integrated processing result. This invention utilizes a CPU dynamic load awareness and FPGA coordinated processing approach. The CPU senses its own load in real time and compares it with a dynamic threshold. Under high load, it intelligently splits data, allowing the CPU to focus on core tasks and the FPGA to undertake hardware acceleration tasks, avoiding overload of a single component and significantly improving overall data processing throughput and response speed. Attached Figure Description

[0016] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures: Figure 1 This is a flowchart of a CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness according to a preferred embodiment of the present invention. Figure 2 This is a schematic diagram of the CPU-FPGA heterogeneous collaborative processing system according to a preferred embodiment of the present invention; Figure 3 This is a software processing flowchart according to a preferred embodiment of the present invention; Figure 4 This is a flowchart of FPGA logic processing according to a preferred embodiment of the present invention; Figure 5 A diagram of a security system for primary and backup machine enumeration based on FPGA and CPU collaboration according to a preferred embodiment of the present invention; Figure 6This is a structural diagram of a CPU-FPGA heterogeneous collaborative processing device based on dynamic load awareness according to a preferred embodiment of the present invention. Detailed Implementation

[0017] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0018] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0019] Figure 1 This is a flowchart of a CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness according to a preferred embodiment of the present invention.

[0020] This invention proposes a CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness. By using CPU dynamic load awareness and FPGA coordinated processing, it can solve the problems of low efficiency when relying solely on CPU computing to handle large-scale parallel computing tasks, and the performance limitations caused by memory bandwidth bottlenecks in high-throughput scenarios. On the other hand, it can also solve the limitations of insufficient flexibility when relying solely on FPGA computing to handle large-scale parallel computing tasks.

[0021] This invention provides a CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness. This method addresses the limitations of CPU's low efficiency in handling large-scale parallel computing tasks, performance constraints due to memory bandwidth bottlenecks in high-throughput scenarios, and the lack of flexibility when relying solely on FPGA for large-scale parallel computing tasks. The invention employs a collaborative approach between CPU and FPGA, where the CPU dynamically senses the load, performs zero-copy data transfer to the FPGA, and the FPGA hardware acceleration engine is reloaded for large-scale data computation; the FPGA handles the hardware acceleration engine reloading. The invention utilizes a dual-port RAM (Random Access Memory) that communicates with both the FPGA and CPU via address and data buses, respectively.

[0022] like Figure 1As shown, this invention provides a CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness, the method comprising: Initialize the CPU and FPGA after power-on reset; Preferably, it includes: After power-on reset, the CPU and FPGA are initialized using double data rate memory (DDR), including setting up zero-copy data areas, dynamic load sensing, data splitting, and data aggregation.

[0023] The CPU selects hardware-accelerated reconfiguration resources based on configuration information and loads them onto the FPGA. The CPU then performs a self-test on the FPGA. Step 101: The CPU selects hardware-accelerated reconfiguration resources based on the configuration information and loads the hardware-accelerated reconfiguration resources into the FPGA; Step 102: The CPU performs a self-test on the FPGA to verify the hardware-accelerated reconfiguration resources loaded in the FPGA; Preferably, the hardware-accelerated reconfiguration resources are stored in FLASH (flash memory), and the CPU selects the hardware-accelerated reconfiguration resources in FLASH.

[0024] like Figure 2 As shown, in this invention, the CPU is responsible for the FPGA hardware acceleration engine reconstruction loading module, initializing the CPU and FPGA zero-copy memory interaction module, initializing the dynamic sensing load module, initializing the data splitting module, and initializing the data aggregation module; the FPGA implements the hardware acceleration engine reconstruction and large-scale data computation.

[0025] The CPU of this invention selects FPGA hardware acceleration engine reconstructed resources for loading based on configuration information, initializes the CPU-FPGA zero-copy memory interaction module, initializes the dynamic sensing load module, initializes the data splitting module, and initializes the data aggregation module.

[0026] The FPGA initialization module of this invention completes the basic FPGA function module, receives the CPU's hardware acceleration engine to reconstruct resources, performs resource reconstruction, and after the resource reconstruction is completed, initializes the large-scale data computing module.

[0027] Step 103: When the FPGA passes the self-test, the CPU receives the data to be processed; the CPU obtains its own load information in real time and compares the load information with the dynamically set load threshold. Preferably, the method further includes: When the FPGA fails the self-test, the CPU updates the hardware accelerated reconfiguration resources based on the configuration information and loads the updated hardware accelerated reconfiguration resources onto the FPGA.

[0028] Preferably, the load threshold is dynamically set based on CPU utilization, data processing throughput, and memory bandwidth utilization.

[0029] The CPU of this invention performs a self-test on the FPGA large-scale data computing module. If successful, the CPU waits to receive network data. If it fails, it re-executes the hardware acceleration engine to reconstruct the resource loading part.

[0030] Step 104: When the load information is greater than the load threshold, the data to be processed is split into first split data and second split data. The CPU processes the first split data and obtains the first processing result. The FPGA processes the second split data and obtains the second processing result. The CPU integrates the first processing result and the second processing result and outputs the integrated processing result.

[0031] Preferably, the method further includes: When the CPU load information is less than or equal to the load threshold, the CPU processes the data to be processed and outputs the processing result. Preferably, it also includes: A zero-copy data area is set between the CPU and the FPGA; The CPU stores the second stream data in the zero-copy data area; The FPGA reads the second split data from the zero-copy data area, processes it, and stores the second processing result in the zero-copy data area.

[0032] Preferably, the zero-copy data area is connected to the CPU and FPGA via the address bus and data bus of the dual-port RAM, respectively.

[0033] Preferably, when the FPGA does not receive a computation start instruction from the CPU, or receives a computation stop instruction, it clears the data in the zero-copy data area.

[0034] This invention receives data to be processed via a CPU and dynamically senses the CPU load. If the CPU load exceeds a preset maximum load value, the FPGA's large-scale data computation function is activated, and a zero-copy data area between the CPU and FPGA is enabled. The data to be processed is split by a distribution module, with some data being processed by the CPU for large-scale data computation and the rest by the FPGA's hardware acceleration engine. After the computation is complete, the data is aggregated and organized by the CPU's data aggregation module and sent out via the network port. If the CPU load does not exceed the preset maximum load value, the data is split by the distribution module and sent to the CPU for large-scale data computation. The computation results are then sent to the aggregation module, and the data is sent out via the network port.

[0035] In this invention, when the FPGA receives a large-scale data computation enable function from the CPU, it retrieves the data to be processed from the zero-copy data area between the CPU and the FPGA. The FPGA then processes the data through its large-scale data computation module and, after processing, places the data back into the zero-copy data area between the CPU and the FPGA. If the FPGA does not receive a large-scale data computation enable function or a large-scale data computation disable function from the CPU, the FPGA clears the zero-copy data area between the CPU and the FPGA and continues to wait for the CPU to enable large-scale data computation for the FPGA. Figure 3 As shown.

[0036] The PHY (Physical Layer) of this invention is used for physical link layer network communication, and transmits and receives network data by connecting to a dual-port RAM.

[0037] The DDR (Double Data Rate) of this invention serves as the memory portion of a dual-port RAM CPU processor, used for system software and application runtime storage.

[0038] The FLASH memory of this invention serves as a persistent storage portion for the CPU processor running dual-port RAM. It is used as a persistent storage memory for system software, file systems, and applications, and the system boots and reads data from here after power-on.

[0039] like Figure 3 As shown, the CPU processing flow includes: S101: After power-on, the reset is completed, and the management module is started to initialize and configure the FPGA through the configuration management interface. The CPU and FPGA zero-copy memory interaction module is initialized, the dynamic sensing load module is initialized, the data splitting module is initialized, and the data aggregation module is initialized. The next step is to go to 102. S102: Select hardware acceleration engine reconstruction resources according to the configuration and load the hardware acceleration engine reconstruction resources into the FPGA: if the loading is successful, proceed to S103 for processing; if the loading fails, proceed to S104 for processing. S103: The CPU performs a self-test on the FPGA large-scale data computing module. If the self-test is successful, it proceeds to S105 for processing; if the self-test fails, it proceeds to S104 for processing. S104: Re-execute S102; S105: Upon receiving the data to be processed, determine whether the data to be processed needs to be split for processing by initializing the dynamic sensing load module. If the data does not need to be split for processing, proceed to S106 for processing; if it needs to be split, proceed to S107 for processing. S106: The received data to be processed is fed into the CPU large-scale data computing module through the splitting module for data processing, and then the next step is to go to S108. S107: Data splitting, some data is put into the CPU large-scale data computing module for data processing, and the next step is to go to S108; some data is put into the CPU and FPGA zero-copy data area, and the next step is to go to S205. S108: The data aggregation module obtains the calculated data and sends it out through the network port.

[0040] like Figure 4 As shown, the FPGA processing flow includes: S201: After power-on, the reset is completed, the management unit is started to receive configuration management instructions, the basic function modules of the FPGA are initialized, and the next step is to go to S202; S202: Waiting for the FPGA to complete the hardware acceleration engine reconstruction. The next step is to proceed to S203.

[0041] S203: If the large-scale data computing function is enabled, proceed to S204; if the large-scale data computing function is not enabled, proceed to S205.

[0042] S204: Obtain the CPU and FPGA zero-copy data area, then proceed to S206; S205: Clear the CPU and FPGA zero-copy data areas, then proceed to S203; S206: Perform large-scale data calculations on the FPGA, place the calculation results into the CPU and FPGA zero-copy data area, and then proceed to S108.

[0043] The CPU of this invention undertakes the function of dynamic reconfiguration and loading of FPGA algorithm resources, which solves the limitation of insufficient flexibility when relying solely on FPGA computing to process large-scale parallel computing tasks.

[0044] The FPGA-implemented hardware acceleration engine of this invention solves the problems of low efficiency when relying solely on CPU computing to process large-scale parallel computing tasks, and the performance limitations caused by memory bandwidth bottlenecks in high-throughput scenarios.

[0045] This invention can be widely applied to various network communication devices or computers. For example... Figure 5 As shown, a security method and system scheme for implementing master / standby machine enumeration based on FPGA and CPU collaboration is as follows: The system consists of an FPGA SoC chip (C001), DDR4 memory (C002), a network PHY chip (C003), FLASH storage (C004), a CPU (C005), a power supply, a clock, and multiple network interface connectors.

[0046] The FPGA SoC chip C001 is implemented using a single Xilinx XCZU7EV integrated SoC chip, which integrates an FPGA and an ARM (Advanced RISC Machines) processor core. The FPGA handles network data transmission, reception, and processing, and also implements ARP protocol processing. The ARM processor configures and manages the FPGA via its internal AXI (Advanced Dextensible Interface) bus.

[0047] DDR4 (Double Data Rate 4 Synchronous Dynamic RAM) memory C002: Selects 4 MTMT40A256M16 chips, which are DDR4, as the memory part of the ARM processor running on the FPGA SoC chip C001, and is used for the memory of system software and application runtime.

[0048] Network PHY chip C003: Multiple RTL8211 gigabit chips are used to implement the network PHY circuit for physical link layer network communication. It is connected to C001 through the RGMII (Reduced Gigabit Media Independent Interface) protocol to send and receive network data.

[0049] FLASH storage C004: Selects one MT25QU256ABA chip, FLASH memory, as the persistent storage part of the ARM processor running in C001, used for persistent storage of system software, file system and application applications, and booting and reading data from here after the system is powered on.

[0050] CPU C005: Select one M300 chip, which is connected to the FPGA SoC chip C001 via the RGMII protocol.

[0051] Figure 6 This is a structural diagram of a CPU-FPGA heterogeneous collaborative processing device based on dynamic load awareness according to a preferred embodiment of the present invention.

[0052] like Figure 6 As shown, the present invention provides a CPU-FPGA heterogeneous collaborative processing device based on dynamic load awareness, the device comprising: The initial unit 601 is used by the CPU to select hardware-accelerated reconfiguration resources according to the configuration information and load the hardware-accelerated reconfiguration resources into the FPGA; the CPU performs a self-test on the FPGA to verify the hardware-accelerated reconfiguration resources loaded in the FPGA. Preferably, after power-on reset, the CPU and FPGA are initialized using double data rate memory (DDR), including setting up a zero-copy data area, dynamic load sensing, data splitting, and data aggregation.

[0053] The judgment unit 602 is used to receive the data to be processed by the CPU when the FPGA passes the self-test; the CPU obtains its own load information in real time and compares the load information with the dynamically set load threshold. When the FPGA fails the self-test, the CPU updates the hardware accelerated reconfiguration resources based on the configuration information and loads the updated hardware accelerated reconfiguration resources into the FPGA.

[0054] Preferably, the load threshold is dynamically set based on CPU utilization, data processing throughput, and memory bandwidth utilization.

[0055] The execution unit 603 is configured to, when the load information exceeds a load threshold, split the data to be processed into a first split data and a second split data; the CPU processes the first split data and obtains a first processing result; the FPGA processes the second split data and obtains a second processing result; and the CPU integrates the first and second processing results and outputs the integrated processing result. Preferably, the execution unit 603 is further configured to: When the CPU load information is less than or equal to the load threshold, the CPU processes the data to be processed and outputs the processing result. Preferably, the execution unit 603 is further configured to: A zero-copy data area is set between the CPU and the FPGA; The CPU stores the second stream data in the zero-copy data area; The FPGA reads the second split data from the zero-copy data area, processes it, and stores the second processing result in the zero-copy data area.

[0056] Preferably, the execution unit 603 is further configured to: The zero-copy data area communicates with the CPU and FPGA via the address bus and data bus of the dual-port RAM, respectively.

[0057] Preferably, the execution unit 603 is further configured to: When the FPGA does not receive a computation start instruction from the CPU, or receives a computation stop instruction, it clears the data in the zero-copy data area.

[0058] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0059] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0062] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0063] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

[0064] The invention has been described with reference to a few embodiments. However, as will be known to those skilled in the art, and as defined in the appended claims, other embodiments besides those disclosed above fall equivalently within the scope of the invention.

[0065] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless otherwise expressly defined herein. All references to “a / / the [device, component, etc.]” ​​are openly interpreted as at least one instance of the device, component, etc., unless otherwise expressly stated. The steps of any method disclosed herein are not necessarily to be performed in the exact order disclosed, unless explicitly stated otherwise.

Claims

1. A CPU-FPGA heterogeneous collaborative processing method based on dynamic load awareness, the method comprising: The CPU selects hardware-accelerated reconfiguration resources according to the configuration information and loads the hardware-accelerated reconfiguration resources into the FPGA; The CPU performs a self-test on the FPGA to verify the hardware-accelerated reconfiguration resources loaded in the FPGA. When the FPGA passes the self-test, the CPU receives the data to be processed; the CPU obtains its own load information in real time and compares the load information with the dynamically set load threshold. When the load information exceeds the load threshold, the data to be processed is split into a first split data and a second split data. The CPU processes the first split data and obtains a first processing result. The FPGA processes the second split data and obtains a second processing result. The CPU integrates the first processing result and the second processing result and outputs the integrated processing result.

2. The method according to claim 1, further comprising: When the FPGA fails the self-test, the CPU updates the hardware acceleration reconfiguration resources based on the configuration information and loads the updated hardware acceleration reconfiguration resources into the FPGA.

3. The method according to claim 1, further comprising: When the CPU load information is less than or equal to the load threshold, the CPU processes the data to be processed and outputs the processing result.

4. The method according to claim 1, further comprising: A zero-copy data area is provided between the CPU and the FPGA; The CPU stores the second split data in a zero-copy data area; The FPGA reads the second split data from the zero-copy data area and processes it, storing the second processing result in the zero-copy data area.

5. According to the method of claim 4, the zero-copy data area is connected to the CPU and the FPGA via the address bus and data bus of the dual-port RAM, respectively.

6. According to the method of claim 4, when the FPGA does not receive a computing start instruction from the CPU, or receives a computing stop instruction, it clears the data in the zero-copy data area.

7. The method according to claim 1, wherein the hardware-accelerated reconfiguration resources are stored in FLASH, and the CPU selects the hardware-accelerated reconfiguration resources in the FLASH.

8. The method according to claim 1, wherein the load threshold is dynamically set based on CPU utilization, data processing throughput and memory bandwidth utilization.

9. The method according to claim 1, further comprising: After power-on reset, the CPU and FPGA are initialized using double data rate memory (DDR), including setting up zero-copy data areas, dynamic load sensing, data splitting, and data aggregation.

10. A CPU-FPGA heterogeneous collaborative processing device based on dynamic load awareness, the device comprising: An initialization unit is used for the CPU to select hardware-accelerated reconfiguration resources according to configuration information and load the hardware-accelerated reconfiguration resources into the FPGA; The CPU performs a self-test on the FPGA to verify the hardware-accelerated reconfiguration resources loaded in the FPGA. The judgment unit is used to receive the data to be processed by the CPU when the FPGA passes the self-test; the CPU obtains its own load information in real time and compares the load information with a dynamically set load threshold. An execution unit is configured to split the data to be processed into a first split data and a second split data when the load information is greater than the load threshold. The CPU processes the first split data and obtains a first processing result, the FPGA processes the second split data and obtains a second processing result, and the CPU integrates the first processing result and the second processing result to output the integrated processing result.

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