Lightweight general-purpose intelligent processing system and method

Abstract

This invention relates to the field of edge data processing technology, and discloses a lightweight edge intelligent processing system and method. The system includes: a unified symbol and knowledge module, which constructs a two-layer symbol representation structure and resolves symbol conflicts according to preset priority rules; an atomic execution and orchestration module, which realizes deterministic task execution through symbol processing units (STUs) and dynamic DAG topology; a global state and resource scheduling module, which performs dynamic resource scheduling based on four-dimensional quantitative indicators and allocates memory according to hierarchical proportions; and a security adaptation module, which tailors security mechanisms according to hardware computing power levels and uses a three-level hash chain to record audit logs. This solution can complete the unified symbolic processing, deterministic execution, full-process security control, and lightweight edge deployment of multimodal data.

Description

Technical Field

[0001] This invention relates to the field of edge-side intelligent processing technology, and in particular to a lightweight general-purpose intelligent processing system and method. Background Technology

[0002] Currently, AI security governance places clear demands on the explainability, auditability, and physical security of AI systems. Existing solutions often employ external security safeguards or post-event review mechanisms, lacking a deterministic verification system deeply embedded in the execution process. This makes it difficult to meet the compliance requirements of normative documents such as the "AI Security Governance Framework" regarding the traceability of AI decisions and physical security constraints. In particular, existing solutions fail to layer and embed the rigid constraints of the physical fact domain with the flexible constraints of the social value domain, thus failing to simultaneously meet the dual requirements of unbreakable physical bottom lines and flexible adaptation to social norms.

[0003] Specifically, existing edge-side intelligent solutions have the following technical shortcomings: Symbolization processing is mostly at a single symbol level, failing to distinguish between core semantics and fine-grained features. Symbol conflict resolution lacks clear priority rules, resulting in the inability to systematically eliminate semantic ambiguity in multi-source heterogeneous data. The atomic execution unit lacks a unified standardized design, task orchestration relies on cloud computing power, it cannot achieve fully offline deterministic reasoning on the edge, and the execution results are not reproducible; Resource scheduling lacks quantitative control indicators, there is no rigid allocation scheme for memory of low computing power hardware, and lightweight deployment lacks operable hardware adaptation standards. The security mechanisms are disconnected from the execution process, and there is no end-to-end traceable audit solution, making it impossible to guarantee compliance in high-reliability scenarios. Summary of the Invention

[0004] This invention provides a unified architecture, deterministic execution, secure embedding, value alignment, low power consumption and lightweight design, full-domain autonomy, cross-domain compatibility, and controllable innovation edge-side general-purpose intelligent processing system and implementation method. It realizes unified processing of multimodal data, deterministic task execution, full-process security control, edge-side controllable knowledge expansion and deterministic autonomous optimization output, reduces the development and implementation cost of edge-side intelligence, and promotes the development of edge-side intelligence technology towards generalization and standardization.

[0005] To achieve the above objectives, the present invention provides a lightweight general-purpose intelligent processing system, comprising: The Unified Symbols and Knowledge Module is used to preprocess and align multimodal data, quantize and encode the obtained standardized feature sequences to extract core semantic features, generate a core symbol set, generate a micro symbol set based on residual features, construct a two-layer symbol representation structure in which core symbols anchor semantics and micro symbols supplement fine-grained features, and resolve conflicts between synonymous and heterogeneous symbols according to the preset priority rule that symbols constrained by the physical fact domain take precedence over system-built core symbols, thereby generating a globally unified symbol system. Atomic execution and orchestration module: It is used to convert the global unified symbol system into a task dependency graph, construct a dynamic DAG topology through loop detection and redundancy pruning, perform symbol completion for nodes with incomplete symbols based on the similarity matching between the historical context template and the current sequence set, and perform pre-physical fact domain verification and post-social value domain verification in sequence. The deterministic atomic execution is completed through the symbol processing unit STU to form the task execution symbol topology. Global State and Resource Scheduling Module: Used to collect computing load, memory access locality, topology dependency and energy consumption characteristics, generate a four-dimensional resource quantization vector, perform resource reallocation when deviating from the steady state benchmark, and allocate memory according to a preset hierarchical ratio to form a three-level storage structure of short-term working memory, medium-term cache memory and long-term knowledge memory, so as to achieve lightweight operation on the edge. Security adaptation module: It is used to perform security mechanism pruning according to the computing power level of the terminal hardware, perform integrity verification and access control on the execution results, and record audit logs using a three-level chain structure of bottom node hash, intermediate block hash and top root hash, so as to obtain the three-level chain structure that is tamper-proof and traceable throughout the entire link.

[0006] Preferably, the preprocessing and modality alignment of the multimodal data includes: The system receives the raw multimodal data stream, strips the heterogeneous encapsulation header through the protocol parser, and maps the text, image, audio, and sensor time-series data to a unified tensor space to generate an initial multimodal tensor set. Obtain the computing power rating identifier of the current edge hardware, and match the corresponding quantization bit width and channel pruning rate from the preset lightweight cross-modal feature extraction strategy library based on the computing power rating identifier. Perform feature dimensionality reduction and modality alignment on the initial multimodal tensor set to generate a multimodal feature tensor sequence. The local symbol reuse rate distribution of the multimodal feature tensor sequence is calculated, redundant feature mask filtering in the spatiotemporal dimension is performed based on a preset quantization threshold, and an irreversible verification fingerprint is generated for the filtered feature fragments in combination with a symbol anti-tampering hash verification mechanism. Lexical segmentation and cross-language word vector alignment are performed on the feature fragments carrying text modalities. The irreversible verification fingerprint and the aligned feature fragments are then dimensionally concatenated to output a standardized multimodal feature sequence.

[0007] Preferably, the obtained standardized feature sequence is subjected to feature quantization encoding to extract core semantic features, generate a core symbol set, generate a micro-symbol set based on residual features, construct a two-layer symbol representation structure in which core symbols anchor semantics and micro-symbols supplement fine-grained features, and resolve conflicts between synonymous and heterogeneous symbols according to a preset priority rule that physical fact domain-constrained symbols take precedence over system-built-in core symbols, generating a globally unified symbol system, including: During conflict resolution, high-priority symbols are retained, low-priority symbols are discarded, and synonym mappings are established and stored in the conflict resolution table. The standardized multimodal feature sequence is input into a cross-modal semantic coding network to extract high-frequency co-occurrence feature clusters, which are mapped to a set of core symbols. A globally unique identifier and basic semantic weight are assigned to each core symbol to generate a basic symbol representation matrix. Based on the marginal distribution features of the basic symbolic representation matrix, the residual feature vector is analyzed to generate a set of micro-symbols for representing fine-grained differences and long-tail distribution. The set of micro-symbols and the core symbolic set are cascaded according to a preset topological hierarchy to construct a two-layer symbolic representation structure. The synonymous heterogeneous nodes in the two-layer symbol representation structure are traversed, and node conflicts are determined according to the preset symbol structure matching rules and hierarchical priority. When the symbol semantic matching similarity does not reach the preset compliance matching threshold, the conflict resolution protocol is automatically triggered. The semantic matching similarity is obtained by calculating the cosine distance between two symbols in the multidimensional semantic feature space. An unambiguous symbol mapping relationship table is generated through dynamic weight allocation and master-slave symbol priority determination. The preset priority rule is as follows: physical fact domain constraint symbols > system built-in core symbols > industry standard knowledge source symbols > high confidence document source symbols > ordinary interactive source symbols; Perform a consistency graph traversal verification on the unambiguous symbol mapping table, eliminate closed-loop dependencies and isolated nodes, encapsulate a metadata structure containing symbol identifiers, semantic weights, mapping relationships and verification fingerprints, and output a globally unified symbol system.

[0008] Preferably, the method is used to convert the globally unified symbol system into a task dependency graph, construct a dynamic DAG topology through loop detection and redundancy pruning, perform symbol completion for nodes with incomplete symbols based on the similarity matching between the historical context template and the current sequence set, and perform pre-physical fact domain verification and post-social value domain verification sequentially. Deterministic atomic execution is completed through the symbol processing unit (STU), forming a task execution symbol topology, including: The metadata structure in the global unified symbol system is semantically graph-based to identify the logical sequence relationship and data flow constraints between symbol nodes and generate an initial task dependency graph. Based on the initial task dependency graph, loop detection and critical path extraction are performed. Independent subgraphs with parallel execution potential are topologically sorted, redundant intermediate nodes are merged, and a dynamic directed acyclic graph (DAG) is constructed. For nodes in the dynamic directed acyclic graph (DAG) with incomplete input symbols due to missing modes or broken context chains, a scheduling layer symbol completion mechanism is triggered. Based on the dual-domain constraint rules, historical context symbols are retrieved and the corresponding inference operators are matched to complete the placeholders and generate a complete node graph. Symbol completion employs a set similarity matching algorithm, which can use any of the following: Jaccard distance, cosine similarity, or Euclidean distance. This embodiment uses the Jaccard similarity matching algorithm as an example, and the specific steps are as follows: Step 1: Perform n-gram segmentation (n=2) on the current incomplete symbol sequence and the historical context template respectively. Step 2, calculate the Jaccard similarity coefficient between the two n-gram sets: ; Step 3: Select the historical template with the highest Jaccard similarity coefficient that meets the PCD rigidity check; Step 4: Fill the missing positions with the corresponding symbols from the template to complete the symbol completion; The complete node graph is input into the symbol processing unit (STU) to perform rigid verification of the preceding physical fact domain (PCD) and flexible verification of the subsequent social value domain (SCD). The preceding physical fact domain verification covers the compliance of physical laws and the correctness of mathematical logic. If the verification fails, the execution of the current node will be directly blocked. The post-social value domain verification covers industry standard compliance and cultural adaptation appropriateness. If the verification fails, the node parameters are fine-tuned and re-verified. The nodes that pass the dual-domain verification are dynamically weighted and bound to resource slots according to the execution sequence, and the task execution symbol topology is output. The symbol processing unit (STU) performs numerical operations using 16-bit fixed-point processing, converting floating-point data into integer operations based on a preset scaling factor.

[0009] Preferably, it is used to collect computational load, memory access locality, topological dependency, and energy consumption characteristics to generate a four-dimensional resource quantization vector. When deviating from the steady-state baseline, it performs resource reallocation and allocates memory according to a preset hierarchical ratio, forming a three-level storage structure of short-term working memory, medium-term cache memory, and long-term knowledge memory, to achieve lightweight operation on the edge, including: Receive the task execution symbol topology and collect in real time the task queue depth, memory page access hit rate, data flow dependency span and instantaneous power consumption fluctuation value of each computing node; The computational load quantification index is the ratio of the current task queue depth to the maximum task queue depth; the memory access locality quantification index is the memory page access hit rate; the topology dependency quantification index is the ratio of the data flow dependency span to the maximum allowed dependency span; and the energy consumption quantification index is the ratio of instantaneous power consumption to rated power consumption. These are concatenated to form a four-dimensional resource quantification vector. Receive the four-dimensional resource quantization vector, calculate the deviation gradient of each dimension quantization index in the vector from the preset steady-state benchmark, and if the deviation gradient of any dimension exceeds the dynamic tolerance threshold, generate the corresponding resource redirection instruction set. Receive the resource redirection instruction set, parse the target resource identifier and priority weight in the instruction set, perform binding migration and slot reallocation on idle computing cores, secondary cache blocks and memory page frames through a dynamic priority queue, and output a resource remapping configuration table; The system receives the resource remapping configuration table and historical scheduling performance feedback data, updates the dynamic tolerance threshold and weight allocation coefficient based on the gradient descent algorithm, writes the updated parameters back to the scheduling strategy library, and outputs the iterative resource scheduling benchmark.

[0010] Preferred options also include: Scene adaptation and template service module: It is used to load industry or region-specific constraint packages through the unified architecture interface and plugin extension mechanism of the underlying standardized execution results, and generate the final output results that meet the business needs of the target scenario through business rule tree mapping and dynamic routing transformation. Upon receiving the controlled system status, the system abstracts and encapsulates the standardized calculation results of the underlying execution engine, symbolic topology resolution logs, and resource scheduling snapshots into APIs and protocols to generate a set of general intelligent service interfaces. The system receives industry or regional identifiers of the target scenario through a unified interface, matches the corresponding exclusive constraint package from the constraint library of the plugin extension mechanism, parses the business rule tree, compliance verification logic and multilingual adaptation parameters in the constraint package, and outputs a scenario-specific configuration set. The output data stream of the general intelligent service interface set is aligned with the scenario-specific configuration set by rules. The standardized data fields are mapped to the business data model of the target scenario through the condition matching engine and dynamic routing table to generate intermediate results for scenario adaptation. The system receives the intermediate results of the scenario adaptation, monitors the business response latency and data format matching degree in real time based on the scenario feature recognition algorithm, dynamically adjusts the plugin loading weight and data conversion threshold, and outputs the final output result that meets the business requirements of the target scenario.

[0011] Preferably, the method is used to perform security mechanism pruning based on the computing power level of the edge hardware, perform integrity verification and access control on the execution results, and record audit logs using a three-level chain structure of bottom-level node hash, intermediate block hash, and top-level root hash, to obtain the end-to-end tamper-proof and traceable three-level chain structure, including: The final output result is received, and the digital signature verification and content digest comparison of the data packet are performed using an asymmetric encryption algorithm. After the verification is passed, the redundant transmission header is stripped to generate a verified secure data stream. Receive the verified secure data stream, perform permission matching based on the target terminal's identity identifier and a preset access control matrix, perform fine-grained data desensitization or route interception, and output a controlled access data stream; The system receives the controlled access data stream, reads the instruction set architecture, available memory capacity and real-time clock frequency of the current edge processor through the system's underlying hardware abstraction layer, and automatically triggers the functional module on-demand pruning strategy when it detects that the available resources of the current edge hardware are lower than the preset lightweight operation threshold. Only the core symbol resolution, STU atomic execution, PCD physical fact domain verification and lightweight hash verification modules are retained, the encryption operation iteration frequency of the security mechanism is reduced, and a lightweight security execution package adapted to the current hardware platform is generated. Receive the runtime logs and access audit records of the lightweight security execution package, call the hash chain storage protocol to serialize and encrypt the log data and package it into blocks, and generate an initial audit hash chain; The three-level chain structure is constructed as follows: calculate the node hash value for each single operation record and concatenate them into the underlying hash sequence according to the time sequence; The hashes of consecutive nodes are assembled into a Merkle tree according to the preset block capacity, and the block header hash is calculated to form a set of intermediate block hashes; The new block header hash and the historical root hash are chained together to generate the top-level root hash, which is then stored in the local encrypted audit area to obtain the three-level chain structure that is tamper-proof and traceable across the entire chain.

[0012] To address the above problems, the present invention also provides a lightweight, general-purpose intelligent processing method, comprising: Multimodal data is preprocessed and modally aligned, core symbols and micro symbols are extracted to construct a two-layer symbol representation structure, and symbol conflict resolution is completed according to the priority rule that constrains symbols in the physical fact domain take precedence over the built-in core symbols of the system, thereby generating a globally unified symbol system. The global unified symbol system is constructed as a task dependency graph. After redundancy pruning, a dynamic DAG topology is formed. Incomplete nodes are filled with symbols based on the set similarity matching of historical context templates. Then, the pre-physical fact domain verification and the post-social value domain verification are performed sequentially. Deterministic atomic transformation is performed through STU to obtain the task execution symbol topology. Collect computational load, memory access locality, topological dependence and energy consumption characteristics, generate each index to be normalized to a four-dimensional quantization vector, perform resource reallocation when deviating from the steady-state benchmark, divide storage areas according to hierarchical memory ratio, and construct a three-level memory structure to adapt to the edge hardware. Security modules are tailored according to the hardware computing power level, the output results are verified and access control is performed, and audit logs are stored in a three-level chain structure of bottom node hash, intermediate block hash, and top root hash.

[0013] Beneficial effects This solution provides an unambiguous semantic unified processing framework for multi-source heterogeneous data through a two-layer symbol system and hierarchical conflict resolution rules. It solves the problem of systematically eliminating semantic ambiguity in multi-source data and improves the accuracy of cross-modal semantic alignment and symbol processing efficiency.

[0014] This solution provides a reproducible inference mechanism for edge devices by standardizing STU atomic execution units and dynamic DAG deterministic orchestration, which solves the defects of edge inference relying on the cloud and the inability to reproduce results, and improves the execution efficiency and consistency of result reproduction of edge inference.

[0015] This solution uses fixed memory rigid allocation and modular tailoring to make the system adaptable to ultra-low computing power hardware with RAM≤32KB, solving the problem of no adaptation standards for lightweight deployment of low computing power hardware, and improving the hardware adaptation coverage and resource utilization efficiency of the edge side.

[0016] This solution provides end-to-end traceability and tamper-proof protection for the edge processing flow through PCD / SCD dual-domain verification and a three-level hash audit chain. It solves the problems of disconnect between security mechanisms and execution processes and difficulty in ensuring compliance, thereby improving the security protection level and compliance audit efficiency of edge data processing.

[0017] This solution supports flexible loading and dynamic adaptation of industry- or region-specific constraints through a plug-in constraint package mechanism and scene tag micro-symbol encoding rules, achieving universal adaptation capabilities across industries and scenarios. It can be migrated and deployed in different high-security scenarios without modifying the core system architecture. Attached Figure Description

[0018] Figure 1 A functional block diagram of a lightweight general-purpose intelligent processing system provided in an embodiment of the present invention; Figure 1 In the middle, the scene adaptation and template service module 104 is drawn with a dashed box and is an optional function module, while the other modules are the basic function modules that are required by the system. Figure 2 This is a flowchart illustrating a lightweight, general-purpose intelligent processing method according to an embodiment of the present invention. The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] This application provides a lightweight general-purpose intelligent processing system and method. The execution subject of the lightweight general-purpose intelligent processing system and method includes, but is not limited to, at least one of electronic devices that can be configured to execute the method provided in this application, such as a server and a terminal. In other words, the lightweight general-purpose intelligent processing system and method can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0021] Reference Figure 1 The diagram shown is a functional block diagram of a lightweight general-purpose intelligent processing system provided in an embodiment of the present invention. The lightweight general-purpose intelligent processing system and method 100 described in this invention can be installed in electronic devices. Depending on the functions implemented, the lightweight general-purpose intelligent processing system and method 100 may include a unified symbol and knowledge module 101, an atomic execution and orchestration module 102, a global state and resource scheduling module 103, a scene adaptation and template service module 104, and a security adaptation module 105. The modules described in this invention can also be called units, which refer to a series of computer program segments that can be executed by the processor of an electronic device and can perform fixed functions, and are stored in the memory of the electronic device.

[0022] In this embodiment, the functions of each module / unit are as follows: The technical terms used in this application are defined as follows: STU (StateTransformUnit): Minimal State Transform Unit, the smallest atomic execution unit fixed at the system firmware level. It adopts a pure functional, stateless design to achieve symbolic deterministic transformation.

[0023] PCD (PhysicsFactDomain): The preceding physical fact domain, a rigid constraint domain representing physical laws, mathematical logic, and equipment operating parameters. If the verification fails, execution is directly blocked.

[0024] SCD (SocietyValueDomain): A post-positioned social value domain that represents a flexible constraint domain of industry norms and cultural adaptation rules, supporting plug-in extensions.

[0025] DAG (Directed Acyclic Graph): A dynamic directed acyclic graph, the core topology for system task orchestration, working with STU to achieve deterministic scheduling and execution of tasks.

[0026] Two-layer symbol system: a unified representation system for multimodal data consisting of core symbols (anchoring basic semantics) and micro symbols (supplementing fine-grained features).

[0027] Global status indicators: Engineering-based quantitative indicators that characterize system topology redundancy and execution stability. They only involve system topology and resource scheduling statistics and have no thermodynamic meaning.

[0028] Ontological design principles of symbolic systems The symbol system of this invention follows the following design principles to ensure the objectivity and scalability of symbol representation: (1) The principle of physical priority: The basic anchor of the core symbol system comes from the objective entities and relationships in the physical fact domain, and the physical fact domain constrains the symbols ( It has the highest priority, and any knowledge access from any source must pass PCD verification to ensure that the symbol system is not contaminated by empirical bias or statistical artifacts.

[0029] (2) Symbol-referential binding principle: Each core symbol obtains semantics through its explicit correspondence with physical entities, rather than through statistical co-occurrence or contextual distribution. Entity symbol E corresponds to identifiable physical or informational entities in the objective world, attribute symbol A corresponds to measurable or determinate features of the entity, and relation symbol R corresponds to verifiable logical or physical relationships between entities.

[0030] (3) Open World Preparatory Principle: The micro-symbol layer reserves an extension interface for unknown concepts in the open world. When the system encounters entities or relationships that cannot be matched with existing core symbols, a temporary representation is generated through the micro-symbol extension mechanism. After PCD verification and manual review, it can be solidified into a new core symbol to realize the incremental evolution of the symbol system.

[0031] (4) Rule traceability principle: All rules in the STU preset rule base can be traced back to physical laws, mathematical axioms, industry standards or verified business processes. There are no black box rules or purely statistical inference rules.

[0032] Unified Symbols and Knowledge Module 101: This module is used to preprocess and align multimodal data, quantize and encode the obtained standardized feature sequences to extract core semantic features, generate a core symbol set, generate a micro symbol set based on residual features, construct a two-layer symbol representation structure in which core symbols anchor semantics and micro symbols supplement fine-grained features, and resolve conflicts between synonymous and heterogeneous symbols according to the preset priority rule that symbols constrained by the physical fact domain take precedence over system-built core symbols, thereby generating a globally unified symbol system.

[0033] In this embodiment, the preprocessing and modality alignment of multimodal data includes: The system receives the raw multimodal data stream, strips the heterogeneous encapsulation header through the protocol parser, and maps the text, image, audio, and sensor time-series data to a unified tensor space to generate an initial multimodal tensor set. Obtain the computing power rating identifier of the current edge hardware, and match the corresponding quantization bit width and channel pruning rate from the preset lightweight cross-modal feature extraction strategy library based on the computing power rating identifier. Perform feature dimensionality reduction and modality alignment on the initial multimodal tensor set to generate a multimodal feature tensor sequence. The local symbol reuse rate distribution of the multimodal feature tensor sequence is calculated, redundant feature mask filtering in the spatiotemporal dimension is performed based on a preset quantization threshold, and an irreversible verification fingerprint is generated for the filtered feature fragments by combining a symbol anti-tampering hash verification mechanism.

[0034] Lexical segmentation and cross-language word vector alignment are performed on the feature fragments carrying text modalities. The irreversible verification fingerprint and the aligned feature fragments are then dimensionally concatenated to output a standardized multimodal feature sequence.

[0035] In this embodiment, the obtained standardized feature sequence is quantized and encoded to extract core semantic features, generate a core symbol set, generate a micro-symbol set based on residual features, construct a two-layer symbol representation structure in which core symbols anchor semantics and micro-symbols supplement fine-grained features, and resolve conflicts between synonymous and heterogeneous symbols according to a preset priority rule that physical fact domain-constrained symbols take precedence over system-built-in core symbols, generating a globally unified symbol system, including: During conflict resolution, high-priority symbols are retained, low-priority symbols are discarded, and synonym mappings are established and stored in the conflict resolution table. The standardized multimodal feature sequence is input into a cross-modal semantic coding network to extract high-frequency co-occurrence feature clusters, which are mapped to a set of core symbols. A globally unique identifier and basic semantic weight are assigned to each core symbol to generate a basic symbol representation matrix. Based on the marginal distribution features of the basic symbolic representation matrix, the residual feature vector is analyzed to generate a set of micro-symbols for representing fine-grained differences and long-tail distribution. The set of micro-symbols and the core symbolic set are cascaded according to a preset topological hierarchy to construct a two-layer symbolic representation structure. The synonymous heterogeneous nodes in the two-layer symbol representation structure are traversed, and node conflicts are determined according to the preset symbol structure matching rules and hierarchical priority. When the symbol semantic matching similarity does not reach the preset compliance matching threshold, the conflict resolution protocol is automatically triggered. The semantic matching similarity is obtained by calculating the cosine distance between two symbols in the multidimensional semantic feature space. An unambiguous symbol mapping relationship table is generated through dynamic weight allocation and master-slave symbol priority determination. The preset priority rule is as follows: physical fact domain constraint symbols > system built-in core symbols > industry standard knowledge source symbols > high confidence document source symbols > ordinary interactive source symbols; Perform a consistency graph traversal verification on the unambiguous symbol mapping table, eliminate closed-loop dependencies and isolated nodes, encapsulate a metadata structure containing symbol identifiers, semantic weights, mapping relationships and verification fingerprints, and output a globally unified symbol system.

[0036] Specifically, the system is equipped with an underlying data foundation and a standardized entry point. The core includes a multimodal unified submodule and a symbol system construction submodule, which are responsible for the unified collection, preprocessing, feature extraction and cross-modal semantic alignment of multimodal data. It completes the symbol standardization conversion of multimodal inputs, knowledge normalization processing, automatic resolution of symbol conflicts, and semantic alignment of multiple languages ​​and multiple domains, and builds a unified symbol system that is unique, unambiguous and computable across the entire domain.

[0037] The system incorporates core logic for symbol anti-tampering hash verification, disordered degree-oriented optimization to remove redundancy, and multilingual mapping, ensuring security and efficiency from the data source. It adopts a lightweight cross-modal feature extraction algorithm system that adapts to hardware computing power, dynamically selecting an appropriate feature extraction strategy based on the hardware computing power level to achieve unambiguous conversion of multimodal features to core-micro symbol combinations, thus eliminating the heterogeneity of multimodal data.

[0038] The core-microsymbol dual-layer unified representation system is the only data and knowledge representation carrier across the entire system. Through a dual-layer structure—core symbols anchoring core semantics and microsymbols supplementing fine-grained information—it achieves unambiguous, low-redundancy, computable, and verifiable unified representation of information across scenarios, modalities, and languages. Microsymbols employ a domain-based activation mechanism: PCD is only enabled. (unit), (Scope), the remaining micro symbols are only for SCD use.

[0039] Among them, (1) Symbol classification and definition Core symbols include entity symbols (E) representing objective entities, attribute symbols (A) representing entity characteristics, relation symbols (R) representing relational logic, and constraint symbols (C) representing control rules; constraint symbol C is further subdivided into physical-fact domain constraint symbols. Symbols constrained by social-value domain The relation symbol R is divided into two categories: (PCD physical-factual relationships, such as: =, >, <, +, -, ×, ÷, parallel, collision, derivation); (SCD social-value relationships, such as: relatives, superiors and subordinates, service, respect, prohibition), the two are semantically independent and do not overlap or mix.

[0040] Micro-symbols: including but not limited to unit micro-symbols , range micro symbol Confidence level microsymbol Scene tag micro symbols Etc. can be expanded according to scenario requirements without adding a new independent symbol hierarchy. PCD only allows the use of... (Units, such as: m, s, kg, ℃, N) The range is specified as ≤5N, ≥3.3V, 0~100℃), and other micro symbols are not loaded in the PCD and do not participate in the calculation.

[0041] Among them, scene tag micro symbols A combination of scene ID and tag ID encoding rule is adopted to ensure uniqueness across the entire domain. The specific rules are as follows: Scene ID encoding: Uses a 2-digit hexadecimal number (00-FF), and assigns a fixed code according to the scene category, such as including but not limited to industrial control=01, medical monitoring=02, government office=03, smart home=04, robot interaction=05, and reserves 06-FF for extended scene codes.

[0042] Tag ID encoding: Uses a 4-digit hexadecimal number (0000-FFFF), and assigns codes according to the sub-tags in the scene. For example, in the industrial control scene, equipment control = 0001 and data acquisition = 0002; in the smart home scene, lighting control = 0001 and home appliance linkage = 0002.

[0043] Complete encoding format: -Scene ID-Tag ID, such as the code for Industrial Control-Equipment Control. -01-0001, the code for smart home lighting control is... -04-0001.

[0044] Conflict avoidance mechanism: When adding a new scene tag micro-symbol, the system automatically verifies the uniqueness of the combination of scene ID + tag ID. If a duplicate exists, the system prompts the user to modify the tag ID. When expanding to a new scene, scene IDs are allocated from the reserved coding range to ensure that there is no conflict with existing scenes.

[0045] Encoding Management: Scene ID encoding is permanently stored in the system configuration area of ​​long-term memory and can only be modified by system administrators through the authorized interface; Tag ID encoding can be dynamically expanded according to scene requirements, and the symbol library index is updated synchronously after expansion.

[0046] (2) The semantic-symbol mapping implementation mechanism adopts a two-level implementation mechanism of feature quantization encoding + global symbol matching, and the matching strategy is adaptively selected based on hardware computing power: Feature quantization encoding: The multimodal feature extraction results are quantized into feature vectors of fixed length, and the dimensional differences are eliminated after normalization.

[0047] Global symbol matching: Low-power hardware uses brute-force matching + feature hash indexing, while medium-to-high-power hardware uses a lightweight similarity matching algorithm. The matching results are directly mapped to the corresponding core-micro symbol combination.

[0048] All mapping relationships are pre-fixed in a symbolic feature template library of long-term memory, supporting dynamic updates based on a knowledge evolution mechanism.

[0049] (3) The coding and anti-tampering design adopts a fixed coding rule of type prefix + 6-digit number. The specific format and coding range allocation are as follows: Type prefix definition: entity symbol E, attribute symbol A, relation symbol R, constraint symbol C, including physical-fact domain constraint symbols. Social-value domain constraint symbols .

[0050] Encoding range allocation: Unique encoding ranges are assigned to partitions based on type to avoid conflicts, such as E: 000001-200000; A: 200001-400000; R: 400001-600000; C: 600001-800000, where... : 600001-700000 : 700001-800000.

[0051] Complete encoding example: Entity symbol industrial sensor is encoded as 000001, attribute symbol temperature is encoded as A200001, relation symbol control is encoded as R400001, physical constraint symbol voltage threshold is encoded as... .

[0052] Encoding ranges are assigned by type and partition to ensure uniqueness, conflict-free operation, and rapid retrieval. Micro-symbols use a simplified encoding format of μ + type abbreviation + 3-6 digit number, such as unit micro-symbols. -001, Confidence level microsymbol -005, balancing conciseness and readability.

[0053] All symbol combinations are automatically assigned a lightweight hash identifier during expansion. Hash integrity is verified throughout the entire process of symbol combination expansion, invocation, update, and storage to prevent symbol pollution and malicious tampering.

[0054] (4) Multilingual mapping and conflict resolution refers to the construction of a multilingual-symbol bidirectional mapping mechanism, which maps the vocabulary, terminology, and cultural expressions of different natural languages ​​to the same set of core-micro symbol combinations, and physical relationships. Social relations They belong to different dimensions, do not conflict with each other, and resolve independently. They distinguish fields, scenes, and cultural characteristics through micro-symbols, thereby achieving cross-language semantic normalization.

[0055] Establish multi-source symbol conflict resolution rules and clarify conflict trigger thresholds. For example, multi-source symbols should determine node conflicts based on hierarchical priority and semantic matching degree. Heterogeneous nodes with low matching degree should automatically initiate the conflict resolution process. Define access standards for each knowledge source, such as requiring industry standards to be national / international open standards and high-confidence document sources to meet certain confidence levels. ≥0.9, conflicts are resolved according to the priority order of PCD physical fact constraints > system built-in core symbols > industry standard knowledge sources > high confidence document sources > ordinary interactive sources to ensure the consistency of the symbol system.

[0056] (5) Symbol entry control rules refer to the hierarchical entry control implemented after symbol combination expansion. Symbols that pass automatic verification are directly entered into the database; when PCD field symbols are entered into the database, the system automatically filters and removes them. , All micro-symbols except those in the physical and mathematical reasoning are guaranteed to be objective. Symbols that fail to pass or are in key areas will trigger a manual review process. After the review is passed, a compliance mark will be added to the database and the symbol will be effective. When running completely offline on the client side, the symbol to be reviewed can only be used for read-only queries of non-core tasks. After connecting to the network, the review will be automatically uploaded and the results will be synchronized.

[0057] Atomic execution and orchestration module 102: It is used to convert the global unified symbol system into a task dependency graph, construct a dynamic DAG topology through loop detection and redundancy pruning, perform symbol completion for nodes with incomplete symbols based on the similarity matching between the historical context template and the current sequence set, and perform pre-physical fact domain verification and post-social value domain verification in sequence. The deterministic atomic execution is completed through the symbol processing unit STU to form the task execution symbol topology.

[0058] In this embodiment, the globally unified symbol system is converted into a task dependency graph. A dynamic DAG topology is constructed through loop detection and redundancy pruning. For nodes with incomplete symbols, symbol completion is performed based on the similarity matching between the historical context template and the current sequence set. A pre-physical fact domain verification and a post-social value domain verification are then performed sequentially. Deterministic atomic execution is completed through the symbol processing unit (STU), forming a task execution symbol topology, including: The metadata structure in the global unified symbol system is semantically graph-based to identify the logical sequence relationship and data flow constraints between symbol nodes and generate an initial task dependency graph. Based on the initial task dependency graph, loop detection and critical path extraction are performed. Independent subgraphs with parallel execution potential are topologically sorted, redundant intermediate nodes are merged, and a dynamic directed acyclic graph (DAG) is constructed. For nodes in the dynamic directed acyclic graph (DAG) with incomplete input symbols due to missing modes or broken context chains, a scheduling layer symbol completion mechanism is triggered. Based on the dual-domain constraint rules, historical context symbols are retrieved and the corresponding inference operators are matched to complete the placeholders and generate a complete node graph. Symbol completion employs a set similarity matching algorithm. The set similarity matching can be any of Jaccard distance, cosine similarity, or Euclidean distance. This embodiment uses the Jaccard similarity matching algorithm as an example, and the specific steps are as follows: Step 1: Perform n-gram segmentation (n=2) on the current incomplete symbol sequence and the historical context template respectively. Step 2, calculate the Jaccard similarity coefficient between the two n-gram sets: ; Step 3: Select the historical template with the highest Jaccard similarity coefficient that meets the PCD rigidity check; Step 4: Fill the missing positions with the corresponding symbols from the template to complete the symbol completion; The complete node graph is input into the symbol processing unit (STU) to perform rigid verification of the preceding physical fact domain (PCD) and flexible verification of the subsequent social value domain (SCD). The preceding physical fact domain verification covers the compliance of physical laws and the correctness of mathematical logic. If the verification fails, the execution of the current node will be directly blocked. The post-social value domain verification covers industry standard compliance and cultural adaptation appropriateness. If the verification fails, the node parameters are fine-tuned and re-verified. The nodes that pass the dual-domain verification are dynamically weighted and bound to resource slots according to the execution sequence, and the task execution symbol topology is output. The symbol processing unit (STU) performs numerical operations using 16-bit fixed-point processing, converting floating-point data into integer operations based on a preset scaling factor.

[0059] Specifically, the system's core execution engine uses STU as the sole atomic execution carrier. Through a dynamic DAG directed acyclic topology, it completes task symbolization decomposition, symbol dependency establishment, parallelism optimization, redundant link pruning, and execution scheduling, thereby achieving deterministic and reproducible task execution.

[0060] The system integrates a scheduling layer symbol completion mechanism, which completes missing input symbols based on dual-domain constraints and inference operators to solve the problem of execution gaps; it embeds operator scheduling optimization and PCD / SCD dual-domain pre / post-verification logic to ensure compliant and efficient execution; it supports diverse orchestration forms such as serial, parallel, and conditional branching to meet the needs of complex task execution.

[0061] The STU (State-Transform-Unit) is the system's sole atomic execution carrier. It employs a purely functional, stateless design to achieve deterministic atomic execution of tasks. The relational symbols within the STU are automatically mapped to the current execution domain. or No cross-domain mapping, no mixed use.

[0062] PCD / SCD are the Physical-Fact Domain and the Social-Value Domain, the core dimensions of the system's dual-domain constraint system, respectively realizing rigid physical bottom-line constraints and flexible social value constraints.

[0063] A DAG is a Directed Acyclic Graph, the core topology for system task orchestration, which works with STUs to achieve deterministic scheduling and execution of tasks.

[0064] Core-microsymbols is a system-wide unified knowledge representation system, comprising firmware-level fixed core symbols and extensible microsymbols. It enables unambiguous, standardized expression of information across modalities, languages, and scenarios. Microsymbols employ a domain-based activation mechanism: PCD is only enabled. (unit), (Scope) Other micro-symbols are limited to SCD use only. Core symbols, PCD basic rules, and STU execution mechanisms are firmware-level fixed and remain unchanged. Micro-symbol combination rules, DAG execution templates, SCD constraint rules, and scene mapping relationships support controllable expansion.

[0065] The global state index is a comprehensive quantitative indicator used to characterize system operating load, symbol conflicts, and link redundancy. It is calculated by weighting structural complexity, decision path length, symbol reuse rate, and constraint satisfaction, and its value range is [not specified]. It is used for system resource scheduling and operational stability monitoring.

[0066] Among them, the PCD / SCD dual-domain constraint system is a dual security and compliance system that builds rigid physical fact constraints and flexible social value constraints. It adopts a hierarchical pluggable design to embed security mechanisms into the entire system process, achieving unbreakable bottom-line protection and flexible scenario adaptation.

[0067] PCD (Physical-Fact Domain) constraints adopt rigid baseline constraints and are graded into core layer and extension layer: the core layer firmware is embedded in the on-chip ROM of the terminal chip, with no software modification interface, and covers physical laws, device operating thresholds, factual accuracy, execution timing and logical compliance constraints; the extension layer consists of industry-specific fact rules, which are encapsulated as independent plug-in packages and support on-demand loading / unloading.

[0068] Use constraint symbols +Entity symbol E +Attribute symbol A +Physical relation symbol +Optional / Symbolic representation, where It is used to express mathematical operations, physical laws and logical relationships. It does not have any micro symbols attached. It adopts a lightweight verification algorithm to adapt to the lightweight requirements of the end side. If it fails the PCD verification, it will directly block the execution.

[0069] SCD (Social-Value Domain) constraints adopt flexible adaptive constraints, and are hierarchically divided into core layer, extension layer and custom layer: the core layer is enabled by default and cannot be uninstalled; the extension layer consists of group specifications and industry standards, which are packaged as regional / industry plug-in packages; the custom layer consists of user-personalized rules, which support plug-in configuration and import / export.

[0070] Covering four dimensions—industry standards, cultural adaptation, and scenario / individual preferences—it achieves precise compliance determination through layered weighted quantitative scoring. For example, the weight of sub-dimensions is ≥50%, and the weights of industry standards, cultural adaptation, and scenario / individual preferences are dynamically allocated according to the scenario. Cultural adaptation differences between different countries / regions are quantified and adapted through region-specific plugin packages. Symbolic representation is completed using constraint symbol C_S + entity symbol E + attribute symbol A + social relationship symbol Rs + adaptation micro-symbols. When the scenario is adaptively optimized, the compliance scoring weight is adapted simultaneously to ensure that the bottom line is not breached.

[0071] Dual-domain collaborative verification and handling is used to verify the entire process of the system. Following the PCD priority principle, a four-level hierarchical handling strategy is formulated. For different types of violations, measures such as partial rollback, core function locking, adaptive adjustment + logging, blocking + manual intervention are implemented. All verification behaviors and handling results are recorded according to the aforementioned hash chain storage rules.

[0072] The STU (Small State Transition Unit) is a fundamental cognitive operator. It employs a pure functional, stateless, and firmware-based design, possessing core characteristics of atomicity, determinism, security, and lightweight operation. Under the same input, hardware environment, and system state, it will always produce a unique output. It can run stably on low-computing-power embedded hardware. The relational symbols within the STU automatically correspond to the current execution domain. or No cross-domain mapping, no mixed use.

[0073] The STU is a fixed ternary structure, including an input symbol port, state transition logic, and an output symbol port. It uses core-micro symbols as input and output carriers to complete deterministic atomic transformations of entity states, temporal processes, and causal relationships. The transformation logic is explicitly defined as a deterministic state transition mapping based on a preset rule base. Example: Input symbol E000001 + A200001 → Output symbol R400001. It follows a three-step closed-loop execution process of symbol input reception → deterministic transformation → output symbol + hash identifier, and does not undertake additional functions such as verification, completion, or scheduling.

[0074] STU's supplementary hardware difference adaptation solution: floating-point operations are uniformly transformed to 16-bit fixed-point, such as a numerical scaling ratio of 1:1000, with a precision loss of ≤2%. Clock jitter is compensated through a task synchronization mechanism, such as synchronizing the system clock once every 10 execution cycles to ensure consistent execution results under different hardware environments.

[0075] The preset scaling factor can be selected according to the hardware precision requirements. This embodiment takes 1:1000 as an example for explanation. For low-computing-power hardware that does not support floating-point arithmetic units, fixed-point processing is a preferred way to achieve deterministic execution. However, the core feature of STU is its pure functional, stateless deterministic transformation mechanism, which is not limited to specific numerical precision.

[0076] The system stores the STU entity in a fixed state, dynamically assembles it into an inference digest for evidence storage based on the ID during runtime, and releases temporary resources after the task is completed to ensure lightweight operation of the system.

[0077] (2) The five basic cognitive operators are system-level independent service components that run in the atomic execution and dynamic orchestration layer. They follow the principles of minimum completeness, pure function execution, standardized interface, and lightweight implementation. They have no functional overlap and can be freely combined to cover the intelligent processing needs of the whole scenario.

[0078] Specifically, it includes: a matching operator for symbol / semantic matching determination; an inference operator for deterministic logical inference; an update operator for system state evolution; a verification operator for dual-domain constraint determination; and an execution operator for physical execution transformation, forming a logical closed loop of matching-inference-verification-update-execution to ensure that the execution process is interpretable, reproducible, and auditable.

[0079] The dynamic DAG topology and STU template identifier orchestration mechanism follows the principles of directed acyclic, node uniqueness, symbol-driven, dynamic reconstruction, and lightweight scheduling, eliminating infinite loops. It can adjust the link structure in real time according to input changes and scenario switching, and is compatible with low-end end-side hardware. (1) STU template identification fully automatic orchestration process: realizes fully automatic orchestration of tasks from decomposition to execution without manual intervention: ① task symbol decomposition; ② symbol dependency generation; ③ symbol pre-completion and integrity verification; ④ PCD / SCD dual-domain constraint precise embedding; ⑤ automatic parallelism optimization; ⑥ redundant link pruning; ⑦ topology solidification and caching.

[0080] (2) Core operating mechanism: Symbol-driven execution is adopted. Execution starts as soon as all input symbols of the STU arrive, and the output symbol triggers the immediate start of the downstream STU, improving resource utilization. It supports dynamic real-time reconstruction and fault self-repair. When the input symbols change or the link breaks, the breakpoint is quickly located and the missing symbols are automatically filled in. The sub-topology reconstruction is completed synchronously without interrupting the core task. The execution trajectory is recorded throughout, and only the STU template ID, inference trace fingerprint and verification result summary are retained for audit traceability. Temporary DAG topology and real-time STU template identifiers are released immediately after the intermediate execution trajectory task ends and are not stored for a long time.

[0081] Define the criteria for redundancy: links with unsigned flow ≥ 50ms or a contribution to task completion < 0.1 are considered redundant. Pruning uses a greedy algorithm, with the core steps being: ① Traverse all links in the current DAG; ② Calculate the contribution of each link using the formula: Contribution = Frequency of symbol flow in the link / Total flow frequency; ③ Sort the links in ascending order of contribution; ④ Start pruning from the link with the lowest contribution until there are no redundant links or the core links are unaffected.

[0082] Global State and Resource Scheduling Module 103: Used to collect computing load, memory access locality, topological dependence and energy consumption characteristics, generate a four-dimensional resource quantization vector, perform resource reallocation when deviating from the steady state benchmark, and allocate memory according to a preset hierarchical ratio to form a three-level storage structure of short-term working memory, medium-term cache memory and long-term knowledge memory, so as to realize lightweight operation on the edge.

[0083] In this embodiment, data on computational load, memory access locality, topological dependence, and energy consumption characteristics are collected to generate a four-dimensional resource quantization vector. When the data deviates from the steady-state baseline, resource reallocation is performed, and memory is allocated according to a preset hierarchical ratio to form a three-level storage structure of short-term working memory, medium-term cache memory, and long-term knowledge memory, achieving lightweight operation on the edge. This includes: The system receives the task execution symbol topology and collects in real time the task queue depth, memory page access hit rate, data flow dependency span, and instantaneous power consumption fluctuation value of each computing node.

[0084] The computational load quantification metric is the ratio of the current task queue depth to the maximum task queue depth; the memory access locality quantification metric is the memory page access hit rate; the topology dependency quantification metric is the ratio of the data flow dependency span to the maximum allowed dependency span; and the energy consumption quantification metric is the ratio of instantaneous power consumption to rated power consumption. These metrics are concatenated to form a four-dimensional resource quantification vector.

[0085] The four-dimensional resource quantization vector is received, and the deviation gradient of each dimension quantization index in the vector from the preset steady-state benchmark is calculated. If the deviation gradient of any dimension exceeds the dynamic tolerance threshold, the corresponding resource redirection instruction set is generated.

[0086] The system receives the resource redirection instruction set, parses the target resource identifier and priority weight in the instruction set, performs binding migration and slot reallocation on idle computing cores, secondary cache blocks and memory page frames through a dynamic priority queue, and outputs a resource remapping configuration table.

[0087] The system receives the resource remapping configuration table and historical scheduling performance feedback data, updates the dynamic tolerance threshold and weight allocation coefficient based on the gradient descent algorithm, writes the updated parameters back to the scheduling strategy library, and outputs the iterative resource scheduling benchmark.

[0088] Specifically, the system includes a global scheduling hub and a data management core. The core includes a global resource scheduling hub submodule, which is responsible for real-time monitoring of global operating status, dynamic scheduling of computing power and memory resources, management of a three-level memory system, automatic knowledge acquisition and expansion coordination, autonomous behavior planning and feedback, and fault tolerance and breakpoint recovery.

[0089] Embedded global state indicator optimization and control logic, real-time monitoring of four-dimensional quantification values, triggering directional disorder optimization strategy when exceeding thresholds; coordinating the collaborative evolution process of automatic knowledge acquisition and expansion, promoting system capability iteration according to the priority of symbol layer-parameter layer-process layer, ensuring that the evolution process is controllable and traceable.

[0090] Leveraging a three-level lazy-loaded memory system and a lightweight consistency protocol, it achieves extremely lightweight storage and data synchronization on the edge. Differentiated memory allocation strategies are developed for hardware with varying computing power, completely avoiding conflicts between memory resource allocation and physical hardware limits. For ultra-low computing power hardware such as 8-bit MCUs with ≤32KB RAM, a fixed resource allocation scheme is adopted: 25% for working memory, 35% for global state memory, and 40% for hardware safety reserved memory. This rigid allocation mode adapts to the operational limitations of low-specification embedded hardware, deploying only a minimally simplified version and disabling high-computing-power-dependent expansion modules. For medium-to-high computing power embedded chips and x86 architecture devices, a flexible dynamic adapter is enabled. The system controls the working memory interval to 20%-30%, the global state memory interval to 30%-40%, and the redundant reserved memory interval to 30%-50%. The resource ratio can be automatically adjusted according to the device load and operating scenario. In this embodiment, the resource threshold for triggering lightweight operation with an 8-bit MCU is ≤32KB RAM and ≤16MHz. The preset lightweight operation threshold can be adjusted according to the actual hardware specifications. This solution relies on a modular tailored architecture to customize an extremely low hardware tailored version for low computing power devices. It fully deploys the full architecture capability for mid-to-high-end hardware, supports fully offline autonomous operation across the entire domain, and reduces the deployment threshold for different levels of edge hardware through layering.

[0091] Among them, the three-level lazy loading memory system adopts hierarchical storage, on-demand loading, dynamic unloading, and compressed access strategies to achieve the unity of ultra-fast access, lightweight operation, and unlimited capacity, and can run stably on mainstream low-end and mid-range embedded chips.

[0092] (1) Hierarchical storage design Working memory (Level 1): On-chip high-speed RAM, a small-capacity high-speed storage area used for temporary calculations, intermediate results, and core symbol caching for the current task. It is garbage collected by the system kernel after the task ends.

[0093] Global State Memory (Level 2): ​​Off-chip low-speed RAM / Flash temporary partition, medium-capacity storage, used to store lightweight task snapshots, breakpoint fingerprints, audit summaries and compliance results, bound to the complete task cycle, supporting abnormal rollback and breakpoint resumption; non-persistent storage of the complete DAG topology and temporary STU execution link.

[0094] Long-term memory (Level 3): Local Flash / ROM / extended storage, with no theoretical upper limit on capacity, used to store core knowledge such as symbol library, constraint rule library, DAG template, etc., loaded on demand, indexed for acceleration, and permanently resident.

[0095] (2) Collaborative Read / Write and Lazy Loading Process When a task starts, data is loaded in the order of working memory → global state memory → long-term memory. The STU template identifier only interacts with the working memory. The phased state is asynchronously synchronized to the global state memory, and the core results are synchronized to the long-term memory. Constant-level location of compressed data is achieved through slice ID + hash index to ensure efficient access.

[0096] (3) Data consistency guarantee mechanism Adaptive consistency protocols are adopted based on the hardware computing power level, and the specific implementation logic is clearly defined: Low-computing-power hardware (e.g., 8-bit MCU): A single-stage commit + hash check rollback is adopted. The process is as follows: after the working memory data is written to the global state memory, a hash check is immediately triggered (to check data integrity). If the check fails, the system rolls back to the state before the write and records the exception log.

[0097] For medium-to-high computing power hardware (ARM-Cortex-M4 and above): an embedded lightweight two-phase commit (2PC) is adopted. The simplified logic is as follows: the participant preparation and confirmation steps are omitted, and the data is submitted directly. After submission, a secondary hash verification is triggered within a short period of time. If the verification fails, a batch rollback is performed to ensure data consistency.

[0098] (4) Memory storage boundary control The system's long-term memory and global state memory only solidify the core micro-symbol knowledge base, constraint rules, business templates, and audit summaries; STU instances, dynamic STU template identifiers, temporary DAG topologies, and intermediate calculation states generated by real-time reasoning are all temporary resources at runtime, which are automatically deconstructed and recycled after the task is completed and are not persisted; newly generated causal relationships and compliance conclusions are uniformly symbolized twice and then stored in the database.

[0099] The system has a built-in deep debugging mode that can be switched on and off. It is normally off by default to ensure low-load, low-overhead, and lightweight operation. It can only be manually enabled through encrypted authentication when authorized. The complete link log generated by the debugging mode is only temporarily cached locally and is prohibited from being uploaded to the external network or persistently stored. The timer is automatically set after each task ends, and the debugging data is automatically cleared and destroyed after a short time, which takes into account the requirements of fault diagnosis capability, data security, and lightweight design.

[0100] The automatic knowledge acquisition and expansion mechanism enables rule-based autonomous optimization, primarily driven by the client side with minimal human intervention. It automatically iterates system capabilities based on statistical data such as STU template identifier logs and dual-domain validation results, reducing external intervention. This includes: Hierarchical evolution design: Evolution is carried out in a hierarchical manner according to the symbol combination layer - the runtime parameter layer - the scenario adaptation process layer, following the priority of the symbol combination layer > the runtime parameter layer > the scenario adaptation process layer, and skipping levels is prohibited; in addition, the five-layer basic architecture, STU atomic ternary structure, core symbol encoding, and PCD core constraint firmware are fixed at the firmware level, prohibiting independent modification and evolution on the end side, and only starting during low system load periods and when no high-priority modules are running, without preempting core task resources.

[0101] Evolutionary effect evaluation and control: A quantitative scoring mechanism is used to evaluate the evolutionary effect, with a defined scoring model: Total score = Efficiency gain × 0.4 + Accuracy gain × 0.4 + Compliance score × 0.2; an effective threshold is set, such as a total score ≥ 75 points being considered effective evolution; the calculation methods for each indicator are defined: Efficiency gain = (Execution time before evolution - Execution time after evolution) / Execution time before evolution × 100%.

[0102] Accuracy gain = (Number of correct executions after evolution - Number of correct executions before evolution) / Total number of executions before evolution × 100%.

[0103] Compliance score = (Total number of checks - Number of violations) / Total number of checks × 100 points.

[0104] When the target is met and there are no violations, it is considered a valid evolution, and the results are stored in long-term memory. Convergence stopping and performance degradation protection conditions are set. For example, if the total score increases by ≤5% after 3 consecutive evolutions, the evolution will stop. If the accuracy decreases by ≥3%, it will roll back to the historical best state to ensure that the evolution process is controllable and avoid performance degradation.

[0105] Evolutionary data sources and selection rules: Prioritize data with high confidence and high reusability, and remove abnormal and non-compliant data. For example, the criteria for judging abnormal data are: deviation from the mean. If the dual-domain constraint verification fails, ensure the validity of the evolutionary raw materials; the evolution results are cached by scenario / task type, supporting reuse within the same domain.

[0106] Evolutionary outcome tiered review rules: Level 1 evolution (symbol layer combination logic extension) automatically triggers manual review when associated with key scenario tags; Level 2 evolution (parameter layer fine-tuning, process layer optimization) is manually reviewed after autonomous completion on the client side; Level 3 evolution (cross-scenario reuse) must be manually reviewed by domain experts.

[0107] The autonomous behavior realization mechanism follows the principles of human-centeredness, controlled autonomy, traceability, and safe closed loop, achieving a balance between human-defined boundaries and system-autonomous execution, and overcoming the shortcomings of existing AI autonomous behavior, such as loss of control over objectives, unreproducible logic, and ambiguous safety boundaries.

[0108] The core design principle of autonomous behavior is that the goals of all autonomous behaviors originate from human symbolic input, and the system has no interface or logic for autonomously generating goals outside the human-preset boundaries; autonomous behavior is limited to execution and optimization within the human-preset boundaries, and core decisions require human authorization; the entire process is symbolically recorded, and dual-domain constraints provide full coverage.

[0109] The core execution process of autonomous behavior pairs includes: Target symbolization input: Humans input natural language targets, which are converted into standardized target symbol combinations, and autonomous behavior is initiated after verification.

[0110] Autonomous planning and orchestration: Retrieve the three-level memory and global state, generate candidate execution paths, select the optimal path and orchestrate exclusive STU template identifiers, and generate a unique digital signature for traceability.

[0111] Autonomous execution and feedback: STU template identifiers are executed according to orchestration logic, and the execution status is collected in real time and deviations are corrected.

[0112] Self-repair of anomalies: Minor anomalies can be self-repaired by symbol completion, rollback, and reconstruction of short links; severe anomalies will immediately block execution, trigger alarms and log retention, and wait for manual intervention.

[0113] The global status indicator optimization mechanism, from the perspective of quantitative control of system disorder, implements real-time monitoring and targeted optimization of the overall system operation status, maintaining a streamlined system architecture, efficient operation, and continuous stability.

[0114] The global status index is a comprehensive quantitative evaluation system designed in an engineering manner that combines the concept of disordered quantification of the system. It focuses on four core aspects of intelligent processing on the edge: architecture topology, decision execution, data storage, and constraint control. It does not involve thermodynamic definitions and only adopts the general design idea of ​​disordered quantification evaluation, which is fully compatible with the lightweight deployment and high real-time business operation requirements of the edge.

[0115] (1) Definition of global status index dimensions The system disorder is decomposed into four quantifiable and operable core dimensions, with the quantifiable values ​​of all dimensions taking values ​​within a certain range. The closer the quantization value is to 0, the more ordered the system is in that dimension; the closer it is to 1, the higher the degree of disorder. Structural complexity is a measure of the disorder of system architecture hierarchy and lightweight task topology, with a core focus on the impact of redundant nodes and invalid links on execution efficiency.

[0116] The global state and resource scheduling module is also used to calculate the structural complexity index C, and the calculation formula is: ,in This refers to the number of redundant nodes, specifically isolated nodes with unsigned inputs / outputs. The number of invalid links refers to empty links that did not participate in symbol circulation. This represents the total number of nodes. The total number of links, C, takes values ​​ranging from... A higher value indicates higher system topology redundancy. When C exceeds a preset threshold, active DAG topology pruning is triggered, and the statistical scope covers all currently running DAG topologies. The correlation mechanism of structural complexity is to trigger active DAG topology pruning when the quantified value exceeds a preset threshold, prioritizing the deletion of isolated nodes and empty links, and simultaneously optimizing node connection relationships to reduce topology complexity.

[0117] The decision path length characterizes the uncertainty of STU template identification and reasoning process, and the degree of dispersion of the confidence of the core focus decision results.

[0118] The calculation logic for decision path length is: Decision path length = 1 - Average decision confidence; where the decision confidence is output by the verification operator based on the verification results of the two-domain constraints, and its value range is... The average confidence level is the arithmetic mean of the decision confidence levels of all STUs within the current task period; this calculation method is an engineered simplification of uncertainty, consistent with the core connotation of probability distribution dispersion.

[0119] The correlation mechanism of decision path length is to trigger parameter layer evolution when the quantized value exceeds the preset threshold, fine-tuning the symbol matching weight of the STU inference operator and the decision threshold to improve decision certainty.

[0120] Symbol reuse rate is a measure of the redundancy of symbol libraries and three-level memory data, with a core focus on the storage resource consumption of duplicate data and invalid information.

[0121] The calculation logic for symbol reuse rate is an optimized implementation based on the information theory data repetition quantification method. ;in This represents the probability of a single data point being repeated. =The number of times the data is repeated / the total amount of data, which is obtained through long-term memory data statistics. Lightweight computing optimization is adapted to the computing power of the edge side, and low computing power hardware uses a lookup table method to simplify the calculation.

[0122] The association mechanism of symbol reuse rate is to trigger intelligent deduplication of memory data when the quantization value is ≥0.4, and to compress and store symbol combinations and constraint rules with high repetition in long-term memory to release storage resources.

[0123] Constraint satisfaction is a measure of the degree of regulatory disorder in PCD / SCD dual-domain constraints, with a core focus on constraint conflicts and the interference of ambiguous rules on compliance execution. The constraint satisfaction rate is normalized and compressed to the [0,1] interval based on the proportion of constraint conflicts and the proportion of fuzzy rules. The formula for calculating the constraint satisfaction rate is: Constraint Satisfaction Rate = Normalized [(Number of Independent Constraint Conflicts + Number of Fuzzy Rules) / Total Number of Constraints]. This formula is consistent with the values ​​of structural complexity, decision path length, and symbol reuse rate. Independent constraint conflicts refer to a single conflict of the same constraint, which is not counted repeatedly. Among them, constraint conflict refers to the situation where the PCD and SCD constraint judgment results are contradictory under the same triggering condition. Fuzzy rules refer to constraint clauses without clear judgment criteria.

[0124] The constraint satisfaction correlation mechanism triggers a constraint system review when the quantified value exceeds a preset threshold. It resolves conflicts according to the principles of PCD priority and core layer constraint priority, supplements the judgment criteria for fuzzy rules, and updates the constraint symbol library synchronously.

[0125] (2) Calculation and monitoring of global status indicators The weighted aggregation method is used to calculate the global status index. The weights are dynamically adapted to hardware computing power and scenario requirements to ensure that the global status index can accurately reflect the system's operating status. The global status center collects data from each dimension in real time at a fixed monitoring cycle, such as the system's preset design threshold, by default every 100ms. It calculates the global status index value and compares it with the threshold range. If the value exceeds the threshold, a directional disorder optimization strategy for the global status index is activated.

[0126] The specific weighting formula for the global state index is as follows: , in , , and The final weights are calculated for the global state and the three-level memory layer, and the sum of the weights is 1.

[0127] Weight dynamic calculation model: Define the hardware computing power coefficient F: F = Actual hardware computing power / Baseline computing power; where the baseline computing power is set as: 8-bit MCU = 80 MIPS, ARM-Cortex-M4 = 168 MIPS, ARM-Cortex-M7 = 1000 MIPS; this coefficient is determined based on the measured computing power data of 10 typical edge hardware types, such as: 8-bit MCU (PIC16F877A, STM8S103), ARM-Cortex-M4 (STM32F407, NXP-LPC1788), ARM-Cortex-M7 (ST... M32H743, NXP-i.MX-RT1052, RISC-V (GD32VF103, ESP32-C3), x86 (Intel-Atom-x5-Z8350, AMD-GX-412TC); Actual test results show that low-performance hardware (8-bit MCU / basic RISC-V) has a computing power 0.5-0.8 times the baseline computing power, medium-performance hardware (ARM-Cortex-M4 / M7) has 0.9-1.5 times, and high-performance hardware (x86 / high-end ARM) has 1.6-2.0 times. Therefore, the range of values ​​for F is set accordingly. It covers the computing power range of mainstream edge hardware.

[0128] Define the scenario importance coefficient S: Assign values ​​to the core requirements of each global state indicator dimension according to the scenario, as shown in the example below: Industrial control scenarios (high reliability): =0.4、 =0.3、 =0.2、 =0.1; Government office scenarios (high security): =0.4、 =0.3、 =0.2、 =0.1; Smart home scenarios (high dynamic range): =0.4、 =0.3、 =0.2、 =0.1; The coefficient is determined based on the edge operation characteristics and general industry requirements of five typical scenarios, such as industrial control, medical monitoring, government office, smart home, and robot interaction. By sorting out the typical characteristics and regular fluctuation patterns of system structure disorder, decision ambiguity, information redundancy, and constraint control disorder in each scenario, the unordered quantification analysis method is used to calculate the impact weight of each dimension on system operating efficiency, and finally determine the S value for different scenarios.

[0129] Calculate the final weights: weights for each dimension Ensure that the weights of the four dimensions sum to 1.

[0130] Weight verification rules: After the weight is adjusted, it must pass the quantitative indicator stability verification - the fluctuation of the quantitative value of the overall status indicator within 10 consecutive monitoring periods must be ≤5%. It can only be officially effective after the verification is passed; if the verification is not passed, it will be automatically rolled back to the weight configuration before the adjustment.

[0131] The hardware benchmark computing power, core symbol global encoding range, and STU basic execution rules are firmware-level fixed parameters, which only support the upgrade of the underlying authorized firmware and prohibit the upper-layer software and the terminal side from tampering with them independently.

[0132] Low-computing-power hardware adaptation optimization addresses the shortcomings of floating-point operations in low-computing-power hardware such as 8-bit MCUs. It adopts a 16-bit fixed-point transformation scheme: all floating-point data is scaled to integer operations at a ratio of 1:1000, and the results are restored by reverse scaling after the operation is completed, ensuring accuracy and avoiding excessive computing power overhead caused by software floating-point operations.

[0133] The normal range for the overall status index is The warning range is The threshold range is : Normal range: Maintain current system operating parameters and perform only routine status monitoring; Warning range: Targeted disorder optimization is performed only on the top two dimensions of contribution to the overall status indicators, without affecting the execution of core tasks; Exceeding the threshold range: Immediately activate the global state indicator targeted optimization strategy and disordered quantification control strategy, suspend level three / four priority modules, such as controllable hierarchical emergence and human-machine collaboration, and prioritize the execution of targeted disordered quantification optimization.

[0134] (3) Hierarchical Directed Disorder Degree Optimization Strategy Targeted disorder optimization takes precedence over automatic knowledge acquisition and expansion mechanisms. If the overall state indicators exceed the warning range, the evolution process is paused, and targeted disorder optimization is prioritized to ensure system stability. 1. Contribution Calculation: The contribution of each dimension to the overall status index is calculated using the formula Contribution = Quantitative value of the dimension × Corresponding weight, and the dimensions are sorted from high to low.

[0135] 2. Targeted Unordered Degree Optimization Execution: Targeted unordered degree optimization operations are performed on each dimension sequentially according to the sorting results. Specific measures are as follows: Structural complexity directional disorder optimization: DAG topology redundancy pruning, node connection relationship optimization, and dynamic adjustment of parallelism.

[0136] Decision path length oriented disorder optimization: STU inference operator parameter fine-tuning, decision confidence threshold calibration, and repeated decision result caching and reuse.

[0137] Symbol reuse rate directional disorder optimization: deduplication and compression of memory data, invalid symbol cleanup, and long-term memory slicing optimization.

[0138] Constraint satisfaction-oriented disorder optimization: conflict constraint resolution, fuzzy rule completion, and redundant constraint elimination.

[0139] 3. Collaborative optimization: For dimensions with strong coupling, such as structural complexity and decision path length, implement collaborative directional disorder optimization to avoid the increase of disorder in other dimensions due to optimization of a single dimension.

[0140] 4. Optimize termination conditions: All domain status indicators drop to the normal range. If the overall status index decreases beyond the threshold for multiple consecutive monitoring cycles, the directional disorder optimization strategy will automatically terminate, and the evolution module and low-priority modules will resume operation.

[0141] Scene Adaptation and Template Service Module 104: This module is an optional additional module used to load industry- or region-specific constraint packages through a unified architecture interface and plugin extension mechanism of the underlying standardized execution results. After business rule tree mapping and dynamic routing transformation, it generates the final output results that meet the business requirements of the target scenario.

[0142] In this embodiment, the underlying standardized execution results are loaded with industry- or region-specific constraint packages through a unified architecture interface and plugin extension mechanism. After business rule tree mapping and dynamic routing transformation, a final output result conforming to the business requirements of the target scenario is generated, including: Upon receiving the controlled system status, the system abstracts and encapsulates the standardized calculation results of the underlying execution engine, symbolic topology resolution logs, and resource scheduling snapshots into APIs and protocols to generate a set of general intelligent service interfaces. The system receives industry or regional identifiers of the target scenario through a unified interface, matches the corresponding exclusive constraint package from the constraint library of the plugin extension mechanism, parses the business rule tree, compliance verification logic and multilingual adaptation parameters in the constraint package, and outputs a scenario-specific configuration set. The output data stream of the general intelligent service interface set is aligned with the scenario-specific configuration set by rules. The standardized data fields are mapped to the business data model of the target scenario through the condition matching engine and dynamic routing table to generate intermediate results for scenario adaptation. The system receives the intermediate results of the scenario adaptation, monitors the business response latency and data format matching degree in real time based on the scenario feature recognition algorithm, dynamically adjusts the plugin loading weight and data conversion threshold, and outputs the final output result that meets the business requirements of the target scenario.

[0143] Specifically, the system application interface and output encapsulation layer encapsulate general intelligent capabilities in an industry-specific and scenario-specific manner, completing functions such as multilingual translation, multi-protocol parsing, and multimodal interaction adaptation. Through a unified architecture and plug-in extension mechanism, it loads industry / region-specific constraint packages and templates, transforming the underlying standardized execution results into the final output that meets the specific business needs of the scenario, thereby reducing the development cost of upper-layer applications.

[0144] It incorporates controlled evolution of embedded translation templates, rapid adaptation to less common languages, and integrated scene-adaptive dynamic optimization logic. It automatically identifies scene characteristics and adjusts execution parameters to achieve optimal operation across multiple scenarios using the same architecture.

[0145] Among them, the cross-domain compatibility mechanism achieves seamless compatibility across multiple modalities, languages, scenarios, and protocols through unified symbolic processing, reducing the cost of cross-domain adaptation. Specifically, it includes: Multimodal compatibility refers to the unified access of multimodal data, lightweight feature extraction, and cross-modal semantic normalization based on the unified multimodal submodule; it supports on-demand pruning and feature dimensionality reduction of multimodal data according to hardware acquisition capabilities, and all multimodal features are ultimately mapped to the same set of core-micro symbol combinations; and the target modality output is achieved through symbol reverse mapping during cross-modal interaction to meet the real-time interaction requirements of the terminal side.

[0146] To improve the accuracy of cross-modal semantic alignment, this method is limited to common scenarios such as industrial control text-sensor data and smart home voice-command, clearly defining the applicable boundaries of the indicators and conforming to the performance limits of lightweight edge-side algorithms.

[0147] Multilingual compatibility refers to the use of phoneme / graphite-level splitting + unified symbol mapping + grammar normalization strategy to support, but not limited to, common languages, professional terms, dialect variants and niche languages; when there is no complete vocabulary, the micro-symbol automatic expansion engine is enabled to quickly complete the adaptation of niche languages, and the uncovered terms are included in the official symbol library after manual review.

[0148] Multi-scenario compatibility refers to the system automatically matching adaptation strategies through scenario label recognition and hardware capability detection, implementing customized optimizations for different types of scenarios such as high reliability, high security, and high dynamism, with automatic switching of adaptation strategies without manual intervention.

[0149] Multi-protocol compatibility refers to building a unified protocol parsing layer, which uses standardized protocol adapter plugins to convert protocols from multiple fields such as industrial control, medical data, and consumer electronics into standardized core-micro symbol streams, enabling protocol-agnostic deterministic execution. Adding new protocol adapters only requires developing the corresponding protocol-symbol mapping plugins, without needing to reconstruct the core architecture.

[0150] The controllable hierarchical emergence mechanism is completely decoupled from the STU+DAG deterministic core execution engine, serving only as an additional auxiliary function. Emergent outputs are for reference only; they cannot modify the main process symbol flow, interfere with STU template identifier arrangement, or override PCD / SCD dual-domain constraint judgments. They operate entirely in isolation, achieving controllable, interpretable, and auditable innovative suggestion outputs under PCD / SCD dual-domain constraints. Specifically, this includes: (1) Core control system It adopts a triple collaborative management system of disorder control, rule switch, and plug-in plug-in. The disorder control dynamically adjusts the degree of innovation freedom based on the global status index value, the rule switch realizes the real-time start and stop and authorization binding of global / hierarchical emergence, and the plug-in plug-in supports the on-demand loading / unloading of emergence functions.

[0151] (2) Three-level emergent architecture The system is designed with three levels of innovation output: Level 1, Level 2, and Level 3, to adapt to scenarios such as daily conversations, content creation, and complex decision-making. The threshold range is dynamically adjusted based on hardware computing power to ensure that the computing power consumption of innovation output does not exceed a reasonable proportion of the remaining hardware computing power. Scenario adaptation rules are established, and some innovation output functions are automatically shut down or disabled in high-reliability and high-security scenarios. A security guarantee mechanism is established to ensure the compliance and controllability of innovation output through multiple dimensions, including constraint fallback, circuit breaker degradation, symbol control, and traceability auditing.

[0152] Semantic novelty ≥ 30%, defined as 1 - cosine similarity with existing symbol combinations in the system, calculated based on a 128-dimensional feature vector of core-micro symbol combinations; Differentiation rate ≥ 10%, defined as the number of differences between the cross-domain solution and the existing solution / the total number of existing solutions × 100%, where differences include functional coverage, execution efficiency, and scenario adaptability, and a quantitative model for clearly defined innovation indicators is established.

[0153] For the weak emergence function of low computing power hardware, the probability weighted operation adopts 16-bit fixed-point transformation, such as a numerical scaling ratio of 1:1000, with an accuracy loss of ≤2%, to ensure that the computing power overhead meets the design requirements.

[0154] The scenario-adaptive and dynamic tuning mechanism automatically identifies scenario characteristics and hardware status, dynamically adjusts core operating parameters, and achieves performance and resource balance of the same architecture in multiple scenarios. This includes: Scene recognition and status awareness: The system automatically identifies scene type and operating status through three-dimensional data fusion of scene label dimension, task feature dimension and hardware status dimension, without human intervention.

[0155] The core strategy for dynamic optimization is to adjust the execution priority, verification strength, parallelism, and caching strategy in a targeted manner according to different scenario characteristics. All parameter adjustments must be coordinated with the dual-domain constraint parameters to ensure the consistency of the underlying constraints.

[0156] Tuning trigger and execution logic: Tuning triggers include scene label switching, hardware load fluctuations, task type changes, and system startup initialization; the core task execution is not interrupted during the tuning process, and parameter adaptability is verified by monitoring the global status index value and double-domain constraint verification after tuning. If the adaptability fails, it will roll back to the default optimal parameters.

[0157] The human-machine collaboration and feedback iteration mechanism, through symbolic feedback access and dynamic decision boundary delineation, enables precise transmission of human intent and continuous upgrading of system capabilities, including: Feedback symbol standardization conversion: Human feedback is converted into a standardized core-micro symbol combination through unified symbols and knowledge layers to ensure that the intention of feedback is conveyed unambiguously.

[0158] Collaborative decision-making boundaries: The scope of autonomous execution and manual review is dynamically divided according to the task level. Low-risk tasks are executed autonomously, medium-risk tasks trigger manual confirmation after execution, and high-risk tasks require manual authorization before execution.

[0159] Feedback Iteration Closed Loop: Symbolic feedback is directly integrated into the STU template identification orchestration logic and parameter optimization process, and compliance feedback is stored in long-term memory to achieve continuous iteration of execution results.

[0160] Priority adaptation: This module has a four-level priority. When a high-priority module is triggered, the feedback iteration process is paused.

[0161] When this module is omitted from deployment, the standardized execution results output by the system atomic execution and orchestration module 102 can be directly output to the outside world through the system's general data interface without needing to undergo scenario-based adaptation and conversion, which can meet the usage requirements of basic general scenarios.

[0162] Security adaptation module 105: It is used to perform security mechanism pruning according to the computing power level of the terminal hardware, perform integrity verification and access control on the execution results, and record audit logs using a three-level chain structure of bottom node hash, intermediate block hash and top root hash, so as to obtain the three-level chain structure that is tamper-proof and traceable throughout the entire link.

[0163] In this embodiment, security mechanisms are pruned based on the computing power level of the edge hardware, integrity checks and access control are performed on the execution results, and an audit log is recorded using a three-level chain structure of bottom-level node hash, intermediate block hash, and top-level root hash, resulting in a fully tamper-proof and traceable three-level chain structure, including: The final output result is received, and the digital signature verification and content digest comparison of the data packet are performed using an asymmetric encryption algorithm. After the verification is passed, the redundant transmission header is stripped to generate a verified secure data stream. Receive the verified secure data stream, perform permission matching based on the target terminal's identity identifier and a preset access control matrix, perform fine-grained data desensitization or route interception, and output a controlled access data stream; The system receives the controlled access data stream, reads the instruction set architecture, available memory capacity and real-time clock frequency of the current edge processor through the system's underlying hardware abstraction layer, and automatically triggers the functional module on-demand pruning strategy when it detects that the available resources of the current edge hardware are lower than the preset lightweight operation threshold. Only the core symbol resolution, STU atomic execution, PCD physical fact domain verification and lightweight hash verification modules are retained, the encryption operation iteration frequency of the security mechanism is reduced, and a lightweight security execution package adapted to the current hardware platform is generated. Receive the runtime logs and access audit records of the lightweight security execution package, call the hash chain storage protocol to serialize and encrypt the log data and package it into blocks, and generate an initial audit hash chain; The three-level chain structure is constructed as follows: calculate the node hash value for each single operation record and concatenate them into the underlying hash sequence according to the time sequence; The hashes of consecutive nodes are assembled into a Merkle tree according to the preset block capacity, and the block header hash is calculated to form a set of intermediate block hashes; The new block header hash and the historical root hash are chained together to generate the top-level root hash, which is then stored in the local encrypted audit area to obtain the three-level chain structure that is tamper-proof and traceable across the entire chain.

[0164] Specifically, the system includes a landing assurance and security compliance layer, which is responsible for hardware abstraction and platform adaptation, full-link hierarchical anti-tampering, operation auditing, log storage and security alarms, and adapts to the full spectrum of edge hardware from low-computing-power embedded chips to high-performance processors, meeting the requirements of high-security scenarios.

[0165] The system embeds dynamic hardware resource scheduling and lightweight deployment optimization logic. It shields hardware differences through standardized driver interfaces in the hardware abstraction layer, supporting modular functional tailoring and adaptive parameter adjustment for scenarios with extremely low computing power. It achieves seven-dimensional full-link anti-tampering protection from symbol to execution to memory to translation to the edge. All operation logs are stored in a hash chain, which is linked in three levels: bottom execution unit hash → intermediate block hash → top root hash. It can only be appended and cannot be modified, meeting compliance audit requirements.

[0166] The end-to-end lightweight anti-tampering mechanism adopts a hierarchical protection, lightweight algorithm, and full-process coverage strategy, balancing high security with lightweight edge-side operation. It constructs a one-way anti-tampering hash chain to perform end-to-end integrity verification on core data such as STU template identifiers, DAG topology structures, and symbol libraries. Specifically, this includes: The core protection architecture consists of a hash chain consisting of three levels: bottom-level execution unit hash, intermediate block hash, and top-level root hash. The top-level root hash serves as the system's root of trust. The primary copy is stored in an on-chip read-only encrypted partition, while the backup is stored in a writable encrypted Flash partition. It supports secure updates and only performs hash chain-based notation on STU template identifiers, symbolic inference results, dual-domain compliance conclusions, and unique task digests. It does not perform complete and fixed storage for instantaneous STU instances or the entire temporary inference chain.

[0167] Methods for implementing graded protection: Level 1 protection (core hardening): The core data is hardened at the hardware level on the on-chip ROM, with no software modification interface.

[0168] Level 2 protection (hash chain protection): Dynamic data is protected by hash chain to ensure integrity throughout its entire lifecycle.

[0169] Level 3 protection (tiered real-time verification): The timing and method of verification are set according to the importance of the data. Core data is verified in real time on a single piece, and dynamic data is verified in batches.

[0170] Tampering classification and handling: Differentiated handling is implemented for minor, moderate and severe tampering. All handling actions are recorded in accordance with the aforementioned hash chain storage rules, which are traceable and verifiable, reducing the detection rate of core data tampering, conforming to the practical application boundaries of cryptographic algorithms, and avoiding absolute statements.

[0171] Fault prediction and proactive protection mechanisms upgrade from passive repair to proactive avoidance by identifying and intervening in early fault symptoms, thereby improving the system's continuous operation capability. This includes: Fault precursor identification: Based on historical data in the three-level memory, a fault prediction model is constructed. The model type is defined as a lightweight decision tree, with core features including CPU load, symbol missing frequency, and number of verification failures. The model training and deployment logic is as follows: offline training on the client side based on historical logs, which is then solidified into a rule base. Fault precursor features are monitored in real time, and anomaly quantification standards are defined, such as: Abnormal hardware load: CPU load ≥90% for 3 consecutive monitoring cycles, or memory usage ≥85% for 2 consecutive monitoring cycles.

[0172] Symbol missing anomaly: Symbol missing frequency ≥ 2 times / 100ms.

[0173] Verification failure exception: Three consecutive failures of dual-domain constraint verification, or a single failure of core data hash verification.

[0174] Early warnings are categorized into low, medium, and high risk levels to ensure that the accuracy and false alarm rates meet the needs of edge applications.

[0175] Proactive protection strategy: Implement targeted prevention for different fault types, and ensure that the core task execution is not interrupted during the protection process. Risk avoidance is achieved through parameter adjustment and resource pre-allocation. This mechanism is a first-priority mechanism and strictly controls computing power consumption.

[0176] Protection effectiveness guaranteed: The fault tolerance rate in high-reliability scenarios meets the industry's high standards. All protection behaviors are recorded according to the aforementioned hash chain storage rules, supporting subsequent traceability and strategy optimization.

[0177] This invention adopts a five-layer unified architecture and a fully closed-loop intelligent processing architecture with core technology modules. The architecture and mechanism are deeply embedded and integrated, with no independent external modules. It is compatible with various hardware deployment environments such as edge, cloud, and terminal, and is especially suitable for resource-constrained terminal embedded platforms such as 32-bit embedded MCUs.

[0178] For platforms with extremely low resources (such as 8-bit MCUs with RAM ≤ 32KB), strictly enforce fixed memory allocation rules (25% working memory, 35% global state memory, and 40% reserved memory). Only STU execution, PCD core constraints, and basic audit subsets can be retained, supporting only the deployment of core security functions and not running complete system modules.

[0179] From top to bottom, the layers are: unified symbol and knowledge layer, atomic execution and dynamic orchestration layer, global state and three-level memory layer, scenario adaptation and template service layer, and edge deployment security and audit layer. Each layer has clear functional boundaries and standardized interfaces. It only supports direct interaction between adjacent layers. Cross-layer calls require authorization from the global state hub. This achieves the separation of data and logic, execution and control, and general architecture and scenario requirements, which conforms to the scientific principles of a general intelligent underlying architecture: fewer layers, decoupling, orthogonality, and scalability.

[0180] Unified Symbols and Knowledge Layer: Input standardization processing, including multimodal data access, symbol binding, semantic alignment, and standardization transformation; Atomic Execution and Dynamic Orchestration Layer: Deterministic task execution, including task decomposition, STU template identification orchestration, and execution scheduling; Global state and three-level memory layer: resource and evolution management, including resource scheduling, three-level lazy loading memory management, and controllable knowledge expansion coordination; Scene adaptation and template service layer: Scene-based output encapsulation, including industry-specific adaptation, multilingual translation, and protocol parsing; Deploy security and audit layers on the device side: ensure security compliance, including hardware adaptation, anti-tampering, and log storage.

[0181] This architecture is deeply coupled with the hardware storage system (ROM / RAM / Flash / cach) and computing units. The core logic can be embedded in the hardware, and the data interaction and scheduling mechanism is adapted to the resource characteristics of different hardware environments. It does not depend on a specific deployment location and has the ability to be deployed across hardware and platforms.

[0182] This plan is divided into a core security layer followed by system optimization and then additional features, with priority levels from highest to lowest: First-level priority (core protection): STU template identification, DAG orchestration, PCD constraint verification, fault prediction and active protection; Second-level priority (system optimization): optimization of global status indicators, end-to-end anti-tampering (core data), global status monitoring, and three-level memory management; Level 3 Priority (Additional Functions): SCD Constraint Validation, Cross-Domain Compatibility, Automatic Knowledge Acquisition and Expansion, Scenario Adaptation and Dynamic Optimization; Four-level priority (innovative functions): controllable hierarchical emergence, human-machine collaboration, and feedback iteration.

[0183] Note: High-priority modules can preempt low-computing-power resources, and low-priority modules will resume operation after high-priority modules have finished executing; when global status indicator optimization is triggered, level 3 / 4 priority modules will be automatically paused.

[0184] The core module's collaboration logic in this solution is: Multiple core technology modules work together in a deep, five-layer unified architecture, following the principle of computing power allocation priority, to form a fully closed-loop, self-consistent edge-side general intelligent processing flow: External multimodal inputs are standardized and converted through a unified symbol and knowledge layer; atomic execution and dynamic orchestration layers enable deterministic execution and fault repair; global state and three-level memory layers provide resource scheduling, memory support, and autonomous optimization; a global state indicator optimization mechanism regulates system disorder in real time; the execution process is protected by PCD / SCD dual-domain constraints and a full-link anti-tampering mechanism; a cross-domain compatibility mechanism enables multi-dimensional, non-discriminatory adaptation; a controllable hierarchical emergence mechanism outputs compliant and innovative suggestions; a human-machine collaboration and feedback iteration mechanism completes the transmission of human intent and system optimization; a fault prediction and proactive protection mechanism monitors and avoids risks throughout the process; finally, the results can be selectively encapsulated into scenario-based output results through a scenario adaptation and template service module (optional), or directly output standardized execution results, with the security and audit layer deployed on the edge side completing hardware adaptation and secure evidence storage.

[0185] The entire process uses standardized core-micro symbol flow interaction, with no implicit dependencies, no data heterogeneity, and no semantic ambiguity, to achieve interpretable, reproducible, auditable, and traceable general intelligent processing on the edge. All core mechanisms have been embedded and lightweight optimized to adapt to resource-constrained edge hardware environments.

[0186] The following describes the implementation of the present invention in conjunction with specific application scenarios: (I) Implementation of 8-bit MCU industrial temperature monitoring scenario Hardware environment: STM8S series MCU, RAM=32KB, main frequency=16MHz, equipped with DS18B20 temperature sensor.

[0187] System configuration: Lightweight trimming mode is enabled, with memory allocated as 20% working memory, 35% state memory, and 45% reserved memory. Only the core subset of the unified symbol and knowledge module, atomic execution and orchestration module, global state and resource scheduling module, and security adaptation module are loaded.

[0188] Execution process: Step 1, the sensor collects temperature data of 150.5℃, and after protocol parsing, the encapsulation head is stripped and mapped to a unified tensor space; Step 2: Extract the core symbols (entity symbol E000001 reactor, attribute symbol A200001 temperature) and generate micro symbols (units). 001℃, range (001-0-200℃), constructing a two-layer symbolic representation; Step 3: Detect synonym conflicts, retain the system's built-in core symbols according to priority rules, and establish synonym mapping relationships; Step 4, STU performs temperature threshold verification: input symbol combination (E000001, A200001, μ-R001) → rule base matching → output safety status symbol, and construct a single-node DAG topology; Step 5: Perform PCD verification to confirm that the temperature value meets the physical threshold range; Step 6: Calculate the node hash value and generate an audit fingerprint according to the three-level chain structure; Step 7: Output the temperature monitoring results to the display module.

[0189] It is used only for scene matching and scheduling. The atomic execution and dynamic orchestration layer arranges STU template identifiers according to the dynamic DAG topology and executes industrial control instructions. The global state and three-level memory layer monitor the equipment operating status in real time. The global state index optimization mechanism is based on the industrial scene S assignment. =0.4 and the hardware computing power coefficient F are used to calculate the weight, maintaining the system's low disorder operation; the fault prediction and active protection mechanism monitors early warning characteristics such as hardware load and missing symbols, and avoids execution risks in advance.

[0190] Results: The system uses ≤28KB of memory, has a single inference latency of ≤10ms, and runs continuously for 72 hours without memory overflow, meeting the real-time monitoring needs of industrial low-computing-power hardware.

[0191] (II) Implementation in Medical Monitoring Scenarios Hardware environment: High-performance embedded hardware with DSP acceleration is used to deploy a full-featured system (including scene adaptation and template service modules).

[0192] Core configuration: Enable PCD / SCD dual-domain full-process triple verification, SCD core layer weight ≥60%, dual STU redundant deployment; locally encrypted cache of physiological data, and automatically clean up sensitive data after the task ends; Key process: Data such as heart rate and blood pressure collected by physiological sensors are converted into standardized symbols by the multimodal unified submodule, and then labeled with scene tags and micro-symbols. The STU template identifier performs data processing and anomaly detection according to medical monitoring rules; if an abnormal physiological parameter is detected, a local alarm is immediately triggered and a log is recorded, and core decisions require authorization from medical staff.

[0193] Security and compliance: A full-chain anti-tampering mechanism ensures the integrity of physiological data and execution logs, and symbol entry into the database is subject to strict manual review to meet medical data compliance requirements.

[0194] Results: Reduces physiological data processing latency, improves anomaly detection accuracy, ensures highly reliable operation to meet the needs of medical scenarios, and reduces the risk of data leakage.

[0195] (III) Implementation of embodied robot scenarios Hardware environment: It adopts medium-to-high computing power embedded hardware (ARM-Cortex-M7 core + dedicated motion control chip) and deploys a full-featured system (including scene adaptation and template service modules); it is equipped with multi-modal sensors, including vision camera, tactile sensor, voice module and odometer. The hardware supports synchronous acquisition and real-time transmission of multi-sensor data, with RAM≥256KB and Flash≥1MB to meet the computing power requirements of robot motion control and multi-modal interaction.

[0196] Core configuration: Enable PCD constraint core layer (including robot motion physical limit constraints, such as joint rotation angle ±120°, movement speed ≤0.5m / s) and service scenario extension layer; SCD constraint loading core layer + human-computer interaction extension layer (including obstacle avoidance priority, voice interaction politeness rules); enable weak + medium emergence plugins to adapt to interactive dialogue optimization and simple task planning innovation output; the three-level memory memory allocation ratio is 25% working memory, 35% global state memory, and 40% reserved memory, and long-term memory preloads robot motion template library, common object recognition symbol library, and human-computer interaction scenario topology template.

[0197] Key processes: Multimodal input standardization: Visual sensors acquire environmental images, such as a water cup; voice modules receive user commands to "get the water cup on the table"; tactile sensors collect contact pressure data. This data is then converted into a core-micro-symbol combination via a unified symbol and knowledge layer: entity symbol E000050 (water cup), intent symbol R400100 (grasp), and scene label micro-symbols. -05-0003 Human-Computer Collaboration - Object Grasping, Range Micro-symbols (≤5N) safe contact threshold, ensuring information consistency through cross-modal semantic alignment.

[0198] Task orchestration and deterministic execution: The global state center parses the target symbol combination, retrieves the grasping task DAG template from long-term memory, and the atomic execution and dynamic orchestration layer automatically completes symbol dependencies, such as the water cup position coordinates → robotic arm motion path. It orchestrates STU template identifiers, environment recognition STU → path planning STU → motion control STU → haptic feedback STU, and embeds PCD constraints, such as joint angle and motion speed verification, and SCD constraints, such as obstacle avoidance priority verification. During execution, STUs are triggered according to the symbol-driven mechanism, the motion control STU outputs standardized control commands to drive the robotic arm to move along the planned path, and the haptic feedback STU monitors the contact pressure in real time to ensure that it meets the safety threshold.

[0199] Autonomous optimization and innovative output: The global state index optimization mechanism is based on the robot scenario S assignment. =0.4 =0.3、 =0.2、 =0.1 and the hardware computing power coefficient F are used to calculate the weight, and the redundancy of the path planning link is adjusted in real time (structural complexity oriented disorder optimization) and the decision confidence (decision path length oriented disorder optimization); the knowledge automatic acquisition and expansion mechanism optimizes the motion parameters and dialogue templates based on the success rate of crawling and the interaction satisfaction data during low load periods; the controllable hierarchical emergence mechanism outputs 2-3 sets of task planning suggestions for users' fuzzy commands, such as help me organize my desktop, such as first grab the water cup → then put away the files → finally wipe the desktop. All innovative outputs are provided as suggestions after PCD / SCD dual-domain verification.

[0200] Safety and fault protection: The end-to-end anti-tampering mechanism performs hash verification on motion control commands, sensor data, and execution logs; the fault prediction and active protection mechanism monitors the joint motor load in real time. If the CPU load is ≥85% for two consecutive cycles, an early warning is triggered. If there are any warning signs such as missing symbols or failure to recognize objects, the backup motion template is activated in advance or an obstacle avoidance emergency response is triggered. If a collision risk is detected, such as PCD constraint violation, a motion interruption command is immediately triggered, the core functions are locked, and the audit log is recorded.

[0201] Cross-domain adaptation: The robot motion control bus protocol, such as CANopen, and sensor data transmission protocols, such as I2C, are parsed through a multi-protocol compatibility mechanism and uniformly converted into a standardized symbol stream; the multi-language compatibility mechanism supports dialect interaction, such as Cantonese and Sichuanese, and achieves accurate command recognition through phoneme decomposition and symbol mapping; the scene adaptation mechanism dynamically adjusts the motion path planning parameters according to environmental changes, such as the increase of obstacles on the desktop, without the need for manual intervention.

[0202] Results: Improves the success rate of robot grasping tasks, reduces motion control response latency, improves the accuracy of human-computer interaction semantic understanding, reduces fault tolerance, enables cross-scene migration, such as expanding from grasping a water cup to grasping a book, with a cycle of ≤3 days, significantly reduces the cost of scene customization development for embodied robots, and enhances the safety and naturalness of human-computer collaboration.

[0203] Compared with existing technologies, this solution adopts a five-layer unified architecture plus hardware-independent core modules, which deeply integrates architecture and mechanism, improves the functional reusability of core modules, reduces cross-scenario migration cycle, and supports general deployment in multiple environments.

[0204] Compared with existing technologies, this solution achieves atomic and deterministic execution through STU+dynamic DAG, enabling reproducible results under the same input and environment, thereby improving execution speed and reducing computational overhead.

[0205] Compared with existing technologies, this solution improves the detection rate of core data tampering and reduces protection costs by adopting an embedded security system with PCD / SCD dual-domain constraints and full-link hierarchical anti-tampering, providing both physical and value-based safeguards.

[0206] Compared with existing technologies, this solution uses a hierarchical and controllable knowledge expansion mechanism with the edge as the main source and light human intervention, without relying on the cloud or manual annotation.

[0207] Compared with existing technologies in terms of cross-domain adaptation, this solution uses a core-micro-symbol system as a unified data foundation, including scene tag micro-symbols encoded with scene ID + tag ID, and core symbols using a type prefix + 6-digit number fixed encoding, to achieve seamless compatibility across multiple modalities, languages, scenarios, and protocols, reducing the adaptation cycle for less common languages ​​and improving adaptation efficiency.

[0208] Compared with existing technologies, this solution improves the semantic similarity of first-level innovation output, compliance rate of second-level innovation output, and semantic novelty by decoupling the core execution engine through a controllable hierarchical innovation output mechanism. The innovation process is also auditable and circuit-breaking compliant.

[0209] like Figure 2The diagram shown is a flowchart illustrating a lightweight general-purpose intelligent processing system and method provided in an embodiment of the present invention.

[0210] In this embodiment, the lightweight general-purpose intelligent processing method includes: Multimodal data is preprocessed and modally aligned, core symbols and micro symbols are extracted to construct a two-layer symbol representation structure, and symbol conflict resolution is completed according to the priority rule that constrains symbols in the physical fact domain take precedence over the built-in core symbols of the system, thereby generating a globally unified symbol system. The global unified symbol system is constructed as a task dependency graph. After redundancy pruning, a dynamic DAG topology is formed. Incomplete nodes are filled with symbols based on the set similarity matching of historical context templates. Then, the pre-physical fact domain verification and the post-social value domain verification are performed sequentially. Deterministic atomic transformation is performed through STU to obtain the task execution symbol topology. Collect computational load, memory access locality, topological dependence and energy consumption characteristics, generate each index to be normalized to a four-dimensional quantization vector, perform resource reallocation when deviating from the steady-state benchmark, divide storage areas according to hierarchical memory ratio, and construct a three-level memory structure to adapt to the edge hardware. Security modules are tailored according to the hardware computing power level, the output results are verified and access control is performed, and audit logs are stored in a three-level chain structure of bottom node hash, intermediate block hash, and top root hash.

[0211] In the several embodiments provided by the present invention, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and there may be other division methods in actual implementation.

[0212] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units. That is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0213] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0214] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0215] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0216] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A lightweight general-purpose intelligent processing system, characterized by, The system includes: The Unified Symbols and Knowledge Module is used to preprocess and align multimodal data, quantize and encode the obtained standardized feature sequences to extract core semantic features, generate a core symbol set, generate a micro symbol set based on residual features, construct a two-layer symbol representation structure in which core symbols anchor semantics and micro symbols supplement fine-grained features, and resolve conflicts between synonymous and heterogeneous symbols according to the preset priority rule that symbols constrained by the physical fact domain take precedence over system-built core symbols, thereby generating a globally unified symbol system. Atomic execution and orchestration module: It is used to convert the global unified symbol system into a task dependency graph, construct a dynamic DAG topology through loop detection and redundancy pruning, perform symbol completion for nodes with incomplete symbols based on the similarity matching between the historical context template and the current sequence set, and perform pre-physical fact domain verification and post-social value domain verification in sequence. The deterministic atomic execution is completed through the symbol processing unit STU to form the task execution symbol topology. Global State and Resource Scheduling Module: Used to collect computing load, memory access locality, topology dependency and energy consumption characteristics, generate a four-dimensional resource quantization vector, perform resource reallocation when deviating from the steady state benchmark, and allocate memory according to a preset hierarchical ratio to form a three-level storage structure of short-term working memory, medium-term cache memory and long-term knowledge memory, so as to achieve lightweight operation on the edge. Security adaptation module: It is used to perform security mechanism pruning according to the computing power level of the terminal hardware, perform integrity verification and access control on the execution results, and record audit logs using a three-level chain structure of bottom node hash, intermediate block hash and top root hash, so as to obtain the three-level chain structure that is tamper-proof and traceable throughout the entire link.

2. The lightweight general-purpose intelligent processing system as described in claim 1, characterized in that, The method for preprocessing and modal alignment of multimodal data includes: The system receives the raw multimodal data stream, strips the heterogeneous encapsulation header through the protocol parser, and maps the text, image, audio, and sensor time-series data to a unified tensor space to generate an initial multimodal tensor set. Obtain the computing power rating identifier of the current edge hardware, and match the corresponding quantization bit width and channel pruning rate from the preset lightweight cross-modal feature extraction strategy library based on the computing power rating identifier. Perform feature dimensionality reduction and modality alignment on the initial multimodal tensor set to generate a multimodal feature tensor sequence. The local symbol reuse rate distribution of the multimodal feature tensor sequence is calculated, redundant feature mask filtering in the spatiotemporal dimension is performed based on a preset quantization threshold, and an irreversible verification fingerprint is generated for the filtered feature fragments in combination with a symbol anti-tampering hash verification mechanism. Lexical segmentation and cross-language word vector alignment are performed on the feature fragments carrying text modalities. The irreversible verification fingerprint and the aligned feature fragments are then dimensionally concatenated to output a standardized multimodal feature sequence.

3. The lightweight general-purpose intelligent processing system as described in claim 1, characterized in that, The obtained standardized feature sequence is quantized and encoded to extract core semantic features, generating a core symbol set. A micro-symbol set is generated based on residual features. A two-layer symbol representation structure is constructed, where core symbols anchor semantics and micro-symbols supplement fine-grained features. Following a preset priority rule that physical fact domain-constrained symbols take precedence over system-built core symbols, conflicts between synonymous and heterogeneous symbols are resolved, generating a globally unified symbol system, including: During conflict resolution, high-priority symbols are retained, low-priority symbols are discarded, and synonym mappings are established and stored in the conflict resolution table. The standardized multimodal feature sequence is input into a cross-modal semantic coding network to extract high-frequency co-occurrence feature clusters, which are mapped to a set of core symbols. A globally unique identifier and basic semantic weight are assigned to each core symbol to generate a basic symbol representation matrix. Based on the marginal distribution features of the basic symbolic representation matrix, the residual feature vector is analyzed to generate a set of micro-symbols for representing fine-grained differences and long-tail distribution. The set of micro-symbols and the core symbolic set are cascaded according to a preset topological hierarchy to construct a two-layer symbolic representation structure. The synonymous heterogeneous nodes in the two-layer symbol representation structure are traversed, and node conflicts are determined according to the preset symbol structure matching rules and hierarchical priority. When the symbol semantic matching similarity does not reach the preset compliance matching threshold, the conflict resolution protocol is automatically triggered. The semantic matching similarity is obtained by calculating the cosine distance between two symbols in the multidimensional semantic feature space. An unambiguous symbol mapping relationship table is generated through dynamic weight allocation and master-slave symbol priority determination. The preset priority rule is as follows: physical fact domain constraint symbols > system built-in core symbols > industry standard knowledge source symbols > high confidence document source symbols > ordinary interactive source symbols; Perform a consistency graph traversal verification on the unambiguous symbol mapping table, eliminate closed-loop dependencies and isolated nodes, encapsulate a metadata structure containing symbol identifiers, semantic weights, mapping relationships and verification fingerprints, and output a globally unified symbol system.

4. The lightweight general-purpose intelligent processing system as described in claim 1, characterized in that, This is used to convert the globally unified symbol system into a task dependency graph. A dynamic DAG topology is constructed through loop detection and redundancy pruning. For nodes with incomplete symbols, symbol completion is performed based on the similarity matching between the historical context template and the current sequence set. A pre-physical fact domain verification and a post-social value domain verification are then performed sequentially. Deterministic atomic execution is completed through the symbol processing unit (STU), forming a task execution symbol topology, including: The metadata structure in the global unified symbol system is semantically graph-based to identify the logical sequence relationship and data flow constraints between symbol nodes and generate an initial task dependency graph. Based on the initial task dependency graph, loop detection and critical path extraction are performed. Independent subgraphs with parallel execution potential are topologically sorted, redundant intermediate nodes are merged, and a dynamic directed acyclic graph (DAG) is constructed. For nodes in the dynamic directed acyclic graph (DAG) with incomplete input symbols due to missing modes or broken context chains, a scheduling layer symbol completion mechanism is triggered. Based on the dual-domain constraint rules, historical context symbols are retrieved and the corresponding inference operators are matched to complete the placeholders and generate a complete node graph. The complete node graph is input into the symbol processing unit (STU) to perform rigid verification of the preceding physical fact domain (PCD) and flexible verification of the subsequent social value domain (SCD). The preceding physical fact domain verification covers the compliance of physical laws and the correctness of mathematical logic. If the verification fails, the execution of the current node will be directly blocked. The post-social value domain verification covers industry standard compliance and cultural adaptation appropriateness. If the verification fails, the node parameters are fine-tuned and re-verified. The nodes that pass the dual-domain verification are dynamically weighted and bound to resource slots according to the execution sequence, and the task execution symbol topology is output. The symbol processing unit (STU) performs numerical operations using 16-bit fixed-point processing, converting floating-point data into integer operations based on a preset scaling factor.

5. The lightweight general-purpose intelligent processing system as described in claim 1, characterized in that, This is used to collect computational load, memory access locality, topological dependency, and energy consumption characteristics, generating a four-dimensional resource quantization vector. When deviating from the steady-state baseline, resource reallocation is performed, and memory is allocated according to a preset hierarchical ratio, forming a three-level storage structure of short-term working memory, medium-term cache memory, and long-term knowledge memory, to achieve lightweight operation on the edge, including: Receive the task execution symbol topology and collect in real time the task queue depth, memory page access hit rate, data flow dependency span and instantaneous power consumption fluctuation value of each computing node; The computational load quantification index is the ratio of the current task queue depth to the maximum task queue depth; the memory access locality quantification index is the memory page access hit rate; the topology dependency quantification index is the ratio of the data flow dependency span to the maximum allowed dependency span; and the energy consumption quantification index is the ratio of instantaneous power consumption to rated power consumption. These are concatenated to form a four-dimensional resource quantification vector. Receive the four-dimensional resource quantization vector, calculate the deviation gradient of each dimension quantization index in the vector from the preset steady-state benchmark, and if the deviation gradient of any dimension exceeds the dynamic tolerance threshold, generate the corresponding resource redirection instruction set. Receive the resource redirection instruction set, parse the target resource identifier and priority weight in the instruction set, perform binding migration and slot reallocation on idle computing cores, secondary cache blocks and memory page frames through a dynamic priority queue, and output a resource remapping configuration table; The system receives the resource remapping configuration table and historical scheduling performance feedback data, updates the dynamic tolerance threshold and weight allocation coefficient based on the gradient descent algorithm, writes the updated parameters back to the scheduling strategy library, and outputs the iterative resource scheduling benchmark.

6. The lightweight general-purpose intelligent processing system as described in claim 1, characterized in that, Also includes: Scene adaptation and template service module: It is used to load industry or region-specific constraint packages through the unified architecture interface and plugin extension mechanism of the underlying standardized execution results, and generate the final output results that meet the business needs of the target scenario through business rule tree mapping and dynamic routing transformation. Upon receiving the controlled system status, the system abstracts and encapsulates the standardized calculation results of the underlying execution engine, symbolic topology resolution logs, and resource scheduling snapshots into APIs and protocols to generate a set of general intelligent service interfaces. The system receives industry or regional identifiers of the target scenario through a unified interface, matches the corresponding exclusive constraint package from the constraint library of the plugin extension mechanism, parses the business rule tree, compliance verification logic and multilingual adaptation parameters in the constraint package, and outputs a scenario-specific configuration set. The output data stream of the general intelligent service interface set is aligned with the scenario-specific configuration set by rules. The standardized data fields are mapped to the business data model of the target scenario through the condition matching engine and dynamic routing table to generate intermediate results for scenario adaptation. The system receives the intermediate results of the scenario adaptation, monitors the business response latency and data format matching degree in real time based on the scenario feature recognition algorithm, dynamically adjusts the plugin loading weight and data conversion threshold, and outputs the final output result that meets the business requirements of the target scenario.

7. The lightweight general-purpose intelligent processing system as described in claim 1, characterized in that, This is used to perform security mechanism pruning based on the computing power level of the edge hardware, perform integrity verification and access control on the execution results, and record audit logs using a three-level chain structure of bottom-level node hash, intermediate block hash, and top-level root hash, resulting in a three-level chain structure that is tamper-proof and traceable across the entire chain, including: The final output result is received, and the digital signature verification and content digest comparison of the data packet are performed using an asymmetric encryption algorithm. After the verification is passed, the redundant transmission header is stripped to generate a verified secure data stream. Receive the verified secure data stream, perform permission matching based on the target terminal's identity identifier and a preset access control matrix, perform fine-grained data desensitization or route interception, and output a controlled access data stream; The system receives the controlled access data stream, reads the instruction set architecture, available memory capacity and real-time clock frequency of the current edge processor through the system's underlying hardware abstraction layer, and automatically triggers the functional module on-demand pruning strategy when it detects that the available resources of the current edge hardware are lower than the preset lightweight operation threshold. Only the core symbol resolution, STU atomic execution, PCD physical fact domain verification and lightweight hash verification modules are retained, the encryption operation iteration frequency of the security mechanism is reduced, and a lightweight security execution package adapted to the current hardware platform is generated. Receive the runtime logs and access audit records of the lightweight security execution package, call the hash chain storage protocol to serialize and encrypt the log data and package it into blocks, and generate an initial audit hash chain; The three-level chain structure is constructed as follows: calculate the node hash value for each single operation record and concatenate them into the underlying hash sequence according to the time sequence; The hashes of consecutive nodes are assembled into a Merkle tree according to the preset block capacity, and the block header hash is calculated to form a set of intermediate block hashes; The new block header hash and the historical root hash are chained together to generate the top-level root hash, which is then stored in the local encrypted audit area to obtain the three-level chain structure that is tamper-proof and traceable across the entire chain.

8. A lightweight, universal intelligent processing method, characterized in that, The method includes: Multimodal data is preprocessed and modally aligned, core symbols and micro symbols are extracted to construct a two-layer symbol representation structure, and symbol conflict resolution is completed according to the priority rule that constrains symbols in the physical fact domain take precedence over the built-in core symbols of the system, thereby generating a globally unified symbol system. The global unified symbol system is constructed as a task dependency graph. After redundancy pruning, a dynamic DAG topology is formed. Incomplete nodes are filled with symbols based on the set similarity matching of historical context templates. Then, the pre-physical fact domain verification and the post-social value domain verification are performed sequentially. Deterministic atomic transformation is performed through STU to obtain the task execution symbol topology. Collect computational load, memory access locality, topological dependence and energy consumption characteristics, generate each index to be normalized to a four-dimensional quantization vector, perform resource reallocation when deviating from the steady-state benchmark, divide storage areas according to hierarchical memory ratio, and construct a three-level memory structure to adapt to the edge hardware. Security modules are tailored according to the hardware computing power level, the output results are verified and access control is performed, and audit logs are stored in a three-level chain structure of bottom node hash, intermediate block hash, and top root hash.

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