Information processing method, apparatus, device, and medium

Abstract

Embodiments of the present disclosure provide an information processing method and device, equipment and medium, relating to the field of resource management. The method comprises: obtaining idle resource information of hardware computing resources of a processor; obtaining resource requirement information of a hardware unit executing a computing task; in the case that the idle resource information and the resource requirement information satisfy a first condition, generating and caching a first type instruction and a second type instruction for the processor to obtain and execute the first type instruction and the second type instruction in parallel; caching an execution result obtained after the processor executes the second type instruction for the hardware unit to read the execution result of the second type instruction. In this way, the running efficiency of the hardware unit is effectively improved, and the utilization rate of the hardware resources in the processor is also improved without affecting the execution of the conventional software.

Description

Technical Field

[0001] This disclosure relates to the field of resource management technology, and in particular to an information processing method, apparatus, equipment and medium. Background Technology

[0002] The Baseboard Management Controller (BMC) chip in a server integrates multiple hardware units to implement different hardware functions, such as compressed transmission of raw video data on the host side, hardware-encrypted transmission of critical data, and network protocol processing. However, these hardware units perform numerous and complex logical operations to implement computational tasks, which consume a considerable amount of time. Consequently, the operating efficiency of these hardware units is low, leading to a degraded performance of the BMC chip.

[0003] Furthermore, with the development of BMC chip technology, the performance of its integrated processor has been continuously improving. However, the software workload running on this processor has not increased significantly accordingly, resulting in idle or underutilized internal hardware computing resources, failing to maximize the utilization of processor hardware resources.

[0004] Therefore, how to improve the operating efficiency of the BMC chip hardware units while simultaneously increasing the utilization rate of its internal processor hardware resources, thereby enhancing the performance of the BMC chip, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides an information processing method, apparatus, device, and medium to at least solve the above-mentioned technical problems existing in the prior art.

[0006] In a first aspect, embodiments of this disclosure provide an information processing method, the method comprising: Obtain information on the available hardware computing resources of the processor; Obtain resource requirements information for hardware units to perform computing tasks; If the idle resource information and resource demand information meet the first condition, generate and cache the first type of instruction and the second type of instruction for the processor to obtain and execute the first type of instruction and the second type of instruction in parallel. The cached result is obtained after the processor executes the second type of instruction, so that the hardware unit can read the result of the second type of instruction. The first type of instruction is the instruction obtained by regenerating the software instructions running on the processor, and the second type of instruction is the instruction used to perform the computing tasks of the hardware unit.

[0007] Secondly, embodiments of this disclosure provide an information processing method apparatus, the apparatus comprising: The acquisition module is used to acquire information about the idle resources of the processor's hardware computing resources; The acquisition module is also used to acquire resource requirement information for hardware units to perform computing tasks; The generation module is used to generate and cache a first type of instruction and a second type of instruction when the idle resource information and resource demand information meet the first condition, so that the processor can obtain and execute the first type of instruction and the second type of instruction in parallel. The cache module is used to cache the execution results obtained by the processor after executing the second type of instructions, so that the hardware unit can read the execution results of the second type of instructions; The first type of instruction is the instruction obtained by regenerating the software instructions running on the processor, and the second type of instruction is the instruction used to perform the computing tasks of the hardware unit.

[0008] Thirdly, embodiments of this disclosure provide a baseboard management controller (BMC), comprising: processor; Hardware unit; A resource management component, connected to both the processor and the hardware unit, performs the following actions: acquiring idle resource information of the processor's hardware computing resources; acquiring resource requirement information of the hardware unit for executing computing tasks; generating and caching a first type of instruction and a second type of instruction when the idle resource information and resource requirement information meet a first condition, for the processor to acquire and execute the first type of instruction and the second type of instruction in parallel; and caching the execution result obtained by the processor after executing the second type of instruction, for the hardware unit to read the execution result of the second type of instruction; wherein the first type of instruction is an instruction obtained by regenerating the software instructions running on the processor, and the second type of instruction is an instruction used to execute the computing tasks of the hardware unit.

[0009] Fourthly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the information processing method of the first aspect.

[0010] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the information processing method according to the first aspect.

[0011] The beneficial technical effects of the information processing method provided in this disclosure are at least as follows: It can acquire idle resource information of the processor's hardware computing resources and resource requirement information of the hardware unit executing computing tasks. When the idle resource information and resource requirement information meet a first condition, that is, when the processor's hardware computing resources are sufficient, it generates and caches a first type of instruction and a second type of instruction, enabling the processor to acquire and execute these two types of instructions in parallel. Subsequently, the result obtained by the processor executing the second type of instruction is cached for the hardware unit to read. In this way, the computing tasks of the hardware unit are transferred to the processor, allowing the processor to execute the first type of instruction while simultaneously utilizing its idle hardware computing resources to execute the second type of instruction constructed based on the computing task. Therefore, without affecting the execution of regular software, it not only effectively improves the operating efficiency of the hardware unit but also enhances the utilization rate of the processor's internal hardware resources.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a system architecture of a related technology provided in an embodiment of this disclosure; Figure 2 This is a flowchart illustrating an information processing method provided in an embodiment of this disclosure. Figure 1 ; Figure 3 This is a flowchart illustrating an information processing method provided in an embodiment of this disclosure. Figure 2 ; Figure 4 This is a schematic diagram of the structure of a BMC chip provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a resource management component provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of an information processing device provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0014] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0015] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0016] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0018] like Figure 1 As shown, the server host 10 is connected to the BMC 20, and the BMC 20 may include multiple first hardware units 21 (i.e., the aforementioned hardware units). These multiple first hardware units 21 are used to implement different hardware functions, such as implementing compressed transmission of raw video data with the server host, and hardware encrypted transmission of key data with the server host. These first hardware units 21 directly determine the core performance indicators of the BMC chip, such as video compression efficiency, network transmission efficiency, and data encryption efficiency.

[0019] In traditional BMC chip designs, the first hardware unit 21 typically employs combinational operations to implement its core computational tasks. Taking color space conversion in video compression as an example, this module needs to convert an image from Red Green Blue (RGB) format to YUV format within a single clock cycle, involving multiple multiplications, additions, and shift operations. Similarly, data encryption functions (such as Advanced Encryption Standard (AES) and the SM4 block cipher algorithm) also require a large number of XOR and shift operations within a single cycle. Because these combinational logic operations have significant path delays, they limit the highest operating frequency achievable by the first hardware unit 21, thus constraining the overall performance of the BMC chip.

[0020] Continue as Figure 1 As shown, the BMC20 also includes a first processor 22 (i.e., the aforementioned processor, such as a RISC-V processor). With the development of BMC chip technology, the performance of the first processor 22 integrated within the BMC20 has been continuously improved. However, the software workload running on the first processor 22 has not increased significantly accordingly. Therefore, the internal hardware computing resources of the first processor 22 (such as arithmetic logic units, multipliers, shifters, etc.) are idle or underutilized, failing to maximize the utilization of the hardware resources of the first processor 22.

[0021] Therefore, how to improve the operating efficiency of the BMC chip hardware unit while increasing the utilization rate of its internal processor hardware resources is a technical problem that urgently needs to be solved in this field.

[0022] Based on this, the present disclosure provides an information processing method, apparatus, device, and medium to at least solve the technical problem of low data prefetching accuracy in the prior art. The information processing method provided by the present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] Figure 2 This is a flowchart illustrating an information processing method provided in an embodiment of this disclosure. Figure 1 .

[0024] like Figure 2 As shown, the information processing method provided in this disclosure embodiment may include the following steps: S210: Obtain information on the available hardware computing resources of the processor.

[0025] Hardware computing resources may include hardware modules used for arithmetic or logical operations, such as adders, subtractors, XOR operators, etc., without specific limitations here.

[0026] This idle resource information can be used to characterize the idle status of the processor's internal hardware computing resources. Specifically, the idle status of the processor's internal hardware resources can be determined by monitoring the software load running on the processor and how it uses those resources; however, no specific limitations are specified here.

[0027] S220: Obtain resource requirement information for the hardware unit to perform computing tasks.

[0028] The hardware unit can be a module within the BMC chip that implements different hardware functions, and the computational task is the task that the hardware unit needs to complete to perform its functions. For example, if the hardware unit is a color space conversion unit, the computational task could be to convert an image from RGB format to YUV format; if the hardware unit is an encryption unit, the computational task could be to encrypt data, which will not be elaborated further here.

[0029] The above resource requirement information can be used to characterize the hardware computing resources required for the hardware unit to perform computing tasks, such as needing 2 adders, 1 multiplier and 1 shifter, without specific limitations here.

[0030] S230, if the idle resource information and resource demand information meet the first condition, generate and cache the first type of instruction and the second type of instruction for the processor to obtain and execute the first type of instruction and the second type of instruction in parallel.

[0031] The first condition can be used to determine whether the idle resource information meets the resource requirement information, that is, whether the idle hardware computing resources on the processor are sufficient to execute the corresponding computing task.

[0032] In some embodiments, the first type of instruction is an instruction obtained by regenerating software instructions running on the processor; the second type of instruction is an instruction used to perform computational tasks of hardware units, which is not specifically limited here.

[0033] S240 caches the execution results obtained by the processor after executing the second type of instruction, so that the hardware unit can read the execution results of the second type of instruction.

[0034] Specifically, the system can obtain information on the processor's available hardware computing resources and the resource requirements of the hardware unit for executing the computing task. When the available resource information and resource requirements satisfy a first condition—that is, the processor's available hardware computing resources are sufficient to cover the hardware computing resources required for the computing task—a first type of instruction and a second type of instruction are generated and cached. This allows the processor to execute the second type of instruction, constructed based on the computing task, in parallel, while executing the first type of instruction. Subsequently, after the processor executes the second type of instruction, the execution result of the second type of instruction is cached so that the hardware unit can read the execution result.

[0035] Based on the information processing method provided in this disclosure, the idle resource information of the processor's hardware computing resources and the resource requirement information of the hardware unit executing computing tasks can be obtained. When the idle resource information and resource requirement information meet a first condition, that is, when the processor's hardware computing resources are sufficient, a first type of instruction and a second type of instruction are generated and cached, enabling the processor to acquire and execute these two types of instructions in parallel. Subsequently, the result obtained by the processor executing the second type of instruction is cached for the hardware unit to read. In this way, the computing tasks of the hardware unit are transferred to the processor, allowing the processor to execute the first type of instruction while simultaneously utilizing its idle hardware computing resources to execute the second type of instruction constructed based on the computing task. This effectively improves the operating efficiency of the hardware unit and the utilization rate of the processor's internal hardware resources without affecting the execution of regular software, thereby improving the performance of the BMC chip.

[0036] When the hardware unit operates efficiently, to avoid unnecessary task migration that consumes processor resources, there is no need to transfer the hardware unit's computational tasks to the processor for execution. Therefore, computational tasks are only transferred to the processor for execution when the hardware unit operates efficiently. Based on this, in order to accurately and comprehensively describe the information processing method provided in this disclosure, in one embodiment, the information processing method provided in this disclosure may further include: Obtain the operating speed of the hardware unit.

[0037] The operating speed of this hardware unit can be used to characterize its processing efficiency when performing its own computing tasks. Specifically, a higher operating speed indicates higher processing efficiency, and vice versa; however, no further limitations are imposed here.

[0038] For example, the operating speed of the hardware unit can be determined by monitoring the execution time or average time required for the hardware unit to perform a single computing task, or by monitoring the number of computing tasks completed by the hardware unit within a preset time window. No specific limitation is made here.

[0039] Based on this, the above-mentioned S230 may specifically include the following steps: If the idle resource information and resource demand information meet the first condition, and the running speed is less than the preset speed threshold, generate and cache the first type of instruction and the second type of instruction.

[0040] The preset speed threshold is a judgment threshold that can be set in advance based on actual experience or circumstances. It can be used to measure whether the operating speed (or operating efficiency) of the hardware unit has dropped to a level where computing tasks need to be offloaded to the processor for assistance. For example, it can be set to 60% or 80% of the rated operating speed of the hardware unit, without specific limitation here.

[0041] Specifically, by acquiring the operating speed of the hardware unit, it is assessed whether the operating speed (or efficiency) of the hardware unit has decreased to the point where the computational task needs to be offloaded to the processor for assistance. Then, if the operating speed of the hardware unit is less than a preset speed value, it indicates that the hardware unit has an "instruction acceleration" requirement. This instruction acceleration refers to accelerating the computational task of the hardware unit within the processor using instructions. At this point, if the idle resource information and the required resource information meet the first condition, then first-type instructions and second-type instructions can be generated and cached, allowing the processor to execute the second-type instructions in parallel while executing the first-type instructions.

[0042] In one example, when the hardware unit is a color space conversion unit, if the rated conversion speed is 100 frames per second, the preset speed threshold can be set to 70 frames per second. When the current operating speed of the color space conversion unit is detected to be only 60 frames per second, it is determined that its operating speed is less than the preset speed threshold. At this time, if the processor's idle hardware computing resources can meet the hardware computing resources required for the computing task, the generation and caching of the first type of instruction and the second type of instruction are triggered, and the computing task is passed to the processor for execution.

[0043] In this embodiment, the operating speed of the hardware unit can be obtained. When the idle resource information and resource demand information meet a first condition, and the operating speed is less than a preset speed threshold, a first type of instruction and a second type of instruction are generated and cached. This allows the processor to acquire and execute the two types of instructions in parallel. Thus, by monitoring the operating speed of the hardware unit and transferring the computational task to the processor when its operating speed is low, not only can the operating efficiency of the hardware unit and the utilization rate of the processor's internal hardware resources be effectively improved without affecting the operation of regular software, but it also avoids prematurely transferring the computational task to the processor before the hardware unit reaches a performance bottleneck, thus preventing the waste of processor resources.

[0044] To accurately determine whether the processor's idle hardware computing resources meet the hardware computing resource requirements of the computing task, in one embodiment, the aforementioned idle resource information may include the idle resource type of the idle computing resources in the processor and the quantity of idle resources corresponding to the idle resource type. The resource requirement information includes the required resource type of the required computing resources and the required quantity of resources corresponding to the required resource type.

[0045] Here, idle computing resources can be currently unused hardware computing resources in the processor. The type of idle resource can be the type of idle computing resource, such as adders, multipliers, subtractors, shifters, etc. The quantity of idle resources can be the specific number currently available for each type of idle resource; for example, there may be 5 idle adders and 3 idle multipliers, but this is not specifically limited here.

[0046] For example, the idle resource information can be obtained by acquiring the current status of various types of computing resources to determine the number of idle resources corresponding to each type of idle computing resource. Alternatively, the idle amount of internal hardware computing resources of the processor can be counted within multiple preset time periods, and the number of idle resources of each type of idle computing resource can be obtained by calculating the average of these idle amounts.

[0047] Accordingly, the aforementioned required computing resources can be the hardware computing resources required by the hardware unit to execute the computing task. The type of required resource can be the type of computing resource required, and the quantity of required resources can be the specific number required for the corresponding type, which will not be elaborated on here.

[0048] Based on this, the aforementioned S230 may specifically include: If the type of idle resource matches the type of required resource, and the number of idle resources corresponding to the type of idle resource is greater than or equal to the number of required resources corresponding to the type of required resource, then generate and cache the first type of instruction and the second type of instruction.

[0049] Specifically, the idle resource information may include the type of idle computing resources in the processor (i.e., idle resource type) and its corresponding quantity (i.e., idle resource quantity). Correspondingly, the resource requirement information may include the type of computing resources required by the hardware unit to execute the computing task (i.e., required resource type) and its corresponding quantity (i.e., required resource quantity). Based on this, when the idle resource type matches the required resource type, and the quantity of each idle resource type is greater than or equal to the quantity of the corresponding required resource type, it can be determined that the idle resource information satisfies the resource requirement information, and then the first type of instruction and the second type of instruction can be generated and cached.

[0050] In one example, the above-mentioned free resource information can be shown in Table 1 below: Table 1

[0051] Based on this, if the resource requirements information of the hardware unit includes 2 adders, 1 multiplier, and 1 XOR operator, and according to Table 1, the idle computing resources on the processor include 5 adders, 3 multipliers, and 6 XOR operators, since the idle resource types include all types of the required resources, and the number of idle resources for each type is greater than or equal to the required number, the first condition is met, and the first type of instruction and the second type of instruction can be generated and cached. Conversely, if the hardware unit also needs a divider, but Table 1 does not contain a divider, then a type mismatch is determined, and instruction generation is not triggered.

[0052] Furthermore, the hardware units in this embodiment can be at least two. Based on this, it is assumed that the hardware units in this embodiment may include hardware unit A and hardware unit B. If hardware unit A requires 2 adders, 1 multiplier, and 1 shift operator, and hardware unit B requires 3 adders and 2 shift operators, then, as shown in Table 1, the available computing resources can include 5 adders, 3 multipliers, and 4 shift operators, which can simultaneously meet the resource requirements of both. Therefore, "instruction acceleration" of hardware unit A and hardware unit B can be achieved simultaneously, i.e., generating the second type of instructions corresponding to hardware unit A and hardware unit B respectively.

[0053] In this embodiment, the idle resource information includes the idle resource type and the quantity of idle resources corresponding to the idle resource type in the processor, while the resource requirement information includes the required resource type and the quantity of resources corresponding to the required resource type. Thus, by matching the resource type and quantity in the idle resource information and the resource requirement information respectively, it is possible to accurately determine whether the idle resource information meets the resource requirement information. Furthermore, when processor resources are sufficient, the computing tasks of the hardware unit can be migrated to the processor for execution via trigger instructions, effectively improving the operating efficiency of the hardware unit and the utilization rate of the hardware computing resources in the processor.

[0054] In order to provide a comprehensive and detailed description of the information processing method provided in the embodiments of this disclosure, in one embodiment, such as Figure 3 As shown, the steps for generating and caching the first type of instructions and the second type of instructions described above may specifically include the following steps: S310 divides multiple registers to obtain the first register group and the second register group.

[0055] S320 uses the first register group to remap software instructions to obtain first type instructions, and caches the first type instructions in the first cache area.

[0056] S330, based on the requirements of the computing task, constructs a second type of instruction using the second register group and caches the second type of instruction in the second cache area.

[0057] It should be noted that processors typically contain multiple general-purpose registers. In this embodiment, these registers can be divided into two groups: a first register group and a second register group. The first register group is used to support the execution of regular software instructions (i.e., first-type instructions), while the second register group is used to construct special-purpose instructions (i.e., second-type instructions) for the computational tasks of the hardware unit. In one example, assuming the processor has 32 general-purpose registers, 25 (e.g., x0 to x24) can be allocated as the first register group for use in the instruction regeneration of regular software; the remaining 7 (e.g., x25 to x31) can be allocated as the second register group for use in the special-purpose instructions constructed for the computational tasks of the hardware unit.

[0058] It should also be noted that the ratio between the first register group and the second register group can be flexibly set according to the actual application scenario. For example, it can be determined based on the number of various types of idle resources in the idle resource information, or the number of various types of required resources in the resource demand information. Generally, the more idle resources or required resources there are, the more registers will be allocated to the second register group, but no specific limitation is made here.

[0059] Thus, by partitioning multiple registers, a first register set is obtained to support the first type of instructions, and a second register set is obtained to construct the second type of instructions. Typically, regular software instructions may use any register. Therefore, after register partitioning, the first register set can be used to remap software instructions to obtain the first type of instructions, which are then cached in the first cache region. Simultaneously, based on the computational task requirements, the second register set is used to construct the second type of instructions, which are then cached in the second cache region. This allows the processor to read the first type of instructions from the first cache region and the second type of instructions from the second cache region, enabling parallel execution of both types of instructions.

[0060] The first cache region and the second cache region are different cache regions, and no specific restrictions are made here.

[0061] In this embodiment, the registers are divided into a first register group and a second register group, serving regular software instructions (i.e., first-type instructions) and hardware computing task instructions (i.e., second-type instructions) respectively. These two types of instructions are stored in different cache areas. Since the hardware resources used by these two types of instructions are independent, the second-type instructions can independently use dedicated register resources (the second register group) and be stored in an independent cache area without affecting the execution of regular software. Therefore, the processor can effectively improve the operating efficiency of hardware units and the utilization rate of internal processor hardware resources without affecting the execution of regular software, and also increase the processor's instruction fetching speed.

[0062] In order to accurately generate the first type of instruction, in one embodiment, the above-mentioned S320 may specifically include: The first operand associated with the second register group in the software instruction is remapped to a free register in the first register group to obtain the first type of instruction.

[0063] It's important to note that during normal software instruction execution, operands might point to register addresses that originally belonged to the second register set. Without remapping, these software instructions will fail to execute correctly when the second register set is occupied by hardware computation tasks.

[0064] In this way, by remapping the first operand of the second register group associated with the software instruction to a free register in the first register group, the first type of instruction can be accurately obtained. Here, the first operand refers to the register operand in the software instruction that originally pointed to the range of the second register group, without being specifically limited here.

[0065] In one example, assume the second register set is x25-x31. A certain sequence of software instructions is: {add x1, x2, x3; sub x27, x5, x6; and x7, x8, x9} In the instruction sub x27, x5, x6, x27 belongs to the second register group. During the remapping process, the system detects that this operand is associated with the second register group, so it searches for a free register (e.g., x12, which is not occupied in the currently executing instruction) in the first register group (x0-x24) and remaps the instruction to sub x12, x5, x6.

[0066] In this embodiment, operands in software instructions that originally pointed to the second register set can be automatically remapped to free registers in the first register set. This way, even if the second register set is completely occupied by hardware computing tasks, regular software instructions can still be executed normally through the first register set without waiting or pausing. This ensures the normal execution of regular software and avoids interference from instructions constructed based on computing tasks.

[0067] In order to accurately generate the second type of instructions, the above-mentioned S330 may specifically include: Break down the computational task requirements; The disassembled requirement information is written into the registers of the second register group; Generate a second type of instruction that uses a register in the second register group as its second operand.

[0068] The requirements for this computational task can be related data that the hardware unit relies on when executing the task, such as operation type, operands, constants, address information, etc., without specific limitations here. Taking the color space conversion task in video functionality as an example, the calculation of the Y value is Y=(77 R+150 G+29 B+128)>>8. The decomposed requirement information may include 77, R, 150, G, 29, B, 128, 8, which will not be elaborated on here.

[0069] Specifically, it can break down the requirement information of the computing task and write the broken down requirement information into the registers in the second register group, thereby generating a second type of instruction with the register bits of the second register group as the second operand.

[0070] In one example, the calculation formula for the color space conversion unit is: Y=(77 R+150 G+29 B+128)>>8(1) U=((-43 R-85 G+128 B+128)>>8)+128(2) V=((128 R-107 G-21 B+128)>>8)+128(3) Taking the calculation of Y as an example, it can be converted into three multiplication instructions, three addition instructions, and one shift instruction: {li x25, 77 / / Load the constant 77 into the x25 register} mul x27, x26, x25 / / x25 multiplied by x26 (R value), the result is assigned to x27 li x25,150 / / Load the constant 150 into the x25 register mul x29, x28, x25 / / x25 multiplied by x28 (G value), the result is assigned to x29 li x25,29 / / Load the constant 29 into the x25 register mul x31, x30, x25 / / x25 multiplied by x30 (B value), the result is assigned to x31 add x26, x27, x29 / / Add x27 and x29, and assign the result to x26 add x25, x31, x26 / / Add x31 and x26, and assign the result to x25 li x28,128 / / Load the constant 128 into the x28 register add x30, x25, x28 / / Add x25 and x28, and assign the result to x30 li x26,8 / / Load the constant 8 into the x26 register srli x31, x30, x26 / / right shift x30 by 8 bits, assign the result to x31} After the above instructions are executed, the value of Y will be obtained in the x31 register. The calculation of U and V can be performed by constructing instructions in a similar manner.

[0071] In this embodiment, by breaking down the computational task requirements of the hardware unit and writing the broken-down requirements into registers in the second register group, a second type of instruction with registers in the second register group as the second operand is generated. In this way, the second type of instruction can be accurately constructed.

[0072] In order to provide a comprehensive and detailed description of the information processing method provided in the embodiments of this disclosure, in one embodiment, the information processing method provided in the embodiments of this disclosure may further include: If there are at least two hardware units and the idle resource information and the resource requirement information corresponding to the at least two hardware units do not meet the first condition, at least one target hardware unit is selected from the at least two hardware units according to their priority, so that the idle resource information and the resource requirement information of the target hardware unit meet the first condition.

[0073] The aforementioned priorities characterize the urgency or importance of task migration for different hardware units. Specifically, if a hardware unit has a higher priority, its computational tasks will be migrated to the processor for execution first, and vice versa. This will not be elaborated further here.

[0074] It should be noted that the hardware units in this embodiment can be at least two. Therefore, when at least two hardware units exist, and the idle resource information and the resource requirement information corresponding to the at least two hardware units do not satisfy the first condition—that is, when at least two hardware units simultaneously request the processor to assist in executing computational tasks, and the processor's idle computing resources may not be able to simultaneously meet the needs of all hardware units—at least one target hardware unit can be selected from the at least two hardware units according to their priority, so that the idle resource information and the resource requirement information of the target hardware unit satisfy the first condition.

[0075] In one example, if the above at least two hardware units include an encryption unit and a color space conversion unit, the encryption unit has a higher priority than the color space conversion unit. If the processor's currently available computing resources can only meet the needs of one of the units, the computing task of the encryption unit will be migrated to the processor for execution. As for the color space conversion unit, it will wait for the next resource check or use other processing methods.

[0076] Furthermore, the method provided in this disclosure may also include: If there are at least two hardware units and the number of free registers is less than the number of required registers, at least one target hardware unit is selected from the at least two hardware units according to their priority, such that the number of free registers is greater than or equal to the number of required registers.

[0077] The required number of registers refers to the sum of the number of registers required for the computing tasks corresponding to at least two hardware units, and no specific limit is specified here.

[0078] In this way, when there are at least two hardware units and the number of free registers is less than the number of required registers, at least one target hardware unit can be selected from the at least two hardware units according to their priority, so that the number of free registers is greater than or equal to the number of required registers.

[0079] Alternatively, if there are at least two hardware units, and the idle resource information and the resource requirement information corresponding to the at least two hardware units do not meet the first condition, and the number of idle registers is less than the number of required registers, at least one target hardware unit is selected from the at least two hardware units according to their priority, such that the number of idle registers is greater than or equal to the number of required registers, and the idle resource information and the resource requirement information of the target hardware unit meet the first condition.

[0080] In one example, assume there are hardware units A and B. Hardware unit A requires 2 adders, 1 multiplier, 1 shifter, and 3 general-purpose registers to construct instructions; hardware unit B requires 3 adders, 2 shifters, and 3 general-purpose registers to construct instructions. If the idle resource information and the resource requirements of these at least two hardware units do not meet the first condition, and / or the number of idle registers is less than the required number of registers, then the computation tasks of hardware unit A and hardware unit B must be executed sequentially according to priority. Conversely, if the idle resource information and the resource requirements of these at least two hardware units meet the first condition, and the number of idle registers is greater than or equal to the required number of registers, then the computation tasks of hardware unit A and hardware unit B can be executed in parallel.

[0081] In this embodiment, when the available computing resources in the processor are limited and insufficient to meet the resource requirements of at least two hardware units, the scarce computing resources in the processor can be allocated to the more needed or more important hardware units according to priority, which effectively improves the rationality of resource allocation in the processor.

[0082] Based on this, in one embodiment, the information processing method provided by this disclosure may further include: Obtain the operating speed of at least two hardware units; The priority of at least two hardware units is determined based on their operating speed.

[0083] Specifically, when there are at least two hardware units, the operating speed of the at least two hardware units can be obtained, and the priority of the at least two hardware units can be determined based on the operating speed of the at least two hardware units.

[0084] It should be noted that the slower the hardware unit runs, the lower its current processing efficiency and the more serious the task backlog may be. Therefore, it can be given higher priority so that it can get the assistance of processor resources in a timely manner. This will not be elaborated on further here.

[0085] In one example, if the at least two hardware components include an encryption unit and a color space conversion unit, and if the encryption unit is currently operating at 30% of its rated speed while the color space conversion unit is currently operating at 70% of its rated speed, then the priority can be determined based on their operating speeds, with the encryption unit having a higher priority than the color space conversion unit.

[0086] In this embodiment, based on the operating speed of at least two hardware units, a higher priority can be assigned to hardware units with lower operating speeds, and a lower priority can be assigned to hardware units with higher operating speeds. This allows for accurate determination of the priority of each hardware unit, facilitating the subsequent rational allocation of idle hardware computing resources within the processor.

[0087] In another embodiment, the information processing method provided in this disclosure may further include: For each hardware unit, obtain the task execution information of the computing task corresponding to the hardware unit; Based on the task execution information of the computing tasks corresponding to the hardware units, predict the execution time required for the processor to execute the computing tasks corresponding to the hardware units; The priority of at least two hardware units is determined based on their respective execution times.

[0088] In some embodiments, the task execution information includes at least one of the operation type and the number of operations corresponding to the operation type. The operation type refers to the specific category of arithmetic or logical operation involved when the hardware unit performs the computation task, such as addition, multiplication, shifting, XOR, etc. The corresponding number of operations refers to the number of times the operation type is executed in the computation task, for example, requiring 3 addition operations or 2 multiplication operations; no specific limitation is made here.

[0089] Furthermore, the execution time required for the processor to execute the corresponding computational task of the hardware unit refers to the estimated execution time required for the processor to complete the computational task under the current hardware resources and operating conditions. Specifically, it can be estimated based on the types of operations included in the computational task and the corresponding number of operations. Since the complexity of different types of operations varies, a simple estimate can be made based on the type of operation and the number of operations, or the total execution time of the computational task can be calculated by combining the average clock cycles or time required by the processor to execute each type of operation.

[0090] In one example, if the computation task of hardware unit A only requires performing addition operations, while the computation task of hardware unit B requires performing multiplication operations, and the complexity of multiplication operations is higher than that of addition operations, it means that the processor will need less time to execute the computation task of hardware unit A. Therefore, it can be determined that the priority of hardware unit A is higher than that of hardware unit B.

[0091] In another example, if the computation task of hardware unit A requires 3 addition operations, while the computation task of hardware unit B requires 5 addition operations, it is clear that, under the same type of operation, the number of operations of hardware unit B is greater than the number of operations of hardware unit A. This indicates that the processor will have a shorter execution time for the computation task of hardware unit A, and it can be determined that the priority of hardware unit A is higher than the priority of hardware unit B.

[0092] In another example, if hardware unit A's computation task requires 3 addition operations, while hardware unit B's computation task requires 2 multiplication operations, and since multiplication is more complex than addition, but hardware unit B's computation task requires fewer multiplication operations than hardware unit A's computation task, if the difference between the two corresponding operation counts is less than a preset number, it indicates that the processor will need less time to execute hardware unit A's computation task. Therefore, hardware unit A's priority is determined to be higher than hardware unit B's priority; conversely, if the difference is greater, hardware unit B's priority is determined to be higher than hardware unit A's priority. This preset number can be determined based on actual circumstances and is not specifically limited here.

[0093] Alternatively, the execution time of different types of operations can be considered (e.g., addition requires 1 clock cycle, multiplication requires 2 clock cycles). If hardware unit A requires 3 addition operations, the processor will need 3 clock cycles to execute that task. If hardware unit B requires 2 multiplication operations, the processor will need 4 clock cycles to execute that task. Clearly, hardware unit A has a shorter execution time, thus its priority is higher than that of hardware unit B.

[0094] In this embodiment, the execution time required for the processor to execute a computing task can be predicted based on at least one of the operation types and corresponding number of operations included in the computing task corresponding to the hardware unit, and higher priority can be assigned to hardware units with shorter execution times. This not only accurately determines the priority order of each hardware unit but also enables the processor to complete the relevant computing tasks as quickly as possible, thereby facilitating the subsequent rational allocation of idle hardware computing resources in the processor.

[0095] Based on the same inventive concept, this disclosure also provides a BMC chip, which can be specifically combined with... Figure 4 A BMC chip provided in the embodiments of this disclosure will be described in detail.

[0096] Figure 4 This is a schematic diagram of the structure of a BMC chip provided in an embodiment of this disclosure.

[0097] like Figure 4 As shown, the BMC chip 400 may include a resource management component 41, a processor 42, and a hardware unit 43. The resource management component 41 may be connected to both the processor 42 and the hardware unit 43, and the specific connection method is not limited.

[0098] Additionally, the processor 42 may be, for example, a RISC-V processor, without specific limitations. The number of hardware units 43 may be at least one, and may include, for example, an encryption unit, a color space conversion unit, etc., without limitation.

[0099] In this way, the resource management component 41 can obtain the idle resource information of the hardware computing resources of the processor 42 and the resource requirement information of the hardware unit 43 to execute computing tasks. Then, when the idle resource information and the resource requirement information meet the first condition, it can generate and cache the first type of instruction and the second type of instruction, so that the processor 42 can obtain and execute the first type of instruction and the second type of instruction in parallel. After the processor 42 finishes executing the second type of instruction, it can cache the execution result corresponding to the second type of instruction, so that the hardware unit 43 can read the execution result of the second type of instruction, thereby realizing the migration of the computing tasks of the hardware unit 43 to the processor 42 for execution.

[0100] For ease of understanding, such as Figure 5 As shown, the resource management component 41 may include a trigger management module 51, which may include a first monitoring unit 511, a second monitoring unit 512, and a resource partitioning judgment unit 513.

[0101] The first monitoring unit 511 is used to monitor the idle resource information of the hardware computing resources of the processor 42; the second monitoring unit 512 is used to monitor the resource requirement information of the hardware unit 43 performing computing tasks; and the resource allocation judgment unit 513 is used to judge whether the idle resource information and the resource requirement information meet the first condition.

[0102] Continue as Figure 5As shown, the resource management component 41 may also include an instruction generation module 52, which may include a register partitioning unit 521, an instruction regeneration unit 522, an instruction construction unit 523, and an instruction control unit 524.

[0103] The register partitioning unit 521 is used to partition multiple registers to obtain a first register group and a second register group; the instruction regeneration unit 522 is used to remap software instructions using the first register group to obtain a first type of instruction; the instruction construction unit 523 is used to construct a second type of instruction using the second register group based on the requirements of the computing task; and the instruction control unit 524 is used to cache the first type of instruction in the first cache and cache the second type of instruction in the second cache.

[0104] In addition, such as Figure 5 As shown, the resource management component 41 may also include an interaction module 53, which may include a first interaction unit 531, a second interaction unit 532, and an interaction control unit 533.

[0105] The first interaction unit 531 is used to migrate computing tasks from the hardware unit to the processor; the second interaction unit 532 is used to provide execution result feedback from the processor to the hardware unit; and the interaction control unit 533 is used to, in the presence of at least two hardware units, migrate the computing tasks of at least two hardware units from their respective hardware units to the processor for execution in sequence according to the priority of the at least two hardware units, or migrate the computing tasks of at least two hardware units from their respective hardware units to the processor for parallel execution.

[0106] Furthermore, based on the same inventive concept, this disclosure provides an information processing apparatus, which can be specifically described in conjunction with the appendix. Figure 6 This disclosure provides a detailed description of an information processing apparatus according to embodiments thereof.

[0107] Figure 6 This is a schematic diagram of the structure of an information processing device provided in an embodiment of this disclosure.

[0108] like Figure 6 As shown, the information processing device 600 may include: The acquisition module 610 is used to acquire the idle resource information of the processor's hardware computing resources; The acquisition module 610 is also used to acquire resource requirement information for the hardware unit to perform computing tasks; The generation module 620 is used to generate and cache a first type of instruction and a second type of instruction when the idle resource information and resource demand information meet the first condition, so that the processor can obtain and execute the first type of instruction and the second type of instruction in parallel. The cache module 630 is used to cache the execution result obtained by the processor after executing the second type of instruction, so that the hardware unit can read the execution result of the second type of instruction; The first type of instruction is the instruction obtained by regenerating the software instructions running on the processor, and the second type of instruction is the instruction used to perform the computing tasks of the hardware unit.

[0109] In one embodiment, the information processing apparatus provided in this disclosure may include: The acquisition module is also used to acquire the operating speed of the hardware unit; The generation module is specifically used to generate and cache the first type of instruction and the second type of instruction when the idle resource information and resource demand information meet the first condition and the running speed is less than the preset speed threshold.

[0110] In one embodiment, the idle resource information includes the idle resource type of the idle computing resources in the processor and the quantity of idle resources corresponding to the idle resource type; the resource requirement information includes the required resource type of the required computing resources and the required quantity of resources corresponding to the required resource type; based on this, the information processing apparatus provided in this disclosure embodiment may include: The generation module is specifically used to generate and cache the first type of instruction and the second type of instruction when the idle resource type matches the required resource type and the number of idle resources corresponding to the idle resource type is greater than or equal to the number of required resources corresponding to the required resource type.

[0111] In one embodiment, the information processing apparatus provided in this disclosure may include: The partitioning module is used to divide multiple registers to obtain a first register group and a second register group; The remapping module is used to remap software instructions using the first register set to obtain instructions of the first type. The construction module is used to construct the second type of instruction based on the requirements of the computing task using the second register set.

[0112] In one embodiment, the information processing apparatus provided in this disclosure may include: The remapping module is specifically used to remap the first operand associated with the second register group in the software instruction to a free register in the first register group to obtain the first type of instruction.

[0113] In one embodiment, the information processing apparatus provided in this disclosure may include: The decomposition module is used to break down the requirements information of the computing task. The write module is used to write the disassembled requirement information into the registers of the second register group; The generation module is specifically used to generate second-type instructions that use registers in the second register group as second operands.

[0114] In one embodiment, the information processing apparatus provided in this disclosure may include: The filtering module is used to filter at least two hardware units to obtain at least one target hardware unit according to the priority of the at least two hardware units when there are at least two hardware units and the idle resource information and the resource requirement information corresponding to the at least two hardware units do not meet the first condition, so that the idle resource information and the resource requirement information of the target hardware unit meet the first condition.

[0115] In one embodiment, the information processing apparatus provided in this disclosure may include: The acquisition module is also used to acquire the operating speed of at least two hardware units; The determination module is also used to determine the priority of at least two hardware units based on their operating speeds.

[0116] In one embodiment, the information processing apparatus provided in this disclosure may include: The acquisition module is also used to acquire, for each hardware unit, the task execution information of the computing task corresponding to the hardware unit, including at least one of the operation type and the number of operations corresponding to the operation type; The prediction module is used to predict the execution time required for the processor to execute the computing task corresponding to the hardware unit based on the task execution information of the computing task corresponding to the hardware unit. The determination module is also used to determine the priority of at least two hardware units based on the execution time corresponding to each of the at least two hardware units.

[0117] It is understood that, when implementing the corresponding information processing method apparatus provided in the above embodiments, the processing can be distributed to different program modules as needed to complete all or part of the processing described above. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0118] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform an information processing method.

[0119] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and, when executed by a processor, will cause the processor to execute the information processing method provided in this application.

[0120] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0121] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0122] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0123] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0124] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 7 As shown, the electronic device 70 includes: a processor 701, and a memory 702 communicatively connected to the processor 701; the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to perform: Obtain information on the available hardware computing resources of the processor; Obtain resource requirements information for hardware units to perform computing tasks; When the idle resource information and the resource demand information meet the first condition, a first type of instruction and a second type of instruction are generated and cached for the processor to acquire and execute the first type of instruction and the second type of instruction in parallel. The execution result obtained by the processor after executing the second type of instruction is cached for use by the hardware unit to read the execution result of the second type of instruction; The first type of instruction is an instruction obtained by regenerating the software instructions running on the processor, and the second type of instruction is an instruction used to execute the computing tasks of the hardware unit.

[0125] The electronic devices and corresponding information processing methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0126] In practical applications, the electronic device 70 may further include at least one network interface 1203. The various components of the electronic device 70 are coupled together via a bus system 704. It is understood that the bus system 704 is used to implement communication between these components. In addition to a data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 All buses are labeled as bus system 704. The number of processors 701 and the number of memories 702 can be at least one. The network interface 703 is used for wired or wireless communication between the electronic device 70 and other devices.

[0127] The memory 702 in this embodiment is used to store various types of data to support the operation of the electronic device 70.

[0128] The methods disclosed in the above embodiments of this disclosure can be applied to processor 701, or implemented by processor 701. Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 701 or by instructions in the form of software. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 701 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 702. Processor 701 reads the information in memory 702 and, in conjunction with its hardware, completes the steps of the aforementioned information processing method.

[0129] In some embodiments, the electronic device 70 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0130] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0131] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0132] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0133] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0135] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An information processing method, characterized in that, include: Obtain the idle resource information of the processor's hardware computing resources in the Baseboard Management Controller (BMC); Obtain the resource requirements information for the hardware units in the BMC to perform computing tasks; When the idle resource information and the resource demand information meet the first condition, a first type of instruction and a second type of instruction are generated and cached for the processor to acquire and execute the first type of instruction and the second type of instruction in parallel. The execution result obtained by the processor after executing the second type of instruction is cached for use by the hardware unit to read the execution result of the second type of instruction; The first type of instruction is an instruction obtained by remapping software instructions running on the processor, and the second type of instruction is an instruction used to execute the computing tasks of the hardware unit. The idle resource information includes the idle resource type of the idle computing resources in the processor and the quantity of idle resources corresponding to the idle resource type; the resource requirement information includes the required resource type of the required computing resources and the required resource quantity corresponding to the required resource type. The step of generating and caching the first type of instruction and the second type of instruction when the idle resource information and the resource demand information meet the first condition further includes: If the idle resource type matches the required resource type, and the number of idle resources corresponding to the idle resource type is greater than or equal to the number of required resources corresponding to the required resource type, then generate and cache the first type of instruction and the second type of instruction. The generation and caching of the first type of instruction and the second type of instruction includes: Divide the registers into a first register group and a second register group; The software instructions are remapped using the first register group to obtain the first type of instructions, and the first type of instructions are cached in the first cache area; Based on the requirements of the computing task, the second type of instruction is constructed using the second register group, and the second type of instruction is cached in the second cache area.

2. The method according to claim 1, characterized in that, Also includes: Obtain the operating speed of the hardware unit; The step of generating and caching a first type of instruction and a second type of instruction when the idle resource information and the resource demand information meet a first condition includes: If the idle resource information and the resource demand information meet the first condition, and the running speed is less than a preset speed threshold, then the first type of instruction and the second type of instruction are generated and cached.

3. The method according to claim 1, characterized in that, The step of remapping the software instructions using the first register set to obtain the first type of instruction includes: The first operand associated with the second register group in the software instruction is remapped to an empty register in the first register group to obtain the first type of instruction.

4. The method according to claim 1, characterized in that, The second type of instruction is constructed using the second register set based on the requirements information of the computing task, including: Decompose the requirements information of the computing task; The disassembled requirement information is written into the registers of the second register group; Generate a second type of instruction that uses the registers of the second register group as the second operand.

5. The method according to claim 1 or 2, characterized in that, Also includes: If at least two hardware units exist, and the idle resource information and the resource requirement information corresponding to the at least two hardware units do not satisfy the first condition, at least one target hardware unit is selected from the at least two hardware units according to their priority, so that the idle resource information and the resource requirement information of the target hardware unit satisfy the first condition.

6. The method according to claim 5, characterized in that, Also includes: Obtain the operating speed of at least two of the hardware units; The priority of at least two of the hardware units is determined based on their operating speeds.

7. The method according to claim 5, characterized in that, Also includes: For each hardware unit, task execution information of the computing task corresponding to the hardware unit is obtained, wherein the task execution information includes at least one of the operation type and the number of operations corresponding to the operation type; Based on the task execution information of the computing task corresponding to the hardware unit, the execution time required for the processor to execute the computing task corresponding to the hardware unit is predicted. The priority of at least two hardware units is determined based on their respective execution times.

8. An information processing device, characterized in that, The device includes: The acquisition module is used to acquire the idle resource information of the hardware computing resources of the processor in the Baseboard Management Controller (BMC). The acquisition module is also used to acquire resource requirement information of the hardware unit in the BMC to perform computing tasks; The generation module is configured to generate and cache a first type of instruction and a second type of instruction when the idle resource information and the resource demand information meet a first condition, so that the processor can acquire and execute the first type of instruction and the second type of instruction in parallel. A cache module is used to cache the execution result obtained by the processor after executing the second type of instruction, so that the hardware unit can read the execution result of the second type of instruction; The first type of instruction is an instruction obtained by remapping software instructions running on the processor, and the second type of instruction is an instruction used to execute the computing tasks of the hardware unit. The idle resource information includes the idle resource type of the idle computing resources in the processor and the quantity of idle resources corresponding to the idle resource type; the resource requirement information includes the required resource type of the required computing resources and the required quantity of resources corresponding to the required resource type; the device includes: The generation module is specifically used to generate and cache the first type of instruction and the second type of instruction when the idle resource type matches the required resource type and the number of idle resources corresponding to the idle resource type is greater than or equal to the number of required resources corresponding to the required resource type. The device includes: The partitioning module is used to divide multiple registers to obtain a first register group and a second register group; The remapping module is used to remap the software instructions using the first register group to obtain the first type of instructions, and cache the first type of instructions to the first cache area. The construction module is used to construct the second type of instruction based on the requirement information of the computing task using the second register group, and cache the second type of instruction to the second cache area.

9. The apparatus according to claim 8, characterized in that, The device includes: The acquisition module is also used to acquire the operating speed of the hardware unit; The generation module is specifically used to generate and cache a first type of instruction and a second type of instruction when the idle resource information and the resource demand information meet a first condition and the running speed is less than a preset speed threshold.

10. The apparatus according to claim 8, characterized in that, The device includes: The remapping module is specifically used to remap the first operand associated with the second register group in the software instruction to an empty register in the first register group to obtain the first type of instruction.

11. The apparatus according to claim 8, characterized in that, The device includes: The decomposition module is used to decompose the requirement information of the computing task; The writing module is used to write the disassembled demand information into the registers of the second register group; The generation module is specifically used to generate a second type of instruction that uses the registers of the second register group as the second operand.

12. The apparatus according to claim 8 or 9, characterized in that, The device includes: The filtering module is configured to, when at least two hardware units exist and the idle resource information and the resource requirement information corresponding to the at least two hardware units do not satisfy the first condition, filter at least one target hardware unit from the at least two hardware units according to the priority of the at least two hardware units, so that the idle resource information and the resource requirement information of the target hardware unit satisfy the first condition.

13. The apparatus according to claim 12, characterized in that, The device includes: The acquisition module is also used to acquire the operating speed of at least two of the hardware units; The determining module is also configured to determine the priority of at least two of the hardware units based on the operating speed of at least two of the hardware units.

14. A baseboard management controller (BMC), characterized in that, include: processor; Hardware unit; A resource management component, connected to both the processor and the hardware unit, is configured to: acquire idle resource information of the processor's hardware computing resources in the Baseboard Management Controller (BMC); acquire resource requirement information of the hardware unit in the BMC for executing computing tasks; and, when the idle resource information and the resource requirement information satisfy a first condition, generate and cache a first type of instruction and a second type of instruction for the processor to acquire and execute the first type of instruction and the second type of instruction in parallel. The execution result obtained by the processor after executing the second type of instruction is cached for the hardware unit to read the execution result of the second type of instruction; wherein, the first type of instruction is an instruction obtained by remapping software instructions running on the processor, and the second type of instruction is an instruction for executing the computing task of the hardware unit; The idle resource information includes the idle resource type of the idle computing resources in the processor and the quantity of idle resources corresponding to the idle resource type; the resource requirement information includes the required resource type of the required computing resources and the required resource quantity corresponding to the required resource type. The resource management component is further configured to: generate and cache a first type of instruction and a second type of instruction when the idle resource type matches the required resource type and the number of idle resources corresponding to the idle resource type is greater than or equal to the number of required resources corresponding to the required resource type; The resource management component is also used to perform: dividing multiple registers to obtain a first register group and a second register group; The software instructions are remapped using the first register group to obtain the first type of instructions, and the first type of instructions are cached in the first cache area; Based on the requirements of the computing task, the second type of instruction is constructed using the second register group, and the second type of instruction is cached in the second cache area.

15. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the information processing method according to any one of claims 1 to 7.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the information processing method according to any one of claims 1 to 7.

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