A computing task processing method and apparatus, a storage medium, and an electronic device

Abstract

This specification discloses a computing task processing method, apparatus, storage medium, and electronic device. The method includes: acquiring a set of node computing tasks; parsing computing logic rules to extract a list of rule parameters, dividing it into basic input parameters and derived dependency parameters; constructing a directed task graph based on the derived dependency parameters to establish logical mapping relationships between computing tasks of each node, obtaining a task dependency topology model; performing closed-loop link detection on the task dependency topology model and, after passing the detection, performing topology sorting to obtain a linear computing sequence of tasks with execution priorities; and finally, compiling and executing the computing tasks according to the linear computing sequence to obtain the computing task results. Using this specification, the dynamic construction of complex computing task dependencies and pre-lockdown prevention are achieved, effectively improving the system's computing task scheduling and execution efficiency and operational stability.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a method, apparatus, storage medium and electronic device for processing computing tasks. Background Technology

[0002] As enterprise information system architectures become increasingly complex, large-scale data processing platforms (such as financial accounting, asset valuation, and business rule engines) involve massive amounts of node computation tasks. These computation tasks typically involve intricate logical nesting and cascading dependencies, meaning that the execution of the target task often requires precisely waiting for the results of multiple preceding derivative tasks. Currently, when processing such data computation flows with strong dependencies, the order of computation is usually hard-coded manually, or the recursive call mechanism of the underlying program stack is simply relied upon during system runtime to drive the state transitions of multi-level data.

[0003] However, the aforementioned conventional task scheduling and computation methods have technical bottlenecks in practical engineering applications. On the one hand, when the computation logic rules change frequently or the number of task nodes is extremely large, the workload of manually maintaining the static computation order increases exponentially, and it is very easy to cause logical errors and deadlocks during system operation due to configuration errors. On the other hand, the computation mechanism based on recursive calls generates a large amount of redundant repeated parsing and computation when processing shared prerequisite dependencies, which greatly wastes the processor's computing resources. Moreover, when facing deep nested relationships or implicit closed-loop dependencies, it is easy to cause thread call stack overflow, which seriously restricts the high-concurrency processing throughput of the computing engine and the operational stability of the underlying system. Summary of the Invention

[0004] This specification provides a computing task processing method, apparatus, storage medium, and electronic device, the technical solutions of which are as follows: Firstly, embodiments of this specification provide a method for processing computational tasks, the method comprising: Obtain a set of node computing tasks in the target data processing scenario, parse each computing logic rule in the set of node computing tasks to extract a list of rule parameters, and divide the list of rule parameters by parameter attributes to obtain basic input parameters and derived dependency parameters. Based on the derived dependency parameters, a logical mapping relationship is established between the computing tasks of each node. Based on the logical mapping relationship, a directed task graph is constructed to obtain a task dependency topology model. The graph nodes of the task dependency topology model are configured as result identifiers of computing tasks, and the directed edges between the graph nodes are configured as the calling relationship between the computing logic rules and the derived dependency parameters. Closed-loop link detection is performed on the task-dependent topology model, and after the detection is passed, the task-dependent topology model is sorted to obtain a linear computation sequence of tasks with execution priority; The task metrics are compiled and executed according to the linear calculation sequence of the task to obtain the calculation task results.

[0005] Secondly, embodiments of this specification provide a computing task processing apparatus, the apparatus comprising: The task processing module is used to obtain a set of node computing tasks in the target data processing scenario, parse each computing logic rule in the set of node computing tasks to extract a list of rule parameters, and divide the list of rule parameters by parameter attributes to obtain basic input parameters and derived dependency parameters. The model building module is used to establish a logical mapping relationship between the computing tasks of each node based on the derived dependency parameters, and to build a task dependency topology model by constructing a directed task graph based on the logical mapping relationship. The graph nodes of the task dependency topology model are configured as result identifiers of computing tasks, and the directed edges between the graph nodes are configured as the calling relationship between the computing logic rules and the derived dependency parameters. The closed-loop detection module is used to perform closed-loop link detection on the task-dependent topology model, and after the detection is successful, perform topological sorting on the task-dependent topology model to obtain a linear computation sequence of tasks with execution priority. The compilation and execution module is used to compile and execute task metrics according to the linear calculation sequence of the task, and obtain the calculation task results.

[0006] Thirdly, embodiments of this specification provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the above-described method steps.

[0007] Fourthly, this specification provides a computer program product storing at least one instruction adapted to be loaded by a processor and to execute the method steps of one or more embodiments of this specification.

[0008] Fifthly, this specification provides a computer program product storing at least one instruction adapted to be loaded by a processor and to execute the method steps of one or more embodiments of this specification.

[0009] Sixthly, embodiments of this specification provide an electronic device that may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to execute the above-described method steps.

[0010] The beneficial effects of the technical solutions provided in some embodiments of this specification include at least the following: In one or more embodiments of this specification, by acquiring node computing tasks and performing low-level deep analysis and parameter attribute division of computing logic rules, a task dependency topology model is dynamically constructed based on derived dependency parameters. In the pre-execution stage, a graph theory closed-loop link detection mechanism and a topology sorting algorithm are introduced to generate a linear computing sequence of tasks. Finally, the compilation and execution of underlying objects are driven by this sequence. This effectively solves the limitations of high manual hard coding maintenance costs and system deadlock and crash caused by misconfiguration of dynamic dependency rules due to the nested and related massive number of complex task nodes. This achieves automated mapping from discrete logic rules to dynamic and safe scheduling at the computer's underlying level. It not only completely blocks the risk of system downtime caused by circular dependencies at the physical memory level and improves the system robustness of the server side when handling high-concurrency and strongly dependent computing flows, but also eliminates the system's repetitive parsing load and thread blocking waiting time by pre-reducing the network graph structure into a one-dimensional linear instruction sequence with absolute priority and combining it with the underlying object compilation mechanism. This achieves high throughput, low latency, and stable collaborative flow of massive data computing task flows. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating a computational task processing method provided in an embodiment of this specification; Figure 2 This is a schematic diagram of a task-dependent topology model construction process provided in the embodiments of this specification; Figure 3 This is a schematic diagram of a closed-loop link detection process provided in the embodiments of this specification; Figure 4 This is a schematic flowchart of a topology sorting process provided in an embodiment of this specification; Figure 5 This is a schematic diagram of the compilation and execution process of a task indicator provided in the embodiments of this specification; Figure 6 This is a schematic diagram of the structure of a computing task processing device provided in the embodiments of this specification; Figure 7 This is a schematic diagram of the structure of an electronic device provided in the embodiments of this specification. Detailed Implementation

[0013] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0014] In the description of this specification, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. In the description of this specification, it should be noted that, unless otherwise expressly specified and limited, "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. Those skilled in the art can understand the specific meaning of the above terms in this specification based on the specific circumstances. Furthermore, in the description of this specification, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0015] The present specification will now be described in detail with reference to specific embodiments.

[0016] To enable those skilled in the art to more clearly understand the system architecture and operating environment upon which this specification is based, and to fully demonstrate the technical feasibility of the computational task processing method described in this specification in practical engineering applications, a computational task processing scenario involved in this specification is explained in detail below.

[0017] In the specific embodiments described in this specification, the target data processing scenario is typically built on a distributed, high-concurrency, multi-terminal interactive network architecture. This architecture mainly includes a configuration client, an access gateway, a core service platform (i.e., the entity that executes the computational task processing method described in this specification), a distributed storage cluster, and a third-party business system. Each terminal interacts with data packets through standard network communication protocols (such as HTTP / HTTPS, RPC, etc.). The specific multi-terminal interactive collaborative processing process is as follows: 1. Configure the interaction between the client and the core service platform (rule distribution and task initialization) Configuration clients are typically visual front-end interfaces or application terminals used by business analysts or R&D personnel. Users enter or modify the calculation logic rules for business metrics (such as adding a calculation formula for a financial or risk control indicator) in the configuration client. The configuration client encapsulates these node calculation tasks into standard data exchange formats (such as JSON or XML) and sends them to the core service platform through the access gateway.

[0018] Upon receiving the request, the core service platform triggers the step of "obtaining the set of node computing tasks in the target data processing scenario". At this interaction node, the service platform is not only responsible for receiving tasks, but also for performing protocol parsing and permission verification, and then transforming the abstract configuration data into processable instance objects in the server's memory.

[0019] 2. Interaction between the core service platform and the distributed storage cluster (parameter resolution and data addressing) During the process of the service platform executing "parsing each computational logic rule to extract the list of rule parameters and perform attribute partitioning", the service platform needs to interact frequently with the distributed storage cluster (such as relational databases, NoSQL databases or distributed cache nodes).

[0020] Specifically, after extracting the rule parameters, the service platform initiates an asynchronous query request to the distributed storage cluster to compare the data dictionary and metadata information. If the storage cluster reports that the parameter has a corresponding physical storage field, the service platform marks it as a "basic input parameter"; if the report indicates that the physical field does not exist but matches other task identifiers, it marks it as a "derived dependency parameter." This interaction process achieves decoupling mapping between rule logic and underlying physical data.

[0021] 3. Distributed node interaction within the core service platform (graph construction, loop detection, and concurrent scheduling) During the directed task graph construction, closed-loop link detection, and topology sorting phases, interactions primarily occur between internal cluster nodes of the core service platform. For massive computing tasks, the service platform can consist of multiple master nodes and worker nodes.

[0022] The master node is responsible for maintaining a global task dependency topology model in shared memory or a distributed coordination component (such as ZooKeeper) and executing cycle detection algorithms such as depth-first search. Once the detection is successful and a linear computation sequence and concurrency level label for the tasks are generated, the master node distributes the divided independent computing units to different worker nodes through an internal RPC (Remote Procedure Call) mechanism. After receiving the instructions, the underlying computing thread pool within the worker node performs computation work in parallel, realizing elastic horizontal scaling of computing resources.

[0023] 4. Interaction between the core service platform and data source / third-party business systems (data computation and result distribution) In the final compilation and execution stage, when the computational task results are obtained, the data interaction process can be referenced as follows: First, when worker nodes execute pre-compiled underlying execution objects, they need to initiate calls to various external data sources (e.g., calling a bank's interface to obtain real-time exchange rates as basic input parameters). Second, once a certain level of computation task obtains a numerical result, the worker node immediately writes the result back to a high-speed shared cache via network I / O, enabling other worker nodes that depend on the result to read it across nodes, thus achieving cross-terminal data relay for derived dependent parameters. Finally, when all computation task sequences have been completed, the core service platform asynchronously pushes the final computation task result to third-party business systems that have subscribed to the metric (such as financial reporting systems, risk control decision engines, etc.) via a message queue, thereby completing the entire multi-terminal collaborative data processing business loop.

[0024] In summary, the computational task processing method provided in this specification does not run in isolation on a single device, but is deeply embedded in a complex network ecosystem with multi-terminal interactions. By standardizing the data message interaction, state synchronization, and asynchronous callback mechanisms between various terminals, this computational task processing method effectively solves the data blocking and deadlock problems caused by chaotic dependencies in multi-system collaborative computing, ensuring the efficiency and consistency of global data flow.

[0025] In one embodiment, such as Figure 1 As shown, a computational task processing method is proposed. This method can be implemented using a computer program and can run on a computational task processing device based on the von Neumann architecture. The computer program can be integrated into an application or run as a standalone utility application. The computational task processing device can be a service platform.

[0026] Specifically, the processing method for this computational task includes: S102: Obtain a set of node computing tasks in the target data processing scenario, parse each computing logic rule in the set of node computing tasks to extract a list of rule parameters, and divide the list of rule parameters by parameter attributes to obtain basic input parameters and derived dependency parameters. The target data processing scenario refers to the computer operating environment that requires complex business rule calculations, massive indicator processing, and streaming data processing, such as distributed financial indicator accounting systems, risk control feature engineering platforms, business decision rule engines, etc.

[0027] A node computing task refers to the smallest unit of operation in a target data processing scenario that can be independently identified and allocated computing resources by a computer scheduling system. Each task typically outputs a specific numerical value or state result. Each stage of the computing task corresponds to a set of computational logic rules.

[0028] Computational logic rules refer to mathematical expressions or logical operation statements encapsulated within the node's computational tasks, existing in the form of computer-readable strings, markup languages, and structured scripts.

[0029] The rule parameter list refers to the set of all input variable identifiers that the current rule must depend on when performing calculations, which is precisely extracted after the compilation and parsing engine performs syntactic deconstruction and scanning of the computational logic rules.

[0030] Basic input parameters refer to the raw data parameters in the rule parameter list whose values ​​are directly derived from reading physical fields from the underlying database, calling external system interfaces, or passing through gateway messages, and do not depend on the output results of other nodes' computing tasks in the current scenario.

[0031] Derived dependency parameters refer to intermediate related parameters in the list of rule parameters whose values ​​are empty or unavailable in the initial state. They can usually only be obtained after other preceding node calculation tasks in the current data processing scenario have been completed and returned results.

[0032] Indicatively, the service platform can subscribe to a specific predefined topic in the distributed message middleware to receive messages containing a set of node computing tasks asynchronously pushed by external business systems in real time. These messages are dynamically loaded into a distributed memory cache. For lightweight computing logic rules arriving in a streaming manner, a streaming parser or template matching engine based on regular expressions is used. According to predefined placeholder extraction rules, a high-speed pattern matching algorithm directly extracts variable parameters from string fragments and assembles them into a list of rule parameters. Then, attributes are categorized by dynamically probing the distributed registry center. For each parameter in the rule parameter list, a non-blocking query request is initiated to the registry center. If the registry center indicates that the parameter exists in the context of a real-time incoming event message, it is immediately categorized as a basic input parameter. If the registry center returns that the parameter belongs to an asynchronous computing state variable in the subscription, it indicates that the parameter needs to wait for other real-time computing nodes to publish results. The service platform's system then categorizes the parameter as a derived dependency parameter and synchronously registers a listener callback handle in memory for subsequent graph construction and task wake-up.

[0033] S104: Establish a logical mapping relationship between the computing tasks of each node based on the derived dependency parameters, and construct a task dependency topology model based on the logical mapping relationship. The graph nodes of the task dependency topology model are configured as result identifiers of the computing tasks, and the directed edges between the graph nodes are configured as the calling relationship between the computing logic rules and the derived dependency parameters. Logical mapping relationships refer to data association structures established in computer memory dictionaries or distributed state tables, used to accurately record and map the matching correspondence between a node's computing task and the derived dependency parameters that it must obtain before executing the operation.

[0034] Task-dependent topology models are instances of directed acyclic graphs (DAGs) data structures that reside in the physical memory of a computer. They use the geometric relationships between vertices and edges in graph theory to strictly constrain and solidify the execution order and data flow paths in a multi-task concurrent system from a spatial structure perspective.

[0035] Graph nodes are model nodes in a task-dependent topology model. Specifically, they are configured as globally unique result identifiers representing the node's computational tasks and are the minimum addressing targets for resource scheduling and status queries.

[0036] Directed edges connect unidirectional memory pointers of two graph nodes in a task-dependent topology model. They have strict directionality and are used to characterize the data flow or trigger dependencies between tasks.

[0037] The specific logical meaning carried by the directed edge of the call pointer relationship clearly defines the pointer link that the current node's computing task must initiate a data reading or call request to the preceding graph node, which is its derived dependency parameter, when parsing its computing logic rules.

[0038] In a schematic manner, the extracted list of rule parameters is traversed. For variables classified as derived dependency parameters, a hash map is instantiated in the system heap memory using the result identifier of the current node's computation task as the key and its corresponding set of derived dependency parameters as the value. This establishes the logical mapping relationship between the computation tasks of each node at the physical level. Subsequently, address space is allocated in memory to instantiate the task dependency topology model. All node computation tasks in the target data processing scenario are read, and the result identifiers are extracted. A graph node object is created for each result identifier. Then, the hash map table constructed above is traversed. For each target graph node, its dependent value set is queried, and memory address addressing is performed in all graph node objects. After the address is hit, the system injects a one-way memory address pointer between the current target graph node and the dependent graph node to complete the writing of the directed edge. The direction of this memory address pointer is configured as a call pointing relationship, that is, from the graph node that needs to execute the computation logic rule to the graph node that provides the derived dependency parameter. This tightly stitches the originally isolated rule expressions into a closed loop and ordered task dependency topology model.

[0039] S106: Perform closed-loop link detection on the task-dependent topology model, and after the detection is passed, perform topological sorting on the task-dependent topology model to obtain a linear computation sequence of tasks with execution priority; Closed-loop link detection refers to the process of scanning the path safety of a topology model built in memory using a preset graph theory traversal algorithm, with the aim of identifying and discovering deadlock loops formed by bidirectional dependencies or multi-level nested circular dependencies between nodes.

[0040] A pass test indicates that after traversing all nodes and directed edges of the topology model, no loop anomaly alarms are triggered in the physical state. At this point, the topology model is confirmed to be a strictly directed acyclic graph.

[0041] Topological sorting can be understood as a basic computer scheduling process that arranges all nodes in a directed acyclic graph into a linear sequence. Its core constraint is that if there is a directed edge from node A to node B in the graph, then node A must be arranged before node B in the generated linear sequence.

[0042] The linear computation sequence of tasks refers to the one-dimensional array, linked list or task queue generated after dimensionality reduction of the multi-dimensional network task-dependent topology model, which is used to directly guide the single-threaded execution or multi-threaded wave concurrent pipeline operation in the underlying processing.

[0043] Indicatively, during closed-loop link detection, a global or local parallel scan of the task-dependent topology model is performed. This is achieved by assigning atomic timestamp indexes to each visited distributed graph node during the graph traversal phase and maintaining the smallest traceable timestamp value. Furthermore, the service platform compares timestamp states across nodes in real-time to accurately identify strongly connected component subgraphs formed by cross-domain calls from multiple microservices. If the total number of nodes within any strongly connected component exceeds one, a distributed deadlock loop is directly triggered, and an abnormal blocking event is initiated. This process proceeds only after ensuring the topology model is proven to be a strictly directed acyclic graph and the detection passes. The reverse topology sorting algorithm, based on the depth-first search post-order traversal mechanism, initiates a reverse recursive tracing network probe from the terminal service graph node with an out-degree of a preset target value (such as zero). It fully records the bottom-up tracing path of each computation-dependent link and arranges and stores the graph nodes that have completed the bottom-level probe in the reverse order of the post-order traversal. Finally, in the shared state storage area of ​​the distributed coordination component, the sequences of each piece are spliced ​​to generate a linear computation sequence with execution priority that can guide the underlying worker threads to perform lock-free concurrent computation according to the correct resource level and priority.

[0044] S108: Compile and execute the task indicators according to the linear calculation sequence of the task to obtain the calculation task results.

[0045] The result of a computation task refers to the numerical, Boolean, or status data records with clear physical meaning generated in the computer's physical memory or registers after the underlying execution object of the task indicator has been processed by the central processing unit or arithmetic unit.

[0046] Indicatively, following the priority order of the linear computation sequence of tasks, task indicators to be processed are extracted one by one. The character expression corresponding to the computational logic rule of the task indicator is used as the physical address index. A matching query of physical memory address is performed in the underlying memory object cache pool built based on the least recently used eviction algorithm. If the matching query does not find a match, the character expression is subjected to deep syntax parsing to generate a low-level execution object that can be directly run by the computer. The generated low-level execution object is then filled back into the memory object cache pool for subsequent high-frequency calls. Subsequently, an independent computational execution scope for the current task indicator is initialized in memory, and the ready basic input parameters and the pre-set system low-level business function library are dynamically injected into the computational execution scope. Finally, the scheduler allocates idle physical threads or virtual threads from the low-level computation thread pool according to the system load status to drive the low-level execution object to perform substantive arithmetic or logical numerical operations in the computational execution scope. The computational task results are directly written into the system high-speed memory shared state table for non-blocking fast cross-domain reading and data calling by tasks downstream of the linear computation sequence and with derivative dependencies.

[0047] In the embodiments of this specification, by acquiring node computing tasks and performing low-level deep analysis and parameter attribute division of computing logic rules, a task dependency topology model is dynamically constructed based on derived dependency parameters. In the pre-execution stage, a graph theory closed-loop link detection mechanism and a topology sorting algorithm are introduced to generate a linear computing sequence of tasks. Finally, the compilation and execution of underlying objects are driven by this sequence. This effectively solves the limitations of high manual hard coding maintenance costs and system deadlock and crashes caused by misconfiguration of dynamic dependency rules due to the nested and related massive number of complex task nodes. This achieves automated mapping from discrete logic rules to dynamic and safe scheduling at the computer's underlying level. It not only completely blocks the risk of system downtime caused by circular dependencies at the physical memory level and improves the robustness of the server side when handling high-concurrency and strongly dependent computing flows, but also eliminates the system's repetitive parsing load and thread blocking waiting time by pre-reducing the network graph structure into a one-dimensional linear instruction sequence with absolute priority and combining it with the underlying object compilation mechanism. This achieves high throughput, low latency, and stable collaborative flow of massive data computing task flows.

[0048] Optional, please see Figure 2 , Figure 2 This is a flowchart illustrating the construction process of a task-dependent topology model as proposed in this specification. Specifically, the following method can be used to construct the task-dependent topology model based on the logical mapping relationship: S202: Initialize a graph data structure instance for the task-dependent topology model; Graph data structure instances refer to the underlying container objects (such as those using adjacency lists, adjacency matrices, or forward star structures) allocated in computer physical memory or distributed cache to carry sets of vertices and edges. They are the physical carriers of task-dependent topological models.

[0049] S204: Traverse the logical mapping relationship and instantiate the result of each node's computation task into a target graph node in the graph data structure instance; A target graph node refers to a data operation entity object that has been allocated a specific physical memory address in a graph data structure instance. It represents the data operation entity object that needs to be logically processed and the rules executed. It is usually configured as the result identifier of the current computing task.

[0050] S206: Traverse the derived dependency parameters corresponding to the task of each node, and address the dependency graph node corresponding to the derived dependency parameter in the graph data structure instance; A dependent graph node refers to an entity object in a graph data structure instance that represents the source of the preceding data that the current target graph node must obtain when performing computation. It is usually configured as the result identifier of the derived dependency parameter.

[0051] S208: Establish a directional memory pointer mapping between the target graph node and the dependency graph node to form a directed edge corresponding to the call pointing relationship.

[0052] Memory pointer mapping refers to a unidirectional addressing path or reference identifier used at the bottom layer of a computer system to connect the physical memory addresses of two independent graph node objects. In the graph, it is represented as a directed edge, which constitutes the channel for data flow or event triggering during task execution.

[0053] Indicatively, the service platform first allocates address space in the heap memory region of main memory to initialize a graph data structure instance for the task-dependent topology model (e.g., instantiating an adjacency list object containing a hash map and a dynamic array). Then, it initiates a high-speed loop to traverse the logical mapping relationship dictionary generated in the previous stage. The result identifier of each node's computation task in the mapping record is used to calculate the memory offset via a hash function and instantiated into a specific object memory block, i.e., the target graph node, in the physical memory of the graph data structure instance. Next, it traverses again the derived dependency parameters corresponding to the configuration rules of each node's computation task and calculates the hash index of the graph data structure instance. Based on the global identifier of the parameter, the corresponding physical memory address is precisely addressed in the region to successfully lock and mount the dependency graph node corresponding to the derived dependency parameter. Finally, the computer's underlying processor, based on the successful address matching, directly writes the memory base address pointing to the dependency graph node object into the pointer array inside the target graph node object at the system's underlying level. This establishes a memory pointer mapping with strict access direction between the target graph node and the dependency graph node, thereby accurately forming a directed edge representing the call pointing relationship at the physical storage level. This realizes the underlying materialization transformation from a discrete abstract logical mapping dictionary to a mesh topology structure with spatial connectivity.

[0054] In the embodiments of this specification, by initializing graph data structure instances at the underlying level and instantiating discrete node computation task identifiers and derived dependency parameters as target graph nodes and dependency graph nodes in the physical addressing space, respectively, and then establishing a strictly directional memory pointer mapping between the two to form directed edges, the massive and abstract computational logic is accurately and structurally transformed into an entity topology network that can be directly and efficiently traversed and spatially addressed at the computer's underlying level. This not only provides data structure support for subsequent closed-loop link detection and dimensionality reduction topology sorting, but also significantly eliminates system I / O bottlenecks and computational overhead when tracing dependencies through direct memory pointer mapping at the physical level, improving the system's graph model construction efficiency and underlying resource collaborative scheduling performance when dealing with large-scale, dynamically cascaded tasks.

[0055] Optional, please see Figure 3 , Figure 3This is a schematic diagram of a closed-loop link detection process proposed in this specification. Specifically, the following method can be used to perform closed-loop link detection on the task-dependent topology model: S302: Perform path traversal on the directed edges and maintain a stack of active nodes for recording the current probe path during the path traversal process; An active node stack refers to a data structure dynamically allocated in computer memory that follows the Last-In-First-Out (LIFO) principle, or a memory space implicitly maintained by the thread call stack, specifically used to temporarily record a complete and continuous probe path from the probe origin to the currently visited graph node.

[0056] S304: When accessing the current graph node, detect whether the current graph node already exists in the active node stack to obtain the node detection result; The current graph node refers to the target memory node object that the computer's underlying instruction pointer or graph traversal algorithm probe is currently reading, accessing, and performing logical operations on within the current time slice.

[0057] The node detection result refers to the boolean status indicator output by the computer system after comparing the physical memory address or globally unique identifier of the current graph node with the set of addresses or identifiers stored in the stack of active nodes.

[0058] S306: If the node detection result indicates that the current graph node already exists in the active node stack, then it is determined that the current detection path has a closed loop, triggering a circular dependency warning; A closed loop refers to a physical deadlock path in a task-dependent topology model, consisting of a series of directed edges connected end to end. This means that the computation task has a direct or indirect circular dependency on its own computation results.

[0059] A circular dependency warning refers to a software or hardware interrupt event or exception triggered by the underlying computer system when a closed loop is detected. This event forces the current scheduled task to be suspended and sends an error message to the upper-level monitoring service.

[0060] S308: If the node detection result is that none of the current graph nodes exist in the active node stack, then the closed-loop link detection is determined to be successful.

[0061] Indicatively, the service platform initiates a closed-loop link detection command for the completed task-dependent topology model. It allocates a linear and continuous address space in the system heap memory area to initialize an active node stack in physical form. Then, following a depth-first search strategy, it traverses the path along the directed edges from any unvisited graph node as the probe root node. During the path traversal, each time the probe visits a new graph node, it physically pushes the memory address reference or global identifier data of that node onto the top of the active node stack to accurately record the extension trajectory of the current probe path. When the current graph node is reached, the feature identifier of the current graph node is immediately extracted and hashed or traversed and matched with all resident elements from the bottom to the top of the active node stack to obtain the node detection result. If the node detection result indicates that the feature identifier of the current graph node already exists in the active node stack, then from the computer's underlying logic, it is confirmed that the probe has accessed the root node that has not yet been backtracked and probed. Then, it is determined that the current probe path has a closed loop that leads to deadlock and immediately triggers a system-level exception throwing program to execute a circular dependency warning, thereby forcibly interrupting the subsequent infinite recursive calls that may cause memory overflow. Conversely, after the probe completes the detection of the current node and all its downstream paths, it will physically pop the node from the active node stack for safe backtracking. If all connected components in the topology model have been fully scanned and the detection results show that none of the visited current graph nodes exist in their respective active node stacks during the entire lifecycle detection comparison, then the topology model is determined to be a strictly directed acyclic graph, and the closed-loop link detection is officially determined to be passed and the probe resources are released.

[0062] In this specification, the above-described method is used to implement a robust, forward-looking computer underlying graph topology defense mechanism with low latency response characteristics. This mechanism not only achieves accurate location and interception of hidden configuration errors at the physical memory level, but also ensures the absolute acyclicity and security of the subsequent task linear scheduling pipeline, thereby improving the fault tolerance and high-concurrency robustness of the entire data processing platform.

[0063] Furthermore, to specifically execute the triggering of the circular dependency warning described in S306, the following methods can be used: Step A2: Extract the sequence of graph nodes that form a closed loop from the active node stack as cycle feature information; A sequence of graph nodes that forms a closed loop refers to an ordered set of all consecutive graph node identifiers in the active node stack of memory, starting from the physical addressing position where the target graph node that was repeatedly hit was first pushed onto the stack, up to the current top of the stack. In the physical sense of graph theory, it represents a complete loop trajectory.

[0064] Cyclic feature information refers to the data context object used to solidify, record, and report deadlock states. In addition to containing the sequence of graph nodes that caused the deadlock, it usually also contains underlying diagnostic metadata such as the memory overflow risk level, the timestamp that triggered the exception, and the batch number of the computation task to which the exception belongs.

[0065] Step A4: Trigger a computation scheduling exception instruction and block computation task processing.

[0066] Computational scheduling exception instructions refer to software and hardware interrupt signals, exception throwing instructions, and event alarm messages issued to the instruction register of the central processing unit or the virtual machine execution engine when a fatal logical error is received.

[0067] Blocking computational task processing refers to the service platform forcibly suspending subsequent parsing operations of the topology model that the current task depends on, clearing the memory ready queue, and refusing to allocate underlying CPU computing threads and physical memory resources to the batch of tasks as a security protection action.

[0068] Indicatively, after the processor of the service platform confirms that the current graph node exists in the active node stack in the memory comparison logic, the system memory scanning module immediately triggers a physical stack slicing operation. Specifically, the system's underlying layer uses an addressing pointer to search backwards from bottom to top in the active node stack of contiguous memory space for the physical offset address or array index where the current graph node was first pushed onto the stack. Then, it uses memory copy instructions to completely extract the contiguous memory data block defined by the offset address up to the current stack top pointer, thereby accurately extracting the graph node sequence that constitutes a closed loop. This sequence is then encapsulated together with hardware status information such as the current system clock and thread ID and serialized into a loop. The ring feature information object generates and throws the highest priority computation scheduling exception instruction (such as a severe runtime interrupt signal) directly at the virtual machine level or operating system kernel level. After the service platform's main control scheduler captures the exception instruction, it immediately forcibly terminates the probe thread that is currently performing graph traversal operations. At the same time, it starts the memory reclamation garbage collector (GC) to perform memory destruction and resource release on the incomplete task dependency topology model and its associated logical mapping relationship dictionary, and forcibly clears the ready queue for subsequent topology sorting and computation execution. Thus, at the forefront of physical hardware resource allocation, it completely blocks the subsequent flow of this batch of computation tasks.

[0069] This specification describes a series of techniques that achieve a low-level defense mechanism that combines rapid damage mitigation and precise accountability. These techniques involve precisely executing slicing operations in the memory stack to extract the sequence of graph nodes forming closed loops as loop feature information, and then triggering the highest-priority computation scheduling exception instruction to forcibly block the computation task processing pipeline. This not only releases computing power and memory addressing space in the first instance through physical-level abnormal interruption, ensuring the overall operational security of the service platform, but also provides R&D and business personnel with extremely accurate code-level and configuration-level repair guidance through the fully extracted loop link context features, significantly reducing system operation and maintenance and troubleshooting costs.

[0070] Optional, please see Figure 4 , Figure 4 This is a flowchart illustrating a topology sorting process proposed in this specification. Specifically, the process involves performing a topology sort on the task-dependent topology model to obtain a linear computation sequence of tasks with execution priorities. The following method can be used as a reference: S402: Scan the in-degree values ​​of each graph node in the task-dependent topology model, and extract the graph nodes with in-degree values ​​that are preset target values ​​into the initial scheduling queue; In a directed graph data structure, the in-degree value refers to the total number of directed edges that precisely point to a specific graph node. In the embodiments of this specification, its physical meaning represents the total number of preceding derived dependency parameters that the computational task corresponding to that graph node needs to wait for.

[0071] The preset target value refers to the threshold condition that triggers a graph node to enter the schedulable state. Optionally, in topology sorting, this value can be configured to zero, which means that all the node's prerequisites have been removed or that there were no dependencies to begin with.

[0072] The initial scheduling queue is a linear buffer storage area in computer memory based on the first-in-first-out (FIFO) principle, used to temporarily store the set of graph nodes that have met the execution conditions (i.e., the in-degree has reached the preset target value) in the current stage.

[0073] S404: Execute node extraction operation cyclically on the initial scheduling queue to write the graph nodes in the initial scheduling queue into the task linear computation sequence through the node extraction operation, assign concurrent hierarchical labels with consistent depth to the graph node set pushed in the same cyclic batch, and virtually strip the directed edges extended from the graph nodes. Concurrency level labels refer to the depth attribute metadata attached to graph nodes during the sorting process. Graph nodes with the same concurrency level label are independent of each other during the physical execution phase and can be safely assigned to different threads on a multi-core processor for lock-free concurrent computation.

[0074] Virtual stripping refers to the operation of removing the physical directed edge objects in computer memory without actually erasing them, but by modifying the status bits or decrementing the association counter, thereby ensuring the integrity and reusability of the physical data of the original topology model.

[0075] S406: Dynamically update the in-degree values ​​of downstream graph nodes affected by the directed edge stripping, and continuously push downstream graph nodes with updated in-degree values ​​that are the preset target values ​​into the initial scheduling queue until all graph nodes in the task-dependent topology model have been extracted.

[0076] Indicatively, the service platform first performs a global scan of the task-dependent topology model residing in main memory via the processor (CPU). The memory controller traverses the attribute blocks of all graph node objects to count their in-degree values, and extracts graph nodes with in-degree values ​​equal to a preset target value (such as 0) and pushes them into an initial scheduling queue initialized in heap memory. Then, it controls the main scheduling thread to enter the core loop stage of topology sorting. To accurately implement batch dequeueing and level labeling, a dual-queue alternation mechanism of "current batch queue" and "next batch buffer queue" is introduced in memory.

[0077] The service platform's system first initializes a depth counter (initial value 1). In a single large loop, all existing graph nodes in the current initial scheduling queue can be extracted at once as an independent loop batch set. For each graph node in this set, the system first sequentially writes its memory address pointer into the storage area of ​​the task's linear computation sequence for persistence. Then, the system uniformly appends the current depth counter value to all graph nodes in this batch set as a concurrent level label for consistent depth (e.g., all labeled Level-1). After labeling, the system performs a virtual stripping operation for each graph node in the batch: it finds all directed edges extending outward from the graph node based on the adjacency list, locates the downstream graph nodes pointed to by these directed edges using address pointers, and dynamically decrements the in-degree values ​​of these downstream graph nodes using underlying atomic decrement operations. After each decrement operation, the system immediately performs a conditional check. Once it finds that the updated in-degree value of a downstream graph node has precisely dropped to the preset target value (i.e., all prerequisite dependencies have been virtually removed), the system continuously pushes this downstream graph node into the next batch buffer queue. Once all graph nodes in the current batch have been processed, the system increments the depth counter by one, assigns the next batch buffer queue to the initial scheduling queue, clears the buffer queue, and starts the next large loop. Then, the control processor continuously executes the closed-loop logic of batch node extraction, labeling, virtual edge stripping, and dynamic downstream in-degree updates until the initial scheduling queue is empty, meaning that all graph nodes in the task-dependent topology model have been safely extracted.

[0078] In this specification, by scanning the in-degree of nodes and introducing an initial scheduling queue for buffering, an innovative batch-based cyclic extraction operation is performed in the core sorting stage. This not only safely and orderly reduces the dimensionality of the two-dimensional topology model into the one-dimensional linear computation sequence of the task, but also achieves a structured sorting scheme that can adapt to the underlying multi-threaded concurrent scheduling mechanism by accurately assigning concurrent hierarchical labels with consistent depth to the node sets extracted in the same batch, and dynamically promoting the update of the in-degree of downstream nodes by combining virtual stripping technology. This improves the system's parsing and reorganization efficiency when dealing with large and complex task dependency networks, and lays the foundation for the safe, lock-free, and high-throughput hierarchical parallel execution of the subsequent computing engine.

[0079] Furthermore, based on S402-S406, the specific execution of compiling and executing the task metrics according to the linear calculation sequence of the task to obtain the calculation task results can be carried out in the following manner: Step B2: Based on the concurrency level labels, divide the linear computation sequence of the task into multiple computational layers; Computational layering refers to the physical or logical aggregation of graph nodes with the same concurrency layer label in a linear computational sequence of tasks within computer memory, forming a batch of tasks. All tasks within the same computational layer have no data dependencies on each other and are capable of absolute parallel execution.

[0080] Step B4: Following the depth order of the concurrency level labels, encapsulate the computational logic rules corresponding to each graph node in the same computational layer into independent computational units and concurrently distribute the independent computational units to the underlying computational thread pool for computation.

[0081] An independent computing unit refers to an executable object instance (such as a thread task class object that implements a specific interface) formed by isolating and encapsulating a single computing logic rule, ready parameter data, and execution context environment at the system's underlying level in order to achieve multi-threaded concurrency. It can independently occupy CPU time slices for computation without being interfered with by other units.

[0082] The underlying computing thread pool refers to a multi-threaded software design pattern that resides in the operating system's memory. It pre-initializes and maintains a certain number of physical or virtual processing threads to concurrently receive, schedule, and execute distributed independent computing units, thereby avoiding the system resource overhead caused by frequent thread creation and destruction.

[0083] Layer-by-layer concurrent distribution combines synchronous blocking and asynchronous concurrency in computer scheduling mechanisms. On the timeline, the system synchronously waits for switching according to the order of layer depth (first layer, second layer, etc.); while at the same layer from a micro perspective, the characteristics of multi-core processors are used to asynchronously and concurrently deliver tasks to multiple processing cores for simultaneous execution.

[0084] Indicatively, the service platform first extracts the linear computation sequence of tasks generated by topological sorting. It then traverses the concurrency level labels carried by each graph node in this sequence. Using hash grouping algorithms or contiguous memory slicing techniques, graph nodes with the same concurrency level labels (e.g., depths of Level-1 and Level-2) are aggregated into different dynamic array sets, thus physically dividing the memory heap into multiple computational layers with clear structural boundaries. Next, the platform controls the computer's underlying scheduling engine to instantiate a low-level computational thread pool optimized for multi-core architecture and initialize a system-level synchronization control primitive (e.g., synchronization barriers, countdown latches). Following the numerical order of the concurrency level labels from shallow to deep (i.e., depth order starting from 1 and increasing), the scheduling engine extracts the first computational layer at the shallowest depth. It then compiles the computational logic rules corresponding to each graph node within this layer into bytecode and encapsulates them, along with their required input variables, into a memory-isolated independent computational unit (e.g., Runnable or Callable task objects).

[0085] The main control thread distributes these independent computational units concurrently and without blocking to the task ready queue of the underlying computational thread pool. Multiple idle physical worker threads within the thread pool then concurrently retrieve these tasks and execute them using a multi-core CPU. During this period, the main control thread enters a blocked, suspended state using the aforementioned synchronization control primitive until the underlying computational thread pool reports that all independent computational units within that computational layer have completed execution and successfully written their results back to the shared state table. At this point, the synchronization barrier is released, the main control thread is awakened, and it continues to advance to the next depth level according to the computational layer order, repeating the above encapsulation and concurrent distribution actions until all computational layers have been stripped away and computation completed.

[0086] This specification employs a series of technical measures, including rigorous physical segmentation of linear computation sequences based on concurrency level labels, innovative cross-layer serial synchronization and intra-layer parallel asynchronous scheduling mechanisms, and encapsulation of each graph node as an independent computation unit before concurrent distribution to the underlying computation thread pool. These measures fully unleash the multi-core and multi-threaded concurrent computation potential of modern computers while ensuring the security of extremely complex business logic data dependencies and the orderliness of topological operations. This enables unrelated tasks at the same level to be processed with maximum throughput, improving the high concurrency throughput and hardware resource utilization of the data processing platform.

[0087] Optional, please refer to Figure 5 , Figure 5 This is a flowchart illustrating the compilation and execution of task metrics. Specifically, the task metrics are compiled and executed according to the linear calculation sequence of the task to obtain the calculation task results. The following method can be used as a reference: S502: Use the character expression of the computation logic rule corresponding to the node computation task as the addressing index to perform a matching query in the memory object cache pool; Character expressions refer to the definition of computational logic rules (such as formula strings or rule script text) that exist in the form of readable strings in node computation tasks. They cannot be directly calculated by the computer's underlying microprocessor, but need to be translated by the compilation environment.

[0088] Addressing indexes are hash keys or memory address pointers used in computer physical memory or key-value storage systems to uniquely locate and quickly retrieve target data blocks.

[0089] S504: If the matching query is successful, the pre-stored underlying execution object is extracted from the memory object cache pool, and the task calculation is performed to obtain the calculation task result; The underlying execution object refers to the memory structure entity, executable bytecode block, function pointer, or abstract syntax tree (AST) instance object that can be directly called by the computer after the character expression has undergone lexical analysis, syntax tree construction, and compilation optimization.

[0090] S506: If the matching query fails, the character expression is parsed to generate a low-level execution object that can be run by the computer, and the generated low-level execution object is filled back into the memory object cache pool.

[0091] Syntax parsing refers to the process by which a system's compiler or interpreter components transform an unstructured string sequence of characters into structured machine instructions or intermediate code that conforms to the underlying operating rules of the computer.

[0092] As an illustration, after the execution engine of the service platform obtains the task metrics to be processed, it first extracts the character expression string corresponding to the task to be calculated by the node. The underlying processor performs data hash calculation on the string using an irreversible cryptographic hash algorithm (such as SHA-256) to generate a unique hash value. This hash value is used as an addressing index to perform high-frequency physical memory address matching queries in the concurrent secure hash mapping table (i.e., memory object cache pool) allocated in the system heap memory. If the underlying query returns a match, it means that the calculation rule has been compiled within the historical period. The system memory controller will directly use the memory base address pointer returned by the match to completely extract the pre-stored underlying execution object (such as a pre-compiled bytecode class instance) from the memory object cache pool, and then inject the ready numerical parameters in the current task context as input parameters into the object. The underlying calculation thread will directly call the underlying calculation instructions to perform task calculation and execution, thereby obtaining the calculation task result at extremely fast speed. Conversely, if the underlying query returns a no-match, it means that the current computing engine is encountering this business logic rule for the first time. The system then suspends the current computing thread and triggers the just-in-time compiler module. The compiler module allocates processor resources to perform deep lexical decomposition and abstract syntax tree construction on the character expression, compiling it from a string state into an executable low-level execution object in real time. While the current computing task uses this newly generated low-level execution object to complete its first numerical calculation, the system's underlying layer simultaneously triggers a memory write operation, persistently filling the generated low-level execution object along with the previously calculated addressing index back into the physical storage block of the memory object cache pool. This ensures that when the service node faces the same logical calculation again, it can directly bypass the compilation overhead and achieve physical retrieval.

[0093] In this specification, a series of techniques are employed to implement a low-level computer scheduling mechanism that allows for compilation once and reuse multiple times. This mechanism eliminates I / O parsing bottlenecks on the computation execution path and achieves overall throughput improvement and stability of concurrent processing with lower main memory space overhead. These techniques include introducing character expressions as addressing indexes into the memory object cache pool for pre-matching queries before execution, directly retrieving pre-stored objects when a match is found, and triggering parsing and backfilling only when a match is missed.

[0094] Optionally, the task calculation and execution described in S504 to obtain the calculation task result can be performed in the following manner: Step C2: Initialize the computation execution scope for the computation task on the current node; The computation execution scope refers to the execution context environment with memory isolation characteristics that is specially allocated in the computer's physical memory or virtual machine stack for the current specific computation task. It is used to temporarily store local variables, state pointers and execution stack frames during the computation process.

[0095] Step C4: Dynamically inject the data values ​​of the basic input parameters and the system's preset business function library into the computation execution scope; Dynamic injection refers to the process by which a computer system loads external data values ​​or dependent objects directly into the target runtime scope at runtime, rather than at compile time, through low-level techniques such as reflection, memory address mapping, or environment variable passing.

[0096] A business function library refers to a class library that is pre-written and packaged in the underlying storage medium of the system, containing specific mathematical models, string processing logic, and a collection of professional domain algorithm code.

[0097] Step C6: Drive the underlying execution object to perform numerical operations within the computation execution scope to obtain the computation task result, and write the computation task result into the memory shared state table for tasks with derived dependencies to read the call table data.

[0098] A shared memory state table is a global hash structure or memory data grid that is allocated in the main memory of a computer and supports safe reading and writing by multiple threads. It is used to seamlessly transfer intermediate calculation results between computing tasks on different nodes.

[0099] Derivative dependencies refer to the physical data dependency attribute that a node computation task located at a later level in a topological sort must obtain the current node's computation result as its input parameter through memory address addressing when the underlying arithmetic logic is executed.

[0100] Indicatively, after the service platform's execution engine extracts the underlying execution object, it uses CP to allocate a protected contiguous address space in the current worker thread's thread-local storage area or independent heap memory to initialize a pure and isolated computational execution scope for the current node's computational task. Then, based on the parameter addressing index generated by pre-parsing, it directly retrieves the data values ​​of ready basic input parameters from the external gateway or local database buffer pool. Using underlying reflection mechanisms and dynamic link library loading technology, it maps these data values ​​and the system's pre-built business function library across memory address spaces and dynamically injects them into the variable symbol table of the computational execution scope. Then... The layer scheduler directs the processor program counter to the entry memory address of the underlying execution object to drive the underlying execution object to perform register-based scalar or vectorized numerical operations within the computation execution scope and obtain the specific computation task result. Before the end of the computation cycle, the worker thread calls the underlying concurrency control primitive to acquire a global write lock, serializes the numerical entity of the computation task result and writes it into the memory shared state table maintained by main memory. This ensures that subsequent tasks downstream of the topology sequence and with derivative dependencies can directly and quickly read and call the data in the table based on the key-value index when they are awakened, thereby completing the physical handover of data in a single-machine environment.

[0101] In this specification, by allocating an independent computational execution scope to node tasks before execution, and dynamically injecting basic input parameters and pre-built business function libraries into this isolated environment, ultimately driving the underlying objects to perform computations and persisting the results to a shared memory state table for downstream calls, this series of technical measures not only eliminates data contention and dirty reads in concurrent computing scenarios at the physical memory level, improving the numerical accuracy and system robustness of computational task results, but also constructs a high-speed data channel from a global perspective through the shared memory state table. This allows complex topology task flows with derivative dependencies to be relayed with extremely low latency in pure memory, improving the overall concurrent throughput and processor instruction execution efficiency in large-scale data processing scenarios.

[0102] The following will combine Figure 6 This specification provides a detailed description of the computing task processing apparatus provided in the embodiments. It should be noted that... Figure 6 The computing task processing device shown is used to execute the instructions in this manual. Figures 1-5 The methods shown in the embodiments are illustrated for ease of explanation, showing only the parts related to the embodiments of this specification. For specific technical details not disclosed, please refer to this specification. Figures 1-5 The example shown.

[0103] Please see Figure 6 This diagram illustrates the structure of a computational task processing device according to an embodiment of this specification. The computational task processing device 1 can be implemented as all or part of a device through software, hardware, or a combination of both. According to some embodiments, the computational task processing device 1 includes a task processing module 11, a model building module 12, a loop closure detection module 13, and a compilation and execution module 14, specifically used for: Task processing module 11 is used to obtain a set of node computing tasks in the target data processing scenario, parse each computing logic rule in the set of node computing tasks to extract a list of rule parameters, and divide the list of rule parameters by parameter attributes to obtain basic input parameters and derived dependency parameters. Model building module 12 is used to establish a logical mapping relationship between computing tasks of each node based on the derived dependency parameters, and to build a task dependency topology model by constructing a directed task graph based on the logical mapping relationship. The graph nodes of the task dependency topology model are configured as result identifiers of computing tasks, and the directed edges between the graph nodes are configured as call pointing relationships between the computing logic rules and the derived dependency parameters. The closed-loop detection module 13 is used to perform closed-loop link detection on the task-dependent topology model, and after the detection is passed, perform topological sorting on the task-dependent topology model to obtain a linear computation sequence of tasks with execution priority; The compilation and execution module 14 is used to compile and execute task indicators according to the linear calculation sequence of the task to obtain the calculation task results.

[0104] It should be noted that the computing task processing device provided in the above embodiments is only illustrated by the division of the above functional modules when executing the computing task processing method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the computing task processing device and the computing task processing method embodiments provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiments, which will not be repeated here.

[0105] The example numbers in this specification are for descriptive purposes only and do not represent the superiority or inferiority of the examples.

[0106] This specification also provides a computer storage medium that can store multiple instructions adapted to be loaded and executed by a processor as described above. Figures 1-5 The specific execution process of the computational task processing method described in the illustrated embodiment can be found in [reference needed]. Figures 1-5 The specific details of the illustrated embodiments will not be elaborated here.

[0107] This specification also provides a computer program product that stores at least one instruction, said at least one instruction being loaded and executed by the processor as described above. Figures 1-5 The specific execution process of the computational task processing method described in the illustrated embodiment can be found in [reference needed]. Figures 1-5 The specific details of the illustrated embodiments will not be elaborated here.

[0108] Please refer to Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of this specification. The electronic device in this specification may include one or more of the following components: a processor 1010, a memory 1020, an input device 1030, an output device 1040, and a bus 1050. The processor 1010, memory 1020, input device 1030, and output device 1040 may be connected to each other via the bus 1050.

[0109] Processor 1010 may include one or more processing cores. Processor 1010 connects to various parts of the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory 1020, and by calling data stored in memory 1020. Optionally, processor 1010 may be implemented using at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). Processor 1010 may integrate one or a combination of central processing unit (CPU), graphics processing unit (GPU), and modem. The CPU mainly handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the displayed content; and the modem is used for wireless communication. It is understood that the modem may also not be integrated into processor 1010 and may be implemented separately through a communication chip.

[0110] The memory 1020 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1020 may include non-transitory computer-readable storage medium. The memory 1020 may be used to store instructions, programs, code, code sets, or instruction sets.

[0111] The input device 1030 is used to receive input instructions or data, and the input device 1030 includes, but is not limited to, a keyboard, mouse, camera, microphone, or touch device. The output device 1040 is used to output instructions or data, and the output device 1040 includes, but is not limited to, display devices and speakers.

[0112] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include radio frequency circuits, input units, sensors, audio circuits, wireless fidelity (WIFI) modules, power supplies, Bluetooth modules, etc., which will not be described in detail here.

[0113] In the embodiments of this specification, the executing entity for each step can be the electronic device described above. Optionally, the executing entity for each step can be the operating system of the electronic device. The operating system can be Android, iOS, or other operating systems; this specification does not limit this.

[0114] exist Figure 7 In the electronic device, the processor 1010 can be used to call a program stored in the memory 1020 and execute it to implement the computing task processing method as described in the various method embodiments of this specification.

[0115] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0116] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in the embodiments of this specification are all authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the features, data, and information involved in this specification were all obtained under full authorization.

[0117] The above-disclosed embodiments are merely preferred embodiments of this specification and should not be construed as limiting the scope of this specification. Therefore, any equivalent variations made in accordance with the claims of this specification shall still fall within the scope of this specification.

Claims

1. A method for processing computational tasks, characterized in that, Applied to a service platform, the method includes: Obtain a set of node computing tasks in the target data processing scenario, parse each computing logic rule in the set of node computing tasks to extract a list of rule parameters, and divide the list of rule parameters by parameter attributes to obtain basic input parameters and derived dependency parameters. Based on the derived dependency parameters, a logical mapping relationship is established between the computing tasks of each node. Based on the logical mapping relationship, a directed task graph is constructed to obtain a task dependency topology model. The graph nodes of the task dependency topology model are configured as result identifiers of computing tasks, and the directed edges between the graph nodes are configured as the calling relationship between the computing logic rules and the derived dependency parameters. Closed-loop link detection is performed on the task-dependent topology model, and after the detection is passed, the task-dependent topology model is sorted to obtain a linear computation sequence of tasks with execution priority; The task metrics are compiled and executed according to the linear calculation sequence of the task to obtain the calculation task results.

2. The method according to claim 1, characterized in that, The process of constructing a directed task graph based on the logical mapping relationship to obtain a task-dependent topology model includes: Initialize a graph data structure instance for the task-dependent topology model; Traverse the logical mapping relationship and instantiate the result of each node's computation task into a target graph node in the graph data structure instance; Iterate through the derived dependency parameters corresponding to the task of each node, and address the dependency graph node corresponding to the derived dependency parameter in the graph data structure instance; A directional memory pointer mapping is established between the target graph node and the dependency graph node to form directed edges corresponding to the call pointing relationship.

3. The method according to claim 1 or 2, characterized in that, The step of performing closed-loop link detection on the task-dependent topology model includes: Perform path traversal on the directed edges and maintain a stack of active nodes to record the current probe path during the path traversal process; When accessing the current graph node, the node detection result is obtained by detecting whether the current graph node already exists in the active node stack; If the node detection result indicates that the current graph node already exists in the active node stack, then it is determined that the current detection path has a closed loop, triggering a circular dependency warning; If the node detection result is that none of the current graph nodes exist in the active node stack, then the closed-loop link detection is determined to be successful.

4. The method according to claim 3, characterized in that, The triggering of circular dependency warnings includes: Extract the sequence of graph nodes that form a closed loop from the active node stack as loop feature information; Trigger a computation scheduling exception instruction and block computation task processing.

5. The method according to claim 1, characterized in that, The step of performing topological sorting on the task-dependent topology model to obtain a linear computation sequence of tasks with execution priorities includes: Scan the in-degree values ​​of each graph node in the task-dependent topology model, and extract the graph nodes with in-degree values ​​that are preset target values ​​into the initial scheduling queue; The node extraction operation is performed cyclically on the initial scheduling queue to write the graph nodes in the initial scheduling queue into the task linear computation sequence through the node extraction operation. Concurrent hierarchical labels with consistent depth are assigned to the graph node set pushed in the same cyclic batch, and the directed edges extending from the graph nodes are virtually stripped. The in-degree values ​​of downstream graph nodes affected by the directed edge stripping are dynamically updated, and downstream graph nodes with updated in-degree values ​​that are at a preset target value are continuously pushed into the initial scheduling queue until all graph nodes in the task-dependent topology model have been extracted.

6. The method according to claim 5, characterized in that, The step of compiling and executing task metrics based on the linear calculation sequence of the task to obtain the calculation task results includes: Based on the concurrency level labels, the linear computation sequence of the task is divided into multiple computational layers; Following the depth order of the concurrency level labels, the computational logic rules corresponding to each graph node in the same computational layer are encapsulated into independent computational units and the independent computational units are concurrently distributed to the underlying computational thread pool for computation.

7. The method according to claim 1, characterized in that, The step of compiling and executing task metrics based on the linear calculation sequence of the task to obtain the calculation task results includes: The character expression of the computation logic rule corresponding to the node computation task is used as the addressing index to perform a matching query in the memory object cache pool; If the matching query is successful, the pre-stored underlying execution object is retrieved from the memory object cache pool, and the task calculation is performed to obtain the calculation task result; If the matching query fails, the character expression is parsed to generate a low-level execution object that can be run by the computer, and the generated low-level execution object is then populated back into the memory object cache pool.

8. The method according to claim 7, characterized in that, The process of performing task calculations to obtain the calculation results includes: Initialize the computation execution scope for the computation task on the current node; The data values ​​of the basic input parameters and the system's pre-set business function library are dynamically injected into the computational execution scope. The underlying execution object is driven to perform numerical operations within the computation execution scope to obtain the computation task result, and the computation task result is written into the memory shared state table for tasks with derived dependencies to read the call table data.

9. A computing task processing device, characterized in that, The device, applied to a service platform, includes: The task processing module is used to obtain a set of node computing tasks in the target data processing scenario, parse each computing logic rule in the set of node computing tasks to extract a list of rule parameters, and divide the list of rule parameters by parameter attributes to obtain basic input parameters and derived dependency parameters. The model building module is used to establish a logical mapping relationship between the computing tasks of each node based on the derived dependency parameters, and to build a task dependency topology model by constructing a directed task graph based on the logical mapping relationship. The graph nodes of the task dependency topology model are configured as result identifiers of computing tasks, and the directed edges between the graph nodes are configured as the calling relationship between the computing logic rules and the derived dependency parameters. The closed-loop detection module is used to perform closed-loop link detection on the task-dependent topology model, and after the detection is successful, perform topological sorting on the task-dependent topology model to obtain a linear computation sequence of tasks with execution priority. The compilation and execution module is used to compile and execute task metrics according to the linear calculation sequence of the task, and obtain the calculation task results.

10. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions adapted for loading by a processor and executing the steps of the method as described in any one of claims 1 to 8.

11. A computer program product, characterized in that, The computer program product stores at least one instruction, which is loaded by a processor and executed according to the steps of the method as described in any one of claims 1 to 8.

12. An electronic device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to execute the steps of the method as described in any one of claims 1 to 8.

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