A load prediction-based SSD cache scheduling method, device and medium

Abstract

This invention discloses an SSD cache scheduling method, device, and medium based on load prediction, relating to the field of computer storage management technology. Its key technical points are: before the load prediction results enter the SSD cache scheduling process, cache candidate records and access segment comparison records are constructed. Residual attribution is performed for the same object and time window for increases in random read latency, expansion of logical address span, and changes in host memory buffer pressure, generating address mapping disturbance residuals and disturbed window markers. Then, the scheduling authority state machine gates cache migration, cache degradation, hot / cold label updates, and stable history write-back, preventing address mapping access disturbances caused by host memory buffer pressure from being mistakenly written as data hotness changes, thereby reducing erroneous cache migration and hot / cold state contamination in DRAM-less SSDs under host memory pressure fluctuation scenarios.

Description

Technical Field

[0001] This invention relates to the field of computer storage management technology, specifically to an SSD cache scheduling method, device, and medium based on load prediction. Background Technology

[0002] With the proliferation of edge computing terminals, lightweight servers, and local intelligent processing devices, DRAM-less NVMe SSDs are often configured as system disks, cache disks, and temporary computing data disks. They are used to carry intermediate data during application startup, video clip caching, lightweight database access, and local inference processes. To reduce controller costs, these SSDs typically do not have independent dynamic random access memory on the controller side. Instead, they utilize the HostMemoryBuffer capability in the NVMe protocol to allocate a portion of the host memory for auxiliary logical address to physical address mapping access. For example, in edge video analytics devices, the device continuously receives surveillance video and writes it to the local cache during the day. At night, it runs a target recognition model according to the task plan, extracting, playing back, and partially re-examining historical video clips. At this time, the host memory carries the operating system page cache and video decoding buffer, as well as the working data during model operation. It also needs to provide the host memory buffer space required for SSD mapping access. When model loading, video playback, and random clip reading occur in clusters, the available space of the host memory, page reclamation status, and application working set will change with the task stage, making the stability of SSD access to address mapping information affected by the host's operating status.

[0003] Existing SSD caching technologies typically predict load changes based on operational data such as historical access frequency, request interval, read / write ratio, queue depth, and access latency, and adjust cache retention, cache migration, write-back, and bypass strategies accordingly. In SSDs with independent controller caches, access latency changes largely reflect data locality changes, cache hit status, and background maintenance pressure. Load prediction based on this type of data has a relatively clear engineering basis. However, in scenarios where DRAM-less SSDs use host memory buffers to store address mapping information, the increase in random access latency may also stem from mapping access disturbances caused by enhanced host memory reclamation, application working set expansion, and increased logical address span. If cache scheduling only updates data hot / cold status based on I / O latency patterns, it may interpret mapping access jitter as a change in data access patterns, thereby prematurely triggering cache object migration, hot / cold label updates, and write-back priority adjustments. This phenomenon causes cache scheduling actions to deviate from the actual data hotness and further expands the mapping access span under high random access loads, ultimately affecting the stability of random I / O in edge devices and local smart terminals. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides the following technical solution: A load prediction-based SSD cache scheduling method includes: Obtain the SSD running status record and host memory buffer pressure record that are accessed using host memory buffer address mapping. Write the load prediction results into the cache candidate record. The cache candidate record records the prediction popularity, prediction confidence and logical address span of the candidate object within the candidate time window. Fragment comparison processing is used to cache candidate records and generate access fragment comparison records. The access fragment comparison records include target access fragments and reference access fragments. The target access fragment is a completed access fragment in the candidate time window where the random read latency increases and the logical address span expands. The reference access fragment is an access fragment in the completed stable access records that meets the load similarity condition with the target access fragment and has a stable logical address span. The access segment comparison record is processed by residual attribution to generate delay residuals. Then, the delay residuals and host memory buffer pressure record are processed by mapping perturbation evaluation to generate address mapping perturbation residuals. The perturbed window markers are generated according to the address mapping perturbation residuals. A scheduling permission state machine is used to process cache candidate records and verification records of the current cache scheduling cycle, generate cache scheduling permissions, and perform cache scheduling actions on candidate objects according to the cache scheduling permissions.

[0005] The present invention also provides an SSD cache scheduling device based on load prediction, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the processor executes the computer program, it implements the aforementioned SSD cache scheduling method based on load prediction.

[0006] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the aforementioned SSD cache scheduling method based on load prediction.

[0007] This invention provides an SSD cache scheduling method, device, and medium based on load prediction, which has the following beneficial effects: This invention constructs cache candidate records and access segment comparison records before the load prediction results enter the SSD cache scheduling. It performs residual attribution for the same object and time window for the same object, the same time window for the increase in random read latency, the expansion of logical address span and the change in host memory buffer pressure, and generates address mapping disturbance residuals and disturbance window tags. Then, the scheduling permission state machine gates cache migration, cache degradation, cold and hot tag update and stable history write-back, so that the address mapping access disturbance caused by host memory buffer pressure is no longer mistakenly written as data hotness change, thereby reducing the error cache migration and cold and hot state pollution of DRAM-less SSD under host memory pressure fluctuation scenarios. Attached Figure Description

[0008] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0010] Please see Figure 1 This embodiment provides an SSD cache scheduling method based on load prediction, including the following specific steps: S1: Obtain the SSD running status record and host memory buffer pressure record that are accessed using the host memory buffer to carry address mapping. Write the load prediction result into the cache candidate record. The cache candidate record records the prediction popularity, prediction confidence and logical address span of the candidate object within the candidate time window.

[0011] In this embodiment, the SSD is a solid-state drive that supports host memory buffering and uses host memory buffering to participate in address mapping access. Before performing cache scheduling, the system reads the host memory buffering enable record of the SSD to confirm that the current SSD is in the running state of host memory buffering participating in address mapping access. The host memory buffering enable record is formed by the device capability registration information in the operating system storage stack, the host memory buffering enable status maintained by the NVMe driver, and the configuration record formed by the storage service during the device initialization phase. It is a device operation record that can be obtained on the host side.

[0012] In one implementation scenario, the edge video analytics device uses an NVMe SSD without independent DRAM cache as the system disk and video cache disk. During the continuous acquisition phase, the device writes monitoring video segments. During the historical segment re-examination phase, it loads the target recognition model and randomly reads historical segments. During the historical segment re-examination phase, model weight loading, video decoding buffering, and random reading of historical segments all occupy host memory resources. The SSD random read latency may be affected by the combined effects of the expansion of logical address span and the competition for host memory buffer resources. In this scenario, the system first confirms that the SSD uses the host memory buffer to participate in address mapping access, and then generates cache candidate records so that subsequent processing is carried out based on the SSD's operating state with address mapping access disturbances.

[0013] The system uses the I / O observation window that has formed an arrival-to-completion closed link before the start of the current cache scheduling cycle as the candidate time window. The arrival-to-completion closed link refers to the time when the same access request has recorded the arrival time of the request, the time when the request was submitted to the device queue, the time when the device returned the completed request, and the completion status. The system first sets the initial length of the candidate time window according to the device type, and then calibrates it according to the number of closed access records and the number of host memory buffer pressure samples. For edge video analysis devices and local inference terminals, the candidate time window length is preferably 200 milliseconds to 2 seconds; for lightweight servers and virtualized nodes, the candidate time window length is preferably 1 second to 10 seconds. The above range is the preferred limit range during initial deployment. During calibration, the system checks whether there are closed access records in the candidate time window that are sufficient to form an access segment, and checks whether it covers no less than 5 host memory buffer pressure sampling points. No less than 5 host memory buffer pressure sampling points is the preferred lower limit, which is used to distinguish between single-point memory state jitter and continuous pressure changes within the same candidate time window.

[0014] When the closed access records within the candidate time window are insufficient to form an access segment, the system does not generate a corresponding candidate object and postpones the relevant access records to the next candidate time window to continue closing. When the closed access records meet the candidate object encapsulation conditions, but the host memory buffer pressure sampling points are less than 5, the system extends the candidate time window within the corresponding preferred limit range. If no less than 5 pressure sampling points can still be obtained after extending to the upper limit of the preferred limit range, the system generates a cache candidate record and writes the host memory buffer pressure record in the cache candidate record into the pressure pending verification state, so that the cache candidate record only participates in candidate sorting and does not enter the cache migration permit generation path. For access requests that arrive within the candidate time window but have not yet formed a completion time, the system writes the access request into the pending closure access record and processes it in the next candidate time window.

[0015] After the candidate time window is determined, the system obtains the SSD running status record and the host memory buffer pressure record within the same candidate time window. The SSD running status record is used to limit the access boundary and logical address boundary of the candidate object, and can at least reflect the logical block range, access type, completion status and queue completion order to which the closed access record belongs. The host memory buffer pressure record is used to characterize the degree to which the memory domain where the host memory buffer is located is affected by host-side resource contention within the candidate time window. The memory domain where the host memory buffer is located refers to the host memory area allocated for the SSD host memory buffer and the host memory management scope in which it is located. The system uses the change in the available capacity of this memory domain as the main source of pressure, and page reclamation activity and the stable state of host memory buffer allocation as the verification source.

[0016] Within the same candidate time window, if the available capacity of the memory domain containing the host memory buffer shows a decreasing trend in at least half of the valid pressure sampling points, and this is accompanied by any pressure direction consistent with enhanced page reclamation activity, decreased host memory buffer allocation size, failed host memory buffer reallocation request, or host memory buffer re-establishment event in the driver record, the system will write the host memory buffer pressure record to the candidate window pressure enhancement state. If the same window confirmation condition is not met, the system will write the host memory buffer pressure record to the normal pressure state. If there are insufficient pressure sampling points and the candidate time window cannot be extended within the preferred limit, the system will write the host memory buffer pressure record to the pressure pending verification state. The candidate window pressure enhancement state is only used for prediction confidence downgrading in S1 and is not used as a direct basis for the establishment of host memory buffer pressure acceptance in S3. S3 will re-execute the pressure acceptance judgment according to the valid pressure sampling records within the respective time periods of the target access segment and the reference access segment.

[0017] The system processes closed access records using a fixed cache management granularity within a single scheduling cycle. Access records within the same cache management granularity range are encapsulated as candidate objects. The cache management granularity is formed by the alignment relationship between the system cache page size and the SSD logical block size as integer multiples, and remains fixed within the current scheduling cycle. For NVMe SSDs with 4KB logical blocks, the cache management granularity is preferably 32KB to 1MB, corresponding to 8 to 256 4KB logical blocks. The specific value is determined according to the access object type: for lightweight database index pages and small block state files in the local inference process, which are biased towards random access, the cache management granularity is preferably 32KB to 128KB; for ordinary application caches and mixed read / write tasks, it is preferably 64KB to 256KB; for continuous video segment reading, it is preferably 512KB to 1MB. The above value range is jointly formed by the system cache page size, the SSD logical block size, and the access object granularity, and is calibrated within the stable operating window based on the average access length of the closed access records.

[0018] When a closed access record lacks a logical block range, has an incomplete completion status, spans multiple cache management granularities, and cannot be split according to the request boundary, the system will not encapsulate the access record as a candidate object. Instead, the access record will be written into the pending allocation record, and the object will be re-encapsulated in the next scheduling cycle. Closed access records that can be classified into the same cache management granularity range will be encapsulated into the same candidate object. After the candidate object encapsulation is completed, the system will generate a candidate object identifier for each candidate object. The candidate object identifier is formed by the SSD device identifier, the candidate time window sequence number, the cache management granularity identifier, and the logical block range covered by the candidate object. The system will write the candidate object identifier, the candidate time window sequence number, and the logical block range into the same cache candidate record to form a binding relationship between the candidate object and the candidate time window. When S2 extracts the target access segment and the reference access segment, it will directly reference the candidate object identifier in the cache candidate record.

[0019] Taking edge video analysis devices as an example, when a candidate object corresponds to the same historical video segment index range that is repeatedly read in the historical segment re-examination task, the candidate object forms a fixed object boundary in S1; when the segment shows an increase in random read latency in S2, the system still uses the candidate object identifier to access the segment for comparison, so that subsequent residual attribution and cache scheduling permission both point to the same candidate object.

[0020] After candidate objects are formed, the system writes the load prediction results into the cache candidate record. The load prediction results are generated by the time series prediction model, access frequency prediction module or application-side cache prediction module in the storage service. The system extracts fields for cache candidate judgment from the load prediction results, so that the load prediction results only generate the predicted heat and predicted confidence of the candidate objects. The predicted heat is used to indicate the degree of support for the candidate object to be accessed again in the subsequent cache scheduling cycle, and serves as the basis for subsequent candidate ranking. The predicted confidence is used to indicate the degree of consistency between the predicted heat and the stable historical access status before the candidate time window, and serves as the basis for subsequent prediction pollution judgment.

[0021] When generating predicted heat, the system reads the revisit intensity output of each candidate object from the load prediction results. If the load prediction results provide a unified output scale of 0 to 1, the system writes the revisit intensity within that output scale as the predicted heat into the cached candidate record. If the load prediction results do not provide a unified output scale, the system uses the set of candidate objects within the same candidate time window as the processing scope, sorts them from low to high according to their revisit intensity, and converts the sorting position into a normalized sorting value within the range of 0 to 1, writing it as the predicted heat into the cached candidate record. When the predicted heat is close to 0, it indicates that the load prediction results are favorable for that candidate object. The support for re-access within subsequent cache scheduling cycles is low; when the predicted heat is close to 1, it indicates that the load prediction result supports the candidate object for re-access within subsequent cache scheduling cycles. When there are fewer than 2 candidate objects, or when the re-access intensity of each candidate object is the same within the same candidate time window, the system will write the predicted heat to 0.50, the predicted confidence to 0.50, and the predicted verification status to the cache candidate record. The predicted heat is only used as a candidate ranking field in the cache candidate record, does not change the eviction weight of the candidate object in the main cache queue, and is not used as a cache migration permission field.

[0022] When forming prediction confidence, the system performs consistency processing between the predicted popularity of candidate objects and the stable historical access status before the candidate time window. The prediction confidence is a value in the range of 0 to 1. The predicted verification status is written into the status field of the cached candidate record along with the prediction confidence. The stable historical access status comes from the historical I / O observation window that has been closed before the current candidate time window. The historical I / O observation window should meet the following requirements: complete object boundary, complete completion status, pressure record is not in the pressure verification status, not written into the predicted verification status, and no disturbed window mark is generated in the historical scheduling cycle.

[0023] The system forms a historical re-access level based on closed access records in stable historical access states. The historical re-access level is formed by the number of read accesses and the number of read access bytes. The system first sorts the candidate objects in the same historical I / O observation window according to the number of read accesses. If the number of read accesses is the same, it sorts them according to the number of read access bytes. The sorting results are divided into low re-access level, medium re-access level and high re-access level. The prediction level corresponding to the current prediction heat is formed according to the prediction heat of the candidate objects in the same candidate time window and is divided into low prediction level, medium prediction level and high prediction level.

[0024] If a candidate object has a consistent historical re-access level in at least three stable historical windows, and the current predicted level is consistent with that historical re-access level, the system will write the prediction confidence level to a value in the range of 0.70 to 0.90. If the current predicted level is inconsistent with that historical re-access level, the system will write the prediction confidence level to a value in the range of 0.30 to 0.55. If a candidate object appears for the first time, or if the stable historical access status is less than three closed I / O observation windows, the system will write the prediction confidence level to 0.50 and write the predicted status to be verified to the cached candidate record. At least three stable historical windows are the preferred lower limit, used to exclude accidental consistent judgments caused by a single historical window.

[0025] If the host memory buffer pressure record within the candidate time window is in the candidate window pressure enhancement state, the system performs a downgrade write based on the above prediction confidence value. The downgraded prediction confidence is not higher than the original prediction confidence and not lower than 0. If the host memory buffer pressure record within the candidate time window is in the pressure pending verification state, the system writes the prediction confidence to 0.50 and writes the prediction pending verification state to the cached candidate record. The candidate objects written to the prediction pending verification state only participate in candidate sorting and do not enter the cache migration permit generation path.

[0026] The system generates a logical address span based on the range of logical mapping units covered by candidate objects. A logical mapping unit is the smallest statistical unit used by the system to describe the dispersion of logical addresses within the current scheduling cycle, and its size is aligned with the granularity of cache management. The system counts the number of logical mapping units covered by candidate objects and the number of discrete continuous segments, and writes both as logical address spans into the cache candidate record. When candidate objects fall concentratedly within a continuous logical address range, the number of discrete continuous segments is relatively small; when candidate objects span multiple discrete logical address ranges, the number of discrete continuous segments increases. Taking a historical segment re-examination task as an example, the replay task... When reading adjacent segments of the same video file, the logical address span of the candidate object is characterized by fewer discrete continuous segments; when the target recognition model jumps to read segment indices at multiple time points based on the detection results, the logical address span of the candidate object is characterized by more discrete continuous segments. The statistical caliber of the logical address span remains consistent in S1, S2, S3 and S4, enabling S2 to extract target access segments with increased random read latency and expanded logical address span based on the same caliber, enabling S3 to judge the logical address span inheritance result based on the same caliber, and enabling S4 to gate cache scheduling permissions based on the disturbed window flag.

[0027] After completing the above processing, the system writes the candidate object identifier, candidate time window, predicted heat, predicted confidence, logical address span, and host memory buffer pressure record into the same cache candidate record, and uses this cache candidate record as the read-only baseline record for the current scheduling cycle. The read-only baseline record is not overwritten by the verification results or cache scheduling results formed in subsequent S2, S3, and S4 within the current scheduling cycle. The target access segment, reference access segment, address mapping perturbation residual, perturbation window mark, and cache scheduling permission formed in subsequent steps all use this cache candidate record as the object source and time source. When subsequent steps need to record verification results, the system writes the verification results into the verification record of the corresponding scheduling cycle without writing back to overwrite the current cache candidate record. This step encapsulates the SSD running status record, host memory buffer pressure record, and load prediction result into a cache candidate record for subsequent access segment comparison, residual attribution, and cache scheduling permission calls.

[0028] S2, use fragment comparison processing to cache candidate records and generate access fragment comparison records. The access fragment comparison records include target access fragments and reference access fragments. The target access fragment is a completed access fragment in the candidate time window where the random read latency increases and the logical address span expands. The reference access fragment is an access fragment in the completed stable access records that meets the load similarity condition with the target access fragment and has a stable logical address span.

[0029] This step follows the execution of the cached candidate records formed in S1. The cached candidate records already contain candidate object identifiers, candidate time windows, prediction popularity, prediction confidence, logical address span, and host memory buffer pressure records. In this step, the system uses the cached candidate records as a read-only reference, without re-dividing candidate object boundaries, redetermining candidate time windows, or changing the statistical caliber of logical address span in S1. The system extracts target access segments and reference access segments around the same candidate object, so that the access segment comparison records can provide a data foundation for the subsequent generation of latency residuals in S3 that is consistent in object, time-closed, and load-comparable.

[0030] The system reads the candidate object identifier and candidate time window from the cached candidate records, and extracts the closed access records of the same candidate object within the candidate time window from the SSD running status records. The closed access records include the request arrival time, the time the request is submitted to the device queue, the device completion return time, the completion status, the access type, the request length, the logical block range, and the queue depth. The request arrival time is used to verify the closed link source of the access request. The time the request is submitted to the device queue and the device completion return time are used to confirm whether the access request is included in the candidate time window. The device completion return time is also used to form the request completion delay. The completion status is used to exclude access records that are not completed normally. The access type is used to distinguish between read access and write access. The request length is used for subsequent load similarity condition judgment. The logical block range is used to generate the logical address span. The queue depth is used to characterize the queuing status of requests carried by the SSD within the same time period. Only access records whose request submission time to the device queue and device completion return time are both within the candidate time window and whose completion status is normal are included in the fragment comparison processing. Access records that lack completion status, lack logical block range, cannot be identified by access type, or do not belong to the current candidate object identifier are written to the fragment source restricted status.

[0031] During target access segment extraction, the system uses candidate object identifiers as object boundaries and candidate time windows as time boundaries to filter read access records from closed access records. The system sorts read access records according to the time when the request is submitted to the device queue and compares whether the logical block interval of the current read access record is consecutively connected to the logical block interval of the previous read access record according to the logical mapping unit. When the starting logical mapping unit of the current read access record is immediately followed by the ending logical mapping unit of the previous read access record, and both belong to the same candidate object identifier, the system treats the current read access record as a consecutive read access record. When there is no consecutive connection between the current read access record and the previous read access record, the system writes the current read access record as a random read access record into the candidate random read sequence. The first read access record is saved as the starting record of the candidate random read sequence and is not used separately to determine the random read connection.

[0032] The system divides candidate access segments from candidate random read sequences. Candidate access segments are located within the same candidate time window and belong to the same candidate object identifier. A candidate access segment contains at least 4 completed random read access records. After being divided according to the device completion return time, both the front segment and the back segment contain at least 2 completed random read access records. This number is the preferred lower limit for candidate access segment comparison, used to form representative values ​​of the front segment request completion delay and the back segment request completion delay, respectively, and to reduce the impact of single completion delay jitter on delay trend judgment. When the system uses a higher minimum sample number as the segment comparison condition in the stable operation window, the higher minimum sample number is not less than 4 and not more than 16, and is determined based on the number of random read access records that can be continuously obtained by the same candidate object in the stable operation window. When the candidate random read sequence does not meet the segment comparison condition, the system writes the target segment insufficient status in the access segment comparison record and does not generate a target access segment.

[0033] The request completion delay is formed by the time difference between the device's completion return time and the time the request is submitted to the device queue, in milliseconds. The request completion delay is used for comparison between the preceding and following segments within the same candidate object and the same candidate time window. It is not directly added to the host memory capacity, queue depth, request length, and logical address span. The system divides the candidate access segment into the preceding segment and the following segment according to the device's completion return time, and forms a representative value for the request completion delay of the preceding segment and a representative value for the request completion delay of the following segment, respectively. The representative value for the request completion delay of the preceding segment is the median value of the request completion delay within the preceding segment, and the representative value for the request completion delay of the following segment is the median value of the request completion delay within the following segment.

[0034] The system uses the minimum discriminative latency increment to determine whether random read latency has increased. The minimum discriminative latency increment is formed by the minimum timing unit of the timestamp in the SSD's running status record and the normal completion latency change boundary in the stable historical access status. The minimum timing unit of the timestamp comes from the timing precision used when the system records the time the request is submitted to the device queue and the time the device returns upon completion. The normal completion latency change boundary comes from the stable historical access status of the same candidate object before the candidate time window. When the normal completion latency change boundary is formed, the system selects the completed stable access records corresponding to the same candidate object identifier, excluding records with incomplete object boundaries, incomplete completion status, pressure records in a pressure pending verification state, write prediction pending verification state, and historical records with disturbed window markers generated by historical scheduling cycles. If at least 6 records remain, the system... The remaining records are sorted in ascending order of requested completion delay. One record with the largest completion delay and one record with the smallest completion delay are removed. The difference between the largest and smallest completion delays in the remaining records is used as the normal completion delay change boundary. The median of the requested completion delays in the remaining records is used as the baseline completion delay. A minimum of 6 records is preferred as the lower limit, which is used to ensure that at least 4 stable historical access records are retained after removing the records at both ends to participate in the boundary formation. If any of the following occurs: fewer than 6 remaining records, the minimum time unit of the timestamp cannot be obtained, the normal completion delay change boundary cannot be formed, or the baseline completion delay cannot be formed, the system writes a historical baseline insufficiency status in the access segment comparison record and does not perform a high-confidence judgment on the increase in delay. The minimum discriminable delay increment is not less than the larger of the minimum time unit of the timestamp and the normal completion delay change boundary.

[0035] When the increment of the representative value of the later request completion delay of a candidate access segment relative to the representative value of the earlier request completion delay is not less than the minimum discriminable delay increment, and the increment of the representative value of the earlier request completion delay relative to the baseline completion delay is less than the minimum discriminable delay increment, the system writes the candidate access segment to the delay rising candidate state. When the increment of the representative value of the earlier request completion delay relative to the baseline completion delay is not less than the minimum discriminable delay increment, the system writes the candidate access segment to the initial delay already increased state and does not use the candidate access segment as the target access segment.

[0036] The system further determines whether the candidate access segment has an expanded logical address span. The logical address span follows the statistical criteria in S1, represented by the number of logical mapping units and the number of discrete continuous segments. The system counts the number of logical mapping units covered by the front and back segments of the candidate access segment, and counts the number of discrete continuous segments formed by logical block intervals in the front and back segments. When the number of logical mapping units in the back segment is greater than the number of logical mapping units in the front segment, and the number of discrete continuous segments in the back segment is greater than the number of discrete continuous segments in the front segment, the system confirms that the logical address span of the back segment has expanded relative to the front segment. If only the request length increases but the number of discrete continuous segments does not increase, the system treats it as an increase in the continuous read range and does not consider it as an expansion of the logical address span. When the number of discrete continuous segments increases but the number of logical mapping units does not increase, the system writes a span pending confirmation status and does not generate a target access segment.

[0037] Candidate access segments that simultaneously meet the conditions of rising latency candidate status and expanding logical address span are written into the target candidate segment field. The system generates a target segment identifier for the target candidate segment. The target segment identifier is formed by the candidate object identifier, the candidate time window number, and the start and end times of the target candidate segment. When multiple target candidate segments belong to the same candidate object and the same candidate time window, the system prioritizes the target candidate segment with the larger number of completed random read access records. When the number of completed random read access records is the same, the target candidate segment whose end time is closest to the end time of the candidate time window is selected as the target access segment for the current scheduling cycle. Target candidate segments that are not selected are written into the backup target segment field and do not participate in the residual attribution processing for the current scheduling cycle.

[0038] When selecting a reference access segment, the system extracts historical access segments corresponding to the candidate object identifier from the completed stable access records before the candidate time window. The historical access segments are formed within the historical I / O observation window before the candidate time window according to the same segment division caliber as the candidate access segments, and belong to the same candidate object identifier as the target access segment. The completed stable access records meet the following conditions: complete object boundary, complete completion status, pressure record is not in the pressure pending verification state, not written to the prediction pending verification state, no disturbance window mark is generated in the historical scheduling cycle, and the logical address span does not show an expanding trend. The system uses the historical access segments corresponding to the same candidate object identifier and does not use access records of other candidate objects to replace the reference access segments. When there are no completed stable access records that meet the conditions for the same candidate object identifier, the system writes the access segment comparison record into the reference segment shortage state.

[0039] The system determines whether historical access segments and target access segments meet the load similarity condition based on request length level, queue depth level, and read request ratio level. The request length level is formed based on completed access records under the same SSD and the same cache management granularity. When the representative value of the request length within a segment does not exceed 1 cache management granularity, it is written as a short request level; when it exceeds 1 cache management granularity but does not exceed 4 cache management granularities, it is written as a medium request level; and when it exceeds 4 cache management granularities, it is written as a long request level. 1 cache management granularity and 4 cache management granularities are the preferred boundaries for request length levels, used to distinguish between small block random access, normal cache access, and long request access. The request length level is only used for load similarity condition judgment and is not directly used as cache scheduling permission. The representative value of the request length is the median value of the request length of each access record within the segment.

[0040] The queue depth level is formed based on the commit queue depth range of the same SSD. When the queue depth representative value within a fragment does not exceed 1 / 3 of the upper limit of the commit queue depth, it is written to the low queue level; when it is greater than 1 / 3 of the upper limit of the commit queue depth but not more than 2 / 3 of the upper limit of the commit queue depth, it is written to the medium queue level; and when it is greater than 2 / 3 of the upper limit of the commit queue depth, it is written to the high queue level. 1 / 3 and 2 / 3 are the preferred boundaries of the queue depth level, used to divide the commit queue load into three matching levels: low, medium, and high. This level is only used for reference access fragment matching. The queue depth representative value is the median value of the queue depth of each access record within the fragment. When the upper limit of the SSD commit queue depth cannot be obtained, the system does not form a queue depth level and writes the corresponding historical access fragment to the load dissimilarity state.

[0041] The read request percentage level is formed based on all closed access records of the same candidate object within the start and end time period of the target access segment and all closed access records of the same candidate object within the start and end time period of the historical access segment. When the read request percentage is no more than 1 / 3, it is written as a low read percentage level; when it is greater than 1 / 3 but no more than 2 / 3, it is written as a medium read percentage level; and when it is greater than 2 / 3, it is written as a high read percentage level. 1 / 3 and 2 / 3 are the preferred boundaries for the read request percentage level, which are used to divide the segment read and write composition into three matching levels: low, medium, and high. This level is only used to determine whether the historical access segment and the target access segment have similar load conditions. The request length level, queue depth level, and read request percentage level are all formed under the same SSD and the same cache management granularity. They are only used to determine whether the historical access segment and the target access segment have similar load conditions and are not directly used as cache scheduling permissions.

[0042] If the historical access segment and the target access segment have the same request length level, the same read request ratio level, and a queue depth level that differs by no more than one level, and the historical access segment contains no fewer than four completed access records, the system determines that they meet the load similarity condition. The low queue level, medium queue level, and high queue level are arranged in ascending order of queue load. A queue depth level that differs by no more than one level means that the low queue level and the medium queue level, and the medium queue level and the high queue level are adjacent. The low queue level and the high queue level are not adjacent. No fewer than four completed access records is the preferred lower limit for the reference access segment, which is used to enable the reference access segment to form completion delay information and logical address span information. If this preferred lower limit is not met, the system writes the corresponding historical access segment into the reference segment insufficiency state, and the historical access segment that does not meet the load similarity condition is written into the load dissimilarity state and is not used as a reference access segment.

[0043] Among historical access segments that meet the load similarity condition, the system selects the historical access segment with a stable logical address span and an end time closest to the start time of the candidate time window as the reference access segment. A stable logical address span means that the number of logical mapping units and the number of discrete continuous segments of the historical access segment are not higher than the corresponding numbers in its stable historical access state. The corresponding numbers are the representative values ​​of the number of logical mapping units and the number of discrete continuous segments of the same candidate object in the stable historical access state. The representative values ​​of the number of logical mapping units and the number of discrete continuous segments are formed by using the median value of the corresponding record in the stable historical access state. When multiple historical access segments meet the load similarity condition and the logical address span stability condition, the system prioritizes the historical access segment that is completely consistent with the request length level, queue depth level, and read request ratio level of the target access segment. If there are still multiple candidates, the historical access segment with an end time closest to the start time of the candidate time window is selected as the reference access segment. When a historical access segment meets the load similarity condition but has an unstable logical address span, the system writes the access segment comparison record into the unstable reference span state and does not use the historical access segment as the reference access segment.

[0044] After the target access segment and reference access segment are determined, the system writes them into the access segment comparison record. The access segment comparison record includes the candidate object identifier, candidate time window, target segment identifier, reference segment identifier, start and end times of the target access segment, start and end times of the reference access segment, target segment completion delay information, reference segment completion delay information, target segment logical address span information, reference segment logical address span information, and load similarity condition results. The access segment comparison status is "comparison successful," which must simultaneously meet the following conditions: the target access segment has been formed, the reference access segment has been formed, and the target access segment... If the reference access segment meets the load similarity condition and the logical address span stability condition, and no target segment shortage state, historical benchmark shortage state, initial latency increased state, reference segment shortage state, load dissimilarity state, reference span unstable state, span pending confirmation state, or segment source restricted state is generated, the access segment comparison record is only used as input for subsequent residual attribution processing when the segment comparison state is a comparison established state. The cache candidate records corresponding to other segment comparison states can still participate in candidate sorting, but they do not enter the residual attribution processing, do not enter the cache migration permission generation path, and do not update the read-only benchmark record in S1.

[0045] After this processing, the system converts the cached candidate records formed by S1 into access segment comparison records. The target access segment is limited to the completed access segments within the same candidate object and the same candidate time window where random read latency increases and logical address span expands. The reference access segment is limited to the access segments with similar loads and stable logical address spans in the historical stable accesses of the same candidate object. The access segment comparison records provide a data foundation for the subsequent generation of latency residuals by S3, which is consistent in terms of object consistency, time closure, load comparability, and logical address span caliber.

[0046] S3 uses residual attribution processing to access fragment comparison records to generate delay residuals. Then, it uses mapping perturbation evaluation to process the delay residuals and host memory buffer pressure records to generate address mapping perturbation residuals. Finally, it generates perturbed window markers according to the address mapping perturbation residuals.

[0047] This step follows the execution of the access segment comparison record formed in S2. The access segment comparison record contains candidate object identifiers, candidate time windows, target access segments, reference access segments, target segment completion delay information, reference segment completion delay information, target segment logical address span information, reference segment logical address span information, load similarity condition results, and segment comparison status. In this step, the system does not reselect the target access segment, does not reselect the reference access segment, and does not change the statistical caliber of logical address span in S1. Instead, it uses the target access segment and reference access segment that have already been established in the access segment comparison record to perform residual attribution processing. When the segment comparison status is a comparison established status, the system performs delay residual generation processing; when the segment comparison status is not a comparison established status, the system writes the residual unavailable status into the access segment comparison record and synchronously writes this status into the verification record of the current cache scheduling cycle.

[0048] This step uses observable fields from SSD running status records and host memory buffer pressure records for processing. The request completion delay comes from the time difference between the device's completion return time and the time the request is submitted to the device queue. The logical address span is represented by the number of logical mapping units and the number of discrete continuous segments. The host memory buffer pressure records are derived from the capacity status of the memory domain where the host memory buffer is located, page reclamation activity, and host memory buffer allocation status.

[0049] The system first reads the candidate object identifier, candidate time window, target access segment, and reference access segment from the access segment comparison record, and verifies the object attribution and time sequence of the target access segment and the reference access segment. If the target access segment and the reference access segment belong to the same candidate object identifier, the start and end times of the target access segment are both within the candidate time window, and the end time of the reference access segment is earlier than the start time of the candidate time window, the system continues to perform delayed residual generation processing. If any of the following occurs: the target access segment and the reference access segment do not belong to the same candidate object identifier, the start and end times of the target access segment are not both within the candidate time window, or the end time of the reference access segment is not earlier than the start time of the candidate time window, the system writes the access segment comparison record to the object time inconsistency state and does not perform delayed residual generation processing. After this verification, the residual attribution is limited to the same candidate object and the correct time sequence.

[0050] After the object and time verification are passed, the system reads the target delay representative value from the target segment completion delay information and the reference delay representative value from the reference segment completion delay information. The target delay representative value adopts the target access segment later request completion delay representative value in S2, and the reference delay representative value adopts the median request completion delay value of the read access records in the reference access segment. Both the target delay representative value and the reference delay representative value are formed by the time difference between the device completion return time of the read access record and the time when the request is submitted to the device queue, and the unit is milliseconds. When there are fewer than 2 read access records in the reference access segment, the system writes the access segment comparison record to the delay residual unavailable state and does not perform delay residual generation processing. No less than 2 records are the minimum sample closure requirement for forming the reference delay representative value. When there are no less than 2 read access records in the reference access segment, the system uses all read access records in the reference access segment formed in S2 to calculate the median request completion delay value.

[0051] The system simultaneously reads the minimum discriminable latency increment formed by S2. The minimum discriminable latency increment comes from the minimum timing unit of the timestamp in the SSD running status record and the normal completion latency change boundary in the stable historical access status, with the unit being milliseconds. When any of the data in the target latency representative value, the reference latency representative value, and the minimum discriminable latency increment cannot be obtained, the system writes the access segment comparison record to the latency residual unavailable state and synchronously writes this state to the verification record of the current cache scheduling cycle, without performing latency residual generation processing.

[0052] When the system generates the delay residual, it first forms the increase of the target delay representative value relative to the reference delay representative value, and then subtracts the minimum discriminable delay increment from this increase. If the result after subtraction is greater than 0, the system uses the result after subtraction as the delay residual; if the result after subtraction is not greater than 0, the system records the delay residual as 0 and writes the access segment comparison record into the delay residual insufficient state. The unit of delay residual is milliseconds, and the value is not less than 0. After this processing, the difference between the target access segment and the reference access segment that does not exceed the timing accuracy and normal delay fluctuation boundary will not be included in the mapping disturbance evaluation.

[0053] After the delay residual is generated, the system reads the number of logical mapping units and the number of discrete continuous segments from the logical address span information of the target segment and the logical address span information of the reference segment. The system compares the number of logical mapping units in the latter part of the target access segment with the number of logical mapping units in the reference access segment, and compares the number of discrete continuous segments in the latter part of the target access segment with the number of discrete continuous segments in the reference access segment. When the number of logical mapping units in the latter part of the target access segment is higher than the number of logical mapping units in the reference access segment, and the number of discrete continuous segments in the latter part of the target access segment is higher than the number of discrete continuous segments in the reference access segment, the system confirms that the logical address span is inherited. If the conditions are not met simultaneously, the system confirms that the logical address span is inherited, and writes the access segment comparison record into the state of "span inheritance is not inherited". The logical address span inheritance is inherited, which means that the target access segment has an expanded address coverage and increased address dispersion relative to the reference access segment. When the logical address span inheritance is not inherited, the delay residual is not included in the address mapping access disturbance.

[0054] The system further reads the host memory buffer pressure record corresponding to the target access segment, as well as the historical host memory buffer pressure record within the historical I / O observation window of the reference access segment. For ease of description, the host memory buffer pressure record corresponding to the target access segment is recorded as the current pressure record, and the historical host memory buffer pressure record within the historical I / O observation window of the reference access segment is recorded as the historical pressure record. The current pressure record originates from the host memory buffer pressure record bound to the candidate time window in S1, and the historical pressure record originates from the host memory buffer pressure record already formed within the historical I / O observation window of the reference access segment. The pressure sampling record includes the sampling time, the available capacity record of the memory domain where the host memory buffer is located, the page reclamation activity record, and the host memory buffer allocation status record. The target access segment and the reference access segment respectively call the pressure record within their respective time windows, without using the pressure record within the candidate time window to replace the pressure record in the historical I / O observation window of the reference access segment.

[0055] Before performing the pressure handling judgment, the system generates a pressure judgment calibration record for the current cache scheduling cycle. The pressure judgment calibration record includes the sampling period of the current pressure record, the sampling period of the historical pressure record, the precision of the available capacity field of the current pressure record, the precision of the available capacity field of the historical pressure record, the system memory page size, the granularity of the host memory buffer allocation configuration in the current pressure record, the granularity of the host memory buffer allocation configuration in the historical pressure record, the lower limit of the effective change of the capacity record, and the lower limit of the effective change of the allocation size record. The sampling period of the current pressure record is formed by the sampling time interval of adjacent pressure sampling records in the current pressure record; the sampling period of the historical pressure record is formed by the sampling time interval of adjacent historical pressure sampling records in the historical pressure record; the precision of the available capacity field is formed by the smallest capacity unit that the corresponding pressure record can stably record; the system memory page size is formed by the host operating system memory management parameters; and the granularity of the host memory buffer allocation configuration is formed by at least one of the host memory buffer enable record, driver configuration record, and host memory buffer allocation status record.

[0056] The effective lower limit of capacity record change is formed by the maximum value that can be obtained from the available capacity field precision of the current pressure record, the available capacity field precision of the historical pressure record, and the system memory page size, and is limited within the range of 4KB to 1MB. When the effective lower limit of capacity record change is lower than 4KB, the value is taken as 4KB; when the effective lower limit of capacity record change is higher than 1MB, the system writes the access segment comparison record to the pressure acceptance undeterminable state and stops executing the pressure acceptance judgment. When the available capacity field precision of the current pressure record, the available capacity field precision of the historical pressure record, and the system memory page size cannot be obtained, the system writes the access segment comparison record to the pressure acceptance undeterminable state and stops executing the pressure acceptance judgment. The effective lower limit of capacity record change is a necessary calibration item for pressure enhancement judgment.

[0057] The effective lower limit of allocation size record changes is formed by the maximum value that can be obtained from the host memory buffer allocation configuration granularity in the current stress record, the host memory buffer allocation configuration granularity in the historical stress record, and the system memory page size. It is limited within the range of 4KB to 2MB. When the effective lower limit of allocation size record changes is lower than 4KB, it is taken as 4KB. When the effective lower limit of allocation size record changes is higher than 2MB, the system does not form an allocation size decline state. When the host memory buffer allocation configuration granularity in the current stress record, the host memory buffer allocation configuration granularity in the historical stress record, and the system memory page size cannot be obtained, the system does not form an allocation size decline state. The effective lower limit of allocation size record changes is only used to determine the allocation size decline state and does not block the determination of page reclamation enhancement state and reallocation failure state.

[0058] The system extracts valid pressure sampling records whose sampling time falls within the start and end time period of the target access segment, and extracts valid historical pressure sampling records whose sampling time falls within the start and end time period of the reference access segment. Valid pressure sampling records refer to pressure sampling records with complete sampling time, complete pressure fields, and not in a pressure pending verification state. When there are no less than 2 valid pressure sampling records within the start and end time period of the target access segment, and no less than 2 valid historical pressure sampling records within the start and end time period of the reference access segment, the system performs pressure acceptance judgment. When there are fewer than 2 valid pressure sampling records in any time period, the system writes the access segment comparison record to the pressure acceptance undeterminable state and stops performing pressure acceptance judgment. The system uses the number of valid pressure sampling records falling within the judgment time period as the admission basis for pressure direction judgment, and does not use pressure sampling records outside the adjacent window to supplement. No less than 2 is the minimum sampling closure requirement for pressure direction judgment, which is used to form the starting sampling value and the ending sampling value in the same time period.

[0059] The pressure acceptance judgment adopts a combination rule of pressure enhancement in the target period and no pressure enhancement in the reference period. In the corresponding period after the target access segment, the system sorts the effective pressure sampling records according to the sampling time and obtains the initial sampling value and the final sampling value respectively. When the available capacity at the end is lower than the initial available capacity and the difference is not less than the lower limit of the effective change of the capacity record, the system writes the available capacity decrease state. When the lower limit of the effective change of the capacity record cannot be obtained from the pressure judgment calibration record, the system does not form the available capacity decrease state, writes the access segment comparison record into the pressure acceptance undeterminable state, and stops executing the pressure acceptance judgment.

[0060] When the page reclamation activity count increases by at least one time relative to the initial sampling record, the system writes a page reclamation enhanced state. The page reclamation activity count comes from at least one of the operating system memory management records and the page reclamation event count collected by the storage service. If any of the following occurs: missing page reclamation activity count field, count wrap-around, or count reset, the system does not form a page reclamation enhanced state, but stress enhancement can still be judged based on the host memory buffer allocation size decrease state and the host memory buffer reallocation failure state.

[0061] When the host memory buffer allocation size decreases relative to the initial sampling record, and the difference is not less than the lower limit of the effective change of the allocation size record, the system writes an allocation size decrease state. When the lower limit of the effective change of the allocation size record cannot be obtained from the pressure judgment calibration record, the system does not form an allocation size decrease state. When a host memory buffer reallocation failure event occurs at least once in the corresponding time period after the target access segment, the system writes a reallocation failure state. The reallocation failure event originates from at least one of the allocation failure events recorded in the host memory buffer allocation status record or the driver-side record. When any of the following situations occur, the system does not form a reallocation failure state: the recording time of the reallocation failure event is not within the corresponding time period after the target access segment, or the event record is missing.

[0062] When the available capacity decreases and at least one of the following states is established: page reclamation enhancement, allocation size decrease, or reallocation failure, the system writes the corresponding time period after the target access segment into the pressure enhancement state. This combination rule ensures that changes in the available host memory capacity do not independently form a host memory buffer pressure enhancement judgment. The corresponding time period of the reference access segment is judged according to the same pressure judgment calibration record and the same sampling caliber. If no pressure enhancement is formed in the corresponding time period of the reference access segment, and the valid historical pressure sampling record of the corresponding time period of the reference access segment is not in the pressure pending verification state, the system confirms that no pressure enhancement is formed in the corresponding time period of the reference access segment.

[0063] If there is increased pressure in the corresponding time period after the target access segment, and no increased pressure occurs in the corresponding time period of the reference access segment, the system confirms that the host memory buffer pressure is accepted. If this condition is not met simultaneously, the system confirms that the host memory buffer pressure is not accepted and writes the access segment comparison record to the pressure acceptance failure state. The host memory buffer pressure acceptance success means that the latency residual of the target access segment is in time in line with the host memory buffer pressure increase state. The host memory buffer pressure acceptance failure means that the latency residual is not included in the address mapping access disturbance driven by the host memory buffer pressure.

[0064] When the latency residual is greater than 0, the logical address span is accepted, and the host memory buffer pressure is accepted, the system writes the latency residual as the address mapping perturbation residual into the verification record of the current cache scheduling cycle. The address mapping perturbation residual and the latency residual have the same dimension, with the unit being milliseconds. When any of the following occurs: no latency residual is generated, the latency residual is equal to 0, the logical address span is not accepted, the host memory buffer pressure is not accepted, or the pressure acceptance is undeterminable, the system records the address mapping perturbation residual as 0 and writes the corresponding state into the access segment comparison record. The address mapping perturbation residual is the result of the latency residual being jointly limited by the logical address span and the host memory buffer pressure.

[0065] The system generates a disturbed window marker based on the address mapping disturbance residual. When the address mapping disturbance residual is greater than 0, and the access segment comparison record is not written to the object time in an inconsistent state, the delay residual is unavailable, the delay residual is insufficient, the span acceptance is not valid, the pressure acceptance is undeterminable, or the pressure acceptance is not valid, the system generates a disturbed window marker. The disturbed window marker includes the candidate object identifier, candidate time window, the start and end time of the target access segment, the start and end time of the reference access segment, the delay residual, the address mapping disturbance residual, the logical address span acceptance result, the host memory buffer pressure acceptance result, and the marker generation time. The marker generation time is the time when the mapping disturbance evaluation is completed within the current cache scheduling cycle. It is not used to change the candidate time window and the boundary of the target access segment. The disturbed window marker is written to the verification record of the current cache scheduling cycle. It does not cover the cache candidate record formed by S1, nor does it rewrite the access segment comparison record formed by S2.

[0066] When the address mapping disturbance residual is equal to 0, or when any of the following states occur: inconsistent access fragment comparison record writing time, unavailable delay residual, insufficient delay residual, span failure, undeterminable pressure, or undetermined pressure, the system will not generate a disturbed window marker. The corresponding candidate object can still participate in candidate sorting, but it will not enter the cache migration permission generation path, will not be written back to a stable historical access state, and will not update the cache candidate record formed by S1.

[0067] This step generates latency residuals, address mapping perturbation residuals, and perturbed window markers. The latency residual represents the remaining latency of the target access segment relative to the reference access segment after deducting normal latency fluctuations. The address mapping perturbation residual represents the latency residual after being jointly limited by logical address span and host memory buffer pressure. The perturbed window marker is used to provide S4 with a basis for cache scheduling gating.

[0068] S4 uses a scheduling permission state machine to process cache candidate records and verification records of the current cache scheduling cycle, generates cache scheduling permissions, and performs cache scheduling actions on candidate objects according to the cache scheduling permissions.

[0069] This step follows the execution of the cache candidate record formed in S1, the disturbed window marker formed in S3, and the verification record of the current cache scheduling cycle. The cache candidate record contains the candidate object identifier, candidate time window, predicted heat, predicted confidence, and logical address span. The disturbed window marker has been written into the verification record of the current cache scheduling cycle by S3 and corresponds to the candidate object identifier and candidate time window. In this step, the system does not recalculate the latency residual, re-determine the logical address span acceptance result, or re-determine the host memory buffer pressure acceptance result. Instead, it uses the disturbed window marker and verification status formed in S3 as the basis for cache scheduling gating. The load prediction result of S1 is used to characterize the access tendency of the candidate object within the candidate time window. S3 is used to identify whether there is address mapping access disturbance in this access tendency. S4 is used to control whether the predicted heat can enter the cache scheduling action based on the disturbance identification result.

[0070] In one implementation, at the beginning of each cache scheduling cycle, the system reads the cache candidate records to be processed within that cache scheduling cycle, the verification record of the current cache scheduling cycle, the cache status record, and the cache policy record. The cache status record includes cache residency status, cache dirty data status, the scheduling permission status of the previous cache scheduling cycle, continuous recovery count, and continuous recovery duration. The cache residency status is used to distinguish whether the candidate object is currently in the cache space; the cache dirty data status is used to distinguish whether the candidate object has data that has not yet been written to non-volatile storage media; the scheduling permission status of the previous cache scheduling cycle is used to determine whether the candidate object is in the recovery process after disturbance isolation; the continuous recovery count and continuous recovery duration are used to determine whether the candidate object meets the recovery confirmation conditions; and the cache policy record is used to provide migration heat boundaries, degradation heat boundaries, trustworthiness admission boundaries, and recovery confirmation conditions.

[0071] The system matches the verification record of the current cache scheduling cycle with the cache candidate record according to the candidate object identifier and the candidate time window. When the candidate object identifier in the verification record is consistent with the candidate object identifier in the cache candidate record, and the candidate time window in the verification record is consistent with the candidate time window in the cache candidate record, the system uses the verification record as the matching verification record of the current cache candidate record. When the verification record belongs to any of the following situations: other candidate object, other candidate time window, or other cache scheduling cycle, the system does not use the verification record for the scheduling permission judgment of the current cache candidate record. When no matching verification record is obtained, the scheduling permission state machine enters the pending verification state and generates one of the following according to the cache residency state: cache retain permission or no migration permission.

[0072] The system categorizes the following states into scheduling blocking states: inconsistent object time, unavailable latency residual, insufficient latency residual, invalid span, undeterminable pressure, and invalid pressure. These states are formed by merging the corresponding states from the S3 verification records without adding new data collection fields. The inconsistent object time state indicates that the object ownership and temporal order between the target access segment, reference access segment, and cache candidate record do not meet the requirements. The unavailable latency residual and insufficient latency residual states indicate that the latency residual has not met the scheduling admission requirements. The invalid span state indicates that the logical address span has not been effectively expanded. The undeterminable pressure and invalid pressure states indicate that the host memory buffer pressure record does not support address mapping disturbance attribution. The system uses scheduling blocking states to uniformly represent verification states that do not meet reliable scheduling admission requirements, maintaining consistency in state transmission between S3 and S4.

[0073] The system reads the cache policy record and obtains the migration-in popularity boundary, degradation popularity boundary, confidence admission boundary, and recovery confirmation condition. The predicted popularity and predicted confidence are based on the values ​​written to the cache candidate record in S1, with values ​​ranging from 0 to 1. The migration-in popularity boundary, degradation popularity boundary, and confidence admission boundary are dimensionless boundary values. Cache capacity occupancy and write-back queue occupancy are recorded as percentages. The migration-in popularity boundary is used to determine whether a candidate object has the conditions to enter the cache space and increase its cache residency priority; the degradation popularity boundary is used to determine whether a candidate object has the conditions to decrease its cache residency priority. Conditions for resident priority; the credibility admission boundary is used to determine whether the predicted popularity allows participation in cache migration, cache degradation, and hot / cold tag updates. The migration popularity boundary, degradation popularity boundary, and credibility admission boundary are initially provided by the cache policy record and are calibrated by the historical access status that has been allowed to stably write back the past. The calibrated migration popularity boundary is limited to 0.60 to 0.90, the calibrated degradation popularity boundary is limited to 0.10 to 0.40, and the calibrated credibility admission boundary is limited to 0.55 to 0.80. The migration popularity boundary is higher than the degradation popularity boundary.

[0074] The calibration of migration heat boundaries, degradation heat boundaries, and credibility admission boundaries uses stable historical access states, cache capacity usage, write-back queue usage, and recent prediction deviation records that match the candidate objects. Stable historical access states that match the candidate objects refer to historical access states where the candidate object identifier is consistent, no disturbed window markers have been generated, no scheduling blocking states have been written, and stable historical write-back has been allowed. Cache capacity usage is determined by the ratio between the currently occupied cache capacity and the total cache capacity. Write-back queue usage is determined by the ratio between the amount of data to be written back in the current write-back queue and the write-back queue capacity. Recent prediction deviation records are recorded by the cache policy based on... The cache scheduling cycle that has recently been verified, has not generated a disturbed window flag, has not been written to the scheduling blocking state, and has allowed stable history writeback is formed. The recent prediction deviation record records the deviation between the predicted heat and the actual access heat. The actual access heat is formed by the number of read accesses and the number of read accesses in the corresponding closed access record, according to the same 0 to 1 normalization calibrator as the predicted heat in S1. When the actual access heat cannot be formed, the recent prediction deviation record is recorded as not being formed. S4 only reads the recently formed recent prediction deviation record and does not use the disturbed window flag, cache scheduling permission, and execution result formed in the current cache scheduling cycle to calibrate the boundary of the current cache scheduling cycle.

[0075] When the caching policy record has not been calibrated, the system uses the default threshold boundaries. When cache capacity utilization is below 50% and write-back queue utilization is below 30%, the migration-in popularity threshold is 0.60 to 0.70; when cache capacity utilization is not below 50% and not above 85%, the migration-in popularity threshold is 0.70 to 0.80; when cache capacity utilization is above 85%, the migration-in popularity threshold is 0.80 to 0.90; and when write-back queue utilization is above 70%, the degradation popularity threshold is 0.10 to... 0.20; When the write-back queue occupancy is not less than 30% and not more than 70%, the degradation hotness boundary is 0.20 to 0.30; When the write-back queue occupancy is less than 30% and the cache capacity occupancy is more than 85%, the degradation hotness boundary is 0.30 to 0.40. For cache capacity occupancy and write-back queue occupancy not covered by the default tier boundary, the higher boundary value among adjacent tiers is taken when forming the migration hotness boundary, and the lower boundary value among adjacent tiers is taken when forming the degradation hotness boundary.

[0076] When the number of stable historical access states matching a candidate object is less than 3 candidate time windows, the confidence admission boundary is no less than 0.70; when the number of stable historical access states matching a candidate object is 3 to 9 candidate time windows, the confidence admission boundary is 0.65 to 0.75; when the number of stable historical access states matching a candidate object is no less than 10 candidate time windows, and the recent prediction deviation records meet the continuous deviation judgment condition, the confidence admission boundary is 0.55 to 0.65. The continuous deviation judgment condition is configured by the cache policy record, and the configuration range is 2 to 5 consecutive verified cache scheduling cycles; if the cache policy record is not configured with continuous deviation judgment conditions... When determining the continuous deviation criteria, the system takes two consecutive verified cache scheduling cycles as the default condition. If the recent predicted deviation record does not record any deviation event that crosses either the migration popularity boundary or the degradation popularity boundary within the cache scheduling cycle corresponding to the continuous deviation criteria, the system confirms that the recent predicted deviation record meets the continuous deviation criteria. If any of the following occurs: the recent predicted deviation record cannot be formed, the number of verified cache scheduling cycles is insufficient, or the number of stable historical access states matching the candidate object is insufficient, the system will not use the credibility admission boundary range of 0.55 to 0.65, and will set the credibility admission boundary to a value of not less than 0.70.

[0077] When any of the following situations occur: cache policy record cannot be obtained, cache capacity usage cannot be generated, write-back queue usage cannot be generated, recent prediction deviation record cannot be generated and the number of stable historical access states is insufficient, migration heat boundary is not higher than degradation heat boundary, or any boundary exceeds the corresponding limit range, the system adopts a conservative scheduling boundary. Among them, the migration heat boundary is 0.80, the degradation heat boundary is 0.20, and the credibility admission boundary is 0.70. When the conservative scheduling boundary is adopted, the system still performs the gating judgment of the disturbed window marking and scheduling blocking state, and does not bypass the disturbance isolation state, the pending verification state, and the recovery confirmation state due to boundary backtracking.

[0078] The recovery confirmation condition is derived from the cache scheduling cycle length and the candidate time window length, and is represented by a continuous recovery count and a continuous recovery duration. The continuous recovery count must be no less than 2 consecutive cache scheduling cycles, and the continuous recovery duration must be no less than the candidate time window length. When the cache scheduling cycle is shorter than the candidate time window, the system determines the minimum continuous recovery count based on the number of cache scheduling cycles required to cover one candidate time window. When the cache scheduling cycle is no less than the candidate time window, the system still requires a continuous recovery count of no less than 2 cache scheduling cycles. When the candidate time window is 2s and the cache scheduling cycle is 500ms, recovery confirmation requires at least 4 consecutive cache scheduling cycles and a continuous recovery duration of 2s. When the candidate time window is 1s and the cache scheduling cycle is 2s, recovery confirmation requires at least 2 consecutive cache scheduling cycles. If any of the data in the cache scheduling cycle length, candidate time window length, and continuous recovery duration cannot be obtained, the scheduling permission state machine enters the pending verification state and generates either a cache retention permission or a non-migration permission according to the cache residency state.

[0079] The scheduling permission state machine includes candidate verification state, disturbance isolation state, pending verification hold state, recovery confirmation state, and baseline scheduling state. Each cached candidate record first enters the candidate verification state upon entering S4. In this state, the system reads the candidate object identifier, candidate time window, matching verification record, prediction confidence, cache residency state, cache dirty data state, scheduling permission state of the previous cache scheduling cycle, continuous recovery count, and continuous recovery duration. The system then determines the scheduling permission state a candidate object should enter based on the following priority: if no matching verification record is obtained, it enters the pending verification hold state; if a matching verification record is obtained and there is a disturbed window marker with an address mapping disturbance residual greater than 0, it enters the backup state. The system enters the disturbance isolation state; when a matching verification record is obtained, there is no disturbance window marker but a scheduling blockage state exists, it enters the pending verification hold state; when a matching verification record is obtained, there is no disturbance window marker and scheduling blockage state, and the scheduling permission state of the previous cache scheduling cycle belongs to either the disturbance isolation state or the recovery confirmation state, it enters the recovery confirmation state; when a matching verification record is obtained, there is no disturbance window marker and scheduling blockage state, the scheduling permission state of the previous cache scheduling cycle does not belong to either the disturbance isolation state or the recovery confirmation state, and the prediction confidence is not lower than the confidence admission boundary, it enters the baseline scheduling state; when the prediction confidence is lower than the confidence admission boundary, it enters the pending verification hold state.

[0080] After the scheduling permission state machine enters the disturbance isolation state, it generates cache retention permits for candidate objects already in the cache-resident state and non-mig-in permits for candidate objects not in the cache-resident state. It prohibits cold / hot label updates and stable history write-back, and resets the continuous recovery count and continuous recovery duration to zero. After the scheduling permission state machine enters the pending verification retention state, it generates cache retention permits for candidate objects already in the cache-resident state and non-mig-in permits for candidate objects not in the cache-resident state. It does not generate cache migration-in permits, cache degradation permits, cold / hot label update permits, or stable history write-back permits. After the scheduling permission state machine enters the recovery confirmation state, the system updates the continuous recovery count based on the current cache scheduling cycle length. The continuous recovery count and continuous recovery duration are both considered. If the continuous recovery count and continuous recovery duration do not simultaneously meet the recovery confirmation conditions, one of the following is generated according to the cache residency state: a cache retention permit or a non-migration permit. If both the continuous recovery count and continuous recovery duration meet the recovery confirmation conditions, and the prediction confidence is not lower than the confidence admission boundary, the scheduling authority state machine enters the baseline scheduling state. If both the continuous recovery count and continuous recovery duration meet the recovery confirmation conditions, but the prediction confidence is lower than the confidence admission boundary, the scheduling authority state machine enters the pending verification retention state. If a disturbed window marker matching a cache candidate record reappears in the recovery confirmation state, the scheduling authority state machine enters the disturbance isolation state and clears the continuous recovery count and continuous recovery duration to zero.

[0081] After the scheduling permission state machine enters the baseline scheduling state, the system generates cache scheduling permissions based on predicted heat, cache residency status, cache dirty data status, migration-in heat boundary, and degradation heat boundary. When the predicted heat is not lower than the migration-in heat boundary, for candidate objects not in the cache residency state, the system generates a cache migration-in permission and writes the candidate object into the cache migration-in queue; for candidate objects already in the cache residency state, the system generates a cache retention permission and increases the residency priority of the candidate object in the cache management queue; when a candidate object is already at the highest residency priority, the system maintains its residency priority unchanged, and when the predicted heat is not higher than the degradation heat... At the boundary, for candidate objects not in a cache-resident state, the system generates a no-migration permit; for cache-resident candidate objects whose cache dirty data state is no dirty data state, the system generates a cache downgrade permit and writes the candidate object into the cache downgrade queue; for cache-resident candidate objects whose cache dirty data state is dirty data state, the system generates a write-back admission permit, and generates a cache downgrade permit after the write-back is completed. When the predicted popularity is higher than the downgrade popularity boundary but lower than the migration popularity boundary, for candidate objects already in a cache-resident state, the system generates a cache-maintain permit; for candidate objects not in a cache-resident state, the system generates a no-migration permit.

[0082] The system generates cold and hot label update permissions and stable history write-back permissions only under the baseline scheduling state and when the matching verification record does not have a disturbed window mark or a scheduling blocking state. The cold and hot label update permissions are executed based on the relationship between the predicted heat and the migration heat boundary and the downgrade heat boundary: when the predicted heat is not lower than the migration heat boundary, the candidate object is updated to a hot object label; when the predicted heat is not higher than the downgrade heat boundary, the candidate object is updated to a cold object label; when the predicted heat is higher than the downgrade heat boundary but lower than the migration heat boundary, the original cold and hot labels remain unchanged. The stable history write-back permission writes the candidate object identifier, candidate time window, predicted heat, predicted confidence, cache scheduling permission, and verification status to the stable history access state. The delay residual, address mapping disturbance residual, and pressure enhancement status corresponding to the disturbed window mark are not written to the stable history access state. Stable history write-back is prohibited for the disturbance isolation state, the pending verification state, and the recovery confirmation state that does not meet the recovery confirmation conditions.

[0083] Write-back admission permission only controls write-backs triggered by cache degradation actions in this method. It does not block independent write-backs performed by the storage system for data consistency, power-loss protection, and capacity reclamation. For cache resident candidate objects whose cache dirty data state is "dirty data state", the system writes the candidate object into the write-back queue triggered by the cache degradation action after generating a write-back admission permission. After the write-back is completed, the system generates a cache degradation permission. If the candidate object completes an independent write-back due to the storage system's own consistency policy, but a cache degradation permission is not generated in this step, the candidate object still maintains its current scheduling permission state, and the independent write-back result does not trigger a stable historical write-back on its own.

[0084] Cache scheduling permissions include candidate object identifiers, candidate time windows, scheduling permission status, and corresponding permission fields. Permission fields include cache migration permission, cache retention permission, no migration permission, cache degradation permission, write-back admission permission, hot / cold tag update permission, and stable history write-back permission. When the cache migration permission is in the permitted state, the system writes the candidate object to the cache migration queue and writes the candidate object identifier and candidate time window to the queue record. When the cache retention permission is in the permitted state, the system maintains the current cache residency status of the candidate object. When the no migration permission is in the permitted state, the system does not write the candidate object to the cache migration queue. When the cache downgrade permission is in the permitted state, the system writes the candidate object into the cache downgrade queue; when the write-back admission permission is in the permitted state, the system writes the candidate object into the write-back queue triggered by the cache downgrade action, and allows the cache downgrade action to be executed after the write-back is completed; when the cold and hot label update permission is in the permitted state, the system updates the cold and hot labels of the candidate object according to the cache scheduling permission; when the stable history write-back permission is in the permitted state, the system writes the corresponding candidate record into the stable history access state. After the cache scheduling action is executed, the system writes the scheduling permission status, permission validity period and execution result into the cache status record for use in the next cache scheduling cycle.

[0085] After processing in this step, S4 connects the load prediction result formed in S1, the disturbed window tag formed in S3, and the cache state record into an executable cache scheduling permission. In load prediction cache scheduling without disturbance isolation, cache migration, cache degradation, and hot / cold label update will be triggered after the predicted heat reaches the heat boundary. In this implementation, a scheduling permission state machine is added before the predicted heat enters the scheduling action to isolate the disturbed window with address mapping disturbance residual greater than 0 from cache migration, cache degradation, hot / cold label update, and stable history write-back. This processing ensures that the address mapping access disturbance caused by the combined pressure of host memory buffer and the expansion of logical address span is not written into the data access heat change chain, thereby reducing the error cache migration and error hot / cold state update of SSDs that use host memory buffer to carry address mapping access in the scenario of host memory buffer pressure fluctuation.

[0086] In one embodiment, the present invention also provides an SSD cache scheduling device based on load prediction. The device includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. The device can be set in a host-side storage service that uses SSDs, or it can be set in an edge computing device, a local inference terminal, a lightweight server, a virtualization node, or a control node with SSD cache scheduling capabilities. The device does not require an independent DRAM cache to be set up inside the SSD and is suitable for SSD operation scenarios that use host memory buffers to participate in address mapping access.

[0087] The processor can be a general-purpose central processing unit, an embedded processor, a system-on-a-chip processor, or a memory control processing unit with instruction execution capability. The memory is used to store computer programs, cache policy records, cache state records, cache candidate records, access segment comparison records, verification records of the current cache scheduling cycle, stable historical access states, and cache scheduling execution results. The memory can include volatile memory and non-volatile memory. Volatile memory is used to store the running records and intermediate states within the current cache scheduling cycle, while non-volatile memory is used to store cache policy records, historical access states, execution logs, and program files.

[0088] When a computer program runs on a processor, it calls the data acquisition thread, candidate record generation thread, access fragment comparison thread, residual attribution thread, mapping perturbation evaluation thread, and scheduling authority state machine thread according to the cache scheduling cycle. The threads pass processing results to each other through structured records, without directly overwriting the baseline record of the previous processing stage. The cache candidate record is saved as a read-only baseline record for the current scheduling cycle. The access fragment comparison record is used to save the target access fragment and the reference access fragment. The verification record is used to save the delay residual, address mapping perturbation residual, perturbed window mark, and scheduling blocking status. The cache status record is used to save the cache resident status, cache dirty data status, scheduling authority status of the previous cache scheduling cycle, continuous recovery count, and continuous recovery duration.

[0089] When the processor executes a computer program, it first calls the SSD runtime status acquisition program segment. This program segment reads the SSD's host memory buffer enable record, closed access record, access type, logical block range, the time the request was submitted to the device queue, the device completion return time, and the completion status through the operating system storage stack, NVMe driver runtime record, I / O completion queue record, or storage service log. At the same time, the processor calls the host memory status acquisition program segment to obtain the available capacity of the memory domain where the host memory buffer is located, page reclamation activity count, host memory buffer allocation size, and host memory buffer reallocation failure record through the operating system memory management record, driver-side host memory buffer allocation record, or storage service sampling record. For access requests that have not formed a closed link from arrival to completion, the processor writes them into the pending access record and does not include them in the candidate object encapsulation of the current cache scheduling cycle.

[0090] The processor then calls a cache candidate record generation segment. This segment uses the I / O observation window that has formed an arrival-to-completion closed link before the start of the current cache scheduling cycle as the candidate time window. It processes closed access records according to a fixed cache management granularity within a single scheduling cycle. Access records within the same cache management granularity are encapsulated as candidate objects. The candidate object identifier is formed by the SSD device identifier, candidate time window number, cache management granularity identifier, and the logical block range covered by the candidate object. The processor writes the load prediction results into the cache candidate records and generates prediction heat, prediction confidence, and logical address span. The load prediction results... The results can come from time series prediction models, access frequency prediction modules, or application-side cache prediction modules. When the load prediction results provide an output scale of 0 to 1, the processor directly reads the re-access intensity within that scale as the prediction heat. When the load prediction results do not provide a unified output scale, the processor sorts the candidate objects within the same candidate time window according to their re-access intensity to form a normalized sorting value in the range of 0 to 1. The prediction confidence is formed based on the stable historical access status before the candidate time window and is written as a value in the range of 0 to 1 into the cache candidate record. The logical address span is formed by the number of logical mapping units and the number of discrete continuous segments.

[0091] The processor then calls the access segment comparison program segment. This program segment reads the candidate object identifier and candidate time window from the candidate records in the cache. It extracts the read access record from the closed access records of the same candidate object within the candidate time window and sorts them according to the time when the request was submitted to the device queue. Except for the first read access record, read access records whose logical block intervals do not belong to the continuously increasing logical mapping units relative to the previous read access record are written into the candidate random read sequence. The processor divides the candidate access segments in the candidate random read sequence and divides the candidate access segments into the front segment and the back segment according to the device completion return time. These segments form the front segment request completion delay representative value, the back segment request completion delay representative value, the front segment logical address span, and the back segment logical address span, respectively. When the increment of the back segment request completion delay representative value relative to the front segment request completion delay representative value is not less than the minimum discriminable delay increment, and the number of back segment logical mapping units and the number of back segment discrete continuous segments are both greater than the corresponding number in the front segment, the processor determines the candidate access segment as the target access segment.

[0092] The processor extracts historical access segments corresponding to candidate object identifiers from the completed stable access records before the candidate time window, and excludes historical access segments with incomplete object boundaries, incomplete completion status, and disturbed window markers generated by historical scheduling cycles. The processor determines whether the historical access segments and the target access segments meet the load similarity condition according to the request length level, queue depth level, and read request ratio level. Among the historical access segments that meet the load similarity condition, the processor selects the historical access segment with stable logical address span and the closest end time to the start time of the candidate time window as the reference access segment. The target access segment and the reference access segment are written into the access segment comparison record as input for subsequent residual attribution processing.

[0093] When the processor calls the residual attribution procedure segment, it reads the target access segment, reference access segment, target segment completion delay information, and reference segment completion delay information from the access segment comparison record. The processor first verifies whether the target access segment and the reference access segment belong to the same candidate object identifier, whether the start and end times of the target access segment are both within the candidate time window, and whether the end time of the reference access segment is earlier than the start time of the candidate time window. After the verification is passed, the processor takes the representative value of the request completion delay of the latter part of the target access segment as the target delay representative value, takes the median value of the request completion delay of the read access record in the reference access segment as the reference delay representative value, and forms the increase of the target delay representative value relative to the reference delay representative value. The processor deducts the minimum discriminable delay increment from this increase, and takes the result that is greater than 0 after deduction as the delay residual. If the result is not greater than 0 after deduction, the delay residual is recorded as 0. If the objects are inconsistent, the time sequence does not meet the requirements, or the delay data is incomplete, the processor does not perform the delay residual generation process and writes the corresponding state into the verification record of the current cache scheduling cycle.

[0094] When the processor calls the mapping perturbation evaluation program segment, it reads the target segment logical address span information and the reference segment logical address span information from the access segment comparison record. If the number of logical mapping units in the latter part of the target access segment is higher than the number of logical mapping units in the reference access segment, and the number of discrete continuous segments in the latter part of the target access segment is higher than the number of discrete continuous segments in the reference access segment, the processor confirms that the logical address span continuation is valid. Simultaneously, the processor reads the host memory buffer pressure record corresponding to the target access segment, as well as the historical host memory buffer pressure record within the historical I / O observation window of the reference access segment. When the latter part of the target access segment corresponds to... If there is increased pressure in a segment, and no increased pressure occurs in the corresponding time period of the access segment, the processor confirms that the host memory buffer pressure is being absorbed. When the latency residual is greater than 0, the logical address span is absorbed, and the host memory buffer pressure is absorbed, the processor writes the latency residual as the address mapping perturbation residual into the verification record of the current cache scheduling cycle. If the above conditions are not met simultaneously, the address mapping perturbation residual is recorded as 0. When the address mapping perturbation residual is greater than 0, the processor generates a perturbation window marker and writes the perturbation window marker into the verification record of the current cache scheduling cycle. The processor does not overwrite the cache candidate record or modify the access segment comparison record.

[0095] When the processor calls the scheduling authority state machine program segment, it reads the cache candidate records and the verification records of the current cache scheduling cycle, and matches them according to the candidate object identifier and candidate time window. If no matching verification record is found, the processor puts the scheduling authority state machine into the pending verification holding state. If the matched verification record contains a disturbed window marker with an address mapping disturbance residual greater than 0, the processor puts the scheduling authority state machine into the disturbance isolation state. If the matched verification record does not contain a disturbed window marker but has a scheduling blocking state, the processor puts the scheduling authority state machine into the pending verification holding state. If the matched verification record does not contain a disturbed window marker or a scheduling blocking state, and the scheduling authority state of the previous cache scheduling cycle belongs to either the disturbance isolation state or the recovery confirmation state, the processor puts the scheduling authority state machine into the recovery confirmation state. When the recovery confirmation conditions are met and the prediction confidence is not lower than the confidence admission boundary, the processor puts the scheduling authority state machine into the baseline scheduling state.

[0096] In the perturbation isolation state and the pending verification hold state, the processor generates cache hold permissions for candidate objects already in the cache resident state and generates no-mig-in permissions for candidate objects not in the cache resident state, and prohibits cold / hot label updates and stable history write-back. In the baseline scheduling state, the processor generates cache scheduling permissions based on predicted heat, cache resident state, cache dirty data state, mig-in heat boundary, and degradation heat boundary. When the predicted heat is not lower than the mig-in heat boundary, the processor generates cache mig-in permissions for candidate objects not in the cache resident state and no-mig-in permissions for candidate objects already in the cache resident state. The processor generates cache-stay permits for candidate objects. When the predicted heat is not higher than the degradation heat boundary, the processor generates no-migration permits for candidate objects that are not in the cache-resident state, generates cache degradation permits for cache-resident candidate objects without dirty data, generates write-back admission permits for cache-resident candidate objects with dirty data, and generates cache degradation permits after the write-back is completed. When the predicted heat is higher than the degradation heat boundary but lower than the migration heat boundary, the processor generates cache-stay permits for candidate objects that are already in the cache-resident state and generates no-migration permits for candidate objects that are not in the cache-resident state.

[0097] The processor executes cache scheduling actions according to cache scheduling permissions. When the cache migration permission is in the permitted state, the processor writes the candidate object to the cache migration queue. When the cache hold permission is in the permitted state, the processor holds the current cache resident state of the candidate object. When the no-migration permission is in the permitted state, the processor does not write the candidate object to the cache migration queue. When the cache downgrade permission is in the permitted state, the processor writes the candidate object to the cache downgrade queue. When the write-back admission permission is in the permitted state, the processor writes the candidate object to the write-back queue triggered by the cache downgrade action, and allows the cache downgrade action to be executed after the write-back is completed. When the hot and cold label update permission is in the permitted state, the processor updates the hot and cold labels of the candidate object. When the stable history write-back permission is in the permitted state, the processor writes the corresponding candidate record to the stable history access state. The stable history write-back permission does not write the latency residual, address mapping perturbation residual, and stress enhancement state corresponding to the disturbed window mark. After the scheduling action is completed, the processor writes the scheduling permission state, permission effective period, and execution result to the cache state record for use in the next cache scheduling cycle.

[0098] In one embodiment, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned SSD cache scheduling method based on load prediction. The computer-readable storage medium can be a non-volatile storage medium, including a read-only memory, flash memory, solid-state drive, disk, optical disk, embedded memory, or a storage medium capable of storing a computer program and being read by a processor. The computer program can be stored in the form of an executable file, a dynamic link library, firmware, a script, or a service process program.

[0099] After the computer program is loaded into the processor and runs, it executes candidate record generation instructions, access segment comparison instructions, residual attribution instructions, mapping disturbance evaluation instructions, scheduling permission state machine instructions, and cache scheduling execution instructions according to the cache scheduling cycle. The candidate record generation instructions are used to read SSD running status records, host memory buffer pressure records, and load prediction results, and generate cache candidate records. The access segment comparison instructions are used to form target access segments within the same candidate object and candidate time window, and select reference access segments with similar load and stable logical address spans from historical stable access records. The residual attribution instructions are used to form the latency residual of the target access segment relative to the reference access segment. The mapping disturbance evaluation instructions are used to combine logical address span acceptance and host memory buffer pressure acceptance to generate address mapping disturbance residuals and disturbed window tags. The scheduling permission state machine instructions are used to generate cache scheduling permissions based on verification records, disturbed window tags, scheduling blocking status, recovery confirmation conditions, and prediction confidence. The cache scheduling execution instructions are used to execute cache migration, cache retention, no migration, cache degradation, write-back admission, cold and hot tag update, and stable history write-back according to the cache scheduling permissions.

[0100] During execution, the computer program uses candidate cache records as read-only baseline records, access fragment comparison records as residual attribution input records, verification records of the current cache scheduling cycle as records carrying the disturbed window flag and scheduling blocking state, and cache state records as state input records for the next cache scheduling cycle. If, during program execution, there are situations such as missing records, insufficient access fragments, incomplete latency data, insufficient stress sampling, failure to obtain matching verification records, or prediction confidence lower than the confidence admission boundary, the computer program writes verification records or cache state records according to preset states and outputs cache retention permission or no migration permission, without generating cache migration permission or stable history write-back permission. Thus, when the program stored in the computer-readable storage medium is executed by the processor, it can complete the cache scheduling control of the SSD that uses host memory buffer to carry address mapping access in accordance with the aforementioned method.

[0101] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0102] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A load prediction based SSD cache scheduling method, characterized in that, include: Obtain the SSD running status record and host memory buffer pressure record that are accessed using host memory buffer address mapping. Write the load prediction results into the cache candidate record. The cache candidate record records the prediction popularity, prediction confidence and logical address span of the candidate object within the candidate time window. Fragment comparison processing is used to cache candidate records and generate access fragment comparison records. The access fragment comparison records include target access fragments and reference access fragments. The target access fragment is a completed access fragment in the candidate time window where the random read latency increases and the logical address span expands. The reference access fragment is an access fragment in the completed stable access records that meets the load similarity condition with the target access fragment and has a stable logical address span. The access segment comparison record is processed by residual attribution to generate delay residuals. Then, the delay residuals and host memory buffer pressure record are processed by mapping perturbation evaluation to generate address mapping perturbation residuals. The perturbed window markers are generated according to the address mapping perturbation residuals. A scheduling permission state machine is used to process cache candidate records and verification records of the current cache scheduling cycle, generate cache scheduling permissions, and perform cache scheduling actions on candidate objects according to the cache scheduling permissions. 2.The method of claim 1, wherein, Obtain the SSD running status record and host memory buffer pressure record that use the host memory buffer to carry address mapping access, and write the load prediction results into the cache candidate record, including: taking the I / O observation window that has formed the arrival to completion closed link before the start of the current cache scheduling cycle as the candidate time window, reading the host memory buffer enable record of the SSD, and obtaining the host memory buffer pressure record within the same candidate time window; Closed access records are processed using a fixed cache management granularity within a single scheduling cycle. Access records within the same cache management granularity are encapsulated as candidate objects, and these candidate objects are bound to candidate time windows. Load prediction results are written into the cache candidate records to form the predicted heat of the candidate objects. Prediction confidence is generated based on the stable historical access status before the candidate time window, and logical address span is generated according to the logical mapping unit range covered by the candidate objects. The written cache candidate records are used as read-only baseline records for this scheduling cycle. 3.The method of claim 2, wherein, The fragment comparison processing of cached candidate records generates access fragment comparison records, including: reading the candidate object identifier and candidate time window in the cached candidate record, extracting the closed access records of the same candidate object within the candidate time window; sorting the read access records in the closed access records according to the time when the request is submitted to the device queue, and writing the read access records that, except for the first read access record, do not belong to the continuously increasing logical mapping unit of the logical block interval relative to the previous read access record into the candidate random read sequence; Candidate access segments are divided from the candidate random read sequence. Based on the device's completion return time, each candidate access segment is divided into a front segment and a back segment, forming a front segment request completion delay representative value, a back segment request completion delay representative value, a front segment logical address span, and a back segment logical address span, respectively. If the increment of the back segment request completion delay representative value relative to the front segment request completion delay representative value is not less than the minimum discriminable delay increment, and the number of back segment logical mapping units and the number of back segment discrete continuous segments are both greater than the corresponding number in the front segment, then the candidate access segment is determined as the target access segment. The target access segment is then written into the access segment comparison record. The request completion delay is the time difference between the device's return time and the time the request is submitted to the device queue. The representative values ​​of the front-end and back-end request completion delays are the median values ​​of the request completion delays within the corresponding segments. The logical address span is represented by the number of logical mapping units and the number of discrete continuous segments. The minimum discriminable delay increment is not less than the larger of the smallest timing unit of the timestamp in the SSD running status record and the completion delay change boundary in the stable historical access status. 4.The method of claim 3, wherein, The reference access segments in the access segment comparison record are generated as follows: historical access segments corresponding to the candidate object identifier are extracted from the completed stable access records before the candidate time window, and historical access segments with incomplete object boundaries, incomplete completion status, and disturbed window markers generated by historical scheduling cycles are excluded. Based on the request length level, queue depth level, and read request percentage level, it is determined whether the historical access segment and the target access segment meet the load similarity condition. The request length level is formed based on the completed access records under the same SSD and the same cache management granularity. The queue depth level is formed based on the commit queue depth range of the same SSD. The read request percentage level is formed based on the read request percentage within the historical access segment and the target access segment. Among the historical access segments that meet the load similarity condition, the historical access segment with a stable logical address span and whose end time is closest to the start time of the candidate time window is selected as the reference access segment; the target access segment and the reference access segment are written into the access segment comparison record, and the access segment comparison record is used as the input for subsequent residual attribution processing; Among them, stable logical address span means that the number of logical mapping units and the number of discrete continuous segments of the historical access segment are not higher than the corresponding numbers in its stable historical access state.

5. The method of claim 4, wherein, Delay residuals are generated by using residual attribution processing to compare access segments with records. This includes: reading the target access segment, reference access segment, target segment completion delay information, and reference segment completion delay information from the access segment comparison records; and performing delay residual generation processing when the target access segment and the reference access segment belong to the same candidate object identifier, the start and end times of the target access segment are both within the candidate time window, and the end time of the reference access segment is earlier than the start time of the candidate time window. The target delay representative value is taken as the target delay representative value, and the median value of the request completion delay of the read access record in the reference access segment is taken as the reference delay representative value. The increase of the target delay representative value relative to the reference delay representative value is formed. The minimum discriminable delay increment is deducted from the increase. The result that is greater than 0 after deduction is taken as the delay residual. If the result is not greater than 0 after deduction, the delay residual is recorded as 0. Delay residual generation is not performed when any of the following occurs: the target access segment and the reference access segment do not belong to the same candidate object identifier; the start and end times of the target access segment are not both within the candidate time window; the end time of the reference access segment is not earlier than the start time of the candidate time window; or the delay data is incomplete. 6.The method of claim 5, wherein, The delay residual and host memory buffer pressure record are processed by mapping perturbation evaluation to generate address mapping perturbation residual. The perturbation window mark is generated according to the address mapping perturbation residual. This includes: reading the target segment logical address span information and the reference segment logical address span information in the access segment comparison record. When the number of logical mapping units in the latter part of the target access segment is higher than the number of logical mapping units in the reference access segment, and the number of discrete continuous segments in the latter part of the target access segment is higher than the number of discrete continuous segments in the reference access segment, the logical address span is confirmed to be valid. Read the host memory buffer pressure record corresponding to the target access segment and the historical host memory buffer pressure record in the historical I / O observation window of the reference access segment. If there is a pressure increase in the corresponding time period after the target access segment and no pressure increase in the corresponding time period of the reference access segment, the host memory buffer pressure is confirmed to be inherited. The pressure increase is formed by the initial and final sample values ​​of the effective pressure sampling records in the same time period, and includes at least one of the following states: decrease in the available capacity of the memory domain where the host memory buffer is located, increase in page reclamation activity count, decrease in host memory buffer allocation size, and occurrence of host memory buffer reallocation failure record. When the latency residual is greater than 0, the logical address span is accepted, and the host memory buffer pressure is accepted, the latency residual is written as the address mapping disturbance residual into the verification record of the current cache scheduling cycle; if none of these conditions are met simultaneously, the address mapping disturbance residual is recorded as 0; when the address mapping disturbance residual is greater than 0, a disturbed window marker is generated, and the disturbed window marker is written into the verification record of the current cache scheduling cycle without overwriting the cache candidate record or rewriting the access fragment comparison record.

7. The method of claim 6, wherein, A scheduling permission state machine is used to process cache candidate records and verification records of the current cache scheduling cycle, and generate cache scheduling permissions. This includes: matching the verification records of the current cache scheduling cycle with the cache candidate records according to the candidate object identifier and candidate time window; classifying the object time inconsistency state, latency residual unavailable state, latency residual insufficient state, span failure state, pressure failure undeterminable state, and pressure failure state into the scheduling blocking state; when no matching verification record is obtained, the scheduling permission state machine enters the pending verification holding state, generates cache holding permissions for candidate objects that are already in the cache resident state, and generates non-migration permissions for candidate objects that are not in the cache resident state. When a disturbed window marker with an address mapping disturbance residual greater than 0 exists in the matched verification record, the scheduling authority state machine enters the disturbance isolation state, generates a cache hold permit for candidate objects already in the cache hold state, generates a non-grab-in permit for candidate objects not in the cache hold state, and prohibits cold and hot label updates and stable history write-back; when no disturbed window marker exists in the matched verification record but a scheduling blocking state exists, the scheduling authority state machine enters the pending verification hold state, generates a cache hold permit for candidate objects already in the cache hold state, and generates a non-grab-in permit for candidate objects not in the cache hold state ... generates a non-grab-in permit for candidate objects not in the cache hold state; when no disturbed window marker exists in the matched verification record but a scheduling blocking state exists, the scheduling authority state machine enters the pending verification hold state, generates a cache hold permit for candidate objects already in the cache hold state, generates a non-grab-in permit for candidate objects not in the cache hold state; when no disturbed window marker exists in the matched verification record but a scheduling blocking state exists, the scheduling authority state machine enters the pending verification hold state, generates a cache hold permit for candidate objects already in the cache hold state, generates a non-grab-in permit for candidate objects not in the cache hold state; when no disturbed window marker exists in the matched verification record but a scheduling blocking state exists, the scheduling authority state machine enters the pending If the certificate record does not contain a disturbed window marker or a scheduling blocking state, and the scheduling authority state of the previous cache scheduling cycle is either a disturbed isolation state or a recovery confirmation state, the scheduling authority state machine enters the recovery confirmation state. If both the continuous recovery count and the continuous recovery duration meet the recovery confirmation conditions, and the prediction confidence is not lower than the confidence admission boundary, the scheduling authority state machine enters the baseline scheduling state. If the three admission conditions of continuous recovery count, continuous recovery duration, and prediction confidence are not met simultaneously, a cache retention permit is generated for candidate objects that are already in the cache residency state, and a non-migration permit is generated for candidate objects that are not in the cache residency state. If there is no disturbed window marker or scheduling blocking state in the matched verification record, the scheduling authority state of the previous cache scheduling cycle does not belong to the disturbed isolation state or the recovery confirmation state, and the prediction confidence is not lower than the confidence admission boundary, the scheduling authority state machine enters the baseline scheduling state; if the prediction confidence is lower than the confidence admission boundary, the scheduling authority state machine enters the pending verification holding state, and generates one of the cache holding permission and non-migration permission according to the cache residency state. 8.The method of claim 7, wherein, Cache scheduling actions are performed on candidate objects according to cache scheduling permissions, including: under the baseline scheduling state, generating cache scheduling permissions based on predicted popularity, cache residency state, cache dirty data state, migration-in popularity boundary, and degradation popularity boundary, wherein the migration-in popularity boundary is higher than the degradation popularity boundary; when the predicted popularity is not lower than the migration-in popularity boundary, generating cache migration-in permissions for candidate objects not in the cache residency state, and generating cache hold permissions for candidate objects already in the cache residency state; when the predicted popularity is not higher than the degradation popularity boundary, generating no migration-in permissions for candidate objects not in the cache residency state, generating cache degradation permissions for cache-residency candidate objects with a cache dirty data state of no dirty data, generating write-back admission permissions for cache-residency candidate objects with a cache dirty data state of dirty data, and generating cache degradation permissions after the write-back is completed; when the predicted popularity is higher than the degradation popularity boundary but lower than the migration-in popularity boundary, generating cache hold permissions for candidate objects already in the cache residency state, and generating no migration-in permissions for candidate objects not in the cache residency state. Only under the baseline scheduling state, and when the matched verification record does not have a disturbed window marker or a scheduling blocking state, are cold / hot label update permits and stable history write-back permits generated. Cache scheduling actions are executed according to cache migration permits, cache retention permits, no migration permits, cache degradation permits, write-back admission permits, cold / hot label update permits, and stable history write-back permits. Among them, the write-back admission permit only controls write-backs triggered by cache degradation actions, and the stable history write-back permit does not write the latency residual, address mapping disturbance residual, and stress enhancement state corresponding to the disturbed window marker. 9.A load prediction based SSD cache scheduling device, characterized in that, The system includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the processor executes the computer program to implement a load prediction-based SSD cache scheduling method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements an SSD cache scheduling method based on load prediction as described in any one of claims 1 to 8.

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