Integrated circuit and computer multi-parameter collaborative diagnosis method and system

Abstract

This application provides a multi-parameter collaborative diagnostic method and system for integrated circuits and electronic computers, applied in the fields of big data processing and integrated circuit fault diagnosis. It captures the operating state of a target register and compares it bit-level with a preset state to determine abnormal registers and bit sets. It then performs reverse signal propagation constraint analysis based on topological connections to obtain signal propagation paths. The system extracts the timing margin and load strength parameters of the paths to generate path evaluation parameters. Based on the path evaluation parameters and a preset rule base, it generates power supply disturbance commands to control the variable power supply to apply disturbances. It then captures the register state again and performs bit deviation analysis to obtain error distribution results. Finally, it uses big data correlation assessment to determine the fault path and root cause, and generates a structured fault diagnosis report to achieve accurate fault location in integrated circuits.

Description

Technical Field

[0001] This application relates to the fields of big data processing and integrated circuit fault diagnosis technology, and in particular to a multi-parameter collaborative diagnosis method and system for integrated circuits and electronic computers. Background Technology

[0002] With the widespread application of integrated circuits in electronic computer systems, their performance and reliability directly affect the overall stability and data processing efficiency of the system. In high-performance computing or long-term continuous operation scenarios, integrated circuits may experience problems such as logic anomalies, register state disorders, or electrical parameters deviating from normal ranges. If these anomalies are not detected in time, they may lead to system errors or even hardware damage. Therefore, there is an urgent need for a method that can perform multi-parameter collaborative diagnosis of integrated circuits to quickly identify potential anomalies and accurately locate faults, thereby improving system reliability and maintenance efficiency.

[0003] In existing technologies, multi-parameter collaborative diagnostic methods typically involve installing the integrated circuit to be diagnosed on a computer motherboard, sequentially acquiring its electrical parameters and abnormal register states, comparing the acquired electrical parameters with preset ranges, and comparing the logic states with preset states to determine whether there are deviations or abnormalities. Then, by combining the comparison results of electrical parameters and logic states, the faults of the integrated circuit can be diagnosed.

[0004] The above methods still have certain limitations in practical applications. Existing technologies typically obtain register bit values ​​by scanning the chain and comparing them bit by bit with expected values, or detect whether electrical parameters such as voltage and current exceed preset ranges using testing equipment, thereby determining whether there is an abnormality in the integrated circuit. However, this method is essentially an independent comparison of register states and electrical parameters, which can only reflect local or overall deviations. When multiple registers are abnormal at the same time, or when abnormal signals are transmitted and accumulated step by step along the signal propagation path between logic gates, the lack of a mechanism to correlate the distribution of erroneous bits with the signal propagation path makes it impossible to effectively track the abnormal propagation process. At the same time, the lack of a unified comprehensive evaluation of timing parameters and load parameters in the path makes it difficult to determine the key impact position of the abnormality in the path, and thus it is impossible to distinguish whether the abnormality is caused by register state deviation or logic gate output abnormality. This makes it difficult to accurately locate the root cause of the integrated circuit fault and its corresponding signal propagation path, affecting the diagnostic accuracy and efficiency of the integrated circuit. Summary of the Invention

[0005] This application provides a multi-parameter collaborative diagnostic method and system for integrated circuits and electronic computers. It correlates the distribution of register error bits with signal propagation paths, path timing, and load parameters to effectively track the abnormal propagation process and accurately locate the root cause of the fault and its corresponding signal propagation path, thereby improving the accuracy and location capability of fault diagnosis.

[0006] To achieve the above objectives, this application adopts the following technical solution: This application provides a multi-parameter collaborative diagnostic method for integrated circuits and electronic computers. The electronic computer executes a test command. The method includes: when an abnormal operation of the integrated circuit is detected, capturing a first operating state of a target register and performing a bit-level comparison between the first operating state and a preset state to determine the abnormal register in the target register and the first set of bits corresponding to the abnormal register; performing reverse signal propagation constraint analysis on the abnormal register based on the topological connection relationship of the target register to determine the signal propagation path of the test command; extracting the timing margin parameter and load strength parameter of the signal propagation path based on the preset timing constraint information of the signal propagation path, and then... The signal propagation path is evaluated and analyzed using load strength parameters to obtain path evaluation parameters. Based on the path evaluation parameters of the signal propagation path, a power supply disturbance command is generated using a preset rule relation library. After the variable power supply executes the power supply disturbance command, the second operating state of the target register is recaptured, and the second bit set corresponding to the abnormal register is determined based on the second operating state. Error bit deviation analysis is performed between the first bit set and the second bit set to obtain error distribution results. The error distribution results are correlated with the path evaluation parameters to determine the fault path and root cause of the integrated circuit, and a fault diagnosis report is generated based on the fault path and root cause.

[0007] This application provides a multi-parameter collaborative diagnostic system for integrated circuits and electronic computers. The system includes: a state processing module, used to capture a first operating state of a target register when an abnormal operation of the integrated circuit is detected, and to perform a bit-level comparison between the first operating state and a preset state to determine the abnormal register in the target register and the first set of bits corresponding to the abnormal register; a path tracing module, used to perform reverse signal propagation constraint analysis on the abnormal register based on the topological connection relationship of the target register to determine the signal propagation path of the test command; and a path evaluation module, used to extract the timing margin parameter and load strength parameter of the signal propagation path based on the preset timing constraint information of the signal propagation path, and to evaluate the signal based on the timing margin parameter and load strength parameter. The system includes a propagation path evaluation analysis module to obtain path evaluation parameters; a power supply regulation generation module to generate a power supply disturbance command based on the path evaluation parameters of the signal propagation path and a preset rule relation library; a state recapture module to recapture the second operating state of the target register after the variable power supply executes the power supply disturbance command, and to determine the second bit set corresponding to the abnormal register based on the second operating state; a deviation analysis module to perform error bit deviation analysis between the first bit set and the second bit set to obtain error distribution results; and an association diagnosis module to perform association evaluation between the error distribution results and the path evaluation parameters to determine the fault path and root cause of the integrated circuit, and to generate a fault diagnosis report based on the fault path and root cause.

[0008] As can be seen from the above technical solution, this application has the following beneficial effects: 1. This application analyzes the deviation of bit changes in the abnormal register before and after power supply disturbance, and combines the topology and timing load parameters of the signal propagation path to achieve accurate quantification of abnormal nodes in integrated circuits. It can quickly identify the contribution of each node to the overall abnormality and improve the accuracy and reliability of fault location. 2. This application utilizes big data analysis methods to correlate and evaluate error distribution results with path evaluation parameters, forming a structured fault diagnosis report. This provides engineers with traceable anomaly patterns, enabling comprehensive visualization analysis of fault root causes and their propagation paths along the signal, and optimizing circuit design and testing strategies. Attached Figure Description

[0009] Figure 1 This is a flowchart of a multi-parameter collaborative diagnostic method for integrated circuits and electronic computers according to this application; Figure 2 This is a schematic diagram illustrating the composition of a multi-parameter collaborative diagnostic system for integrated circuits and electronic computers according to this application. Detailed Implementation

[0010] The terms "first," "second," and "third," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.

[0011] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0012] To ensure clarity and conciseness in the description of the following embodiments, a brief introduction to the related technologies is given first: In the prior art, an integrated circuit (IC) refers to a circuit structure formed by integrating electronic components such as transistors, resistors, and capacitors onto the same chip substrate using semiconductor technology. An integrated circuit typically consists of multiple logic gate units and register units. The logic gate units are used to implement basic logical operations such as AND, OR, and NOT, while the register units are used to store data states and to transfer and retain data under clock control.

[0013] Research has revealed that existing technologies typically employ separate acquisition and independent comparison of register states and electrical parameters for fault diagnosis. For example, register bit values ​​are captured via a scan chain and compared bit-by-bit with expected values, or electrical parameters such as voltage and current are tested using testing equipment to detect whether they exceed preset ranges, thereby identifying anomalies. However, this approach primarily relies on comparisons of single-point data, reflecting only deviations in the electrical state of a single register or the overall system. When multiple registers exhibit anomalies simultaneously, or when abnormal signals propagate and accumulate along the signal propagation path between logic gates, the lack of analytical methods that combine the distribution of erroneous bits with the specific signal propagation path makes it difficult to effectively track the propagation process of the anomaly within the circuit. Furthermore, existing technologies often analyze timing parameters (such as signal arrival time and gate delay) and load parameters (such as drive capability and load capacitance) separately, lacking a comprehensive evaluation mechanism. This makes it difficult to accurately identify key influencing nodes under conditions of power fluctuations or changes in timing margins, thus failing to effectively distinguish whether the anomaly is caused by a register state error or a logic gate output anomaly. Ultimately, this makes fault location difficult to pinpoint to the specific logic unit and its signal propagation path, affecting the accuracy and efficiency of the diagnostic results.

[0014] To address the aforementioned problems, this application provides a multi-parameter collaborative diagnostic method for integrated circuits and electronic computers. The electronic computer executes a test command. The method includes: when an abnormal operation of the integrated circuit is detected, capturing a first operating state of a target register and performing a bit-level comparison between the first operating state and a preset state to determine the abnormal register in the target register and the first set of bits corresponding to the abnormal register; performing reverse signal propagation constraint analysis on the abnormal register based on the topological connection relationship of the target register to determine the signal propagation path of the test command; extracting the timing margin parameter and load strength parameter of the signal propagation path based on the preset timing constraint information of the signal propagation path, and then... The signal propagation path is evaluated and analyzed using degree parameters and load strength parameters to obtain path evaluation parameters. Based on the path evaluation parameters of the signal propagation path, a power supply disturbance command is generated in conjunction with a preset rule relation library. After the variable power supply executes the power supply disturbance command, the second operating state of the target register is recaptured, and the second bit set corresponding to the abnormal register is determined according to the second operating state. Error bit deviation analysis is performed between the first bit set and the second bit set to obtain error distribution results. The error distribution results are correlated with the path evaluation parameters to determine the fault path and root cause of the integrated circuit, and a fault diagnosis report is generated based on the fault path and root cause.

[0015] Example 1: As Figure 1 As shown, this application provides a multi-parameter collaborative diagnostic method for integrated circuits and electronic computers, wherein the electronic computer executes test commands, and the specific steps of the method are as follows: S1, when an abnormal operation of the integrated circuit is detected, the first operating state of the target register is captured, and the first operating state is compared with the preset state at the bit level to determine the abnormal register in the target register and the first bit set corresponding to the abnormal register.

[0016] In S1, a test command is an instruction issued by a computer to trigger specific operations or status acquisition of an integrated circuit. It controls the target register to perform read / write operations, scan chain capture, or specific functional unit operations, thereby obtaining the register's operating status and related logic signal information for use in integrated circuit fault analysis.

[0017] An integrated circuit malfunction refers to a situation where, under normal operating conditions, the logic state or electrical parameters of the target register deviate from the preset standard, manifesting as bit errors or register outputs that do not meet expectations.

[0018] Target register: refers to the register unit in an integrated circuit used to store and transmit signals. Its state can be read by a computer through a scan chain or read / write interface.

[0019] First operating state: refers to the actual logical value and state information of each bit of the target register captured at the detection time, including the bit of the target register and the first bit value corresponding to the bit.

[0020] Preset state: refers to the reference bit value of the target register under normal working conditions when executing a fixed test command, including the standard logic value of each bit; the preset state includes the bits of the target register and the standard bit value corresponding to each bit.

[0021] An abnormal register is a target register whose logic value of at least one bit is inconsistent with the standard value when compared.

[0022] The first bit set refers to the set of all bits in the exception register and their matching results, including the normal bits and error bits of the exception register.

[0023] Bit-level comparison: This refers to the operation of comparing each bit value of the target register in its first operating state with the corresponding bit value in the preset state. The bit-level comparison method is as follows: For example, the first operating state of target register A is [1, 0, 1], and the first operating state of target register B is [0, 1, 1]. When executing the test command, the theoretical operating state (preset state) of target register A is [1, 1, 1], and the theoretical operating state of target register B is [0, 0, 1]. During the bit-level comparison process, each bit value of target registers A and B is read sequentially and compared with its corresponding preset state bit value to obtain the bit matching result. That is, for target register A, bit 1 matches (1 vs 1), bit 2 matches (0 vs 1), and bit 3 matches (1 vs 1). Therefore, the erroneous bit of target register A is the 2nd bit, and the normal bits are the 1st and 3rd bits. Target register A is marked as an abnormal register. For destination register B, bit 1 matching (0 vs 0) indicates a match, bit 2 matching (1 vs 0) indicates a mismatch, and bit 3 matching (1 vs 1) indicates a match. Therefore, the erroneous bit of destination register B is bit 2, and the normal bits are bits 1 and 3. Destination register B is marked as an abnormal register.

[0024] In S1, the first running state is compared bit-level with the preset state to determine the exception register in the target register and the first bit set corresponding to the exception register. One possible implementation is as follows: S101, for each target register, perform a bit-by-bit matching operation between the first bit value of each bit in the first running state and the standard bit value of the corresponding bit in the preset state to obtain the matching result of each bit. The matching result includes bit value matching and bit value mismatch. In S101, bit value refers to the logical state of each bit in the target register, such as 0 or 1. In the first running state, it is recorded as the first bit value, and in the preset state, it is recorded as the standard bit value.

[0025] Bit-by-bit matching operation: The first bit value of each bit in the first running state is compared one by one with the standard bit value of the corresponding bit in the preset state to determine whether they are the same. The matching result includes two cases: the bit values ​​are the same or the bit values ​​are different.

[0026] S102, if the matching result is that the bit values ​​are consistent, then the bit corresponding to the matching result is recorded as a normal bit; if the matching result is that the bit values ​​are inconsistent, then the bit corresponding to the matching result is marked as an error bit, and the target register corresponding to the error bit is marked as an abnormal register. In S102, normal bit: refers to the bit whose bit value is consistent in the bit-by-bit matching operation, indicating that the current state of the bit is consistent with the preset state and there is no abnormality.

[0027] Error bit: refers to a bit whose value is inconsistent during the bit-by-bit matching operation, indicating that the current state of the bit does not match the preset state and there is an anomaly.

[0028] S103, the normal bits and error bits corresponding to the exception register are encapsulated and stored to obtain the first bit set.

[0029] In S103, packaged storage refers to storing the normal bits and error bits of each fault register according to a unified data structure or recording method to form a complete set of first bits, which facilitates fault assessment of integrated circuits.

[0030] This application performs a bit-level comparison between the first operating state and the preset state of the target register in step S1 to identify abnormal registers and their error bits. The normal bits and error bits of the abnormal registers are then encapsulated and stored to form a first bit set. This allows for a comprehensive reflection of register operating deviations using big data analysis, enabling timely location of faults caused by abnormal register states or logic gate output deviations in integrated circuits, thereby improving the accuracy and efficiency of fault diagnosis.

[0031] S2, based on the topological connection relationship of the target register, perform reverse signal propagation constraint analysis on the abnormal register to determine the signal propagation path of the test command.

[0032] In S2, the topology of the target register refers to the electrical connection structure between the target register and logic gates, as well as other registers in the integrated circuit. This includes the connection between the target register and the input terminals of the logic gates, and the connection between the output terminals of the logic gates and the target register. The topology of the target register can usually be extracted from the netlist file or design exchange format file of the integrated circuit, and the signal flow is represented in the form of a directed graph.

[0033] Signal propagation path: This refers to the complete physical logic path that a test signal takes when executing a test command, starting from a source (such as an input port or a previous-level register), passing through a combination of logic gates (such as AND gates, OR gates, NOT gates, etc.), and finally reaching the target register (especially the exception register). The signal propagation path includes at least the exception register and the target logic gates it passes through.

[0034] Reverse signal propagation constraint analysis (RSCA) starts from the known output state of an abnormal register (i.e., the combination of bit values ​​in the first bit set), and, based on the logic type and function of the target logic gate directly connected to the abnormal register, reversely derives the possible valid bit value combinations at the input of the target logic gate, and further traces back to the previous level register or input port, thus determining the source path of the signal step by step. RSCA fully utilizes the constraints of circuit logic to eliminate impossible bit value combinations, obtaining bit value combinations that satisfy the logic of the target logic gate; for example, for an AND gate, all inputs must be 1 when the output is 1; at least one input must be 0 when the output is 0.

[0035] The reverse signal propagation constraint analysis works as follows: For example, suppose the output of an exception register R is connected to the output of a two-input AND gate G, and a bit in the exception register R is 1 (i.e., the bit captured by the target register is 1). According to the logic of the AND gate, the output is 1 if and only if both inputs are 1. Therefore, reverse analysis shows that both inputs of the AND gate G must have been 1 at the previous time step. If these two inputs are connected to the previous-level target registers R1 and R2 respectively, it can be deduced that the output values ​​of R1 and R2 should be 1 and 1 respectively. If there are multiple possible input combinations (for example, for an OR gate, all inputs must be 0 when the output is 0, but there are multiple combinations when the output is 1), then all possible valid bit value combinations are recorded to form a set of branch nodes. The AND gate is a logic type of the target logic gate.

[0036] One possible implementation of step S2 is as follows: S201, retrieve the exception register and the corresponding first bit set, the first bit set including the normal bits and error bits of the exception register; It should be noted that an exception register is a type of target register, that is, a target register containing error bits. Therefore, exception registers can be used to perform reverse signal propagation constraint analysis using the topological connection relationship of target registers.

[0037] S202, based on the connection relationship between the logic gate output and the target register, determine the target logic gate output and the logic type of the target logic gate that are directly connected to the exception register; In S202, the connection relationship between the logic gate output and the target register refers to the physical connection information between the output pin of the target logic gate and the input pin of the target register. This information can be obtained from the netlist or routing file of the integrated circuit.

[0038] Logic gates are units in integrated circuits that implement basic logic operations, including AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, etc. Among them, the target logic gate is a type of logic gate, which is a logic gate that is directly connected to the exception register currently being analyzed.

[0039] Logical type: refers to the type of Boolean operation implemented by the logic gate, such as AND, OR, NOT, etc. The logical type determines the truth table relationship between the input and output and is the basis for reverse operation.

[0040] S203, Based on the normal bits and error bits of the exception register, and in combination with the bit values ​​corresponding to the normal bits and error bits respectively, determine the bit value combination of the exception register; Bit value combination: refers to the sequence of specific logical values ​​(0 or 1) of all bits in a register. For example, the bit value combination of an 8-bit register can be [1,0,1,1,0,0,1,0]. For exception registers, the bit value combination includes the bit value corresponding to the normal bit (which should be consistent with the preset state) and the bit value corresponding to the error bit (the actual captured value that is inconsistent with the preset state).

[0041] S204, the bit value combination of the exception register is input in reverse to the output of the target logic gate, and the inverse operation is performed according to the logic type of the target logic gate to obtain at least one valid bit value combination corresponding to the input of the target logic gate; Inverse operation: This refers to inferring the set of possible input values ​​based on the output value of the target logic gate. Since logic operations are usually not injective (one output may correspond to multiple input combinations), the result of inverse operation is one or more possible combinations of input bit values, where these combinations of bit values ​​must satisfy the following condition: when the bit value combination is input to the target logic gate, performing a forward operation according to its logic type results in exactly the known output value.

[0042] The reverse operation is performed as follows: For example, suppose the target logic gate is a two-input AND gate, and its output is connected to a bit in the exception register, where the value of this bit is 0. The truth table of the AND gate indicates that when the output is 0, the input combination can be (0,0), (0,1), or (1,0). Therefore, the reverse operation yields three possible valid bit value combinations: (0,0), (0,1), and (1,0). If the value of this bit is 1, the reverse operation yields only one valid combination: (1,1). For the OR gate, when the output is 0, there is only (0,0); when the output is 1, there are three possibilities: (1,0), (0,1), and (1,1). For the NOT gate, the reverse operation is deterministic: when the output is 0, the input is 1; when the output is 1, the input is 0.

[0043] Valid bit value combination: refers to the logically feasible input bit value combination obtained through reverse operation. These bit value combinations will be used for subsequent mapping to the next level target register.

[0044] S205, based on the connection relationship between the target register and the input terminal of the logic gate, the effective bit value combination of the input terminal of the target logic gate is mapped to the corresponding output terminal node of the upper-level register to form a branch node set, and the branch node set is iteratively backtracked to determine the signal propagation path of the test command. The signal propagation path includes at least the exception register and the target logic gate.

[0045] The connection relationship between the target register and the logic gate inputs refers to which output of the next higher level register (or the output of another logic gate) each input of the logic gate is specifically connected to. This connection relationship can be obtained from the netlist or routing file of the integrated circuit.

[0046] Branch node set: This refers to the set of all possible upstream signal source nodes in a single reverse operation. Each node corresponds to a previous-level exception register (or input port) and its assumed output value under the valid bit value combination. Due to the existence of multiple possible input combinations, the branch node set may contain multiple nodes, each representing a possible signal propagation branch.

[0047] Iterative backtracking: This refers to repeatedly executing the process from S202 to S205, using the currently obtained previous-level exception register as the starting exception register for the new round (assuming its output value must be the value derived from the reverse operation), and continuing to trace upstream until reaching the chip's input port or a register with a known state (such as an observable register in the scan chain), thus forming one or more complete signal propagation paths. During the iteration process, if a branch causes a contradiction (for example, a register needs to satisfy two different output values ​​simultaneously), that branch is pruned; the remaining branches constitute possible signal propagation paths.

[0048] The iterative backtracking method is as follows: For example, starting from the exception register R0 (bit value 0), it is found to be connected to the output of AND gate G1. Reverse operation yields three possible input combinations for G1: (0,0), (0,1), and (1,0). The two inputs of G1 are connected to the previous level exception registers R1 and R2, respectively. This forms three branches: Branch 1 assumes R1=0, R2=0; Branch 2 assumes R1=0, R2=1; Branch 3 assumes R1=1, R2=0. For each branch, starting from R1 and R2 respectively, the reverse analysis continues on their respective input target logic gates. If, in subsequent backtracking, branch 2 causes R1 to be both 0 and 1 (a contradiction), then branch 2 is discarded. All the branches that remain without contradiction are the possible signal propagation paths, and each signal propagation path records all target logic gates and exception registers along that path.

[0049] Step S2 of this application performs reverse signal propagation constraint analysis on the abnormal register based on the topological connection relationship of the target register. Combining the node connection relationship, logic gate type and bit value combination data extracted from the netlist file, big data analysis is used to perform correlation mining. The possible effective bit value combinations of the upstream logic gate input are deduced from the actual bit value combination of the abnormal register and the complete signal propagation path is determined by iterative backtracking. In this way, isolated error bits are associated with specific paths, so that the abnormality can be traced on the path formed by the target logic gate and the abnormal register. This provides a clear path range and structural framework for the application of power supply disturbance and the location of fault root causes.

[0050] S3. Based on the preset timing constraint information of the signal propagation path, extract the timing margin parameter and load strength parameter of the signal propagation path, and perform evaluation analysis on the signal propagation path based on the timing margin parameter and load strength parameter to obtain path evaluation parameters.

[0051] In S3, the preset timing constraints for signal propagation paths refer to the timing requirements predetermined during the integrated circuit design phase to ensure the normal operation of the circuit. These include preset clock constraints and preset gate delay constraints. The preset clock constraints specify at least the clock signal period, duty cycle, setup time, and hold time. The preset gate delay constraints specify at least the maximum permissible propagation delay for each logic gate (such as AND gate, OR gate, NOT gate, etc.) under standard conditions.

[0052] Timing margin parameter: This refers to the difference between the actual arrival time of the test signal and the time boundary required by the preset constraint. For faulty registers, the timing margin parameter reflects the margin of their data signal relative to the clock edge (such as setup time margin or hold time margin); for target logic gates, the timing margin parameter reflects the degree of deviation of their output response delay from the preset gate delay constraint. The timing margin parameter can be positive (meets timing requirements) or negative (violates timing requirements).

[0053] Load strength parameter: This refers to the ratio of the equivalent capacitance of the subsequent load driven by the output of the target logic gate to its output drive current. It is used to measure the ease with which the logic gate drives the load. The larger the load strength parameter, the heavier the load driven by the logic gate, the slower the output signal transition, and the more likely it is to cause timing problems.

[0054] Evaluation and analysis refers to comparing the extracted timing margin parameters and load strength parameters with preset benchmark values, calculating the deviation of each node (abnormal register, target logic gate), and structurally encapsulating and accumulating the deviation values ​​of each node according to the topological order of the signal propagation direction, thereby obtaining a set of quantitative parameters that can reflect the quality of the entire path and the contribution of local nodes.

[0055] Path evaluation parameters refer to structured data obtained through evaluation and analysis, used to describe the overall quality of the signal propagation path and the quality of each node within it. These parameters include at least local and overall evaluation parameters. Path evaluation parameters are the basis for generating power supply disturbance commands and for assessing the root causes of associated faults.

[0056] In S3, based on the preset timing constraint information of the signal propagation path, the timing margin parameter and load strength parameter of the signal propagation path are extracted. One possible implementation method is as follows: S311, retrieve the exception register and target logic gate in the signal propagation path; S312, when the electronic computer executes the test command, the arrival time of the test signal of the abnormal register, as well as the output response delay and output drive current of the target logic gate are collected; The test signal arrival time refers to the actual time it takes for the test signal to travel along the propagation path to the data input terminal of the current exception register from the issuance of the test command or the output of the previous level register. This test signal arrival time is used to calculate the timing margin parameter of the exception register, and can be obtained through on-chip timing monitoring circuits (such as time-to-digital converters TDC) or timing measurement methods based on scan chains.

[0057] The output response delay of the target logic gate refers to the time required for its output to change accordingly after a change in the input signal. This output response delay is used to calculate the timing margin parameter of the target logic gate and can be obtained through gate-level simulation or on-chip path delay measurement circuit.

[0058] The output drive current of the target logic gate refers to the amount of current that the target logic gate can provide when it outputs a high or low level. This output drive current is used to calculate the load strength parameters of the target logic gate, and can be read from the integrated circuit's process library (e.g., lib file) or measured by an on-chip current sensor.

[0059] S313, Based on the arrival time of the test signal of the exception register and the preset clock constraint, calculate the timing margin parameter of the exception register, and based on the output response delay of the target logic gate and the preset gate delay constraint, calculate the timing margin parameter of the target logic gate. Among them, the preset clock constraint refers to the clock period, setup time requirement, and hold time requirement determined during integrated circuit design. The preset clock constraint is used as a benchmark for calculating timing margin parameters. For example, for a synchronous circuit with a clock period of 10ns and a setup time requirement of 1ns, the hold time requirement is: the signal must remain stable 1ns before the rising edge of the clock arrives.

[0060] The timing margin parameter of the exception register is calculated as follows: For example, suppose the preset clock period is T1, the register setup time requirement is T2, and the actual time for the test signal to reach the register data input terminal relative to the same clock edge (i.e., the test signal arrival time) is T3. Then, the setup time margin parameter = (T1 - T3) - T2. If the result of the time margin parameter is positive, it means that the exception register meets the setup time requirement; if the result of the time margin parameter is negative, there is a setup time violation.

[0061] Preset gate delay constraints refer to the maximum propagation delay of each logic gate specified in the technology library under standard operating conditions (voltage, temperature, process angle). Preset gate delay constraints are used to determine whether the actual delay of the target logic gate exceeds the limit. For example, the maximum delay of a two-input AND gate in a certain technology library is 0.5ns.

[0062] The timing margin parameter of the target logic gate is calculated as follows: For example, if the preset gate delay constraint of the target logic gate is D1 and the actual measured output response delay is D2, then the timing margin parameter of the logic gate = D1 - D2. If the result of the timing margin parameter is positive, it means that the delay of the target logic gate is within the constraint range; if the result of the timing margin parameter is negative, it means that the delay of the target logic gate exceeds the limit.

[0063] S314, for any of the signal propagation paths, determine the successor connection node of the target logic gate in the signal propagation path, the successor connection node including the next target logic gate or an exception register; The successor connection node refers to the next-level circuit node directly connected to the output of the current target logic gate along the signal propagation direction. This circuit node can be the input of another logic gate or the input of an exception register.

[0064] S315, obtain the current capacitance of the successor connection node, and analyze the output drive current of the target logic gate with the current capacitance of the successor connection node to obtain the load strength parameter of the target logic gate; The current capacitance of the successor node refers to the equivalent load capacitance of the successor node, including the input capacitance of the next logic gate, interconnect capacitance, and any additional parasitic capacitance. The capacitance value of this equivalent load capacitance can be obtained from the parasitic parameter extraction file of the integrated circuit (such as the SPEF file).

[0065] The load strength parameter of the target logic gate can be obtained as follows: For example, suppose the output drive current of the target logic gate is I, and the current capacitance of the subsequent connection node is C. Then the load strength parameter = C / I, where the unit of the load strength parameter is (farad / ampere). The larger the value, the heavier the load and the more difficult it is to drive the logic gate. Another common method is to calculate the RC time constant as the load strength parameter, i.e., load strength parameter = R×C, where R is the equivalent output resistance of the logic gate, and R is inversely proportional to the drive current I; C is the current capacitance of the subsequent connection node.

[0066] S316. According to the topological order of the signal propagation path, the timing margin parameters of each abnormal register and the timing margin parameters of each target logic gate are encapsulated to obtain the timing margin parameters of the signal propagation path, and the load strength parameters of each target logic gate are encapsulated to obtain the load strength parameters of the signal propagation path.

[0067] The topological order of the signal propagation path refers to the order in which the signal passes through the nodes along the propagation direction from upstream (near the input port or the starting point of the test command) to downstream (the end exception register). This order passes through the exception register and the target logic gate in sequence.

[0068] Encapsulation refers to storing the parameter values ​​of each node on the path into an ordered data structure (such as an array, list, or vector) according to the topological order described above, so that they can be used.

[0069] The encapsulation method is as follows: for example, put the timing margin parameters of all exception registers and target logic gates into array A in sequence, and put the load strength parameters of all target logic gates into array B in sequence. Array A and array B together constitute the timing margin parameters and load strength parameters of the signal propagation path.

[0070] This application, through steps S311-S316, can systematically reflect the timing margin and load intensity of each node in the signal propagation path. Since the signal arrival time of the fault register interacts with the output delay and drive capability of the target logic gate, the timing margin and load intensity between nodes affect the stability of the downstream signal. Through structured analysis along the signal propagation direction, potential timing violations or overloaded nodes in the path can be naturally identified. This local information is accumulated to form overall path evaluation parameters, thus reasonably revealing the contribution of each node to signal integrity and path reliability. This allows for clear quantification of the fault impact range of the fault register and the risk of the critical path, providing a scientific basis for power supply disturbance application and fault root cause location.

[0071] In S3, an evaluation analysis is performed on the signal propagation path based on the timing margin parameter and load strength parameter to obtain path evaluation parameters. One possible implementation method is as follows: S321, retrieve the timing margin parameters and load strength parameters of the signal propagation path, and obtain the timing margin reference value corresponding to the preset clock constraint and the gate delay reference value corresponding to the preset gate delay constraint according to the preset timing constraint information. Among them, the timing margin baseline value refers to the standard value used as a reference when evaluating the timing margin of the exception register. It is usually taken as 0 (indicating that the timing just meets the requirements) or the design target value (such as a positive margin of 100ps).

[0072] Gate delay baseline: refers to the standard value used as a reference when evaluating the timing margin of the target logic gate. It is usually taken as 0 (meaning that the actual delay is equal to the maximum allowable delay) or as a typical delay value given in the technology library.

[0073] S322, Perform difference calculation between the timing margin parameter of each abnormal register in the signal propagation path and the timing margin reference value to obtain the first timing deviation value of each abnormal register; Among them, difference calculation: that is, subtraction operation, is used to calculate the degree of deviation between parameters.

[0074] First timing deviation value: refers to the difference between the actual timing margin parameter of the abnormal register and the timing margin baseline value; when the first timing deviation value is negative, it means that the timing margin of the register is lower than the baseline, and there is a timing risk.

[0075] The method for performing the difference calculation is as follows: For example, if the timing margin baseline value is 0 and the timing margin parameter of a certain exception register is -0.2ns, then the first timing deviation value = (-0.2) - 0 = -0.2ns.

[0076] S323, Perform difference calculation between the timing margin parameter of each target logic gate in the signal propagation path and the gate delay reference value to obtain the second timing deviation value of each target logic gate; The second timing deviation value refers to the difference between the actual timing margin parameter of the target logic gate and the gate delay benchmark value. When the second timing deviation value is negative, it indicates that the actual delay of the logic gate exceeds the benchmark, and there may be a delay fault.

[0077] S324, retrieve the load strength parameters of each target logic gate in the signal propagation path, and obtain the standard load threshold corresponding to each target logic gate; Standard load threshold: This refers to the maximum load intensity value (e.g., maximum permissible C / I ratio or maximum permissible load capacitance) that a logic gate can operate normally under typical drive capabilities as specified in the technology library. Exceeding this threshold indicates that the logic gate drive load is too heavy.

[0078] S325, perform difference calculation between the load strength parameter of each target logic gate and the corresponding standard load threshold to obtain the load deviation value of each target logic gate; Load deviation value: equal to the actual load strength parameter minus the standard load threshold. A positive load deviation value indicates that the logic gate is driven by an excessive load, which may affect signal propagation quality.

[0079] S326, according to the topological order of the signal propagation path, the first timing deviation value of each abnormal register, the second timing deviation value of each target logic gate, and the load deviation value are structurally encapsulated to form the local evaluation parameters of the signal propagation path; Local evaluation parameters are structured data that records the deviation of each node (abnormal register or target logic gate) along the signal propagation path from the ideal reference, used to locate weak points in the path. The encapsulation structure of local evaluation parameters can be: a dictionary or an array of objects, where each element contains a node identifier (such as register name or logic gate name), node type, and corresponding deviation value (first timing deviation value, second timing deviation value, or load deviation value).

[0080] S327, Perform cumulative calculation on the local evaluation parameters according to the signal propagation direction to obtain the overall evaluation parameters of the signal propagation path; Cumulative calculation refers to combining the deviation values ​​of each node on the path into a single value according to certain rules (such as summation, weighted summation, taking the maximum value, or taking the root mean square) to reflect the overall quality of the entire path.

[0081] Cumulative calculation method: For example, a weighted summation method can be used: Suppose there are K nodes on the path, and the comprehensive deviation value of each node = α × time series deviation value + β × load deviation value (if the node is a register, the load deviation value is 0). The overall evaluation parameter is the sum of the comprehensive deviation values ​​of the K nodes. Here, α and β are weight parameters used to adjust the relative importance of time series deviation and load deviation in the overall evaluation. By adjusting these weight parameters, the assessment of time series risk or load risk can be emphasized. Those skilled in the art can set the values ​​of α and β according to actual needs, for example, both can be set to 0.5.

[0082] Overall evaluation parameter: This refers to the quantitative index obtained by accumulating the deviation values ​​of each node on the path. The larger the value, the more serious the accumulated time sequence deviation and load deviation of the path, and the worse the path quality.

[0083] S328, The local evaluation parameters and the overall evaluation parameters are structurally encapsulated to obtain the path evaluation parameters of the signal propagation path.

[0084] Path evaluation parameters: These are data structures that contain both local and overall evaluation parameters, used to generate power supply disturbance commands and locate faults. The encapsulation structure of path evaluation parameters can be an object or structure containing two fields: the first field stores local evaluation parameters, and the second field stores overall evaluation parameters.

[0085] This application, through steps S321-S328, systematically quantifies the timing and load deviations of each node along the signal propagation path into structured data. Since the actual parameters of the exception register and target logic gate differ from the baseline values, the difference calculation directly reveals the potential timing risks or load stresses of each node. Accumulating these deviation values ​​along the signal propagation direction reflects the overall quality of the path and identifies critical nodes that may lead to signal integrity degradation or timing violations. Local evaluation parameters provide precise location information for individual nodes, while overall evaluation parameters form a comprehensive quantitative index for the entire path, naturally revealing the weak points and risk levels of the signal propagation path. This provides a scientific basis for power supply disturbance strategy formulation and fault root cause analysis, achieving global visualization analysis from the node level to the path level.

[0086] S4. Based on the path evaluation parameters of the signal propagation path, a power supply disturbance command is generated in combination with a preset rule relation library.

[0087] In S4, the pre-defined rule base refers to a pre-established set of rules used to map path evaluation parameters (local and global evaluation parameters) to power supply disturbance commands. This rule base contains at least two types of mapping relationships: one is the correspondence between local evaluation category identifiers and power supply adjustment types; the other is the correspondence between global evaluation parameter ranges and adjustment ranges. The rule base can be stored in the form of lookup tables, decision trees, or conditional statements.

[0088] Power supply disturbance instructions are instructions used to control variable power supplies to change their output voltage or drive capability. They consist of two parts: the type of power supply regulation and the range of regulation amplitude. The purpose of power supply disturbance instructions is to actively change the operating voltage of the integrated circuit to observe changes in the state of the fault register bits, thereby helping to distinguish between the root cause and propagation effects of a fault.

[0089] One possible implementation of step S4 is as follows: S401, Perform sign determination and amplitude segmentation on the local evaluation parameters to obtain the local evaluation category identifier; The sign determination refers to judging the positive or negative value of the deviation value of each node in the local evaluation parameters. A positive deviation value indicates that the timing or load condition of that node is better than the benchmark (no risk), while a negative deviation value indicates that it is worse than the benchmark (risk exists).

[0090] Amplitude segmentation processing refers to dividing the absolute value of the deviation into several intervals (such as slight, moderate, and severe), with each interval corresponding to a level. For example, load deviation values ​​can be divided into: 0-0.1 for slight, 0.1-0.3 for moderate, and greater than 0.3 for severe.

[0091] Local evaluation category label: This refers to the data pairs generated based on the sign and magnitude segmentation results, used to characterize the anomaly type of each node on the path. For example, {negative register timing deviation, moderate} or {positive logic gate load deviation, severe}.

[0092] In S401, the sign determination and amplitude segmentation processing of the local evaluation parameters are performed as follows: For example, assuming the load deviation value of a target logic gate is +0.25, and the amplitude segmentation threshold is set to (0 ≤ slight ≤ 0.1, 0.1 < moderate ≤ 0.3, severe > 0.3), it is determined to be a positive deviation and moderate severity, and the local evaluation category identifier is generated as {overload, moderate}. Assuming the first timing deviation value of an abnormal register is -0.15, it is determined to be a negative deviation and moderate, and the identifier {insufficient timing, moderate} is generated.

[0093] S402, based on the local evaluation category identifier, match the corresponding power supply adjustment type in the preset rule relationship library. The power supply adjustment type includes voltage boost adjustment type, voltage suppression adjustment type and drive capability allocation adjustment type. Voltage boost regulation type: This refers to a regulation method that increases the supply voltage, suitable for anomalies caused by insufficient timing margin (negative deviation). Increasing the voltage can speed up the switching speed of logic gates and improve timing.

[0094] Voltage suppression regulation type: refers to the regulation method of reducing the supply voltage. It is suitable for scenarios where noise needs to be reduced due to light load or excessive power consumption, or for detecting the impact of voltage drop on anomalies.

[0095] Drive capability allocation adjustment type: refers to the adjustment method of changing the load intensity by adjusting the drive capability of logic gates (such as enabling the backup drive unit), which is suitable for scenarios where the load deviation is positive (overload).

[0096] S403, based on the overall evaluation parameters, match the corresponding adjustment range in the preset rule relationship library, and combine the power supply adjustment type with the adjustment range to form a power supply disturbance command.

[0097] Adjustment range: This refers to the adjustment range of the power supply voltage or drive capability, such as "+5%", "-3%", or "upgrade by one level". The larger the overall evaluation parameter value (the higher the risk), the larger the corresponding adjustment range.

[0098] In S403, the power supply adjustment type and the adjustment range are combined as follows: The power supply adjustment type (e.g., voltage boost adjustment type) obtained in S402 and the adjustment range (e.g., +5%) obtained in S403 are directly concatenated into a single instruction, such as "voltage boost 5%". This instruction is then sent to the variable power supply for execution.

[0099] This application, through the execution of step S4, transforms the quantified results of path evaluation parameters into specific power supply disturbance commands for precise adjustment of the voltage or drive capability of each node in the integrated circuit. By performing sign determination and amplitude segmentation on local evaluation parameters, the timing insufficiency of the abnormal register or the excessive load of the target logic gate can be clearly distinguished. Combined with the overall evaluation parameters, the adjustment range is determined, thereby forming a power supply disturbance command that can be directly issued to the variable power supply. By actively inducing changes in the bit state of the abnormal register, the distinction between the fault root cause and the signal propagation effect becomes clearer, overcoming the shortcomings of existing technologies that rely solely on passive observation and cannot accurately locate anomalies, thus achieving refined and controllable analysis for integrated circuit fault diagnosis.

[0100] S5, after the variable power supply executes the power supply disturbance instruction, recapture the second operating state of the target register, and determine the second bit set corresponding to the abnormal register based on the second operating state.

[0101] In S5, variable power supply refers to a power module whose output voltage or drive capability can be controlled by computer commands, and can dynamically adjust power supply parameters (such as increasing or decreasing voltage, or changing drive capability) according to power supply disturbance commands.

[0102] Second operating state: refers to the actual logical values ​​and status information of each bit in the target register that are recaptured after the power supply disturbance instruction is executed, including the second bit value corresponding to each bit.

[0103] The second bit set refers to the set of abnormal registers and their normal and error bits obtained through bit-level comparison after a power supply disturbance. Its data structure is the same as the first bit set and is used for subsequent deviation analysis.

[0104] One possible implementation of step S5 is as follows: S501, after the variable power supply executes the power supply disturbance instruction, the second operating state of the target register is captured. The second operating state includes the bit bits of the target register and the second bit value corresponding to the bit bits. The second bit value refers to the logical value (0 or 1) actually read from each bit of the target register after the power supply disturbance.

[0105] S502, based on the preset state, perform a bit-level comparison on the second operating state to determine the abnormal register after the power supply disturbance instruction is executed, as well as the normal bit and error bit of the abnormal register, as the second bit set.

[0106] The second bit set: After a power supply disturbance, the same bit-level comparison method (bit-by-bit matching) as in S1 is used to compare the second bit value of each bit in the second operating state with the standard bit value of the corresponding bit in the preset state, record the matching result, and encapsulate it to obtain the second bit set. The data structure of this set is the same as that of the first bit set in S1 (including register identifier, bit position, and normal / error flag).

[0107] This application achieves precise capture and analysis of the target register state of the integrated circuit after power supply disturbance by executing step S5. By controlling the variable power supply to adjust the voltage or drive capability according to the power supply disturbance command, possible timing or load anomalies are actively triggered, thereby observing the response of the abnormal register bits. The second operating state of the target register is recaptured and compared bit by bit with the preset state to generate a second bit set. This clearly distinguishes between new anomalies caused by power supply disturbance and original anomalies, thereby revealing the sensitivity of the abnormal register under different power supply conditions. This makes the fault propagation path and root cause location more accurate, providing reliable data support for deviation analysis and power supply strategy optimization.

[0108] S6, perform error bit deviation analysis on the first bit set and the second bit set to obtain the error distribution result.

[0109] In S6, error bit deviation analysis refers to identifying changes in abnormal registers (including the addition or removal of error bits, the disappearance or addition of registers) by comparing the bit sets captured before and after a power supply disturbance (the first bit set and the second bit set), thereby quantifying the impact of power supply disturbances on the circuit state.

[0110] Error bit deviation analysis methods: For example, compare whether the number and position of error bits in the same register in the two sets before and after the disturbance have changed, and determine which register errors have been suppressed (reduced), which have remained unchanged, and which have newly appeared.

[0111] Error distribution result: refers to the data structure obtained by organizing the above change information (first change information, second change information, and third change information) according to the signal propagation path, which is used for subsequent evaluation in association with path evaluation parameters.

[0112] One possible implementation of step S6 is as follows: S601, using the first bit set as a reference, traverse each exception register and determine whether the exception register exists in the second bit set; Specifically, each abnormal register recorded in the first bit set is used as a query object to search for whether there is a register with the same identifier in the second bit set.

[0113] S602, if the abnormal register exists in the second bit set, then perform a change analysis on the number and position of the error bits and normal bits, and use the result of the change analysis as the first change information of the abnormal register; Change analysis refers to comparing the changes in the number of erroneous bits, their specific positions, and the normal bits in the first and second bit sets of the same register.

[0114] Change analysis method: For example, if a register has 3 error bits in the first bit set (positions 1, 3, and 5) and only 1 error bit in the second bit set (position 3), then the change analysis result is: the number of error bits decreases by 2 (positions 1 and 5 return to normal), and position 3 is still an error.

[0115] First change information: refers to structured data that records the results of the above change analysis, including at least: register identifier, list of error bits before the disturbance, list of error bits after the disturbance, number of errors reduced, and error retention location.

[0116] S603, if the exception register does not exist in the second bit set, then mark the exception register as a reduced exception register and record the second change information of the reduced exception register; Reduced exception register: refers to a register that is no longer marked as exception after a power supply disturbance (i.e., all its bits are consistent with the preset state).

[0117] The second change information refers to the information that records the change of the register from abnormal to normal, including the register identifier, the list of erroneous bits before the disturbance, and a mark indicating that all errors have been eliminated.

[0118] S604, if an abnormal register is detected that exists in the second bit set but does not exist in the first bit set, then the abnormal register is marked as a newly added abnormal register and the third change information of the newly added abnormal register is recorded; New abnormal register: refers to an abnormal register that appears after a power supply disturbance (the state was normal before the disturbance, but an error bit appeared after the disturbance).

[0119] The third change information refers to the information that records the change of the register from normal to abnormal, including the register identifier, the list of faulty bits after the disturbance, and the newly added abnormal flag.

[0120] S605, the first change information, the second change information and the third change information are mapped to the signal propagation path to form an error distribution result.

[0121] Error distribution result: refers to the complete data structure obtained by associating the three types of information, namely the first change information, the second change information and the third change information, according to the topological order of the signal propagation path. Each path corresponds to a set of change information, which is used for correlation evaluation in integrated circuit diagnosis.

[0122] Mapping method: For example, based on the signal propagation path determined in S2, the change information (first, second, or third change information) of each abnormal register is appended to the corresponding register node in the path; for reduced or added abnormal registers, they are also marked at the corresponding positions in the path. This ultimately forms a path-based error distribution result, facilitating the location of the root cause of the fault.

[0123] This application performs big data analysis on the bit changes of abnormal registers before and after power supply disturbances by executing step S6. By comparing the first bit set with the second bit set, it statistically analyzes the increase, decrease and position change of error bits, and identifies the disappearance or addition of abnormal registers. These changes are classified into first change information, second change information and third change information, and then mapped according to the signal propagation path to generate a structured error distribution result. The application extracts the pattern of each node being affected by the disturbance from the massive data, providing reliable data support for fault diagnosis of integrated circuits.

[0124] S7. Perform a correlation evaluation between the error distribution results and the path evaluation parameters to determine the fault path and root cause of the integrated circuit, and generate a fault diagnosis report based on the fault path and root cause.

[0125] In S7, correlation assessment refers to the comprehensive analysis of error distribution results (reflecting bit changes before and after power supply disturbances) and path evaluation parameters (reflecting the inherent quality of the path) to determine the contribution of each node (abnormal register and target logic gate) to the overall abnormality, thereby locating the root cause of the fault.

[0126] The correlation assessment method is as follows: For example, there is an abnormal register R and its upstream target logic gate G on a signal propagation path. Before the power supply disturbance, R has three error bits. When the voltage is increased by 8%, the state of R is captured again, and it is found that the number of error bits has decreased to one, with only one error bit remaining. At this time, referring to the local evaluation parameters, it can be found that the second timing deviation value of G is negative, and the load deviation value is positive, indicating that G itself has excessive delay and drives an excessively heavy load. The voltage increase speeds up the switching speed of G and improves the output waveform, thereby reducing the error captured by R. Therefore, it is determined that the error of R is caused by the timing or load problem of the upstream G, and R itself is not the root cause of the fault; the root cause of the fault should be upstream. Conversely, if the number of error bits of R does not change after the voltage increase, remaining at three, but the local evaluation parameters show that the first timing deviation value of R is negative, it indicates that R itself has a setup time violation, and its memory cell may have a physical defect. In this case, R should be marked as the root cause of the fault. By comparing the error distribution results with the local evaluation parameters in this way, the abnormal contribution of each node can be calculated, thereby distinguishing whether the root cause of the fault is the register or the logic gate.

[0127] Fault path: refers to the complete path taken from the test input port, along the signal propagation direction, through the nodes marked as fault roots (exception registers or target logic gates), and finally to the terminal exception register. The fault path records the entire process of the test signal propagating from the input to the fault root, and then continuing to propagate to the exception register.

[0128] Root cause of failure: refers to the specific node where the path anomaly originates. If an abnormal register with an anomaly contribution greater than the first threshold is marked as the root cause of failure, it indicates that its own memory unit has a physical defect or timing violation; if a target logic gate with an anomaly impact greater than the second threshold is marked as the root cause of failure, it indicates that its latency exceeds the limit or its drive load is too heavy, which in turn leads to errors in downstream registers.

[0129] Fault Diagnosis Report: This refers to structured information that includes fault path identification, fault root cause name and type, anomaly type description, and a summary of error bit changes before and after power supply disturbance. The report can be output in text format to help engineers locate hardware defects or optimize circuit design.

[0130] In S7, the error distribution results are correlated with the path evaluation parameters to determine the fault path and root cause of the integrated circuit. One possible implementation method is as follows: S701, traverse each exception register and target logic gate on the signal propagation path; S702, based on the error distribution result, determine the bit change information corresponding to the abnormal register, the bit change information including first change information, second change information and third change information; The bit change information is a data structure used to record the state changes of each abnormal register before and after the power supply disturbance, storing the first change information, the second change information, and the third change information.

[0131] S703, compare the bit change information corresponding to the abnormal register with the local evaluation parameters of the path evaluation parameters to obtain the abnormal contribution degree of the abnormal register, and mark the abnormal register with the abnormal contribution degree greater than the preset first threshold as the root cause of the integrated circuit fault. Anomaly Contribution: This is a value between 0 and 1, used to measure the likelihood that the anomaly register itself is the root cause of the fault; the larger the value, the higher the likelihood that the register itself has a physical defect or timing violation.

[0132] First threshold: A pre-set boundary value for determining whether the abnormal register is the root cause of the fault. For example, the first threshold can be set to 0.7. This threshold can be adjusted according to the actual diagnostic accuracy requirements.

[0133] In S703, the method for comparing the bit change information corresponding to the exception register with the local evaluation parameters of the path evaluation parameters is as follows: Based on the error distribution results, the total number of error bits in the first bit set of the abnormal register is counted, and then the total number of error bits in the second bit set is counted. If the number of error bits decreases after the disturbance, it indicates that the power supply disturbance has improved the error of the register; if the number of error bits remains unchanged or increases, it indicates that the improvement effect is not obvious or that degradation has occurred.

[0134] Power supply disturbances primarily alter the driving capability and signal delay of upstream logic gates, with limited direct impact on the register storage cells themselves. Therefore, the greater the reduction in error bits after a disturbance, the more likely the register error is caused by a problem with the upstream logic gate, and the lower the likelihood that the register itself is the root cause of the fault. Conversely, the smaller the reduction in error bits or even the increase after a disturbance, the less sensitive the register error is to power supply disturbances, and the higher the likelihood that the register itself has physical defects or timing violations.

[0135] Simultaneously, the first timing deviation value of the abnormal register is read from the local evaluation parameters. If the first timing deviation value is negative, it indicates that the register itself has timing risks; the larger the absolute value of the negative deviation, the more serious the risk. In this case, the suspicion level of the register as a root cause of the fault should be further increased.

[0136] Based on the above analysis, the rule for determining the anomaly contribution is as follows: First, calculate the degree of change in the number of erroneous bits before and after the disturbance. Subtract the number of erroneous bits after the disturbance from the number of erroneous bits before the disturbance, and then divide by the number of erroneous bits before the disturbance to obtain a change ratio. The closer this ratio is to 1, the lower the anomaly contribution; the closer this ratio is to 0 or a negative number, the higher the anomaly contribution. Then, the negative part of the first time-series deviation value is converted into a risk factor, which, together with the change ratio, adjusts the final contribution. Specifically, when the first time-series deviation value is negative, an increment positively correlated with the absolute value of the negative deviation is added to the change ratio; when the first time-series deviation value is non-negative, this increment is not added. The final value obtained is the anomaly contribution.

[0137] The calculated anomaly contribution is compared with a preset first threshold. If the anomaly contribution is greater than the first threshold, the anomaly register is marked as the root cause of the integrated circuit's fault; otherwise, the anomaly of the anomaly register is considered to be caused by an upstream node (anomaly register or a target logic gate), and the same analysis is performed on the upstream node: if the upstream node is an anomaly register, the analysis in step S703 is repeated; if the upstream node is a target logic gate, the process proceeds to step S704 to calculate its anomaly impact to determine whether it is the root cause of the fault.

[0138] S704, for each target logic gate, based on the signal propagation path, determine the abnormal registers adjacent to the downstream of the target logic gate, and based on the second timing deviation value and load deviation value of the target logic gate in the local evaluation parameters, combined with the abnormal contribution degree of the abnormal registers adjacent to the downstream of the target logic gate, calculate the abnormal influence degree of the target logic gate. Anomaly Impact: A comprehensive indicator that measures the inherent defects of the target logic gate and its contribution to anomalies in downstream registers. The higher the anomaly impact, the more likely the logic gate is to be the root cause of the fault.

[0139] The method for calculating the anomaly impact of the target logic gate is as follows: Based on the signal propagation path, determine the abnormal registers adjacent to the downstream of the target logic gate, and read the second timing deviation value and load deviation value of the target logic gate from the local evaluation parameters; The timing status of the target logic gate is determined based on the second timing deviation value. When the second timing deviation value is negative, it indicates that the target logic gate has a risk of exceeding the delay limit. The larger the absolute value of the negative deviation, the higher the delay risk. When the second timing deviation value is non-negative, it indicates that the target logic gate has no timing abnormalities. The load status of the target logic gate is determined based on the load deviation value. When the load deviation value is positive, it indicates that the driving load of the target logic gate exceeds the design range, and the larger the value, the heavier the driving load. When the load deviation value is negative, it indicates that there is no abnormality in the load of the target logic gate. Simultaneously, the abnormal contribution of the adjacent downstream abnormal registers is analyzed. When the abnormal contribution is less than the first threshold, it indicates that the abnormal register itself is less likely to be the root cause of the fault, and its abnormality is more likely to be caused by the upstream node. At this time, the judgment degree of the target logic gate as the root cause of the fault should be increased. When the abnormal contribution is greater than or equal to the first threshold, it indicates that the abnormal register itself has a high probability of being abnormal. At this time, the judgment degree of the target logic gate as the root cause of the fault should be reduced. Based on the above analysis, the risk level is first determined according to the intervals of the second timing deviation value and the load deviation value within their respective reference ranges and a preset value is assigned. Then, the value corresponding to the risk level is adjusted according to the abnormal contribution of the abnormal register. When the abnormal contribution is low, the corresponding value is increased, and when the abnormal contribution is high, the corresponding value is decreased. Subsequently, the adjusted timing-related value and load-related value are combined with the abnormal contribution of the abnormal register and processed. The abnormal impact of the target logic gate is obtained by sequentially performing inversion processing and superposition processing. The abnormal impact degree is compared with a preset second threshold. When the abnormal impact degree is greater than the second threshold, the target logic gate is marked as the root cause of the integrated circuit failure. Otherwise, the target logic gate is considered not to be the root cause of the failure, and the upstream node is analyzed along the signal propagation path. If the upstream node is an abnormal register, the analysis in step S703 is used. If the upstream node is the target logic gate, the analysis in step S704 is used.

[0140] S705, mark the target logic gate whose abnormal impact is greater than a preset second threshold as the root cause of the integrated circuit failure; Second threshold: A pre-set numerical limit for determining whether a target logic gate is the root cause of a fault. If the threshold is exceeded, the logic gate is marked as the root cause of a fault. For example, the second threshold can be set to 0.6. This threshold can be adjusted according to the actual diagnostic accuracy requirements.

[0141] S706, the signal propagation path containing the fault root cause is determined as the fault path of the integrated circuit.

[0142] Specifically, if at least one node (an exception register or a target logic gate) on a signal propagation path is marked as the root cause of a fault, then that path is marked as a fault path. The starting point of the fault path is the test input port, the ending point is the terminal exception register, and the root cause node is located at a certain position in the path.

[0143] In S7, a fault diagnosis report is generated based on the fault path and fault root cause. One feasible approach is to traverse each signal propagation path marked as a fault path, identify the fault root cause nodes on the path, including abnormal registers and target logic gates; extract the abnormal information of each fault root cause node, including bit change information of the abnormal register and timing deviation and load deviation values ​​of the target logic gate; combine the bit change situation before and after the power supply disturbance to determine the contribution of each fault root cause node to the downstream abnormal register; organize the start point, end point, fault root cause node name, node type, abnormal type, and bit change summary of the fault path according to the path order; and form a structured fault diagnosis report from the organized information, output in text or tabular form, for engineers to locate hardware defects or optimize circuit design.

[0144] This application achieves comprehensive big data analysis of anomalies at each node along the signal propagation path of an integrated circuit by executing step S7. It correlates the error distribution results with path evaluation parameters, quantifies the bit changes, timing deviations, and load deviations of the abnormal register and the target logic gate, and obtains the anomaly contribution and impact of each node. This allows for the precise location of the fault root cause and its path along the signal propagation path. The results are then structured into a fault diagnosis report, extracting anomaly patterns from a large amount of collected data, and providing engineers with quantifiable and traceable fault analysis basis.

[0145] Example 2: As Figure 2 As shown, this application provides a multi-parameter collaborative diagnostic system for integrated circuits and electronic computers. The functions of the system modules correspond to the method steps of Embodiment 1 above, and will not be elaborated further here. The system modules are as follows: a state processing module, used to capture the first operating state of the target register when an abnormal operation of the integrated circuit is detected, and to perform a bit-level comparison between the first operating state and a preset state to determine the abnormal register in the target register and the first bit set corresponding to the abnormal register; a path tracing module, used to perform reverse signal propagation constraint analysis on the abnormal register according to the topological connection relationship of the target register to determine the signal propagation path of the test command; and a path evaluation module, used to extract the timing margin parameter and load strength parameter of the signal propagation path according to the preset timing constraint information of the signal propagation path, and to evaluate the timing margin parameter and load strength parameter of the signal propagation path according to the preset timing constraint information of the signal propagation path. The margin parameter and load strength parameter are used to evaluate and analyze the signal propagation path to obtain path evaluation parameters; the power supply regulation generation module is used to generate a power supply disturbance command based on the path evaluation parameters of the signal propagation path and a preset rule relation library; the state recapture module is used to recapture the second operating state of the target register after the variable power supply is controlled to execute the power supply disturbance command, and determine the second bit set corresponding to the abnormal register based on the second operating state; the deviation analysis module is used to perform error bit deviation analysis on the first bit set and the second bit set to obtain error distribution results; the correlation diagnosis module is used to perform correlation evaluation on the error distribution results and the path evaluation parameters to determine the fault path and fault root cause of the integrated circuit, and generate a fault diagnosis report based on the fault path and fault root cause.

[0146] The foregoing has shown and described the basic principles, main features, and advantages of this application. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this application. Various changes and modifications can be made to this application without departing from the spirit and scope thereof, and all such changes and modifications fall within the scope of this application as claimed. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A multi-parameter collaborative diagnostic method for integrated circuits and electronic computers, characterized in that, The electronic computer executes test commands, the method comprising: When an abnormal operation of an integrated circuit is detected, the first operating state of the target register is captured, and the first operating state is compared with a preset state at the bit level to determine the abnormal register in the target register and the first set of bits corresponding to the abnormal register. Based on the topological connection relationship of the target register, reverse signal propagation constraint analysis is performed on the abnormal register to determine the signal propagation path of the test command; Based on the preset timing constraint information of the signal propagation path, the timing margin parameter and load strength parameter of the signal propagation path are extracted, and the signal propagation path is evaluated and analyzed based on the timing margin parameter and load strength parameter to obtain the path evaluation parameter; Based on the path evaluation parameters of the signal propagation path, a power supply disturbance command is generated in combination with a preset rule relation library; After the variable power supply executes the power supply disturbance command, the second operating state of the target register is recaptured, and the second bit set corresponding to the abnormal register is determined based on the second operating state. Perform error bit deviation analysis on the first bit set and the second bit set to obtain the error distribution results; The error distribution results are correlated with the path evaluation parameters to determine the fault path and root cause of the integrated circuit, and a fault diagnosis report is generated based on the fault path and root cause.

2. The method according to claim 1, characterized in that, The first operating state includes the bits of the target register and the first bit value corresponding to the bit. The preset state includes the bits of the target register and the standard bit value corresponding to the bit. The step of performing a bit-level comparison between the first operating state and the preset state to determine the abnormal register in the target register and the set of first bits corresponding to the abnormal register includes: For each target register, a bit-by-bit matching operation is performed between the first bit value of each bit in the first running state and the standard bit value of the corresponding bit in the preset state to obtain the matching result of each bit. The matching result includes bit value matching and bit value mismatch. If the matching result is that the bit values ​​are consistent, the bit corresponding to the matching result is recorded as a normal bit. If the matching result is that the bit values ​​are inconsistent, the bit corresponding to the matching result is marked as an error bit, and the target register corresponding to the error bit is marked as an abnormal register. The normal bits and error bits corresponding to the exception register are encapsulated and stored to obtain the first bit set.

3. The method according to claim 2, characterized in that, The topological connections of the target register include the connections between the target register and the input terminals of the logic gates, and the connections between the output terminals of the logic gates and the target register. The target register includes an exception register. Based on the topological connections of the target register, the reverse signal propagation constraint analysis is performed on the exception register to determine the signal propagation path corresponding to the exception register, including: Retrieve the exception register and its corresponding first bit set, the first bit set including the normal bits and error bits of the exception register; Based on the connection relationship between the logic gate output and the target register, determine the target logic gate output and the logic type of the target logic gate that are directly connected to the exception register. Based on the normal bits and error bits of the exception register, and combined with the bit values ​​corresponding to the normal bits and error bits respectively, the combination of bit values ​​of the exception register is determined. The bit value combination of the exception register is input in reverse to the output of the target logic gate, and the inverse operation is performed according to the logic type of the target logic gate to obtain at least one valid bit value combination corresponding to the input of the target logic gate. Based on the connection relationship between the target register and the input terminal of the logic gate, the effective bit value combination of the input terminal of the target logic gate is mapped to the corresponding output terminal node of the upper-level register to form a branch node set. The branch node set is iteratively backtracked to determine the signal propagation path of the test command. The signal propagation path includes at least the exception register and the target logic gate.

4. The method according to claim 3, characterized in that, The preset timing constraint information includes preset clock constraints and preset gate delay constraints. Based on the preset timing constraint information of the signal propagation path, the timing margin parameters and load strength parameters of the signal propagation path are extracted, including: Retrieve the exception register and target logic gate in the signal propagation path; When the computer executes the test command, the arrival time of the test signal of the abnormal register, as well as the output response delay and output drive current of the target logic gate are collected. Based on the arrival time of the test signal of the abnormal register and the preset clock constraint, the timing margin parameter of the abnormal register is calculated, and based on the output response delay of the target logic gate and the preset gate delay constraint, the timing margin parameter of the target logic gate is calculated. For any of the signal propagation paths, determine the successor connection node of the target logic gate in the signal propagation path, wherein the successor connection node includes the next target logic gate or an exception register; Obtain the current capacitance of the successor node, and analyze the output drive current of the target logic gate with the current capacitance of the successor node to obtain the load strength parameter of the target logic gate; According to the topological order of the signal propagation path, the timing margin parameters of each exception register and the timing margin parameters of each target logic gate are encapsulated to obtain the timing margin parameters of the signal propagation path, and the load strength parameters of each target logic gate are encapsulated to obtain the load strength parameters of the signal propagation path.

5. The method according to claim 4, characterized in that, The evaluation analysis of the signal propagation path based on the timing margin parameter and load strength parameter is performed to obtain path evaluation parameters, including: The timing margin parameters and load strength parameters of the signal propagation path are retrieved, and the timing margin reference value corresponding to the preset clock constraint and the gate delay reference value corresponding to the preset gate delay constraint are obtained according to the preset timing constraint information. The timing margin parameters of each abnormal register in the signal propagation path are respectively calculated with the timing margin reference value to obtain the first timing deviation value of each abnormal register. The timing margin parameter of each target logic gate in the signal propagation path is calculated by performing a difference calculation with the gate delay reference value to obtain the second timing deviation value of each target logic gate; Retrieve the load strength parameters of each target logic gate in the signal propagation path, and obtain the standard load threshold corresponding to each target logic gate; The load strength parameter of each target logic gate is compared with the corresponding standard load threshold to calculate the difference and obtain the load deviation value of each target logic gate. According to the topological order of the signal propagation path, the first timing deviation value of each abnormal register, the second timing deviation value of each target logic gate, and the load deviation value are structurally encapsulated to form the local evaluation parameters of the signal propagation path. The local evaluation parameters are cumulatively calculated according to the signal propagation direction to obtain the overall evaluation parameters of the signal propagation path; The local evaluation parameters and the overall evaluation parameters are structurally encapsulated to obtain the path evaluation parameters of the signal propagation path.

6. The method according to claim 5, characterized in that, The path evaluation parameters include local evaluation parameters and overall evaluation parameters. The path evaluation parameters based on the signal propagation path, combined with a preset rule relational library, generate a power supply disturbance command, including: The local evaluation parameters are subjected to sign determination and amplitude segmentation to obtain local evaluation category identifiers; Based on the local evaluation category identifier, the corresponding power supply adjustment type is matched in the preset rule relationship library. The power supply adjustment type includes voltage boost adjustment type, voltage suppression adjustment type, and drive capability allocation adjustment type. Based on the overall evaluation parameters, the corresponding adjustment range is matched in the preset rule relationship library, and the power supply adjustment type is combined with the adjustment range to form a power supply disturbance command.

7. The method according to claim 1, characterized in that, After the control variable power supply executes the power supply disturbance command, it recaptures the second operating state of the target register and determines the second bit set corresponding to the abnormal register based on the second operating state, including: After the variable power supply executes the power supply disturbance command, the second operating state of the target register is captured. The second operating state includes the bit bits of the target register and the second bit value corresponding to the bit bits. Based on the preset state, a bit-level comparison is performed on the second operating state to determine the abnormal register after the power supply disturbance instruction is executed, as well as the normal bits and error bits of the abnormal register, which are used as the second bit set.

8. The method according to claim 7, characterized in that, The step of performing error bit deviation analysis on the first bit set and the second bit set to obtain error distribution results includes: Based on the first set of bits, traverse each exception register and determine whether the exception register exists in the second set of bits. If the abnormal register exists in the second bit set, then the number and position of the erroneous bits and normal bits are analyzed for changes, and the result of the change analysis is used as the first change information of the abnormal register. If the exception register does not exist in the second bit set, then the exception register is marked as a reduced exception register and the second change information of the reduced exception register is recorded; If an abnormal register is detected that exists in the second bit set but not in the first bit set, the abnormal register is marked as a newly added abnormal register and the third change information of the newly added abnormal register is recorded. The first change information, the second change information, and the third change information are mapped to the signal propagation path to form an error distribution result.

9. The method according to claim 8, characterized in that, The path evaluation parameters include local evaluation parameters. The step of performing a correlation evaluation between the error distribution results and the path evaluation parameters to determine the fault path and root cause of the integrated circuit includes: Iterate through each abnormal register and target logic gate along the signal propagation path; Based on the error distribution results, determine the bit change information corresponding to the abnormal register. The bit change information includes first change information, second change information, and third change information. The bit change information corresponding to the abnormal register is compared with the local evaluation parameters of the path evaluation parameters to obtain the abnormal contribution degree of the abnormal register, and the abnormal register with the abnormal contribution degree greater than the preset first threshold is marked as the root cause of the integrated circuit fault. For each target logic gate, based on the signal propagation path, the abnormal registers adjacent to the downstream of the target logic gate are determined, and based on the second timing deviation value and load deviation value of the target logic gate in the local evaluation parameters, combined with the abnormal contribution degree of the abnormal registers adjacent to the downstream of the target logic gate, the abnormal influence degree of the target logic gate is calculated. The target logic gate whose abnormal impact is greater than a preset second threshold is marked as the root cause of the integrated circuit failure; The signal propagation path containing the root cause of the fault is identified as the fault path of the integrated circuit.

10. A multi-parameter collaborative diagnostic system for integrated circuits and electronic computers, characterized in that, The system includes: The status processing module is used to capture the first operating state of the target register when an abnormal operation of the integrated circuit is detected, and to perform a bit-level comparison between the first operating state and a preset state to determine the abnormal register in the target register and the first set of bits corresponding to the abnormal register. The path tracing module is used to perform reverse signal propagation constraint analysis on the abnormal register based on the topological connection relationship of the target register, and determine the signal propagation path of the test command; The path evaluation module is used to extract the timing margin parameters and load strength parameters of the signal propagation path based on the preset timing constraint information of the signal propagation path, and to perform evaluation analysis on the signal propagation path based on the timing margin parameters and load strength parameters to obtain path evaluation parameters. The power supply regulation generation module is used to generate power supply disturbance commands based on the path evaluation parameters of the signal propagation path and in combination with a preset rule relation library. The state recapture module is used to recapture the second operating state of the target register after the control variable power supply executes the power supply disturbance command, and determine the second bit set corresponding to the abnormal register based on the second operating state; The deviation analysis module is used to perform error bit deviation analysis on the first bit set and the second bit set to obtain the error distribution results; The correlation diagnosis module is used to perform correlation evaluation between the error distribution results and the path evaluation parameters to determine the fault path and root cause of the integrated circuit, and generate a fault diagnosis report based on the fault path and root cause.

Images