Data error correction methods, apparatus, computer equipment, readable storage media and program products
By performing target scan-granular data reading and error correction code verification after DRAM refresh operations, errors in the memory are corrected in a timely manner, solving the problem of data error accumulation in DRAM and improving data accuracy and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING QINGYUN TECHNOLOGY CO LTD
- Filing Date
- 2026-07-01
- Publication Date
- 2026-07-31
AI Technical Summary
In the prior art, dynamic random access memory (DRAM) is prone to charge interference after frequent read and write operations, which can lead to data errors. Furthermore, the error correction mechanism that relies on data access cannot correct errors in a timely manner, causing correctable errors to accumulate into uncorrectable errors.
After the DRAM refresh operation, the memory data is read according to the target scan granularity and error correction code verification is performed to correct correctable errors in a timely manner. The corrected data is then written back to the memory. By distributing the data processing process across multiple refresh cycles, the impact on normal read and write operations is reduced.
It improves the accuracy and reliability of DRAM data, prevents correctable errors from accumulating into uncorrectable errors, and reduces the impact on normal read and write operations without significantly increasing memory access load.
Smart Images
Figure CN122489337A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a data error correction method, apparatus, computer device, computer-readable storage medium, and computer program product. Background Technology
[0002] With the continuous development of computer systems and storage technologies, Dynamic Random Access Memory (DRAM) has been widely used in various computing devices due to its high density and high access speed. In actual operation, DRAM needs to be accessed frequently for reading and writing. However, multiple read and write operations may cause charge interference, which can lead to data flipping in the memory cells, resulting in data errors or even data loss.
[0003] To address the aforementioned issues, related technologies typically employ error correction codes (ECC) to protect data. When a correctable error (CE) occurs, the error can be detected during data reading, and the correct data can be recovered through error correction operations. Subsequently, the corrected data is written back to memory, thereby ensuring data accuracy.
[0004] However, this method typically relies on data access to trigger error correction, which cannot guarantee timely repair of all storage cells that experience CE errors. In the presence of CE errors, if the relevant storage cells are continuously disturbed (e.g., by frequent access attacks), the errors may accumulate further, evolving into uncorrectable errors (UCEs), ultimately making data recovery impossible. Summary of the Invention
[0005] Therefore, it is necessary to provide a data error correction method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve data accuracy in response to the above-mentioned technical problems.
[0006] Firstly, this application provides a data error correction method, including:
[0007] After the refresh operation in the current data processing cycle is completed, the data in the target memory is read according to the target scan granularity to obtain the current data to be verified, and the error correction code is used to verify the current data to be verified to obtain the verification result.
[0008] When the obtained verification result indicates that the current data to be verified has a correctable error, the current data to be verified is corrected to obtain the target data.
[0009] Write the target data back to the target memory.
[0010] In one embodiment, the step of reading data from the target memory according to the target scanning granularity to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result, includes:
[0011] The target row address and the corresponding starting column address are determined based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle;
[0012] The target column address range is determined based on the target scan granularity, the target row address, and the starting column address;
[0013] The data corresponding to each column address within the target column address range is read sequentially to obtain the current data to be verified, and the current data to be verified is verified by error correction code to obtain the verification result.
[0014] In one embodiment, the target scanning granularity is determined based on system performance requirements or storage access efficiency.
[0015] In one embodiment, the step of performing error correction code verification on the current data to be verified to obtain a verification result includes:
[0016] The current data to be verified is verified based on the error correction code to obtain the number of error bits;
[0017] When the number of erroneous bits is less than or equal to the error correction threshold of the error correction code, it is determined that the current data to be verified contains a correctable error.
[0018] In one embodiment, the step of performing error correction code verification on the current data to be verified to obtain a verification result further includes:
[0019] When the number of erroneous bits is greater than the error correction threshold, it is determined that the current data to be verified contains an uncorrectable error.
[0020] In one embodiment, the method further includes:
[0021] After the refresh operation in the current data processing cycle is completed, the scan operation in the next data processing cycle is executed; the refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time; the refresh cycle is the time period required to execute the refresh operation; the data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
[0022] Secondly, this application also provides a data error correction device, the device comprising:
[0023] The scanning module is used to read the data in the target memory according to the target scanning granularity after the refresh operation in the current data processing cycle is completed, to obtain the current data to be verified, and to perform error correction code verification on the current data to be verified to obtain the verification result.
[0024] The error correction module is used to correct the current data to be verified when the obtained verification result indicates that there is a correctable error in the current data to be verified, so as to obtain the target data.
[0025] The write-back module is used to write the target data back to the target memory.
[0026] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.
[0027] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.
[0028] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the methods in any of the above embodiments.
[0029] The aforementioned data error correction method, apparatus, computer equipment, computer-readable storage medium, and computer program product, for the data error correction cycle in the data processing cycle, process the data in the target memory according to the target scan granularity to obtain the current data to be verified, and perform error correction code verification on the current data to be verified to obtain the verification result; when the verification result indicates that the current data to be verified has correctable errors, the current data to be verified is corrected to obtain the target data, and the target data is written back to the target memory. After the refresh cycle ends, data is read from the target memory, which can promptly perform error correction code verification on the data in the target memory and promptly write back the corrected data, preventing correctable errors from accumulating further and evolving into uncorrectable errors, thereby improving the accuracy and reliability of the data. Furthermore, since the data error correction cycle is executed after the refresh operation corresponding to the refresh cycle, and by processing the data in the target memory according to the target scan granularity, the data processing process can be distributed across multiple refresh cycles, and the amount of data processed each time can be controlled, thereby reducing the impact on normal read and write operations without significantly increasing the memory access load, thus improving the accuracy and reliability of the data. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a flowchart illustrating a data error correction method in one embodiment;
[0032] Figure 2 This is a schematic diagram illustrating the execution of multiple data processing cycles in one embodiment;
[0033] Figure 3 This is a structural block diagram of a data error correction device in another embodiment;
[0034] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0036] In one embodiment, such as Figure 1 As shown, a data error correction method is provided. This embodiment illustrates the method by applying it to a terminal. It is understood that this method can also be applied to a storage controller. In this embodiment, the method includes the following steps:
[0037] Step 102: After the refresh operation in the current data processing cycle is completed, the data in the target memory is read according to the target scan granularity to obtain the current data to be verified, and the error correction code is used to verify the current data to be verified to obtain the verification result.
[0038] The data processing cycle refers to the cycle of refreshing and processing the data in the target memory, which includes the refresh cycle and the data error correction cycle. The refresh cycle is used to refresh the data in the target memory to maintain data validity, and the data error correction cycle is used to detect and correct errors in the data in the target memory. The target memory can be dynamic random access memory (DRAM) or other volatile or non-volatile memory that supports error correction code verification.
[0039] Optionally, in this embodiment, multiple data processing cycles are included, each of which includes a refresh cycle and a data correction cycle, and the data correction cycle is executed after the corresponding refresh cycle is completed.
[0040] Optionally, in other embodiments, the data error correction cycle is not executed after every refresh cycle, but is executed at a preset interval, such as once every several refresh cycles, thereby reducing the occupation of memory bandwidth resources while ensuring data reliability.
[0041] Furthermore, to improve data accuracy and reliability, error correction codes are verified on the data in the target memory during the data error correction cycle. This proactively detects and corrects erroneous data in the storage unit without relying on external access triggers, thereby preventing correctable errors (CE) from accumulating and evolving into uncorrectable errors (UCE). Therefore, for the data error correction cycle in the current data processing cycle, the data in the target memory is processed according to the target scan granularity to obtain the current data to be verified. The target scan granularity refers to the amount of data processed each time, which can be determined based on the data bit width of the target memory interface. For example, when the data bit width of the target memory interface is 256 bits, the target scan granularity can be 256 bits, or it can be an integer multiple thereof, such as 512 bits, 1024 bits, etc.
[0042] After obtaining the current data to be verified, error correction code verification is performed on the current data to obtain the verification result. Among them, error correction code verification refers to detecting errors in the current data to be verified based on preset error correction codes, and correcting the erroneous data when the error correction conditions are met.
[0043] Step 104: When the verification result indicates that there are correctable errors in the current data to be verified, the current data to be verified is corrected to obtain the target data.
[0044] Among them, correctable errors refer to error types in the current data to be verified where the number of erroneous bits does not exceed the error correction capability range of the preset error correction code. The error correction code can locate the erroneous data and restore it to correct data when the number of erroneous bits is within its error correction capability range. For example, when using the Single Error Correction-Double Error Detection (SEC-DED) error correction code, single-bit errors can be corrected, while double-bit errors can be detected but not corrected.
[0045] Optionally, when it is determined that there are correctable errors in the current data to be verified, the error bits in the current data to be verified can be located based on the error correction code, and the error bits can be flipped or replaced to restore the correct data and obtain the target data.
[0046] Step 106: Write the target data back to the target memory.
[0047] Specifically, after correcting the current data to be verified, the target data is obtained, and the target data is written back to the original storage location corresponding to the current data to be verified, so as to update the erroneous data in the target memory.
[0048] In the above embodiments, for the data error correction cycle within the data processing cycle, the data in the target memory is processed according to the target scan granularity to obtain the current data to be verified, and the current data to be verified is checked using error correction codes to obtain the verification result. When the verification result indicates that the current data to be verified contains correctable errors, the current data to be verified is corrected to obtain the target data, and the target data is written back to the target memory. After the refresh cycle ends, data is read from the target memory, which allows for timely error correction code verification of the data in the target memory and timely writing back of the corrected data, preventing correctable errors from accumulating further and evolving into uncorrectable errors, thereby improving the accuracy and reliability of the data. Furthermore, since the data error correction cycle is executed after the refresh operation corresponding to the refresh cycle, and the data in the target memory is processed according to the target scan granularity, the data processing process can be distributed across multiple refresh cycles, and the amount of data processed each time can be controlled. This reduces the impact on normal read and write operations without significantly increasing the memory access load, thereby improving the accuracy and reliability of the data.
[0049] Furthermore, in one embodiment, the above-mentioned reading of data in the target memory according to the target scan granularity to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result, includes: determining the target row address and the corresponding starting column address based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle; determining the target column address range based on the target scan granularity, the target row address, and the starting column address; sequentially reading the data corresponding to each column address within the target column address range to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result.
[0050] Since the data error correction process includes multiple data processing cycles, in the data error correction cycle of the current data processing cycle, the data in the target memory continues to be processed from the current scan position. The current scan position is the termination position where the data was written back in the previous data error correction cycle, thus ensuring the continuity of data processing, which is the physical location of the last target data written back to the target memory in the previous data processing cycle.
[0051] During data processing, the target row address and the corresponding starting column address are determined based on the current scan position. For example, if each row in the target memory contains 64 column addresses, and each column address corresponds to 256 bits of data; and the current scan position is at the 10th column address of the 100th row, then the target row address is determined to be the 100th row, and the starting column address is determined to be the 10th column address.
[0052] Then, by combining the target scan granularity, target row address, and starting column address, the target column address range can be determined, which is the column address range corresponding to this data processing. Continuing with the example above, if the target scan granularity is 512 bits, it corresponds to reading data from 2 column addresses. Therefore, the target column address range can be determined to be: column 10 to column 11.
[0053] Finally, the data corresponding to each column address within the target column address range is obtained sequentially to get the current data to be verified, and the error correction code is used to verify the current data to be verified to obtain the verification result.
[0054] In the above embodiments, by segmenting the data in the target memory according to the target scan granularity, the amount of data processed each time can be controlled, allowing the data processing process to be distributed across multiple data processing cycles. This reduces the impact on normal read and write operations without significantly increasing the memory access load. Furthermore, by determining the target row and column address ranges based on the current scan position, continuous processing of data in the target memory is achieved, avoiding repeated processing of completed data or omission of unprocessed data, thereby ensuring the continuity of data processing and improving data accuracy.
[0055] In one embodiment, the target scan granularity is determined based on system performance requirements or storage access efficiency.
[0056] Optionally, the target scan granularity can be set based on system performance requirements, memory bandwidth resources, and data processing cycle configuration. For example, when the system load is high or the impact of read / write operations is sensitive, the target scan granularity can be set to a smaller value, such as 256 bits, to reduce the system resource consumption of a single data processing operation; while when the system load is low or the processing efficiency requirement is high, the target scan granularity can be set to a larger value, such as 4*256 bits, to improve data processing efficiency.
[0057] Optionally, the target scan granularity can also be adjusted according to the row and column organization structure of the target memory so that each data processing falls within a continuous column address range as much as possible, thereby reducing the overhead caused by address switching.
[0058] Optionally, in order to match the data processing process with the data transmission method of the target memory, avoid the additional overhead caused by crossing the transmission boundary, and improve data processing efficiency, the target scanning granularity in this embodiment can also be determined according to system performance requirements or storage access efficiency.
[0059] In one embodiment, the above-mentioned verification of the current data to be verified by error correction code to obtain the verification result includes: verifying the current data to be verified based on the error correction code to obtain the number of error bits; when the number of error bits is less than or equal to the error correction threshold of the error correction code, it is determined that the current data to be verified has a correctable error.
[0060] Optionally, a check synthesis is generated based on the error correction code corresponding to the current data to be checked, and the presence of an error and the corresponding number of erroneous bits in the current data to be checked are determined based on the check synthesis. The error correction code may include at least one of the following: Single Error Correction Double Error Detection (SEC-DED) error correction code, multi-bit error correction code (such as BCH code, Reed-Solomon code, etc.).
[0061] The error correction threshold refers to the maximum number of erroneous bits that the error correction code can correctly correct under the current configuration. Its value is determined by the encoding method and error correction capability of the error correction code. For example, when using the SEC-DED error correction code, the error correction threshold is 1.
[0062] For example, when the number of erroneous bits is less than or equal to the error correction threshold of the error correction code, it means that the error in the current data to be verified is within the error correction capability of the error correction code, and can be located and recovered by the error correction code, thereby determining that there is a correctable error in the current data to be verified.
[0063] Furthermore, in another embodiment, the above-mentioned verification result obtained by performing error correction code verification on the current data to be verified also includes: when the number of error bits is greater than the error correction threshold, determining that the current data to be verified has an uncorrectable error.
[0064] Specifically, when the number of erroneous bits exceeds the error correction threshold of the error correction code, it indicates that the error in the current data to be verified exceeds the error correction capability of the error correction code and cannot be correctly recovered by the error correction code, thus determining that the current data to be verified contains an uncorrectable error.
[0065] In the above embodiments, the error correction code is used to verify the data to be verified to obtain the number of error bits. Based on the number of error bits and the error correction threshold, it can be accurately determined whether there are correctable errors in the current data to be verified.
[0066] In one embodiment, the method further includes: after the refresh operation in the current data processing cycle is completed, performing the scan operation in the next data processing cycle; the refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time; the refresh cycle is the time period required to perform the refresh operation; the data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
[0067] In actual execution, there are multiple data processing cycles, each including a data error correction cycle and a refresh cycle. Since the data processing in the error correction cycle does not rely on continuous time slices but proceeds incrementally based on the current processing position, after completing the refresh operation in the previous data processing cycle, the refresh operation for the next data processing cycle is performed on the target memory from the current refresh position. In other words, the refresh cycle in the next data processing cycle partially overlaps with the data error correction cycle in the current data processing cycle; that is, the data error correction cycle in the current data processing cycle and the flush operation in the next data processing cycle can be executed in parallel.
[0068] For example, in combination Figure 2 , Figure 2 This is a schematic diagram illustrating the execution of multiple data processing cycles in one embodiment. After the refresh operation is completed in the first data processing cycle, the corresponding data error correction operation begins, which is the process of reading data for verification and writing the corrected data back to the target memory as described in the above embodiment. Simultaneously with the scan operation in the first data processing cycle, the refresh operation in the second data processing cycle begins execution, until all data processing cycles are completed.
[0069] In the above embodiments, by overlapping the data error correction cycle and the refresh cycle in time, the data processing can be distributed across multiple refresh cycles, thereby reducing the impact on normal read and write operations while continuously repairing erroneous data and improving the accuracy and reliability of the data.
[0070] In one exemplary embodiment, by calculating the execution time of the data processing process, it can be demonstrated that, when using a segmented processing method, data processing of the entire target memory space can be completed within a preset time.
[0071] For example, assume the current refresh operation takes 32ms, the register refresh cycle is configured to be 6h, and the register target scan granularity is configured to process two 256-bit data blocks at a time. Since a complete processing of the entire DRAM space requires processing 16384 word lines (WL), and each word line corresponds to 64 256-bit data blocks, the total number of data blocks required to process the entire DRAM space is 16384 × 64 256-bit data blocks. Because only two 256-bit data blocks are processed at a time, completing one full-space processing operation requires (16384 × 64) / 2 = 524288 processing operations.
[0072] Since each refresh operation takes 32ms, and a processing operation is performed after each refresh, the total time required to complete the above 524288 processing operations is 524288 × 32ms = 4.66h. Therefore, with a refresh cycle configured at 6h, the above processing method can complete the data processing of the entire DRAM space within the preset cycle, meeting the system configuration requirements.
[0073] For example, assume the current refresh operation takes 32ms, the register refresh cycle is configured to be 12h, and the register target scan granularity is configured to process one 256-bit data block at a time. Since a complete processing of the entire DRAM space requires processing 16384 word lines (WL), and each word line corresponds to 64 256-bit data blocks, the total number of data blocks required to process the entire DRAM space is 16384 × 64 256-bit data blocks. Because only one 256-bit data block is processed at a time, completing one full-space processing operation requires (16384 × 64) / 1 = 1048576 processing operations.
[0074] Since each refresh operation takes 32ms, and a processing operation is performed after each refresh, the total time required to complete the above 1,048,576 processing operations is approximately 1,048,576 × 32ms ≈ 9.32 hours. Therefore, with a refresh cycle configured at 12 hours, the above processing method can complete the data processing of the entire DRAM space within the preset cycle, meeting the system configuration requirements.
[0075] In another embodiment, the register refresh cycle can be configured to 24 hours, and the target scan granularity of the register can be configured to process 4 or 8 256-bit data segments at a time. When processing 4 256-bit data segments at a time, completing one full-space processing requires (16384 × 64) / 4 = 262144 executions, or 262144 × 32 ms ≈ 2.33 hours. When processing 8 256-bit data segments at a time, completing one full-space processing requires (16384 × 64) / 8 = 131072 executions, or 131072 × 32 ms ≈ 1.17 hours. Therefore, with a refresh cycle configured to 24 hours, the above processing methods can complete the data processing of the entire DRAM space within the preset cycle, meeting the system configuration requirements.
[0076] In other embodiments, the time required to complete one full-space data processing operation can be determined based on the time of a refresh operation, the storage space size of the target memory, and the amount of data processed each time. Specifically, when the time of a refresh operation increases, the amount of data processed each time can be increased, or the target period configured in the register can be adjusted so that the time required to complete one full-space data processing operation does not exceed the target period. For example, the target period ≥ refresh operation time × total number of data blocks required to process the entire DRAM space / number of data blocks processed each time.
[0077] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0078] Based on the same inventive concept, this application also provides a data error correction device for implementing the data error correction method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data error correction device embodiments provided below can be found in the limitations of the data error correction method described above, and will not be repeated here.
[0079] In one exemplary embodiment, such as Figure 3As shown, a data error correction device is provided, including: a scanning module 100, an error correction module 200, and a write-back module 300, wherein:
[0080] The scanning module is used to read the data in the target memory according to the target scanning granularity after the refresh operation in the current data processing cycle is completed, to obtain the current data to be verified, and to perform error correction code verification on the current data to be verified to obtain the verification result.
[0081] The error correction module is used to correct the current data to be verified when the verification result indicates that there are correctable errors in the current data to be verified, so as to obtain the target data.
[0082] The write-back module is used to write the target data back to the target memory.
[0083] In one embodiment, the scanning module includes:
[0084] The positioning unit is used to determine the target row address and the corresponding starting column address based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle.
[0085] The range determination unit is used to determine the target column address range based on the target scan granularity, the target row address, and the starting column address.
[0086] The reading unit is used to sequentially read the data corresponding to each column address within the target column address range to obtain the current data to be verified, and to perform error correction code verification on the current data to be verified to obtain the verification result.
[0087] In one embodiment, the target scanning granularity in the scanning module is determined based on system performance requirements or storage access efficiency.
[0088] In one embodiment, the error correction module includes:
[0089] The verification unit is used to verify the current data to be verified based on the error correction code and obtain the number of erroneous bits.
[0090] The first judgment unit is used to determine that there is a correctable error in the current data to be verified when the number of erroneous bits is less than or equal to the error correction threshold of the error correction code.
[0091] In one embodiment, the above-mentioned error correction module further includes:
[0092] The second judgment unit is used to determine that there is an uncorrectable error in the current data to be verified when the number of erroneous bits is greater than the error correction threshold.
[0093] In one embodiment, the above-mentioned apparatus further includes:
[0094] The parallel execution module is used to execute the scan operation in the next data processing cycle after the refresh operation in the current data processing cycle is completed. The refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time. The refresh cycle is the time period required to perform the refresh operation. The data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
[0095] Each module in the aforementioned data error correction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.
[0096] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 4 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data to be verified. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When executed by the processor, the computer program implements a data error correction method.
[0097] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0098] In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: after completing the refresh operation in the current data processing cycle, reading data in the target memory according to the target scan granularity to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain a verification result; when the verification result indicates that the current data to be verified has a correctable error, correcting the current data to be verified to obtain the target data.
[0099] In one embodiment, when the processor executes the computer program, it further performs the following steps: determining the target row address and the corresponding starting column address based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle; determining the target column address range based on the target scan granularity, the target row address, and the starting column address; sequentially reading the data corresponding to each column address within the target column address range to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result.
[0100] In one embodiment, the target scan granularity used by the processor when executing a computer program is determined based on system performance requirements or memory access efficiency.
[0101] In one embodiment, when the processor executes the computer program, it further performs the following steps: verifying the current data to be verified based on the error correction code to obtain the number of error bits; when the number of error bits is less than or equal to the error correction threshold of the error correction code, it is determined that the current data to be verified has a correctable error.
[0102] In one embodiment, when the processor executes the computer program, it further performs the following steps: when the number of error bits is greater than the error correction threshold, it determines that the current data to be verified has an uncorrectable error.
[0103] In one embodiment, when the processor executes the computer program, it further performs the following steps: after performing a refresh operation on the target memory in the current data processing cycle, performing a refresh operation on the target memory from the current refresh position in the next data processing cycle.
[0104] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: after completing the refresh operation in the current data processing cycle, it performs the scan operation in the next data processing cycle; the refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time; the refresh cycle is the time period required to perform the refresh operation; the data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
[0105] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: determining the target row address and the corresponding starting column address based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle; determining the target column address range based on the target scan granularity, the target row address, and the starting column address; sequentially reading the data corresponding to each column address within the target column address range to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result.
[0106] In one embodiment, the target scan granularity used when the computer program is executed by the processor is determined based on system performance requirements or storage access efficiency.
[0107] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: verifying the current data to be verified based on the error correction code to obtain the number of error bits; when the number of error bits is less than or equal to the error correction threshold of the error correction code, it is determined that the current data to be verified has a correctable error.
[0108] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: when the number of error bits is greater than the error correction threshold, it is determined that the current data to be verified contains an uncorrectable error.
[0109] In one embodiment, when the computer program is executed by the processor, it further implements the following steps: after the refresh operation in the current data processing cycle is completed, the scan operation in the next data processing cycle is executed; the refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time; the refresh cycle is the time period required to perform the refresh operation; the data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
[0110] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps: determining the target row address and the corresponding starting column address based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle; determining the target column address range based on the target scan granularity, the target row address, and the starting column address; sequentially reading the data corresponding to each column address within the target column address range to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result.
[0111] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: determining the target row address and the corresponding starting column address based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle; determining the target column address range based on the target scan granularity, the target row address, and the starting column address; sequentially reading the data corresponding to each column address within the target column address range to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result.
[0112] In one embodiment, the target scan granularity used when the computer program is executed by the processor is determined based on system performance requirements or storage access efficiency.
[0113] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: verifying the current data to be verified based on the error correction code to obtain the number of error bits; when the number of error bits is less than or equal to the error correction threshold of the error correction code, it is determined that the current data to be verified has a correctable error.
[0114] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: when the number of error bits is greater than the error correction threshold, it is determined that the current data to be verified contains an uncorrectable error.
[0115] In one embodiment, when the computer program is executed by the processor, it further implements the following steps: after the refresh operation in the current data processing cycle is completed, the scan operation in the next data processing cycle is executed; the refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time; the refresh cycle is the time period required to perform the refresh operation; the data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
[0116] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A data error correction method, characterized by, The method includes: After the refresh operation in the current data processing cycle is completed, the data in the target memory is read according to the target scan granularity to obtain the current data to be verified, and the error correction code is used to verify the current data to be verified to obtain the verification result. When the obtained verification result indicates that the current data to be verified has a correctable error, the current data to be verified is corrected to obtain the target data. Write the target data back to the target memory.
2. The method of claim 1, wherein, The step of reading data from the target memory according to the target scanning granularity to obtain the current data to be verified, and performing error correction code verification on the current data to be verified to obtain the verification result, includes: The target row address and the corresponding starting column address are determined based on the current scan position; the current scan position is the physical location of the last target data written back to the target memory in the previous data processing cycle. The target column address range is determined based on the target scan granularity, the target row address, and the starting column address; The data corresponding to each column address within the target column address range is read sequentially to obtain the current data to be verified, and the current data to be verified is verified by error correction code to obtain the verification result.
3. The method of claim 1, wherein, The target scanning granularity is determined based on system performance requirements or storage access efficiency.
4. The method of claim 1, wherein, The step of performing error correction code verification on the current data to be verified to obtain the verification result includes: The current data to be verified is verified based on the error correction code to obtain the number of error bits; When the number of erroneous bits is less than or equal to the error correction threshold of the error correction code, it is determined that the current data to be verified contains a correctable error.
5. The method of claim 4, wherein, The step of performing error correction code verification on the current data to be verified to obtain the verification result also includes: When the number of erroneous bits is greater than the error correction threshold, it is determined that the current data to be verified contains an uncorrectable error.
6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: After the refresh operation in the current data processing cycle is completed, the scan operation in the next data processing cycle is executed; the refresh cycle in the next data processing cycle and the data error correction cycle in the current data processing cycle partially overlap in time; the refresh cycle is the time period required to execute the refresh operation; the data error correction cycle is the time period required to read, verify, correct, and write back the data in the target memory.
7. A data error correction apparatus, characterized by comprising: The device includes: The scanning module is used to read the data in the target memory according to the target scanning granularity after the refresh operation in the current data processing cycle is completed, to obtain the current data to be verified, and to perform error correction code verification on the current data to be verified to obtain the verification result. The error correction module is used to correct the current data to be verified when the obtained verification result indicates that there is a correctable error in the current data to be verified, so as to obtain the target data. The write-back module is used to write the target data back to the target memory.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.