Test adapter plates, patch panels, and methods of preparation

Abstract

This invention discloses a test adapter board, a panel, and a manufacturing method. The test adapter board, through the design of the number of metal layers, the function of each metal layer, the shape of the test adapter board, and the conductive vias in the test adapter board, facilitates high-speed signal impedance matching, improves signal integrity, ensures the success rate of DDR memory controller training, and simultaneously reduces R&D costs.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, specifically to a test adapter board, a panel, and a preparation method. Background Technology

[0002] In the research and development and testing of Double Data Rate (DDR) memory modules and their DRAM chips, especially in the post-Signal Integrity (SI) simulation verification stage, obtaining real and reliable physical layer signals is crucial for evaluating product performance and stability. Since the connections between the DRAM chips and the module PCB on the DDR memory module are all in BGA package form, and the surface space of the module is limited, it is impossible to directly place test points on the interconnect path between the DRAM chips and the DDR memory module. Therefore, a dedicated testing tool called an "interposer" has emerged and become an indispensable core component in this testing process.

[0003] The adapter board works as follows: First, the target DRAM chip is removed from the DDR memory module under test, and ball-mounting is performed on the DRAM chip pads and the BGA_PAD on the bottom of the adapter board. Then, the adapter board is soldered to the original DRAM chip location in the DDR memory module. Finally, the removed DRAM chip is soldered onto the adapter board. Through this "sandwich" stacking structure, the adapter board can extract all or part of the high-speed bus signals from the DRAM chip from the BGA area, and test points are designed on its board edges or at specific locations to facilitate signal capture and analysis by high-speed oscilloscope probes or dedicated connectors.

[0004] With the evolution of DDR memory technology from DDR3 to DDR5, signal rates have increased to 5600 MT / s and above, resulting in a qualitative change in the requirements for signal integrity. Especially for domestic CPU platforms, whose DDR memory controller training algorithms are still in the continuous optimization stage, the physical consistency of bus signals—including impedance matching, transmission delay, and crosstalk control—is subject to almost stringent requirements. Any disturbance to the original signal path can lead to system training failure, making testing impossible. Against this backdrop, adapter boards have evolved from simple "signal extraction tools" into "precision test devices that must be highly consistent with the electrical characteristics of the original channels," and their design and manufacturing face multi-dimensional technical challenges. At DDR5 speeds, signal rise times have entered the picosecond range. Any minute electrical discontinuity in the adapter board's stack-up design, impedance control, reference plane integrity, and via residual post handling can become the "last straw" that breaks the camel's back during system training.

[0005] Physical space and interference avoidance: The adapter board is used to bring out test points, and its planar dimensions are usually larger than the original DRAM chips. This can cause interference between the adapter board and the original component structure on the DDR memory module.

[0006] Adaptability to harsh process environments: The entire installation process involves at least two high-temperature welding operations. The adapter plate must have rapid heat conduction and sufficient mechanical strength.

[0007] Diverse specification requirements: Generational differences in DDR memory technology (DDR3, DDR4, DDR5) and the bit width configuration of DRAM chips (x8, x16) determine the differences in their pin definitions, signal arrangements, and impedance characteristics. This means that testing organizations need to prepare various types of adapter boards for different specifications to meet various testing needs. Summary of the Invention

[0008] This invention provides a test adapter board, a test adapter board panel, and a method for manufacturing the test adapter board. This test adapter board is used for post-simulation testing of DDR memory modules. It helps improve signal integrity, avoids structural interference, and has good adaptability to different process environments. Furthermore, by using panelization to manufacture test adapter boards of different specifications, various testing needs can be met while significantly reducing costs.

[0009] The present invention provides the following technical solution: a test adapter board for post-simulation testing of DDR memory modules, the test adapter board comprising: a core layer and a plurality of metal layers of equal number located on both sides of the core layer, wherein adjacent metal layers are separated by an insulating layer, and the core layer has at least 4 metal layers on one side, the two outermost metal layers being the top pad layer and the bottom pad layer, respectively.

[0010] The test adapter board is divided into a central region and an edge region surrounding the central region, with a missing section in the edge region extending from the interior of the core layer to the bottom pad layer. Multiple array pads are arranged one-to-one in the top pad layer and bottom pad layer located in the central region. The corresponding two array pads are electrically connected through a first conductive via that passes through the test adapter board. The first conductive via is filled with metal. Multiple signal test pads and multiple ground test pads are provided in the top pad layer located in the edge region. Each signal test pad is connected to a second conductive via, and each ground test pad is connected to a third conductive via. The second conductive via and the third conductive via are filled with metal. The remaining metal layers between the bottom pad layer and the core layer are all reference power layers; The top-level pad layer is provided with signal lead wires that connect the array pads and the signal test point pads. Signal lead wires are provided in at least one of the remaining metal layers of the top pad layer and the core layer, and their two ends are connected to the array pads and the signal test point pads through the first conductive via and the second conductive via, respectively. The metal layer adjacent to the top pad layer is a reference power layer. The first metal layer on the core layer facing the top pad layer is a reference power layer. At least one reference power layer is provided between any two metal layers with signal lead-out wires.

[0011] In some implementations, the metal layers on one side of the core layer are four layers, which are arranged sequentially along the direction from the core layer to the top pad layer as follows: second reference power layer, inner signal layer, first reference power layer and top pad layer; The second reference power layer is laid out entirely as a grounding layer; The inner signal layer is provided with signal lead wires, the two ends of which are connected to the array pads and the signal test point pads through the first conductive via and the second conductive via, respectively. The first reference power layer is laid out entirely as a grounding layer.

[0012] In some implementations, the metal layers on one side of the core layer are four layers, which are arranged sequentially along the direction from the core layer to the top pad layer as follows: second reference power layer, inner signal layer, first reference power layer and top pad layer; The second reference power layer is laid out entirely as a grounding layer; The inner signal layer is provided with signal lead wires, the two ends of which are connected to the array pads and the signal test point pads through the first conductive via and the second conductive via, respectively. The first reference power layer is divided into a ground layer and a positive power layer.

[0013] Note: The above "whole layer laying" refers to the entire metal layer being either a grounding layer or a positive power supply layer. Some areas are allowed to be empty to avoid conductive vias, that is, a gap is left between the metal layer and non-grounded or non-power supply conductive vias.

[0014] Note: The metal layer on the other side of the core layer is either the ground layer or the positive power layer.

[0015] In some embodiments, the thickness of the core layer is ≥1.2mm, the thickness of the central region of the test adapter is 1.8mm to 2.2mm, and the difference between the thickness of the central region and the thickness of the edge region of the test adapter is in the range of 0.9mm to 1.1mm.

[0016] In some embodiments, the first conductive via, the second conductive via, and the third conductive via are filled with copper.

[0017] In some embodiments, the surfaces of the array pads, the signal test pads, and the ground test pads all include a chemically plated nickel layer and an immersion gold layer, wherein the thickness of the chemically plated nickel layer is in the range of 110 μ" to 130 μ" and the thickness of the immersion gold layer is in the range of 2 μ" to 3 μ".

[0018] In some embodiments, the test adapter plate is rectangular and has a first side and a second side opposite to each other, the central region is rectangular, the inner and outer boundaries of the edge regions are both rectangular, and the boundary of the central region is parallel to the inner and outer boundaries of the edge regions on the same side. In the orthographic projection view of the plane where the test adapter board is located, the distance from the signal test pad located on the first side to the central region is greater than the distance from the signal test pad located on the second side to the central region; the number of signal test pads located on the first side is greater than the number of signal test pads located on the second side; the distance from the ground test pad located on the first side to the central region is greater than the distance from the ground test pad located on the second side to the central region; the number of ground test pads located on the first side is greater than the number of ground test pads located on the second side; and the distance from the first side to the central region is greater than the distance from the second side to the central region.

[0019] The present invention provides the following technical solution: a test adapter board panel, comprising multiple test adapter boards arranged in an array, wherein the test adapter boards are the test adapter boards described above.

[0020] In some implementations, test adapter boards in the same row are the same size and have the same layout, while there are at least two rows of test adapter boards with different sizes and layouts.

[0021] This invention provides the following technical solution: a method for preparing a test adapter board as described above, comprising: A first intermediate state board is formed, which includes the core layer, metal layers other than the bottom pad layer, and the insulating layer. The core layer and the insulating layer are complete and basically flush. The array pads, signal test point pads, and ground test point pads have not yet been formed in the top pad layer. All the metal layers of the core layer facing the bottom pad layer are located only in the central area. A marking silkscreen is formed on the insulating layer farthest from the top pad layer. The marking silkscreen marks the boundary line between the central area and the edge area. The first conductive via, the second conductive via, and the third conductive via are formed, and copper paste is filled into the three vias. A controlled-depth milling process is used to remove the portion of the insulating layer located in the edge region between the bottom pad layer and the core layer, and the milling endpoint is controlled to reach the interior of the core layer, leaving a portion of the core layer thickness in the edge region.

[0022] In some embodiments, the method further includes: chemically plating nickel and immersion gold on the pad areas where the first conductive via, the second conductive via, and the third conductive via are located, after the copper paste filling operation and before the controlled depth milling operation, to form the array pad, the signal test point pad, and the ground test point pad.

[0023] The first, second, and third conductive vias are filled with metal, such as copper paste, which greatly improves heat conduction. This reduces soldering time and improves device reliability when soldering the test adapter board to DRAM chips and DDR memory modules. The thickness of the section from the core layer to the bottom pad layer in the edge region of the test adapter board is missing, giving the board a boss-like shape. This missing portion avoids other components on the DDR memory module, such as capacitors. Furthermore, the reduced thickness of the second and third conductive vias connected to the ground and signal test pads reduces residual pile effects and improves signal integrity. Each side of the core layer has at least four metal layers, allowing signal traces to be placed in at least two layers, enabling the routing of all required signals. Consistent bus signals contribute to successful training of the CPU's memory controller. With sufficient metal layers for signal trace routing and enough for ground or positive power layers, adequate design space is provided for impedance matching of each type of signal.

[0024] Furthermore, this test adapter board can be fabricated by piecing together different boards, and a single fabrication process can simultaneously produce the test adapter boards required for DDR memory modules of different generations and bit widths. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the stacked structure of the test adapter board of the present invention.

[0026] Figure 2 This is the layout of the top pad layer of the test adapter board of the present invention.

[0027] Figure 3 This is the layout of the first reference power layer of the test adapter board of the present invention.

[0028] Figure 4 This is the layout of the inner signal layer of the test adapter board of the present invention.

[0029] Figure 5 This is a layout of the second reference power layer of the test adapter board of the present invention.

[0030] Figure 6 This is the layout of the third reference power layer of the test adapter board of the present invention.

[0031] Figure 7 This is the layout of the fourth reference power layer of the test adapter board of the present invention.

[0032] Figure 8 This is the layout of the fifth reference power layer of the test adapter board of the present invention.

[0033] Figure 9 This is the layout of the bottom pad layer of the test adapter board of the present invention.

[0034] Figure 10 This is a schematic diagram of the controlled-depth milling area of ​​the test adapter plate of the present invention.

[0035] Figure 11 This is a schematic diagram illustrating the application scenario of the test adapter board of the present invention.

[0036] Figure 12 This is a comparison image of the adapter board before and after the solder pad surface plating leveling process.

[0037] Figure 13 This is a panel diagram of the test adapter board of the present invention.

[0038] The attached figures are labeled as follows: L1, Top pad layer; PP1, First insulating layer; L2, First reference power layer; PP2, Second insulating layer; L3, Inner signal layer; PP3, Third insulating layer; L4, Second reference power layer; C, Core layer; L5, Third reference power layer; PP4, Fourth insulating layer; L6, Fourth reference power layer; PP5, Fifth insulating layer; L7, Fifth reference power layer; PP6, Sixth insulating layer; L8, Bottom pad layer; V1, First conductive via; V2, Second conductive via; V3, Third conductive via; Pad1, Array pad; Pad2, Signal test pad; Pad3, Ground test pad; Line1, CA bus signal line; H, non-electric positioning hole; GND1, first grounding reference plane; Line 2, data line; Line 3, data strobe signal line; Line 4, clock signal line; GND2, second grounding reference plane; PWR1, First power reference plane; PWR2, second power supply reference plane; GND3, the third grounding reference plane; S. Milling area marking silkscreen; 1. Test adapter board for DDR memory module post-simulation; 2. DDR module; 3. DRAM chip; 4. Slot; T1, thickness; T2, milling depth; D1, first spacing; D2, second spacing; H0, stamp perforation. Detailed Implementation

[0039] The present invention will be further described below with reference to specific embodiments, but the scope of protection of the present invention is not limited thereto.

[0040] refer to Figures 1 to 12 The present invention provides a test adapter board 1 for post-simulation testing of DDR memory modules. The test adapter board 1 includes: a core layer C and a plurality of metal layers of equal number located on both sides of the core layer C. Adjacent metal layers are separated by an insulating layer. There are at least 4 metal layers on one side of the core layer C. The two outermost metal layers are the top pad layer L1 and the bottom pad layer L8, respectively.

[0041] If the core layer C has 4 metal layers on one side, then test adapter board 1 is an 8-layer board. Alternatively, the core layer C can have 5 or 6 metal layers on one side, then test adapter board 1 is a 10-layer or 12-layer board.

[0042] The test adapter board 1 is divided into a central area and an edge area surrounding the central area. The thickness section from the inside of the core layer C to the bottom pad layer L8 in the edge area is missing.

[0043] refer to Figure 10 The test adapter board 1 is shaped like a boss, and the thickness section from the inside of the core layer C to the bottom pad layer L8 can be removed using a controlled-depth milling process. The missing thickness section can avoid the densely packed capacitors and other components in the DDR memory module, and can also avoid other DRAM chips 3 adjacent to the DRAM chip 3 to be tested.

[0044] Multiple array pads Pad1 are set one-to-one in the top pad layer L1 and bottom pad layer L8 located in the central area. The two corresponding array pads Pad1 are electrically connected through the first conductive via V1 that penetrates the test adapter board. The first conductive via V1 is filled with metal.

[0045] The array pad Pad1 is specifically a ball grid array package pad.

[0046] Figure 12 This demonstrates the array of pads Pad1 within the top pad layer L1. Combined with... Figure 10 and Figure 11The array pad Pad1 in the top pad layer L1 is used to connect the DRAM chip 3 to be tested, and the array pad Pad1 in the bottom pad layer L8 is used to connect the circuit board of the DDR module 2.

[0047] Combination Figure 2 and Figure 10 Multiple signal test pads Pad2 and multiple ground test pads Pad3 are set in the top pad layer L1 located in the edge region. Each signal test pad Pad2 is connected to a second conductive via V2, and each ground test pad Pad3 is connected to a third conductive via V3. The second conductive via V2 and the third conductive via V3 are filled with metal.

[0048] The first conductive via V1, the second conductive via V2, and the third conductive via V3 are filled with metal, which can reduce the resistance of the conductive via and improve heat conduction, thereby effectively reducing the duration of solder pad blowing and improving the overall system reliability.

[0049] refer to Figure 10 The lengths of the second conductive via V2 and the third conductive via V3 are shorter than the length of the first conductive via V1. Since their ends are free ends, this design reduces the residual pile effect and helps to improve signal integrity.

[0050] The remaining metal layers between the bottom pad layer L8 and the core layer C are all reference power layers.

[0051] The reference power layer can be grounded entirely, connected to positive power for the entire layer, or partially grounded and partially connected to positive power.

[0052] refer to Figure 2 The top layer L1 contains signal lead wires that connect the array pad Pad1 and the signal test point pad Pad2.

[0053] The signal leads in the top pad layer L1 are connected to signals such as the Command / Address bus (CA bus) signals, used to transmit command and address signals. In DDR5, the CA bus needs to reference the ground plane, while in DDR3 / DDR4 it references the positive power plane.

[0054] refer to Figure 1 and Figure 4 Signal lead wires are provided in at least one of the remaining metal layers of the top pad layer L1 and the core layer C, and their two ends are connected to the array pad Pad1 and the signal test point pad Pad2 through the first conductive via V1 and the second conductive via V2, respectively.

[0055] For example, a data line Line2, a data strobe signal line Line3, and a clock signal line Line4 are provided in this metal layer.

[0056] The metal layer adjacent to the top pad layer L1 is the reference power layer. The first metal layer on the core layer C facing the top pad layer L1 is the reference power layer. At least one reference power layer is set between any two metal layers with signal lead-out wires.

[0057] For the metal layers on the side of the core layer C facing the bottom pad layer L8, except for the array pad Pad1 set in the bottom pad layer L8, the other metal layers are ground layers or positive power layers.

[0058] Combination Figures 2 to 5 In some implementations, the metal layers on one side of the core layer C are four layers, which are sequentially arranged along the direction from the core layer C to the top pad layer L1 as follows: second reference power layer L4, inner signal layer L3, first reference power layer L2 and top pad layer L1. The second reference power layer L4 is laid out in its entirety as a grounding layer; Signal lead wires are provided in the inner signal layer L3, and their two ends are connected to the array pad Pad1 and the signal test point pad Pad2 through the first conductive via V1 and the second conductive via V2, respectively. The first reference power layer L2 is laid out entirely as a grounding layer.

[0059] In other embodiments, the metal layers on one side of the core layer C are four layers, which are sequentially arranged along the direction from the core layer C to the top pad layer L1 as follows: second reference power layer L4, inner signal layer L3, first reference power layer L2 and top pad layer L1. The second reference power layer L4 is laid out in its entirety as a grounding layer; Signal lead wires are provided in the inner signal layer L3, and their two ends are connected to the array pad Pad1 and the signal test point pad Pad2 through the first conductive via V1 and the second conductive via V2, respectively. The first reference power layer L2 is divided into a ground layer and a positive power layer.

[0060] For DDR5, the first reference power layer L2 is entirely divided as a ground plane. For DDR3 and DDR4, their CA bus needs to reference a positive power plane. Therefore, the area in their first reference power layer L2 opposite to the CA bus is set as a positive power plane, and the remaining area is set as a ground plane.

[0061] In some implementations, the thickness of the core layer C is ≥1.2mm, the thickness of the central region of the test adapter 1 is 1.8mm to 2.2mm, and the difference between the thickness of the central region and the thickness of the edge region of the test adapter 1 is in the range of 0.9mm to 1.1mm.

[0062] The core layer C is thick enough to provide a safety redundancy for the subsequent deep milling process that removes part of the thickness of the core layer C from the edge areas. If the thickness of the central area of ​​the test adapter board 1 is too large, it may cause structural interference with the connector that plugs into the DDR memory module during use; if the thickness is too small, it will be difficult to process. If the thickness removed from the edge areas of the test adapter board 1 is too large, the remaining core layer C will be too thin, which is not conducive to supporting the metal layers on it.

[0063] In some embodiments, the first conductive via V1, the second conductive via V2, and the third conductive via V3 are formed by a copper paste filling process, i.e., they are filled with copper.

[0064] refer to Figure 1 Copper paste filling technology can create a solid copper pillar structure. This structure provides a low-thermal-resistance metal path for heat transfer, allowing heat to be quickly conducted from the soldering iron to the solder balls placed on the underlying L8 pad layer during manual soldering operations, completing reliable soldering within seconds. Compared to traditional resin-filled vias, copper paste filling significantly shortens the soldering heating time, effectively avoiding process risks such as PCB substrate carbonization and pad peeling caused by prolonged localized heating, and significantly improving the first-time soldering success rate.

[0065] In some embodiments, array pad Pad1, signal test pad Pad2, and ground test pad Pad3 all include a chemically plated nickel layer and an immersion gold layer, wherein the thickness of the chemically plated nickel layer is in the range of 110 μ" to 130 μ" and the thickness of the immersion gold layer is in the range of 2 μ" to 3 μ".

[0066] refer to Figure 12 During the fabrication of test adapter board 1, after copper paste filling to form conductive pillars, a plated over filled via (POFV) process is used to treat the pad surface to ensure pad flatness. This is crucial for the bottom pad ball placement and soldering of array pads Pad1. A flat pad surface ensures that the height of each solder ball is consistent after placement, avoiding defects such as cold solder joints and bridging. After the surfaces of all array pads Pad1, signal test point pads Pad2, and ground test point pads Pad3 are formed, no vias are visible on the surface layer of test adapter board 1.

[0067] The electroplating leveling process includes nickel plating and subsequent immersion gold operation.

[0068] A thick nickel layer (typically 120 μ") effectively blocks the diffusion of copper atoms, preventing the formation of brittle gold-tin compounds (gold brittleness) with the solder, while providing sufficient nickel layer consumption margin for multiple soldering operations.

[0069] A thin gold layer ensures excellent solderability and contact conductivity, while also meeting the skin effect transmission requirements of high-speed signals. Gold has better conductivity than nickel, and a thin gold layer is beneficial for high-frequency signal transmission.

[0070] Compared to electroplating, immersion gold technology can provide a more uniform plating thickness and has no electroplating leads, making it suitable for the fine processing of array pads (Pad1).

[0071] In some implementations, reference Figure 10 The test adapter plate 1 is rectangular and has a first side and a second side that are opposite to each other. The central area is rectangular, and the inner and outer boundaries of the edge areas are both rectangular. The boundary of the central area is parallel to the inner and outer boundaries of the edge areas on the same side.

[0072] In the orthographic projection view of the plane where the test adapter board 1 is located, the distance from the signal test pad Pad2 located on the first side to the center area is greater than the distance from the signal test pad Pad2 located on the second side to the center area. The number of signal test pads Pad2 located on the first side is greater than the number of signal test pads Pad2 located on the second side. The distance from the ground test pad Pad3 located on the first side to the center area is greater than the distance from the ground test pad Pad3 located on the second side to the center area. The number of ground test pads Pad3 located on the first side is greater than the number of ground test pads Pad3 located on the second side. The distance from the first side to the center area is greater than the distance from the second side to the center area.

[0073] At the end of the test adapter board 1 facing the gold fingers of the DIMM slot, the number of signal test point pads Pad2 and ground test point pads Pad3 should be minimized as much as possible, and their layout should be recessed inward to avoid interference between the test adapter board 1 and the DIMM slot structure when the test adapter board 1 is inserted into the DIMM slot.

[0074] The number of signal test pads Pad2 and ground test pads Pad3 near the DIMM slot is less than that on the side farther from the DIMM slot, and the board edge is closer to the DRAM chip 3. The area where the DRAM chip 3 is located is opposite to the central area of ​​the test adapter board 1, and the central area of ​​the test adapter board 1 is slightly recessed inward than the area occupied by the DRAM chip 3, typically by 2mm.

[0075] refer to Figure 13 The embodiments of the present invention also provide a test adapter board 1 panel, including multiple test adapter boards 1 arranged in an array, wherein the test adapter board 1 is the test adapter board 1 described above.

[0076] In some implementations, the test adapter boards 1 in the same row are the same size and have the same layout, while there are at least two rows of test adapter boards 1 with different sizes and different layouts.

[0077] For example Figure 13 In the diagram, the first row of test adapter board 1 is used for post-simulation of 8-bit DDR3 memory modules, the second row is used for post-simulation of 16-bit DDR3 memory modules, the third row is used for post-simulation of 8-bit DDR5 memory modules, the fourth row is used for post-simulation of 16-bit DDR5 memory modules, the fifth row is used for post-simulation of 16-bit DDR4 memory modules, and the sixth row is used for post-simulation of 8-bit DDR4 memory modules.

[0078] A stamp hole H0 is provided between adjacent test adapter boards 1 to facilitate the separation of test adapter boards 1.

[0079] The line width and spacing of key signal lines differ between test adapter boards of different specifications, thereby meeting different impedance matching requirements.

[0080] Taking an 8-layer board as an example, the CA bus signal line Line1 of the test adapter board 1 of different specifications is set on the first layer (i.e., the top pad layer L1), and the data line Line2, data strobe signal line and clock signal line Line4 are set on the third layer.

[0081] The total thickness of the various specifications of the test adapter board 1, as well as the thickness of each metal layer and insulating layer, are consistent. The core layer C is sufficiently thick, and all metal layers are made of the same material. The insulating layers within the same layer are also made of the same material, and the core layer C is made of the same material. Only the line width and line spacing need to be designed independently to meet the impedance matching requirements of DDR memory modules of different generations. This greatly improves the utilization rate of the circuit board material. In actual production, the cost of a single test adapter board 1 can be controlled within 100 yuan, while the price of similar products from overseas is about 1000 yuan, which has extremely high economic benefits.

[0082] Based on the same inventive concept, embodiments of the present invention also provide a method for preparing the test adapter board 1 as described above, including the following operations. The specific description will be based on a test adapter board 1 used for simulation of an 8-layer DDR memory module.

[0083] Step 1: Form the first intermediate state board, which includes a core layer C, metal layers except for the bottom pad layer L8, and an insulating layer. The core layer C and the insulating layer are complete and basically flush. All the metal layers of the core layer C facing the bottom pad layer L8 are located only in the central area. A marking silkscreen is formed on the insulating layer farthest from the top pad layer L1. The marking silkscreen marks the boundary between the central area and the edge area. The array pad Pad1, signal test point pad Pad2, and ground test point pad Pad3 have not yet been formed in the top pad layer L1.

[0084] refer to Figure 1The first intermediate state board includes, in sequence, a top pad layer L1, a first insulating layer PP1, a first reference power layer L2, a second insulating layer PP2, an inner signal layer L3, a third reference power layer L5, a core layer C, a third reference power layer L5, a fourth insulating layer PP4, a fourth reference power layer L6, a fifth insulating layer PP5, a fifth single-point power layer, a sixth insulating layer PP6, and a bottom pad layer L8. Copper is used as the conductor in each metal layer.

[0085] refer to Figure 2 In the current state, only the CA bus signal line Line1 and other traces are formed in the top pad layer L1. The array pad Pad1, signal test point pad Pad2, and ground test point pad Pad3 have not yet been formed.

[0086] refer to Figure 1 In its current state, the first insulating layer PP1 is a complete layer, basically flush with the core layer C. The first insulating layer PP1 is a prepreg.

[0087] refer to Figure 3 The first reference power layer L2 is laid entirely on to form the first ground reference plane GND1. The first ground reference plane GND1 avoids the non-grounded second conductive via V2 and the first conductive via V1. Figure 3 The non-electric positioning hole H is also marked; it is a through hole used for testing the positioning of adapter board 1. The first grounding reference plane GND1 avoids the non-electric positioning hole H.

[0088] refer to Figure 1 In its current state, the second insulating layer PP2 is a complete layer, basically flush with the core layer C. The second insulating layer PP2 is a prepreg.

[0089] refer to Figure 4 In the current state, the inner signal layer L3 contains data line Line2, data strobe signal line Line3, clock signal line Line4, and other necessary signal lines.

[0090] refer to Figure 1 Currently, the third insulating layer PP3 is a complete layer, almost flush with the core layer C. The third insulating layer PP3 is a prepreg.

[0091] refer to Figure 5 The second reference power layer L4 is laid out in its entirety to form the second ground reference plane GND2. The second ground reference plane GND2 avoids the non-grounded first conductive via V1, the second conductive via V2, and the non-electrical positioning hole H.

[0092] refer to Figure 1 In its current state, the core layer C is a complete flat plate with a thickness of 1.2mm, and is made of glass fiber reinforced epoxy resin laminate FR4.

[0093] refer to Figure 6 A first power reference plane PWR1 is formed in the third reference power layer L5 for connecting to the positive power supply. The first power reference plane PWR1 is only formed in the central area of ​​the test adapter plate 1, avoiding the first conductive via V1 which is not connected to the positive power supply.

[0094] refer to Figure 1 Currently, the fourth insulating layer PP4 is a complete layer, almost flush with the core layer C. The fourth insulating layer PP4 is a prepreg.

[0095] refer to Figure 7 A second power reference plane PWR2 is formed in the fourth reference power layer L6 for connecting to the positive power supply. The second power reference plane PWR2 is only formed in the central area of ​​the test adapter plate 1, avoiding the first conductive via V1 which is not connected to the positive power supply.

[0096] refer to Figure 1 Currently, the fifth insulating layer PP5 is a complete layer, almost flush with the core layer C. The fifth insulating layer PP5 is a prepreg.

[0097] refer to Figure 8 A third ground reference plane GND3 is formed in the fifth reference power layer L7 for grounding. The third ground reference plane GND3 is formed only in the central area of ​​the test adapter plate 1, avoiding the non-grounded first conductive via V1.

[0098] refer to Figure 9 and combined Figure 1 Currently, the sixth insulating layer PP6 is a complete layer, almost flush with the core layer C. The sixth insulating layer PP6 is a prepreg. A milling area marking "S" is silkscreened on the sixth insulating layer PP6.

[0099] Note: In the current state, the first conductive via V1, the second conductive via V2, and the third conductive via V3 have not yet been formed. The areas marked in each figure are their locations.

[0100] Step 2: Form the first conductive via V1, the second conductive via V2, and the third conductive via V3, and fill them with copper paste.

[0101] Step 3: Perform nickel plating and chemical gold plating on the areas where the first conductive via V1, the second conductive via V2 and the third conductive via V3 are located, to form array pad Pad1, signal test point pad Pad2 and ground test point pad Pad3.

[0102] Each pad undergoes a 120μ" thick electroless nickel plating followed by a 2-3μ" thick immersion gold plating. The thick nickel layer effectively blocks copper diffusion and prevents gold embrittlement. The thin gold layer meets the skin effect transmission requirements for high-speed signals, ensuring that the waveform of high-frequency signals is not distorted after being taken out through the test points.

[0103] After this step is completed, an array of pads (Pad1) is formed in the bottom pad layer (L8) for connecting the circuit board of the DDR memory module. (Reference) Figure 12 At this time, array pads Pad1, signal test point pads Pad2, and ground test point pads Pad3 are formed in the top layer L1.

[0104] Operation 4: Use controlled depth milling to remove the portion of the insulating layer located in the edge region between the bottom pad layer L8 and the core layer C, and control the milling endpoint to the interior of the core layer C, retaining a portion of the core layer C thickness in the edge region.

[0105] refer to Figure 3 After controlled-depth milling, the test adapter plate 1 is shaped like a boss. The milling depth T2 of the edge area is 1mm, and the thickness T1 of the test adapter plate 1 is 2mm.

[0106] The residual stakes in the second conductive via V2 and the third conductive via V3 in the edge region are shortened, which helps to improve signal integrity.

[0107] This helps eliminate reflections, resonances, and insertion loss degradation caused by residual stubs to high-speed signals. Actual measurements show that at a DDR5 memory module speed of 5600MT / s, the signal eye diagram opening captured by the test adapter board 1 of this invention is approximately 20% higher than that of traditional solutions, and the bit error rate is significantly reduced.

[0108] refer to Figure 10 and Figure 11 In use, the array pads Pad1 in the bottom pad layer L8 of the test adapter board are first ball-mounted and then soldered onto the circuit board of the DDR memory module. Then, the DRAM chip 3 (after re-balling) is soldered onto the array pads Pad1 in the top pad layer L1. The DDR memory module is placed in slot 4, specifically a DIMM slot 4. The dimension from the center area of ​​the test adapter board 1 to the edge area away from slot 4 is denoted as the first pitch D1, and the dimension from the center area of ​​the test adapter board 1 to the edge area closer to slot 4 is denoted as the second pitch D2. To avoid structural interference and reduce the risk of short circuits, the second pitch D2 is smaller than the first pitch D1. Furthermore, the number and density of the second and third pads in the edge area from the center area of ​​the test adapter board 1 away from slot 4 are greater than the number and density of the second and third pads in the edge area on the opposite side.

[0109] An 8-layer board is the optimal solution, as it allows for full signal output while providing sufficient space for precise impedance matching. 10-layer or 12-layer boards increase thickness and residual post length, resulting in slightly inferior overall performance compared to an 8-layer board.

[0110] Copper paste filling of conductive vias improves thermal conductivity. The core layer C is sufficiently thick to provide safety redundancy. Through a unified 8-layer board design, test adapter boards of various generations and bit widths can be obtained in a single prototyping, significantly reducing economic costs. Optimization is achieved simultaneously in three dimensions: extreme high-speed signal integrity, process reliability, and multi-specification coverage economy.

[0111] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Those skilled in the art can make non-substantial modifications or equivalent substitutions based on the above embodiments without departing from the inventive concept, and these modifications and substitutions do not alter the essential characteristics of the invention. The scope of protection of the present invention is defined by the appended claims.

Claims

1. A test adapter board for post-simulation testing of DDR memory modules, characterized in that, The test adapter board includes: a core layer and multiple metal layers of equal number located on both sides of the core layer, wherein adjacent metal layers are separated by an insulating layer, and the core layer has at least 4 metal layers on one side, with the two outermost metal layers being the top pad layer and the bottom pad layer, respectively. The test adapter board is divided into a central region and an edge region surrounding the central region, with a missing section in the edge region extending from the interior of the core layer to the bottom pad layer. Multiple array pads are arranged one-to-one in the top pad layer and bottom pad layer located in the central region. The corresponding two array pads are electrically connected through a first conductive via that passes through the test adapter board. The first conductive via is filled with metal. Multiple signal test pads and multiple ground test pads are provided in the top pad layer located in the edge region. Each signal test pad is connected to a second conductive via, and each ground test pad is connected to a third conductive via. The second conductive via and the third conductive via are filled with metal. The remaining metal layers between the bottom pad layer and the core layer are all reference power layers; The top-level pad layer is provided with signal lead wires that connect the array pads and the signal test point pads. Signal lead wires are provided in at least one of the remaining metal layers of the top pad layer and the core layer, and their two ends are connected to the array pads and the signal test point pads through the first conductive via and the second conductive via, respectively. The metal layer adjacent to the top pad layer is a reference power layer. The first metal layer on the core layer facing the top pad layer is a reference power layer. At least one reference power layer is provided between any two metal layers with signal lead-out wires.

2. The test adapter board according to claim 1, characterized in that, The core layer has four metal layers on one side, which are arranged sequentially along the direction from the core layer to the top pad layer as follows: second reference power layer, inner signal layer, first reference power layer and top pad layer. The second reference power layer is laid out entirely as a grounding layer; The inner signal layer is provided with signal lead wires, the two ends of which are connected to the array pads and the signal test point pads through the first conductive via and the second conductive via, respectively. The first reference power layer is laid out entirely as a grounding layer.

3. The test adapter board according to claim 1, characterized in that, The core layer has four metal layers on one side, which are arranged sequentially along the direction from the core layer to the top pad layer as follows: second reference power layer, inner signal layer, first reference power layer and top pad layer. The second reference power layer is laid out entirely as a grounding layer; The inner signal layer is provided with signal lead wires, the two ends of which are connected to the array pads and the signal test point pads through the first conductive via and the second conductive via, respectively. The first reference power layer is divided into a ground layer and a positive power layer.

4. The test adapter board according to claim 1, characterized in that, The thickness of the core layer is ≥1.2mm, the thickness of the central region of the test adapter board is 1.8mm to 2.2mm, and the difference between the thickness of the central region and the thickness of the edge region of the test adapter board is in the range of 0.9mm to 1.1mm.

5. The test adapter board according to claim 1, characterized in that, The first conductive via, the second conductive via, and the third conductive via are filled with copper.

6. The test adapter board according to claim 1, characterized in that, The array pads, the signal test pads, and the ground test pads all include a chemical nickel plating layer and an immersion gold layer, wherein the thickness of the chemical nickel plating layer is in the range of 110 μ" to 130 μ" and the thickness of the immersion gold layer is in the range of 2 μ" to 3 μ".

7. The test adapter board according to claim 1, characterized in that, The test adapter plate is rectangular and has a first side and a second side opposite to each other. The central region is rectangular. The inner and outer boundaries of the edge regions are both rectangular. The boundary of the central region is parallel to the inner and outer boundaries of the edge regions on the same side. In the orthographic projection view of the plane where the test adapter board is located, the distance from the signal test pad located on the first side to the central region is greater than the distance from the signal test pad located on the second side to the central region; the number of signal test pads located on the first side is greater than the number of signal test pads located on the second side; the distance from the ground test pad located on the first side to the central region is greater than the distance from the ground test pad located on the second side to the central region; the number of ground test pads located on the first side is greater than the number of ground test pads located on the second side; and the distance from the first side to the central region is greater than the distance from the second side to the central region.

8. A test adapter board panel, characterized in that, It includes multiple test adapter boards distributed in an array, wherein the test adapter boards are the test adapter boards according to any one of claims 1 to 7.

9. A method for preparing a test adapter board as described in any one of claims 1 to 7, characterized in that, include: A first intermediate state board is formed, which includes the core layer, metal layers other than the bottom pad layer, and the insulating layer. The core layer and the insulating layer are complete and basically flush. The array pads, signal test point pads, and ground test point pads have not yet been formed in the top pad layer. All the metal layers of the core layer facing the bottom pad layer are located only in the central area. A marking silkscreen is formed on the insulating layer farthest from the top pad layer. The marking silkscreen marks the boundary line between the central area and the edge area. The first conductive via, the second conductive via, and the third conductive via are formed, and copper paste is filled into the three vias. A controlled-depth milling process is used to remove the portion of the insulating layer located in the edge region between the bottom pad layer and the core layer, and the milling endpoint is controlled to reach the interior of the core layer, leaving a portion of the core layer thickness in the edge region.

10. The preparation method according to claim 9, characterized in that, Also includes: After the copper paste filling operation and before the controlled depth milling operation, the pad areas where the first conductive via, the second conductive via, and the third conductive via are located are chemically plated with nickel and immersed in gold to form the array pad, the signal test point pad, and the ground test point pad.

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