A memory chip test case intelligent generation method, device and medium

Abstract

This invention discloses an intelligent method, device, and medium for generating test cases for memory chips, relating to the field of memory chip testing technology. The method includes: based on a fault syntax knowledge base, matching fault primitives according to the testing objectives of the memory chip, extracting corresponding sensitive access operations and verification response conditions along a ternary inference chain, and constraining the execution path of the sensitive access operations according to a memory chip access rule constraint syntax tree to form a generation task. The generation task is input into a test case generation model, and AI-assisted test case generation is performed by combining sensitive access operations, verification response conditions, anomaly tags, and constrained execution paths to output candidate chip test cases. The candidate chip test cases are then subjected to executability verification and screening through the memory chip access rule constraint syntax tree to form a target test case set. This invention enhances the executability, verifiability, and relevance of test case generation by converting constraint tags into a memory chip access rule constraint syntax tree.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing technology, and in particular to a method, device and medium for intelligent generation of memory chip test cases. Background Technology

[0002] As the capacity, interface types, and access timing complexity of memory chips continue to increase, chip testing is gradually evolving from manually writing test cases based on experience to developing technologies such as rule parsing, fault modeling, and AI-assisted test case generation. These technologies typically generate test cases based on chip specifications, test records, and anomaly response information, focusing on read / write access, erase / write control, timing constraints, and fault verification.

[0003] Existing memory chip test case generation technologies typically focus on single rule matching or sample-driven generation when dealing with memory chip access rules, abnormal segments, and fault verification relationships. There is a lack of unified association expression between access constraints, fault triggering operations, and verification response conditions, making it difficult for the generated test cases to simultaneously meet the requirements of rule executability and fault observability, thus affecting the stability of the test case generation process and the relevance of verification. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides an intelligent method for generating test cases for memory chips to solve the problem of the difficulty in coordinating the expression of memory chip access rule constraints and fault verification chains in the generation of test cases for memory chips.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides an intelligent generation method for memory chip test cases, comprising: collecting test association information of the memory chip; parsing memory chip access rules and extracting abnormal test fragments from the test association information; converting the memory chip access rules into constraint labels; converting abnormal test fragments into abnormal labels to form basic data of the memory chip; extracting fault primitives from the basic data of the memory chip; matching the fault primitives with the sensitive access operations that trigger the fault and the verification response conditions for observing the fault to form a ternary inference chain; converting the constraint labels into a constraint syntax tree of memory chip access rules; and connecting the constraint syntax tree of memory chip access rules with the ternary inference chain. The system associates data to form a fault grammar knowledge base. Based on this knowledge base, fault primitives are matched according to the testing objectives of the memory chip. Corresponding sensitive access operations and verification response conditions are extracted along the ternary inference chain. The execution path of the sensitive access operations is constrained according to the memory chip access rule constraint syntax tree to form a generation task. This task is input into the test case generation model, and AI-assisted test case generation is performed by combining sensitive access operations, verification response conditions, anomaly labels, and constrained execution paths to output candidate chip test cases. The executability of the candidate chip test cases is verified and filtered through the memory chip access rule constraint syntax tree to form a target test case set.

[0008] As a preferred embodiment of the intelligent generation method for memory chip test cases described in this invention, the steps of collecting test association information of the memory chip, parsing memory chip access rules from the test association information and extracting abnormal test fragments, converting memory chip access rules into constraint labels, and converting abnormal test fragments into abnormal labels to form basic data of the memory chip are as follows:

[0009] Collect the rule files and historical test record files of the memory chip before testing, and perform format standardization processing on the rule files and historical test record files to form test-related information;

[0010] The content that restricts the access process of the memory chip in the test association information is parsed to extract the access conditions and access restrictions of the memory chip during the test execution process, and to form the memory chip access rules;

[0011] Locate test records that show test failures and abnormal interruptions in the test association information, extract the test operations before the abnormal response and the feedback after the abnormal response to form abnormal test segments;

[0012] Semantic annotation is performed on memory chip access rules and abnormal test segments. The content that limits the test execution path in the memory chip access rules is converted into constraint tags, and the content that represents the abnormal triggering process and abnormal response status in the abnormal test segments is converted into abnormal tags. The constraint tags and abnormal tags are associated according to the test execution process to form the basic data of memory chips.

[0013] As a preferred embodiment of the intelligent generation method for memory chip test cases described in this invention, the steps of extracting fault primitives from the basic data of the memory chip, matching the fault primitives with the sensitive access operations that trigger the fault and the verification response conditions for observing the fault, and forming a ternary inference chain are as follows:

[0014] Based on the anomaly tags, the test operations before the anomaly response occurs and the feedback results after the anomaly response occurs are extracted. The test operations are taken as the anomaly triggering process and the feedback results are taken as the anomaly response status.

[0015] The failure phenomena in memory chip testing are identified based on the abnormal triggering process and abnormal response status, and the failure phenomena are categorized into fault primitives. The test operations allowed by the memory chip access rules are filtered based on constraint labels, and sensitive access operations are matched from the allowed test operations.

[0016] Based on the abnormal response state, feedback features reflecting the occurrence of fault primitives are extracted, and the feedback features are organized into verification response conditions.

[0017] The fault primitives, sensitive access operations, and verification response conditions are associated in the order from fault triggering to fault observation to form a ternary inference chain.

[0018] As a preferred embodiment of the intelligent generation method for memory chip test cases described in this invention, the specific steps for converting constraint labels into a memory chip access rule constraint syntax tree are as follows:

[0019] Based on constraint tags, extract the allowed test operations and their order of execution in the memory chip access rules, set the test operations as syntax nodes, and connect the syntax nodes in order to form the initial access path;

[0020] Based on the access conditions and access restrictions corresponding to the constraint labels, the access conditions and access restrictions are configured into the initial access path. The initial access path is then validated according to rules, and access paths that do not conform to the access rules of the storage chip are deleted to obtain the retained access path.

[0021] The syntax nodes and the reserved access paths are combined to form the memory chip access rule constraint syntax tree.

[0022] As a preferred embodiment of the intelligent generation method for memory chip test cases described in this invention, the specific steps for associating the memory chip access rule constraint syntax tree with the ternary inference chain to form a fault syntax knowledge base are as follows:

[0023] Extract the sensitive access operations from the ternary inference chain, match the sensitive access operations with the syntax nodes in the memory chip access rule constraint syntax tree, and obtain the syntax nodes corresponding to the sensitive access operations.

[0024] Based on the syntax node corresponding to the sensitive access operation, the access path of the corresponding syntax node is extracted along the memory chip access rule constraint syntax tree, and the access conditions and access restrictions in the access path are verified with the sensitive access operation.

[0025] When a sensitive access operation meets the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is bound to the corresponding access path. When a sensitive access operation does not meet the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is deleted, resulting in a filtering inference chain.

[0026] The filtering inference chain and the storage chip access rule constraint syntax tree are linked and stored together to form a fault syntax knowledge base.

[0027] As a preferred embodiment of the intelligent generation method for memory chip test cases described in this invention, the steps of matching fault primitives based on the fault syntax knowledge base and the testing purpose of the memory chip, extracting the corresponding sensitive access operations and verification response conditions along the ternary inference chain, and constraining the execution path of the sensitive access operations according to the memory chip access rule constraint syntax tree to form a generation task are as follows:

[0028] Based on the testing objectives of the memory chip, the fault primitives corresponding to the testing objectives are matched in the fault syntax knowledge base. Along the ternary inference chain where the fault primitives are located, the sensitive access operations and verification response conditions corresponding to the fault primitives are extracted.

[0029] The sensitive access operation is input into the memory chip access rule constraint syntax tree. The syntax node corresponding to the sensitive access operation is matched in the memory chip access rule constraint syntax tree. The execution path corresponding to the sensitive access operation is extracted along the connection relationship between the syntax nodes. The access conditions and access restrictions in the memory chip access rule constraint syntax tree are configured into the execution path.

[0030] The fault primitives, sensitive access operations, verification response conditions, and execution paths are combined to form a generation task.

[0031] As a preferred embodiment of the intelligent generation method for memory chip test cases described in this invention, the step of inputting the generation task into the test case generation model and combining it with sensitive access operations, verification response conditions, anomaly tags, and constrained execution paths to generate AI-assisted test cases and output candidate chip test cases is as follows:

[0032] The generated task is input into the test case generation model. The test case generation model parses the constrained execution path in the generated task and arranges the test operations according to the order of execution in the execution path to obtain the path sequence.

[0033] The sensitive access operation is embedded in the path sequence at the position corresponding to the fault trigger, and the operations that do not belong to the constrained execution path in the path sequence are deleted to obtain the trigger sequence. The operation features corresponding to the abnormal triggering process are extracted based on the abnormal label, and the operation features are added to the test position adjacent to the sensitive access operation in the trigger sequence to obtain the enhancement sequence.

[0034] Based on the verification response condition configuration, the feedback observation method corresponding to the enhancement sequence is configured, and the feedback observation method is associated with the enhancement sequence to obtain the test case framework. The test case generation model is used to semantically complete and format the test case framework to generate candidate chip test cases.

[0035] As a preferred embodiment of the intelligent generation method for memory chip test cases according to the present invention, the step of performing executability verification and screening of candidate chip test cases through a memory chip access rule constraint syntax tree to form a target test case set includes the following specific steps:

[0036] The execution path in the candidate chip test case is matched with the access path in the memory chip access rule constraint syntax tree to obtain the path matching result;

[0037] The access conditions in the candidate chip test cases are compared with the access conditions of the corresponding syntax nodes in the memory chip access rule constraint syntax tree to obtain the condition comparison results.

[0038] Based on the path matching results and condition comparison results, candidate chip test cases with mismatched execution paths and access conditions that do not conform to the memory chip access rules are filtered out to obtain executable candidate test cases.

[0039] The feedback observation methods in the executable candidate test cases are matched with the verification response conditions in the generation task. Executable candidate test cases that can provide feedback on fault responses are retained to form the target test case set.

[0040] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements any step of the intelligent generation method for memory chip test cases as described in the first aspect of the present invention.

[0041] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any step of the intelligent generation method for memory chip test cases as described in the first aspect of the present invention.

[0042] The beneficial effects of this invention are as follows: by converting constraint labels into a memory chip access rule constraint syntax tree, and associating the memory chip access rule constraint syntax tree with a ternary inference chain, a fault syntax knowledge base is formed. This achieves a structured and unified expression between memory chip access rules, sensitive access operations, and verification response conditions, improves the matching degree between candidate chip test cases and actual memory chip access rules, and enables test cases to simultaneously have fault triggering basis and response observation basis, thereby enhancing the executability, verifiability, and relevance of test case generation. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart of a method for intelligently generating test cases for memory chips.

[0045] Figure 2 A flowchart for constructing test-related information collection and basic data.

[0046] Figure 3 A flowchart for constructing a syntax tree for memory chip access rules.

[0047] Figure 4 A flowchart for building a fault grammar knowledge base.

[0048] Figure 5 This chart compares the executability of test cases for candidate chips under different generation methods.

[0049] Figure 6 This is a graph showing the performance changes of multiple metrics under different levels of complexity. Detailed Implementation

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0052] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0053] Reference Figures 1-6 This is one embodiment of the present invention, which provides a method for intelligently generating test cases for memory chips, including the following steps:

[0054] S1. Collect the test association information of the memory chip, parse the memory chip access rules from the test association information and extract abnormal test fragments, convert the memory chip access rules into constraint labels, convert the abnormal test fragments into abnormal labels, and form the basic data of the memory chip.

[0055] S1.1. Collect the rule files and historical test record files of the memory chip before testing, and perform unified format processing on the rule files and historical test record files to form test-related information.

[0056] Specifically, the system collects rule files and historical test record files generated before the storage chip is tested. Text is extracted from the access operation names, execution order, and execution conditions in the rule files, and fields are extracted from the test item names, operation times, and feedback results in the historical test record files. The extracted content is then formatted uniformly according to the same chip identifier, the same test item name, and the same test execution order to eliminate differences in field naming and record order between different files, forming test association information that can simultaneously represent the rule content before the storage chip is tested and the historical test execution content.

[0057] S1.2. Parse the content that restricts the access process of the memory chip in the test association information, extract the access conditions and access restrictions of the memory chip during the test execution process, and form the memory chip access rules.

[0058] Specifically, based on test association information, the content that restricts the memory chip access process is located within the test association information. For each item restricting the memory chip access process, the test operation name, the state that must be met before the test operation starts, the allowed sequence of test operations, and the boundaries that cannot be broken during the execution of the test operation are read item by item. The state that must be met before the test operation starts is organized into access conditions, and the allowed sequence of test operations and the boundaries that cannot be broken during the execution of the test operation are organized into access restrictions. Then, the access conditions and access restrictions are mapped to the test operations in the test execution process, forming memory chip access rules that can restrict the memory chip test execution process.

[0059] S1.3. Locate the test records that show test failures and abnormal interruptions in the test association information, extract the test operations before the abnormal response occurs and the feedback after the abnormal response occurs, and form abnormal test segments.

[0060] Specifically, based on test association information, test records that have failed or been interrupted are searched for in the test association information. The location of the test failure or interruption during the test execution process is used as the location. The test operations before the abnormal response occurred are traced back according to the execution order of the test records. At the same time, the feedback after the abnormal response occurred is read. The test operations before the abnormal response occurred and the feedback after the abnormal response occurred are associated with the same test execution process. Ordinary test records that did not participate in the abnormal triggering are removed to form an abnormal test segment that can characterize the abnormal triggering process and the abnormal response status.

[0061] S1.4. Semantically annotate the memory chip access rules and abnormal test segments. Convert the content that limits the test execution path in the memory chip access rules into constraint tags, and convert the content that represents the abnormal triggering process and abnormal response status in the abnormal test segments into abnormal tags. Associate the constraint tags and abnormal tags according to the test execution process to form the basic data of the memory chip.

[0062] Specifically, semantic annotation is performed on the memory chip access rules to identify the test operation sequence, access conditions and access restrictions from the memory chip access rules. The test operation sequence is labeled as path sequence constraints, the access conditions are labeled as operation preconditions, and the access restrictions are labeled as boundary constraints. The path sequence constraints, operation preconditions and boundary constraints are associated with the corresponding test operations to form constraint labels.

[0063] Semantic annotation is performed on abnormal test segments to identify the test operations before the abnormal response and the feedback after the abnormal response. The test operations before the abnormal response are labeled as abnormal triggering processes, and the feedback after the abnormal response is labeled as abnormal response states. The abnormal triggering processes and abnormal response states are associated with the same test execution process to form abnormal labels. The constraint labels and abnormal labels are associated with the same test execution process to form the basic data of the memory chip.

[0064] S2. Extract fault primitives from the basic data of the memory chip, match the sensitive access operation that triggers the fault and the verification response condition of the observed fault according to the fault primitives, form a ternary inference chain, convert the constraint label into a memory chip access rule constraint syntax tree, and associate the memory chip access rule constraint syntax tree with the ternary inference chain to form a fault syntax knowledge base.

[0065] S2.1. Extract the test operations before the occurrence of the abnormal response and the feedback results after the occurrence of the abnormal response based on the abnormal label. Treat the test operations as the abnormal triggering process and the feedback results as the abnormal response status.

[0066] Specifically, based on the exception labels, the content marked as the exception triggering process in the exception labels is read according to the recording order in the same test execution process to obtain the test operations that directly participated in the exception triggering before the exception response occurred;

[0067] Read the content marked as abnormal response status in the abnormal label to obtain the feedback result after the abnormal response occurs; take the obtained test operation as the abnormal triggering process and the obtained feedback result as the abnormal response status, and match the abnormal triggering process and abnormal response status according to the same test execution process to form an abnormal triggering process and abnormal response status that can be used to identify failure phenomena in memory chip testing.

[0068] S2.2. Identify failure phenomena in memory chip testing based on abnormal triggering process and abnormal response status, and classify failure phenomena into fault primitives. Filter test operations allowed by memory chip access rules based on constraint labels, and match sensitive access operations from the allowed test operations.

[0069] Specifically, based on the abnormal triggering process and abnormal response status, the test operation sequence before the abnormal response occurs is reconstructed according to the chronological order of the test execution process. Then, the test operation sequence is compared with the feedback results in the abnormal response status to obtain the failure phenomenon in the memory chip test caused by the test operation.

[0070] For failure phenomena in memory chip testing, failure phenomena with the same triggering method and the same feedback behavior are grouped into the same fault primitive according to the classification method of the same test operation causing the same feedback result; based on the constraint label, the test operations allowed to be executed in the memory chip access rules are read, and test operations that do not conform to the memory chip access rules are eliminated.

[0071] The allowed test operations are matched one by one with the test operations in the abnormal triggering process. Test operations that originate from the memory chip access rules and can trigger the failure phenomenon corresponding to the fault primitives again are retained to form sensitive access operations.

[0072] It should be noted that fault primitives are used to represent the minimum fault type that needs to be identified in memory chip testing. Fault primitives include failure causes obtained by merging abnormal triggering processes and abnormal response states.

[0073] Sensitized access operations are used to trigger the failure phenomena corresponding to fault primitives. Sensitized access operations include test operations that conform to the memory chip access rules and can trigger the corresponding failure phenomena again.

[0074] It should also be noted that the expression for the merge relation of fault primitives is:

[0075] ;

[0076] in, Indicates the first A fault primitive; Indicates the first One failure phenomenon; Indicates the first The abnormal triggering process category is obtained by classifying the abnormal triggering process corresponding to each failure phenomenon. Indicates the first The abnormal response status category is obtained by classifying the abnormal response status corresponding to each failure phenomenon. Indicates the first The category of abnormal triggering process corresponding to each fault primitive; Index variables representing failure phenomena; Indicates the fault primitive index variable; Indicates the first The abnormal response state category corresponding to each fault primitive; when the abnormal triggering process of the failure phenomenon belongs to Furthermore, the abnormal response state of the failure phenomenon belongs to At that time, the failure phenomena will be merged into the first... Fault primitives.

[0077] S2.3. Extract feedback features reflecting the occurrence of fault primitives based on abnormal response states, and organize the feedback features into verification response conditions.

[0078] Specifically, based on the abnormal response state, the feedback results in the abnormal response state are read, and the feedback results are matched with the failure phenomena corresponding to the fault primitives according to the test execution process corresponding to the feedback results. During the matching process, the content that can indicate test failure, abnormal interruption, or inconsistency between the feedback results and the expected execution state is used as the feedback feature reflecting the occurrence of the fault primitive.

[0079] Then, according to the fault primitives corresponding to the feedback features, the feedback features are organized into verification response conditions that can be used to observe whether the fault primitives occur, so that the verification response conditions can limit the feedback results that need to be observed after the fault primitives are triggered, thus forming verification response conditions.

[0080] It should be noted that the verification response conditions are used to observe whether the fault primitives are triggered. The verification response conditions include the feedback characteristics and feedback result requirements obtained from the abnormal response status.

[0081] S2.4. Associate the fault primitives, sensitive access operations, and verification response conditions in the order from fault triggering to fault observation to form a ternary inference chain.

[0082] Specifically, based on fault primitives, sensitive access operations, and verification response conditions, each fault primitive is used as an associated object. Sensitive access operations that can trigger the corresponding failure phenomenon of the fault primitive are written into the trigger position of the fault primitive, thus forming a trigger relationship between sensitive access operations and fault primitives.

[0083] Next, the verification response conditions that can reflect the occurrence of the fault primitive are written into the observation position of the fault primitive to form an observation relationship between the fault primitive and the verification response conditions. According to the order of the test execution process, the sensitive access operation, the fault primitive and the verification response conditions are arranged in sequence, so that the sensitive access operation is located at the fault trigger end, the fault primitive is located at the fault representation end and the verification response conditions are located at the fault observation end.

[0084] For each fault primitive, perform integrity checks on the sensitive access operation and verification response conditions. Delete fault primitive associations that lack sensitive access operations or verification response conditions, and retain fault primitive associations that simultaneously possess fault triggering end, fault characterization end, and fault observation end, forming a ternary inference chain.

[0085] It should be noted that the ternary inference chain is used to guide the generation of subsequent candidate chip test cases. The ternary inference chain includes the triggering and observation relationships between sensitive access operations, fault primitives, and verification response conditions.

[0086] S2.5. Extract the allowed test operations and their order of execution based on the constraint tags of the memory chip access rules, set the test operations as syntax nodes, and connect the syntax nodes in order to form the initial access path.

[0087] Specifically, based on constraint tags, the content marked as path order constraints in the constraint tags is read to obtain the test operations allowed to be executed by the memory chip access rules and the order of the test operations; then each allowed test operation is set as a syntax node, so that each syntax node corresponds to an executable action in the test execution process;

[0088] The syntax nodes are connected in sequence, so that the syntax node corresponding to the previous test operation points to the syntax node corresponding to the next test operation. During the connection process, test operation connections that do not appear in the constraint label are deleted, and test operation connections allowed by the memory chip access rules are retained. The connected syntax nodes are arranged according to the test execution process to form the initial access path.

[0089] S2.6. Based on the access conditions and access restrictions corresponding to the constraint labels, configure the access conditions and access restrictions into the initial access path, perform rule verification on the initial access path, delete access paths that do not conform to the access rules of the storage chip, and obtain the retained access path.

[0090] Specifically, based on the initial access path and constraint labels, the content marked as operation pre-constraints in the constraint labels is read to obtain the access conditions that need to be met before each test operation is executed. Then, the content marked as boundary limit constraints in the constraint labels is read to obtain the access restrictions that cannot be broken when each test operation is executed.

[0091] Configure access conditions to the entry position of the corresponding syntax node in the initial access path, so that the corresponding syntax node enters execution after the access conditions are met. Configure access restrictions to the execution position of the corresponding syntax node in the initial access path, so that the corresponding syntax node is subject to access restrictions during execution.

[0092] According to the storage chip access rules, each configured initial access path is validated. The rule validation includes verifying whether the syntax node entry position has the access conditions, verifying whether the syntax node execution position meets the access restrictions, and verifying whether the connection relationship between the syntax nodes before and after meets the storage chip access rules. Initial access paths that lack access conditions, exceed access restrictions, or whose connection relationship does not meet the storage chip access rules are deleted, and initial access paths that can be executed according to the access conditions and access restrictions are retained to obtain the retained access paths.

[0093] S2.7. Combine the syntax nodes and the reserved access paths to form a memory chip access rule constraint syntax tree.

[0094] Specifically, the syntax nodes are arranged according to the test execution order in the retained access path. The syntax node at the beginning of the test is taken as the access starting point, and the subsequent syntax nodes are attached in sequence according to the connection relationship in the retained access path. For syntax nodes with the same test operation in multiple retained access paths, the syntax nodes corresponding to the same test operation are merged, and different subsequent test operations are retained as different access branches.

[0095] Then, the access conditions and access restrictions already configured in the retained access path are written into the corresponding syntax nodes and the connection positions between the syntax nodes, so that each access branch has the corresponding execution premise and execution boundary; the syntax nodes that have been merged, attached and configured with conditions are organized together with the retained access path to form a storage chip access rule constraint syntax tree for constraining the subsequent test case generation path.

[0096] The memory chip access rule constraint syntax tree is used to limit the range of subsequent candidate chip test cases generated. The memory chip access rule constraint syntax tree includes syntax nodes, the connection relationship between syntax nodes, access conditions, access restrictions, and access branches formed by different test operation sequences.

[0097] S3. Based on the fault grammar knowledge base, match fault primitives according to the testing purpose of the memory chip, extract the corresponding sensitive access operations and verification response conditions along the ternary inference chain, and constrain the execution path of the sensitive access operations according to the memory chip access rule constraint syntax tree to form a generation task. Input the generation task into the test case generation model, and combine the sensitive access operations, verification response conditions, anomaly labels and constrained execution paths to generate AI-assisted test cases, and output candidate chip test cases.

[0098] S3.1. Extract the sensitive access operation from the ternary inference chain, match the sensitive access operation with the syntax node in the memory chip access rule constraint syntax tree, and obtain the syntax node corresponding to the sensitive access operation.

[0099] Specifically, the sensitive access operation corresponding to each fault primitive is read from the ternary inference chain to obtain the test operation name and fault trigger position of the sensitive access operation; then, the syntax nodes are searched one by one in the memory chip access rule constraint syntax tree to read the test operation name and test execution position corresponding to the syntax node.

[0100] The test operation name of the sensitive access operation is matched for consistency with the test operation name corresponding to the syntax node, and the fault trigger position of the sensitive access operation is matched for order with the test execution position of the syntax node. When the test operation name is consistent and the execution order can carry over the fault trigger process, the matched syntax node is taken as the syntax node corresponding to the sensitive access operation. When the test operation name is inconsistent or the execution order cannot carry over the fault trigger process, the corresponding syntax node is excluded, and the syntax node corresponding to the sensitive access operation is obtained.

[0101] S3.2. Based on the syntax node corresponding to the sensitive access operation, extract the access path of the corresponding syntax node along the memory chip access rule constraint syntax tree, and verify the access conditions and access restrictions in the access path with the sensitive access operation.

[0102] When a sensitive access operation meets the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is bound to the corresponding access path. When a sensitive access operation does not meet the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is deleted, resulting in a filtered inference chain.

[0103] Specifically, based on the syntax node corresponding to the sensitive access operation, the syntax node corresponding to the sensitive access operation is found in the storage chip access rule constraint syntax tree from the access starting point along the syntax node connection relationship. The syntax node connection relationship passed through during the search process, the access conditions configured at the syntax node entry position, and the access restrictions configured at the syntax node execution position are merged into the access path of the corresponding syntax node.

[0104] Check the execution state that must be met before the sensitive access operation triggers the fault primitive against the access conditions in the access path item by item, and check the operation sequence boundary, access state boundary and storage area boundary involved in the execution of the sensitive access operation against the access restrictions in the access path item by item.

[0105] When a sensitive access operation satisfies both the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is bound to the corresponding access path, so that the fault primitive, sensitive access operation and verification response condition in the ternary inference chain fall into the access path allowed by the memory chip access rules.

[0106] If the sensitive access operation does not simultaneously satisfy the access conditions and access restrictions in the access path, delete the ternary inference chain containing the sensitive access operation, and retain the ternary inference chain that can be bound to the access path to obtain the filtering inference chain.

[0107] S3.3. Link the filtering inference chain and the storage chip access rule constraint syntax tree to form a fault syntax knowledge base.

[0108] Specifically, the access path in the syntax tree of the memory chip access rule constraint is used as the associated storage location. Sensitized access operations that have been bound in the filtering inference chain are written to the fault triggering location of the corresponding access path. Fault primitives in the filtering inference chain are written to the fault representation location of the corresponding access path. Verification response conditions in the filtering inference chain are written to the fault observation location of the corresponding access path.

[0109] According to the relationship of "sensitized access operation triggers fault primitives, and verification response conditions observe fault primitives" under the same access path, the filtering inference chain is saved in correspondence with the syntax nodes, access conditions and access restrictions in the memory chip access rule constraint syntax tree, so that each access path can be mapped to executable fault trigger content and fault observation content.

[0110] Delete the filtering inference chain content that does not correspond to the access path, and retain the filtering inference chain content that can be carried by the syntax tree that can be constrained by the storage chip access rules, forming a fault syntax knowledge base.

[0111] The fault syntax knowledge base is used to provide executable fault testing basis for subsequent generation tasks. The fault syntax knowledge base includes access paths, fault primitives, sensitive access operations, verification response conditions, access conditions, and access restrictions.

[0112] S3.4. Based on the testing objectives of the memory chip, match the fault primitives corresponding to the testing objectives in the fault syntax knowledge base, and extract the sensitive access operations and verification response conditions corresponding to the fault primitives along the ternary inference chain where the fault primitives are located.

[0113] Specifically, the testing objectives of the memory chip are first collected, and then the testing objectives of the memory chip are matched with the fault primitives associated with the access paths in the fault syntax knowledge base to filter out the fault primitives that are consistent with the testing objectives of the memory chip. Then, using the filtered fault primitives as the search entry point, the ternary inference chain where the fault primitive is located is located in the fault syntax knowledge base, and the sensitive access operation that can trigger the fault primitive is read from the front end of the ternary inference chain, and the verification response condition that can be observed from the back end of the fault primitive is read.

[0114] Fault primitives, sensitive access operations, and verification response conditions are grouped together according to the same ternary inference chain, so that each fault primitive corresponds to a sensitive access operation to trigger the fault and a verification response condition to observe the fault, thus forming a fault generation basis corresponding to the testing purpose of the memory chip.

[0115] S3.5. Input the sensitive access operation into the memory chip access rule constraint syntax tree, match the syntax node corresponding to the sensitive access operation in the memory chip access rule constraint syntax tree, extract the execution path corresponding to the sensitive access operation along the connection relationship between the syntax nodes, and configure the access conditions and access restrictions in the memory chip access rule constraint syntax tree into the execution path.

[0116] Specifically, the sensitive access operation is written into the matching entry of the storage chip access rule constraint syntax tree, and the test operation name, fault trigger position, and required execution state for triggering in the sensitive access operation are read; then, the test operation name, test execution position, and node entry condition corresponding to each syntax node in the storage chip access rule constraint syntax tree are read item by item, the test operation name in the sensitive access operation is matched with the test operation name corresponding to the syntax node, the fault trigger position in the sensitive access operation is matched with the test execution position of the syntax node in the storage chip access rule constraint syntax tree, and the required execution state for triggering in the sensitive access operation is matched with the entry condition of the syntax node.

[0117] When the test operation name is consistent, the test execution position can connect to the fault trigger position, and the node entry condition can meet the execution state required for triggering, the corresponding syntax node is retained.

[0118] When the test operation name is inconsistent, the test execution position cannot connect to the fault trigger position, or the node entry condition cannot meet the execution state required for triggering, the corresponding syntax node is excluded, and the syntax node corresponding to the sensitive access operation is obtained.

[0119] Locate the syntax node corresponding to the sensitive access operation in the memory chip access rule constraint syntax tree. Then, along the connection relationship between the syntax nodes in the memory chip access rule constraint syntax tree, read the syntax nodes that pass from the access start point to the syntax node corresponding to the sensitive access operation, and read the syntax nodes that pass from the syntax node corresponding to the sensitive access operation to the feedback observation position. Arrange them according to the order of connection between the syntax nodes to form the execution path corresponding to the sensitive access operation.

[0120] By constraining the access conditions and access restrictions in the syntax tree corresponding to the execution path through the memory chip access rules, the access conditions are configured to the entry position of the corresponding syntax node in the execution path, so that the execution path can limit the state that each test operation needs to meet before execution.

[0121] Configure access restrictions at the execution location of the corresponding syntax node in the execution path so that the execution path can limit the boundaries that cannot be broken during the execution of each test operation; write the configured access conditions, access restrictions and syntax node connection order into the execution path to form an execution path constrained by the syntax tree of the memory chip access rules.

[0122] S3.6. Combine fault primitives, sensitive access operations, verification response conditions, and execution paths to form a generation task.

[0123] Specifically, fault primitives are used as the test targets of the generation task. The fault primitives are written into the generation task to indicate the content location of the failure phenomenon to be triggered. Then, the sensitive access operation is written into the syntax node position corresponding to the fault trigger in the execution path, so that the generation task clearly indicates that the test operation in the execution path triggers the fault primitive.

[0124] Write the verification response conditions into the syntax node position corresponding to the fault observation in the execution path, so that the generated task clearly defines the feedback results to be observed after the fault primitive is triggered; arrange the fault primitive, sensitive access operation and verification response conditions in groups according to the test execution order in the execution path, and retain the access conditions and access restrictions in the execution path, so that the generated task simultaneously contains the fault test target, fault triggering method, fault observation method and executable test order, thus forming the generated task.

[0125] S3.7. Input the generated task into the test case generation model, parse the constrained execution path in the generated task through the test case generation model, and arrange the test operations according to the order of execution in the execution path to obtain the path sequence.

[0126] Specifically, the task is input into the test case generation model. The model, based on the execution path in the task, identifies the sequential relationship of test operations according to the connection order between syntax nodes in the execution path. The model then reads the access conditions and restrictions corresponding to each syntax node in the execution path, configuring the access conditions before the corresponding test operation and the access restrictions during the execution of the corresponding test operation. The model then arranges the test operations according to the execution path, from the access start point to the fault trigger position and then to the fault observation position, deleting test operations that do not belong to the execution path and retaining those that can handle sensitive access operations and verify response conditions. Finally, the model organizes the retained test operations according to the sequential relationship in the execution path to obtain a path sequence. This path sequence represents the test operation skeleton of the candidate chip test cases, including the test operations arranged according to the execution path, the sequential relationship between test operations, the access conditions corresponding to the test operations, the access restrictions corresponding to the test operations, and the fault trigger position corresponding to the sensitive access operation.

[0127] It should be noted that the test case generation model is obtained by training an existing LSTM-Seq2Seq model, which includes an input layer, encoder, context vector, decoder and output layer.

[0128] The input layer receives the input training sequence obtained from the generation task. The encoder performs temporal encoding on the fault primitives, sensitive access operations, verification response conditions, anomaly labels, and constrained execution paths in the input training sequence. The context vector represents the test target, fault trigger content, feedback observation requirements, anomaly trigger features, and path constraint information in the input training sequence. The decoder generates the test operation sequence, fault trigger location, and feedback observation method step by step based on the context vector. The output layer organizes the decoder output into candidate chip test cases.

[0129] When training the test case generation model, historical generated tasks and candidate chip test cases that have passed executability verification are collected. The historical generated tasks are used as input samples, and the candidate chip test cases that have passed executability verification are used as output samples. The fault primitives, sensitive access operations, verification response conditions, anomaly labels, and constrained execution paths in the historical generated tasks are ordered so that fault primitives correspond to test objectives, sensitive access operations correspond to fault triggering content, verification response conditions correspond to feedback observation requirements, anomaly labels correspond to anomaly triggering features, and constrained execution paths correspond to the allowed order of test operations, thus forming the input training sequence.

[0130] The test cases of candidate chips that have passed executability verification are sequentially organized. The test operation sequence, fault trigger location, feedback observation method, access condition, and access restriction in the test cases of candidate chips that have passed executability verification are extracted. The test operation sequence, fault trigger location, feedback observation method, access condition, and access restriction are arranged according to the test operation execution order to form an output training sequence. The input training sequence is input into the LSTM-Seq2Seq model, and the output training sequence is used as the target output of the LSTM-Seq2Seq model. Through sequence mapping training, the LSTM-Seq2Seq model learns the correspondence between historical generation tasks and test cases of candidate chips that have passed executability verification, resulting in a trained LSTM-Seq2Seq model. The trained LSTM-Seq2Seq model is then used as the test case generation model.

[0131] S3.8. Embed the sensitive access operation into the path sequence at the position corresponding to the fault trigger, and delete the operations in the path sequence that do not belong to the constrained execution path to obtain the trigger sequence. Extract the operation features corresponding to the abnormal triggering process based on the abnormal label, and add the operation features to the test position adjacent to the sensitive access operation in the trigger sequence to obtain the enhancement sequence.

[0132] Specifically, by matching the test operation names, required execution states, and fault triggering locations in the sensitive access operations with the test operation locations in the path sequence, based on the sequence of test operations, access conditions, access restrictions, and fault triggering locations in the path sequence.

[0133] When there is a test operation position in the path sequence that corresponds to the fault trigger position, the sensitive access operation is written to the fault trigger position, so that the path sequence contains a test operation that can trigger the fault primitive at the fault trigger position.

[0134] The path sequence after the sensitive access operation is written is compared with the constrained execution path item by item. Test operations that do not appear in the constrained execution path are deleted, as are test operations that do not meet the access conditions or exceed the access restrictions. Test operations that are located in the constrained execution path and can accept the sensitive access operation are retained. The test operations are rearranged according to the order of the retained test operations to obtain the trigger sequence.

[0135] Based on the test operation name, test operation sequence, pre-trigger access conditions, and adjacent operations of the exception response corresponding to the exception triggering process, the test operation name is used to represent the specific operation involved in the exception triggering process, the test operation sequence is used to represent the execution order before and after the exception triggering process occurs, the pre-trigger access conditions are used to represent the execution state that needs to be met before the exception triggering process occurs, and the adjacent operations of the exception response are used to represent the test operation closest to the exception response. The above content forms the operation features. Then, the test position of the sensitive access operation is located in the triggering sequence, and the operation features are matched with the sensitive access operation. The operation features that are consistent with the triggering direction of the sensitive access operation are added to the adjacent test positions before or after the sensitive access operation, while retaining the original access conditions and access restrictions in the triggering sequence. This makes the triggering sequence not only include the sensitive access operation, but also the adjacent operation content in the historical exception triggering process, resulting in an enhanced sequence.

[0136] S3.9. Configure the feedback observation method corresponding to the enhancement sequence based on the verification response conditions, and associate the feedback observation method with the enhancement sequence to obtain the test case framework. Use the test case generation model to semantically complete and format the test case framework to generate candidate chip test cases.

[0137] Specifically, based on the feedback characteristics and feedback result requirements used to observe the occurrence of fault primitives in the verification response conditions, the sensitive access operation and the test position used for feedback reading, verification or abnormal interruption record after the sensitive access operation are located in the enhancement sequence.

[0138] The feedback features are written into the corresponding feedback read position or verification position in the enhancement sequence, and the feedback result requirements are written into the output requirements corresponding to the feedback read position or verification position to form a feedback observation method.

[0139] The feedback observation method is associated with the sensitized access operation, operation characteristics, access conditions and access restrictions in the enhancement sequence, so that the enhancement sequence can collect feedback results according to the verification response conditions after the fault primitive is triggered.

[0140] The enhanced sequences and feedback observation methods that have been associated are organized into a use case framework, resulting in a use case framework that can simultaneously represent the test operation sequence, fault trigger content, and feedback observation requirements. The use case framework is used to provide the basic structure for candidate chip test cases.

[0141] The test case generation model semantically completes the test case framework. By using the enhancement sequence, feedback observation method, access conditions and access restrictions in the test case framework, the execution content corresponding to each test operation is supplemented according to the test operation order in the enhancement sequence, so that each test operation has a clear operation name, execution position and sequential relationship.

[0142] Then, supplement the feedback reading content and verification content after the fault primitive is triggered according to the feedback observation method, so that the candidate chip test cases can observe and verify the feedback results corresponding to the response conditions after the sensitive access operation is completed; perform consistency sorting on the completed test operations according to the access conditions and access restrictions, delete the execution content that is inconsistent with the access conditions and access restrictions, and retain the test operations that can be executed along the constrained execution path.

[0143] The test case generation model arranges the completed test operations, sensitive access operations, feedback observation methods, access conditions, and access restrictions according to a unified test case format to generate candidate chip test cases.

[0144] S4. The executableness of candidate chip test cases is verified and filtered by the syntax tree of memory chip access rules to form a target test case set.

[0145] S4.1. Match the execution path in the candidate chip test case with the access path in the memory chip access rule constraint syntax tree to obtain the path matching result.

[0146] Specifically, the execution path in the candidate chip test cases is expanded according to the test operation sequence to obtain the test operation sequence, the access conditions corresponding to the test operations, and the access restrictions corresponding to the test operations; then, the access path in the memory chip access rule constraint syntax tree is expanded according to the syntax node connection relationship to obtain the syntax node connection relationship, the access conditions corresponding to the syntax nodes, and the access restrictions corresponding to the syntax nodes.

[0147] The test operation sequence is matched with the syntax node connection relationship item by item, so that each test operation in the candidate chip test case corresponds to a syntax node in the memory chip access rule constraint syntax tree.

[0148] When the test operation sequence can completely correspond to the syntax node connection relationship, a path matching result is formed where the execution path and the access path match. When the test operation sequence lacks a corresponding syntax node or the test operation sequence is inconsistent with the syntax node connection relationship, a path matching result is formed where the execution path and the access path do not match. The path matching result is used to indicate whether the execution path in the candidate chip test case conforms to the access path in the memory chip access rule constraint syntax tree. The path matching result includes execution path and access path matching and execution path and access path not matching.

[0149] S4.2. Compare the access conditions in the candidate chip test cases with the access conditions of the corresponding syntax nodes in the memory chip access rule constraint syntax tree to obtain the condition comparison results.

[0150] Specifically, the candidate chip test cases that correspond to the memory chip access rule constraint syntax tree in the path matching results are used as comparison objects. The access conditions in the candidate chip test cases are expanded item by item according to the test operation order in the candidate chip test cases, and the access conditions of the corresponding syntax nodes are expanded according to the syntax node connection relationship in the memory chip access rule constraint syntax tree.

[0151] The access conditions in the candidate chip test cases at the same test operation position are compared with the access conditions of the corresponding syntax node. First, it is compared whether the access conditions in the candidate chip test cases have the operation prerequisite state required by the corresponding syntax node. Then, it is compared whether the access conditions in the candidate chip test cases fall within the execution range allowed by the corresponding syntax node. Finally, it is compared whether the access conditions in the candidate chip test cases are consistent with the connection relationship before and after the corresponding syntax node.

[0152] When an access condition has a prerequisite state, falls within the execution scope, and is consistent with the preceding and following connections, a condition comparison result of access condition matching is formed; when an access condition lacks a prerequisite state, exceeds the execution scope, or is inconsistent with the preceding and following connections, a condition comparison result of access condition mismatch is formed. The condition comparison result is used to indicate whether the access condition in the candidate chip test case conforms to the access condition of the corresponding syntax node in the memory chip access rule constraint syntax tree. The condition comparison result includes access condition matching and access condition mismatch.

[0153] S4.3. Based on the path matching results and condition comparison results, candidate chip test cases that do not match the execution path or whose access conditions do not conform to the memory chip access rules are eliminated to obtain executable candidate test cases.

[0154] Specifically, candidate chip test cases marked as having mismatched execution paths are included in the scope of elimination, and candidate chip test cases marked as having mismatched access conditions are included in the scope of elimination.

[0155] The candidate chip test cases are matched with the scope to be eliminated. Candidate chip test cases that do not match the execution path or whose access conditions do not conform to the memory chip access rules are deleted. The candidate chip test cases that are not deleted are retained so that the retained candidate chip test cases have both the execution path consistent with the memory chip access rule constraint syntax tree and the access conditions consistent with the corresponding syntax node. The retained candidate chip test cases are used as executable candidate test cases that can be executed according to the memory chip access rules.

[0156] It should be noted that, Figure 5 This indicates the ability of candidate chip test cases obtained by different test case generation methods to be converted into executable candidate test cases under different simulation scenario complexities. The three curves in the figure correspond to three generation methods. Control group 1: Historical test record generation, which means that test cases are generated only based on historical test operations, historical feedback results and abnormal records in historical test record files, without building a memory chip access rule constraint syntax tree, and without associating the test case generation process with the ternary inference chain.

[0157] Control group 2 refers to using memory chip access rules for general rule matching when generating candidate chip test cases, such as verifying the test operation sequence and some access conditions, but not converting constraint labels into memory chip access rule constraint syntax trees, nor associating memory chip access rule constraint syntax trees with ternary inference chains to form a fault syntax knowledge base.

[0158] The method of this invention refers to converting constraint tags into a memory chip access rule constraint syntax tree, associating the memory chip access rule constraint syntax tree with a ternary inference chain to form a fault syntax knowledge base, generating candidate chip test cases based on the fault syntax knowledge base, and performing execution path matching and access condition comparison through the memory chip access rule constraint syntax tree to obtain executable candidate test cases. Figure 5 As can be seen, as the complexity of the simulation scenario increases from the first to the third level, the feasibility of all three methods decreases, but the experimental group always maintains the highest level.

[0159] S4.4. Match the feedback observation methods in the executable candidate use cases with the verification response conditions in the generation task, retain the executable candidate use cases that can provide feedback on fault responses, and form the target use case set.

[0160] Specifically, the test location of the feedback observation method is located according to the test operation sequence in the executable candidate test cases, and the feedback reading location, verification location and feedback result requirements in the feedback observation method are matched item by item with the verification response conditions in the generated task;

[0161] When the feedback reading position or verification position in the feedback observation method can take over the feedback observation process after the sensitive access operation, and the feedback result is required to cover the feedback features in the verification response condition that reflect the occurrence of the fault primitive, the corresponding executable candidate test case is retained.

[0162] When the feedback observation method cannot handle the feedback observation process after the sensitive access operation, or when the feedback result cannot cover the feedback features in the verification response conditions, the corresponding executable candidate test cases are deleted; the remaining executable candidate test cases are then grouped according to the corresponding fault primitives to form the target test case set.

[0163] It should be noted that, as Figure 6 The figure shows the changes of multiple evaluation metrics under different simulation scenario complexities. The horizontal axis represents the simulation scenario complexity, and the vertical axis represents the proportion. The multiple curves in the figure correspond to different evaluation metrics, including path matching rate, access condition matching rate, executability rate, fault triggering rate, fault response feedback rate, and target fault coverage rate.

[0164] Among them, the path matching rate reflects whether the execution path in the candidate chip test case is consistent with the access path in the memory chip access rule constraint syntax tree; the access condition matching rate reflects whether the access conditions in the candidate chip test case meet the access conditions of the corresponding syntax node in the memory chip access rule constraint syntax tree; the executable rate reflects the proportion of candidate chip test cases that form executable candidate cases after execution path matching and access condition comparison; the fault triggering rate reflects whether the executable candidate cases contain sensitive access operations that can trigger fault primitives; the fault response feedback rate reflects whether the feedback observation method in the executable candidate cases can meet the verification response conditions; and the target fault coverage rate reflects the degree of coverage of the target test case set on the fault primitives corresponding to the test objective.

[0165] This embodiment also provides a computer device applicable to the intelligent generation method for memory chip test cases, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the intelligent generation method for memory chip test cases as proposed in the above embodiment.

[0166] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0167] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the intelligent generation method for memory chip test cases as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0168] In summary, this invention achieves a structured and unified expression between memory chip access rules, sensitive access operations, and verification response conditions by: transforming constraint labels into a memory chip access rule constraint syntax tree, and associating the memory chip access rule constraint syntax tree with a ternary inference chain to form a fault syntax knowledge base. This improves the matching degree between candidate chip test cases and actual memory chip access rules, and enables test cases to simultaneously possess fault triggering basis and response observation basis, thereby enhancing the executability, verifiability, and relevance of test case generation.

[0169] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for intelligently generating test cases for memory chips, characterized in that, include: Collect test association information of memory chips, parse memory chip access rules from test association information and extract abnormal test fragments, convert memory chip access rules into constraint labels, convert abnormal test fragments into abnormal labels, and form basic data of memory chips; Extract fault primitives from the basic data of the memory chip, match the sensitive access operation that triggers the fault and the verification response condition of the observed fault according to the fault primitives to form a ternary inference chain, convert the constraint label into a memory chip access rule constraint syntax tree, and associate the memory chip access rule constraint syntax tree with the ternary inference chain to form a fault syntax knowledge base. Based on the fault grammar knowledge base, fault primitives are matched according to the testing purpose of the memory chip. The corresponding sensitive access operations and verification response conditions are extracted along the ternary inference chain. The execution path of the sensitive access operations is constrained according to the memory chip access rule constraint syntax tree to form a generation task. The generation task is input into the test case generation model. The sensitive access operations, verification response conditions, anomaly labels and constrained execution paths are combined to generate AI-assisted test cases and output candidate chip test cases. The executableness of candidate chip test cases is verified and filtered by constraining the syntax tree of memory chip access rules, forming a target test case set.

2. The intelligent generation method for memory chip test cases as described in claim 1, characterized in that, The process of collecting test association information of the memory chip, parsing memory chip access rules from the test association information and extracting abnormal test fragments, converting memory chip access rules into constraint labels, and converting abnormal test fragments into abnormal labels to form basic data of the memory chip, is as follows: Collect the rule files and historical test record files of the memory chip before testing, and perform format standardization processing on the rule files and historical test record files to form test-related information; The content that restricts the access process of the memory chip in the test association information is parsed to extract the access conditions and access restrictions of the memory chip during the test execution process, and to form the memory chip access rules; Locate test records that show test failures and abnormal interruptions in the test association information, extract the test operations before the abnormal response and the feedback after the abnormal response to form abnormal test segments; Semantic annotation is performed on memory chip access rules and abnormal test segments. The content that limits the test execution path in the memory chip access rules is converted into constraint tags, and the content that represents the abnormal triggering process and abnormal response status in the abnormal test segments is converted into abnormal tags. The constraint tags and abnormal tags are associated according to the test execution process to form the basic data of memory chips.

3. The intelligent generation method for memory chip test cases as described in claim 2, characterized in that, The process involves extracting fault primitives from the basic data of the memory chip, matching the fault primitives with the sensitive access operations that trigger the fault, and observing the verification response conditions of the fault to form a ternary inference chain. The specific steps are as follows: Based on the anomaly tags, the test operations before the anomaly response occurs and the feedback results after the anomaly response occurs are extracted. The test operations are taken as the anomaly triggering process and the feedback results are taken as the anomaly response status. The failure phenomena in memory chip testing are identified based on the abnormal triggering process and abnormal response status, and the failure phenomena are categorized into fault primitives. The test operations allowed by the memory chip access rules are filtered based on constraint labels, and sensitive access operations are matched from the allowed test operations. Based on the abnormal response state, feedback features reflecting the occurrence of fault primitives are extracted, and the feedback features are organized into verification response conditions. The fault primitives, sensitive access operations, and verification response conditions are associated in the order from fault triggering to fault observation to form a ternary inference chain.

4. The intelligent generation method for memory chip test cases as described in claim 3, characterized in that, The specific steps for converting constraint labels into a memory chip access rule constraint syntax tree are as follows: Based on constraint tags, extract the allowed test operations and their order of execution in the memory chip access rules, set the test operations as syntax nodes, and connect the syntax nodes in order to form the initial access path; Based on the access conditions and access restrictions corresponding to the constraint labels, the access conditions and access restrictions are configured into the initial access path. The initial access path is then validated according to rules, and access paths that do not conform to the access rules of the storage chip are deleted to obtain the retained access path. The syntax nodes and the reserved access paths are combined to form the memory chip access rule constraint syntax tree.

5. The intelligent generation method for memory chip test cases as described in claim 4, characterized in that, The steps for associating the memory chip access rule constraint syntax tree with the ternary inference chain to form a fault syntax knowledge base are as follows: Extract the sensitive access operations from the ternary inference chain, match the sensitive access operations with the syntax nodes in the memory chip access rule constraint syntax tree, and obtain the syntax nodes corresponding to the sensitive access operations. Based on the syntax node corresponding to the sensitive access operation, the access path of the corresponding syntax node is extracted along the memory chip access rule constraint syntax tree, and the access conditions and access restrictions in the access path are verified with the sensitive access operation. When a sensitive access operation meets the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is bound to the corresponding access path. When a sensitive access operation does not meet the access conditions and access restrictions in the access path, the ternary inference chain containing the sensitive access operation is deleted, resulting in a filtering inference chain. The filtering inference chain and the storage chip access rule constraint syntax tree are linked and stored together to form a fault syntax knowledge base.

6. The intelligent generation method for memory chip test cases as described in claim 5, characterized in that, The process involves using a fault grammar knowledge base to match fault primitives based on the testing objectives of the memory chip, extracting corresponding sensitive access operations and verification response conditions along a ternary inference chain, and constraining the execution path of the sensitive access operations according to the memory chip access rule constraint syntax tree to generate a task. The specific steps are as follows: Based on the testing objectives of the memory chip, the fault primitives corresponding to the testing objectives are matched in the fault syntax knowledge base. Along the ternary inference chain where the fault primitives are located, the sensitive access operations and verification response conditions corresponding to the fault primitives are extracted. The sensitive access operation is input into the memory chip access rule constraint syntax tree. The syntax node corresponding to the sensitive access operation is matched in the memory chip access rule constraint syntax tree. The execution path corresponding to the sensitive access operation is extracted along the connection relationship between the syntax nodes. The access conditions and access restrictions in the memory chip access rule constraint syntax tree are configured into the execution path. The fault primitives, sensitive access operations, verification response conditions, and execution paths are combined to form the generation task.

7. The intelligent generation method for memory chip test cases as described in claim 6, characterized in that, The process involves generating task input test case generation models, combining sensitive access operations, verification response conditions, anomaly labels, and constrained execution paths to generate AI-assisted test cases, and outputting candidate chip test cases. The specific steps are as follows: The generated task is input into the test case generation model. The test case generation model parses the constrained execution path in the generated task and arranges the test operations according to the order of execution in the execution path to obtain the path sequence. The sensitive access operation is embedded in the path sequence at the position corresponding to the fault trigger, and the operations that do not belong to the constrained execution path in the path sequence are deleted to obtain the trigger sequence. The operation features corresponding to the abnormal triggering process are extracted based on the abnormal label, and the operation features are added to the test position adjacent to the sensitive access operation in the trigger sequence to obtain the enhancement sequence. Based on the verification response condition configuration, the feedback observation method corresponding to the enhancement sequence is configured, and the feedback observation method is associated with the enhancement sequence to obtain the test case framework. The test case generation model is used to semantically complete and format the test case framework to generate candidate chip test cases.

8. The intelligent generation method for memory chip test cases as described in claim 7, characterized in that, The step of performing executability verification and screening of candidate chip test cases through the memory chip access rule constraint syntax tree to form a target test case set is as follows: The execution path in the candidate chip test case is matched with the access path in the memory chip access rule constraint syntax tree to obtain the path matching result; The access conditions in the candidate chip test cases are compared with the access conditions of the corresponding syntax nodes in the memory chip access rule constraint syntax tree to obtain the condition comparison results. Based on the path matching results and condition comparison results, candidate chip test cases with mismatched execution paths and access conditions that do not conform to the memory chip access rules are filtered out to obtain executable candidate test cases. The feedback observation methods in the executable candidate test cases are matched with the verification response conditions in the generation task. Executable candidate test cases that can provide feedback on fault responses are retained to form the target test case set.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the intelligent generation method for memory chip test cases according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the intelligent generation method for memory chip test cases according to any one of claims 1 to 8.

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