A cache coherency verification system and method

Abstract

This invention provides a cache consistency verification system and method, relating to the field of accelerator card function verification. The system can add a test request module and a test response module to a first accelerator card and a second accelerator card respectively. These modules guide the first device consistency module in the first accelerator card and the second device consistency module in the second accelerator card to execute the cache consistency processing flow. The test request module and the test response module can also record the data read by the first and second device consistency modules and report the recorded data to the host for verification. Thus, through hardware-level guidance, the cache consistency function of the first and second accelerator cards can be verified.

Description

Technical Field

[0001] This invention relates to the field of accelerator card function verification, and in particular to a cache consistency verification system and method. Background Technology

[0002] To improve the efficiency of heterogeneous computing, a cache coherency function can be set in the accelerator card. This function allows multiple accelerator cards to use the data in the memory of one of the accelerator cards during the computing process, without the need for the central processing unit to transfer data between the accelerator cards.

[0003] In related technologies, since the cache coherency function of the accelerator card is implemented by the underlying hardware and does not require the participation of the central processing unit, it cannot be tested and verified by running test software in the central processing unit. Summary of the Invention

[0004] The purpose of this invention is to provide a cache consistency verification system and method, which can verify the cache consistency function between the first accelerator card and the second accelerator card through hardware-level boot.

[0005] To address the aforementioned technical problems, this invention provides a cache consistency verification system, comprising: A first accelerator card, a second accelerator card, and a host are connected together; the first accelerator card is connected to the second accelerator card, and the host is connected to both the first and second accelerator cards. The first accelerator card includes a first memory, a first device consistency module, and a test request module; the second accelerator card includes a second device consistency module and a test response module. The test request module is used to control the first device consistency module to write first data to the first memory according to a preset address; send the preset address to the test response module; initiate a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module; and report the third data to the host. The test response module is used to initiate a read operation to the second device consistency module according to a preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it; controls the second device consistency module to modify the cached first data to the second data; and reports the first data and the second data to the host. The host is used to verify the cache consistency between the first and second accelerator cards based on the received reported data.

[0006] This invention also provides a cache consistency verification method, applied to a cache consistency verification system. The cache consistency verification system includes a first accelerator card, a second accelerator card, and a host. The first accelerator card is connected to the second accelerator card, and the host is connected to both the first and second accelerator cards. The first accelerator card includes a first memory, a first device consistency module, and a test request module. The second accelerator card includes a second device consistency module and a test response module. The methods include: The test request module controls the first device consistency module to write the first data to the first memory according to the preset address; The test request module sends a preset address to the test response module; The test response module initiates a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it; The test response module controls the second device consistency module to modify the cached first data to the second data; The test response module reports the first and second data to the host; The test request module initiates a read operation to the first device consistency module according to a preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module. The test request module reports third-party data to the host; The host verifies the cache consistency between the first and second accelerator cards based on the received reported data.

[0007] This invention provides a cache consistency verification system, comprising: a first accelerator card, a second accelerator card, and a host; the first accelerator card is connected to the second accelerator card, and the host is connected to both the first and second accelerator cards; the first accelerator card includes a first memory, a first device consistency module, and a test request module; the second accelerator card includes a second device consistency module and a test response module; the test request module is used to control the first device consistency module to write first data to the first memory according to a preset address; send the preset address to the test response module; initiate a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module; and report the third data to the host; the test response module is used to initiate a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it; control the second device consistency module to modify the cached first data to second data; and report the first data and the second data to the host; the host is used to verify the cache consistency function of the first and second accelerator cards based on the received reported data.

[0008] The beneficial effects of this invention are as follows: This invention can add a hardware module for verifying cache consistency functionality to the first accelerator card and the second accelerator card. Specifically, a test request module can be added to the first accelerator card, and a test response module can be added to the second device consistency module. During testing, the test request module can control the first device consistency module in the first accelerator card to write first data to the first memory in the first accelerator card according to a preset address, and send the preset address to the test response module. The test response module initiates a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it. Subsequently, the test response module can also control the second device consistency module to modify the cached first data to second data. Then, the test response module can report the first data and the second data to the host. The test request module can initiate a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module. Subsequently, the test request module reports the third data to the host. The host can then verify the cache consistency functionality of the first and second accelerator cards based on the data reported by the test request module and the test response module. In this way, by setting up a test request module and a test response module to guide the first device consistency module and the second device consistency module to execute the cache consistency process in the underlying hardware, and recording the data read by the first device consistency module and the second device consistency module and reporting it to the host for comparison, the present invention can verify the cache consistency function of the first accelerator card and the second accelerator card in the underlying hardware.

[0009] The present invention also provides a cache consistency verification method, which has the above-mentioned beneficial effects. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0011] Figure 1 This is a block diagram of the structure of an existing heterogeneous computing system; Figure 2 This is a structural block diagram of a first cache consistency verification system provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a second cache consistency verification system provided in an embodiment of the present invention; Figure 4This is a structural block diagram of the third cache consistency verification system provided in an embodiment of the present invention; Figure 5 This is a flowchart of a cache consistency verification method provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] To improve the efficiency of heterogeneous computing, a cache coherency function can be set in the accelerator card. This function allows multiple accelerator cards to use the data in the memory of one of the accelerator cards during the computing process, without the need for the central processing unit to transfer data between the accelerator cards.

[0014] When verifying the cache coherency function of an accelerator card, there are two main issues. First, since the cache coherency function is implemented by the underlying hardware and does not require the involvement of the central processing unit (CPU), it cannot be verified by running test software on the CPU. Second, because multiple accelerator cards are typically connected via a host, and cache coherency can also be configured between the host and the accelerator cards, it is difficult to rule out the influence of the host on the accelerator cards during functional verification. For easier understanding, please refer to [link to documentation]. Figure 1 , Figure 1 The diagram shows the structural block of an existing heterogeneous computing system. Accelerator card 1 and accelerator card 2 are interconnected via a switch, which is also connected to a processor. In this case, the processor is located in the communication link between accelerator card 1 and accelerator card 2. When verifying the cache coherency mechanism between accelerator card 1 and accelerator card 2, it is difficult to eliminate interference from the central processing unit.

[0015] In view of this, to address the technical problem of how to effectively verify the cache consistency function of an accelerator card, the present invention provides a cache consistency verification system. A dedicated hardware module for function verification can be set in the accelerator card, and the cache consistency function of the first accelerator card and the second accelerator card can be verified through hardware-level boot.

[0016] The cache consistency verification system provided in this embodiment is described below. Please refer to... Figure 2 , Figure 2This is a structural block diagram of a first cache consistency verification system provided in an embodiment of the present invention. The system may include a first accelerator card, a second accelerator card, and a host. The first accelerator card is connected to the second accelerator card, and the host is connected to both the first and second accelerator cards. The first accelerator card may include a first device consistency module, a test request module, and first memory. The first device consistency module is connected to the test request module and the first memory. The second accelerator card may include a second device consistency module and a test response module. The second device consistency module is connected to the test response module. A high-speed interconnect link is provided between the first and second accelerator cards, and the first device consistency module and the test request module communicate with the second device consistency module and the test response module through this high-speed interconnect link. Furthermore, the test request module and the test response module are connected to the host.

[0017] It should be noted that the test request module and the test response module are hardware modules. This embodiment does not limit the hardware implementation of these two modules; for example, they can be based on programmable logic devices. The type of programmable logic device can be selected as needed, such as an FPGA (Field Programmable Gate Array) or other programmable logic devices.

[0018] It should be noted that this embodiment does not limit the connection method between the test request module, the test response module, and the host. The connection can be configured according to actual application requirements. For example, the test request module and the test response module can connect to the host via a bus interface, which can be any type of bus interface, such as the JTAG interface (Joint Test Action Group). It is important to note that in this embodiment, the test request module, the test response module, and the host only transmit test data; the host will not interact with the device consistency modules in the first and second accelerator cards, thus avoiding interference with test verification.

[0019] Furthermore, this embodiment does not limit the specific high-speed interconnect link and link structure, and can refer to relevant technologies of high-speed interconnect protocols. A high-speed interconnect protocol is a protocol that supports memory sharing, cache coherency processing, and improves communication between the processor and accelerators and memory expansion devices. Examples include the CXL protocol (Compute Express Link), the CCIX protocol (Cache Coherent Interconnect for Accelerators), and the UCIe protocol (Universal Chiplet Interconnect Express).

[0020] In one embodiment, the first accelerator card further includes a first multiplexer and a first high-speed interconnect module, with the first device conformance module and test request module connected to the first multiplexer, and the first multiplexer connected to the first high-speed interconnect module; the second accelerator card further includes a second multiplexer and a second high-speed interconnect module, with the second device conformance module and test response module connected to the second multiplexer, and the second multiplexer connected to the second high-speed interconnect module; the first high-speed interconnect module is connected to the second high-speed interconnect module via a high-speed interconnect link.

[0021] In simple terms, both the test request module and the first device consistency module can communicate with the second accelerator card via the first multiplexer and the first high-speed interconnect module. The first multiplexer enables link multiplexing and can forward relevant data to both the test request module and the first device consistency module. Similarly, both the test response module and the second device consistency module can communicate with the first accelerator card via the second multiplexer and the second high-speed interconnect module. The second multiplexer enables link multiplexing and can forward relevant data to both the test response module and the second device consistency module. This embodiment does not limit the specific types of the first and second high-speed interconnect modules; for example, both can be CXL modules.

[0022] In another embodiment, the system may further include a connection board, which includes a first connector, a second connector, and a power module. The first and second connectors are connected via signal lines, and the power module is connected to both the first and second connectors. The first connector is connected to the first accelerator card, and the second connector is connected to the second accelerator. Please refer to [reference needed]. Figure 3 , Figure 3 The structural block diagram of the second cache consistency verification system provided in the embodiment of the present invention shows the connection relationship between the host, the first accelerator card, the second accelerator card, and the connection board.

[0023] Furthermore, the first accelerator card also includes a first bus interface and a second memory, the test request module is connected to the first bus interface and the second memory, and the first bus interface is connected to the host; the second accelerator card also includes a second bus interface and a third memory, the test response module is connected to the second bus interface and the third memory, and the second bus interface is connected to the host.

[0024] In this embodiment, the test request module can save test-related data to the second memory, and the test response module can save test-related data to the third memory. The host can access the second memory and the third memory through the first bus interface and the second bus interface, respectively, to obtain the data required for verifying the function. Please refer to... Figure 4 , Figure 4The diagram shows the structure of the third cache consistency verification system provided in this embodiment of the invention, illustrating the complete structure of the first accelerator card and the second accelerator card.

[0025] Based on the above system architecture description, in this system, the Device Coherence Engine (DCOH) is the core hardware module for achieving cache consistency between accelerator cards. The Device Coherence Engine can be connected to the memory in the accelerator card, and this module has an internal cache (…). Figure 2 (The cache is not shown in the diagram). The device consistency module allows the current accelerator card to read and cache memory data from other accelerator cards. For example, in... Figure 2 In this process, the second accelerator card can access the first memory of the first accelerator card through the second device consistency module and cache the data in the first memory in the second device consistency module.

[0026] The purpose of this embodiment is to perform hardware functional verification of the device consistency module. Therefore, this embodiment can add a test request module to the first accelerator card and a test response module to the second accelerator card. The test request module and test response module can be connected to the host to guide the device consistency module of each accelerator card to execute the cache consistency process based on these two newly added modules. The specific functions of the test request module and test response module are as follows: The test request module is used to control the first device consistency module to write first data to the first memory according to a preset address; send the preset address to the test response module; initiate a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module; and report the third data to the host. The test response module is used to initiate a read operation to the second device consistency module according to a preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it; controls the second device consistency module to modify the cached first data to the second data; and reports the first data and the second data to the host. The host is used to verify the cache consistency function of the first accelerator card and the second accelerator card based on the received reported data.

[0027] For easier understanding, please refer to Figure 5 , Figure 5 This is a flowchart of a cache consistency verification method provided in an embodiment of the present invention. The specific test process for cache consistency is described below: S101, The test request module controls the first device consistency module to write the first data to the first memory according to the preset address.

[0028] In this step, the test request module can initiate a write operation to the first device consistency module according to a preset address, so that the first device consistency module writes the first data to the first memory according to the preset address.

[0029] In one implementation, the host writes a preset address and a test start command into the register of the test request module. Upon receiving the test start command, the test request module initiates a write operation to the first device consistency module based on the preset address. When the first device consistency module detects the write operation initiated by the test request module based on the preset address, it writes preset first data into the first memory based on the preset address.

[0030] As can be seen, the preset address can be sent from the host to the test request module. Furthermore, the value of the preset address can be set by the host. This embodiment does not limit the specific value of the first data and can be set according to actual application requirements. For example, the data corresponding to the preset address in the first memory can all be set to 0.

[0031] Furthermore, since the test request module can be connected to the host via the first bus interface, the host can write the preset address and test start command into the register of the test request module via the first bus interface.

[0032] S102. The test request module sends a preset address to the test response module.

[0033] In this step, the test request module can send the preset address to the test response module to trigger the latter to control the second device consistency module to read data from the first memory.

[0034] In one implementation, the test request module can generate a test start data packet using a preset address and a test start command, and send the test start data packet to the test response module.

[0035] In this embodiment, the test request module can generate a test start data packet using a preset address and a test start command, and send this data packet to the test response module to trigger the test response module to start the test. It should be noted that this embodiment does not limit the specific form of the test start data packet; for example, it can be a TLP packet (Transaction Layer Packet) corresponding to a BAR (Base Address Register) operation command. The preset address and the test start command can be written into the payload field of the TLP packet corresponding to the BAR operation command to obtain the aforementioned test start data packet.

[0036] In one implementation, the test request module can send the aforementioned test start data packet to a first multiplexer. Upon receiving the test start data packet, the first multiplexer can send the test start data packet to a second accelerator card via a first high-speed interconnect module.

[0037] S103. The test response module initiates a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it.

[0038] In this step, the test response module can initiate a read operation to the second device consistency module based on a preset address upon receiving the test start data packet sent by the test request module. Since the preset address points to the first memory of the first accelerator card, the second device consistency module can first read the first data from the first device consistency module based on the preset address. Subsequently, the second device consistency module can create a cache line in its own cache and save the preset address and the first data accordingly into that cache line. Therefore, the first data obtained by the test response module should be the same as the first data written by the test request module; if they are different, it indicates a fault in the second accelerator card.

[0039] In one implementation, the first device consistency module can be used to: When a read operation initiated by the second device consistency module based on a preset address is detected, the first data is sent to the second device consistency module, and the cache information of the second device consistency module is recorded.

[0040] In this embodiment, since the second device consistency module does not record relevant data when the test response module initiates a read operation to the first device consistency module based on the preset address for the first time, it can initiate a read operation to the first device consistency module based on the preset address. When the first device consistency module detects the read operation initiated by the second device consistency module, it can send the first data to the second device consistency module.

[0041] The first device consistency module can also record the cache information of the second device consistency module. Thus, when the first device consistency module needs to read data corresponding to the preset address again, to ensure consistency, the first device consistency module can send a sniffing data packet to the second device consistency module based on the cache information to request the latest data corresponding to the preset address.

[0042] In one implementation, the second multiplexer can be used to send the test start data packet to the test response module when the test start data packet is received.

[0043] In this embodiment, the test start data packet can be transmitted to the second multiplexer via the first multiplexer. When the second multiplexer receives the data packet from the first accelerator card and determines that the data packet is a test start data packet, it can send it to the test response module. For example, when the second multiplexer determines that the data packet is a TLP packet corresponding to a BAR space operation command, it sends the data packet to the test response module.

[0044] S104, The test response module controls the second device consistency module to modify the cached first data to the second data.

[0045] S105, the test response module reports the first and second data to the host.

[0046] In steps S104-S105, the test response module can first record the first data for subsequent comparison. Furthermore, the test response module can also control the second device consistency module to modify the cached data and reread the second data corresponding to the preset address from the cache to the second device consistency module, thereby recording the second data. The cache modification verifies whether the caching function of the second device consistency module is normal; on the other hand, it verifies whether the first device consistency module will obtain the latest data from the second device consistency module when it reads data from the preset address again.

[0047] In one embodiment, the test response module can also be used to record first data and second data to a third memory. In this case, the host can retrieve the first and second data recorded by the test response module from the third memory. For example, since the test response module can be connected to the host via a second bus interface, the host can access the third memory through the second bus interface to obtain the first and second data recorded by the test response module. In another embodiment, the test response module can also be used to: Upon receiving the test start data packet, a read operation is initiated to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it. Record the first data, and then control the second device consistency module to read the cached data in the cache according to the preset address and use it as the data to be modified; The modified data is obtained by incrementing the data to be modified by one, and the operation count is also incremented by one; the initial value of the operation count is zero. A write operation is initiated on the second device consistency module based on the preset address and the modified data, so that the second device consistency module modifies the cached data. Determine whether a sniffing data packet sent by the first device consistency module has been received; If no sniffing data packet is received, the process proceeds to the step of controlling the second device consistency module to read cached data from the cache according to the preset address; If a sniffing data packet is received, the second device consistency module is controlled to read the second data in the cache according to the preset address, record the second data and the number of operations, clear the number of operations to zero, and proceed to the step of initiating a read operation to the second device consistency module according to the preset address; Report the first data, the second data, and the number of operations to the host.

[0048] In this embodiment, the test response module can initiate a read operation to the second device consistency module according to a preset address. At this time, since the second device consistency module has cached data, it can return the cached data. The test response module can use the cached data as the data to be modified, increment the data to be modified by one to obtain the modified data, and increment the operation count by one; the initial value of the operation count is zero. Subsequently, the test response module can initiate a write operation to the second device consistency module according to the preset address and the modified data. When the second device consistency module detects the write operation, it can modify the cached data to the modified data. The test response module can repeat the above modification to verify whether the cache modification is normal.

[0049] Furthermore, the test request module will subsequently control the first device consistency module to reread the data corresponding to the preset address. The first device consistency module will then send sniffing packets to the second accelerator card to obtain the latest second data. Upon detecting this sniffing packet, the test response module can stop modifying the cached data and control the second device consistency module to read the second data from the cache according to the preset address, thereby recording the second data and the number of operations. The test response module can then report the first data, the second data, and the number of operations to the host. Under normal circumstances, the relationship between the first data, the second data, and the number of operations should be: the difference between the first data and the second data should equal the number of operations. If they differ, it indicates a fault in the second accelerator card.

[0050] In another implementation, the test response module is also used for: When a read operation is initiated to the second device consistency module, a timer is started, and the timer is stopped when the data returned by the second device consistency module is received, so as to obtain the latency information of the second device consistency module in response to the read operation; Report the first data, the second data, the number of operations, and the latency information to the host.

[0051] In this embodiment, since the time consumed by the second device consistency module to read data from the first memory and its own cache are different, the location at which the second device consistency module reads data can be verified by recording the latency information.

[0052] S106. The test request module initiates a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module.

[0053] In this step, since the test response module needs some time to control the second device consistency module to read data and modify the cache, the test request module can wait for a preset time (such as 100ns) after sending the preset address to the test response module. When the wait ends, it initiates a read operation to the first device consistency module according to the preset address and reports the third data sent by the first device consistency module to the host.

[0054] Furthermore, the test request module can initiate a read operation to the first device consistency module based on a preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module. It is understood that since the data in the second device consistency cache has been modified, the second data in the second device consistency cache should be the latest data at that preset address. Therefore, the third data needs to be compared with the first data in the first memory and the second data cached by the second device consistency module to determine whether the cache consistency function is normal. If the third data matches the first data, it indicates that the cache consistency function is invalid, and the first device consistency module failed to obtain the latest data; if the third data matches the second data, it indicates that the cache consistency is normal. Of course, other test conditions can also be set to more comprehensively verify the cache consistency function, as described in the following embodiments.

[0055] In one implementation, the first device consistency module can be used to: When a read operation initiated by the test request module based on a preset address is detected, if cached information has been recorded, a sniffing data packet containing the preset address is sent to the second device consistency module so that the second device consistency module returns the second data based on the preset address.

[0056] The second multiplexer can be used to send sniffing data packets to the test response module and the second device consistency module respectively when sniffing data packets are received.

[0057] As described above, since the second device consistency module has requested the cached data corresponding to the preset address, the cached data may change. Therefore, the first device consistency module can send a sniffing data packet containing the preset address to the second device consistency module. When the second device consistency module receives the sniffing data packet, if it determines that the cached data corresponding to the preset address has been modified, it can return the latest cached data (i.e., the second data) to the first device consistency module.

[0058] In addition, when the second multiplexer receives a sniffing data packet, it can send the sniffing data packet to the test response module and the second device consistency module respectively. On the one hand, it triggers the test response module to stop modifying the cached data, and on the other hand, it triggers the second device consistency module to send the second data to the first device consistency module.

[0059] S107. The test request module sends the third data and reports it to the host.

[0060] In one implementation, the test request module can also be used to record third data to the second memory. In this case, the host can retrieve the third data recorded by the test request module from the second memory. For example, the host can access the second memory through the first bus interface to obtain the third data recorded by the test request module. Normally, the third data recorded by the test request module should be consistent with the second data recorded by the test response module; if they are inconsistent, it indicates a failure in the cache consistency function.

[0061] S108. The host verifies the cache consistency function of the first and second accelerator cards based on the received reported data.

[0062] In one implementation, the host can also be used to access the second memory and the third memory through the first bus interface and the second bus interface respectively, to obtain the third data recorded by the test request module and the first data and the second data recorded by the test response module, so as to verify the cache consistency function of the first accelerator card and the second accelerator card based on the data.

[0063] As mentioned above, if the third data reported by the test request module is consistent with the second data reported by the test response module, it indicates that the cache consistency function is normal. Furthermore, after confirming that the third data is consistent with the second data, it can be further determined whether the difference between the number of operations reported by the test response module and the first and second data is the same. If the difference between the number of operations reported by the test response module and the first and second data is the same, it can be determined that the cache consistency function is normal.

[0064] Based on the above embodiments, the present invention can add hardware modules for verifying cache consistency functionality to the first accelerator card and the second accelerator card. Specifically, a test request module can be added to the first accelerator card, connected to a first device consistency module in the first accelerator card, and the first device consistency module is connected to a first memory in the first accelerator card. A test response module can be added to the second device consistency module, connected to a second device consistency module in the second accelerator card. The first accelerator card is connected to the second accelerator card via a high-speed interconnect link, and the first device consistency module and the test request module communicate with the second device consistency module and the test response module via the same high-speed interconnect link. Additionally, the test request module and the test response module are also connected to a host. During testing, the test request module controls the first device consistency module to write first data to the first memory according to a preset address and sends the preset address to the test response module. The test response module initiates a read operation to the second device consistency module according to the preset address, causing the second device consistency module to read the first data from the first device consistency module according to the preset address and cache it. Subsequently, the test response module records the first data and controls the second device consistency module to modify the cached data according to the preset address and read the second data from the cache. Subsequently, the test response module records the second data and reports the first and second data to the host. After waiting for a preset time, the test request module initiates a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest second data corresponding to the preset address from the first memory and the second device consistency module. Then, the test request module records the second data and reports it to the host. The host verifies the cache consistency function of the first and second accelerator cards based on the data reported by the test request module and the test response module. Thus, by setting the test request module and the test response module to guide the first and second device consistency modules to execute the cache consistency process in the underlying hardware, recording the data read by each module and reporting it to the host for comparison, this invention can verify the cache consistency function of the first and second accelerator cards in the underlying hardware.

[0065] In another implementation, the test request module can also be used for: The third data is shifted left by a preset number of bits to obtain the fourth data; The first device consistency module writes fourth data to the first memory according to a preset address; Wait for a preset time, and when the wait ends, initiate a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest sixth data corresponding to the preset address from the first memory and the second device consistency module; Report the fourth and sixth data to the host; When the number of left shift and write operations reaches the preset number, a test stop command is sent to the test response module; The test response module can also be used for: A read operation is initiated to the second device consistency module according to the preset address, so that the second device consistency module reads the fourth data from the first device consistency module according to the preset address and caches it; The second device consistency control module modifies the cached fourth data to the fifth data; Report the fourth and fifth data to the host; Upon receiving a test stop command, the control of the second device consistency module to modify cached data is stopped.

[0066] In this embodiment, to verify the consistency of the first device consistency module and the second device consistency module in multiple rounds of data read and write, the test process may further include: S201. The test request module shifts the third data to the left by a preset number of bits to obtain the fourth data.

[0067] S202, The test request module controls the first device consistency module to write the fourth data to the first memory according to the preset address.

[0068] S203. The test response module initiates a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the fourth data from the first device consistency module according to the preset address and caches it.

[0069] S204. The test response module controls the second device consistency module to modify the cached fourth data to the fifth data.

[0070] S205, The test response module reports the fourth and fifth data to the host.

[0071] S206. The test request module waits for a preset time, and when the wait ends, it initiates a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest sixth data corresponding to the preset address from the first memory and the second device consistency module.

[0072] S207. The test request module reports the fourth and sixth data to the host.

[0073] S208. When the number of left shift and write operations reaches the preset number, the test request module sends a test stop command to the test response module. S209. When the test response module receives the test stop command, it stops controlling the second device consistency module to modify the cached data.

[0074] In this embodiment, after reading the third data, the test request module can shift the second data left by a preset number of bits (e.g., 8 bits) to obtain the fourth data. Then, it controls the first device consistency module to write the fourth data to the first memory according to a preset address. Subsequently, the test request module controls the second device consistency module to read the fourth data and modify the cached fourth data to the sixth data. Similarly, after waiting for a preset time, the test request module controls the first device consistency module to read the latest fifth data corresponding to the preset address from the second device consistency module and the first memory. This process can continue for multiple rounds. The third, fourth, fifth, and sixth data are also reported to the host so that the host can verify the cache consistency function of the first and second accelerator cards. Finally, when the number of left shift and write operations reaches a preset number, the test request module can send a test stop command to the test response module to stop the test process.

[0075] In another implementation, the host is also used for: The system determines whether the reported data meets preset conditions. If it does, the cache consistency function of the first and second accelerator cards is considered normal. Specifically, the third and sixth data reported by the test request module are consistent with the second and fifth data reported by the test response module, respectively; the fourth data reported by the test request module is consistent with the fourth data reported by the test response module; the difference between the number of operations reported by the test response module and the first and second data is the same; and the latency for the second device consistency module to read data from the first device consistency module is greater than the latency for the second device consistency module to read data from its own cache. This effectively verifies the consistency of the first and second device consistency modules in multiple rounds of data read / write operations.

[0076] Based on the above embodiments, the specific process of cache consistency verification is described below with a specific example. Figure 4In the system shown, the host configures the physical address of the first memory to 0x1000 via JTAG and begins testing. The test request module of the first accelerator card initiates an operation to set the physical address of the first memory (0x1000) to 0 to the first device consistency module. After the first device consistency module returns a successful write, the test request module initiates a BAR space operation TLP packet, sending the physical address of the first memory (0x1000) and test start information to the second accelerator card via the first high-speed interconnect module. The second multiplexer module of the second accelerator card detects the BAR space operation TLP packet and sends it to the test response module. The test response module sends a command to the second device consistency module to read the address of the first memory (0x1000) and starts timing. Receiving a return value of 0 and a delay of 100ns, the data and delay are written to address 0 of the third memory of the second accelerator card. The data is incremented by 1 to obtain 1, written to the cache line corresponding to the address of the first memory (0x1000) of the second device consistency module, and the operand is recorded as 1. This operation is then repeated.

[0077] After sending the test start information, the test request module of the first accelerator card initiates a read operation on address 0x1000 of the first memory to the first device consistency module after an interval of 100ns (default setting). At this time, the first device consistency module discovers that address 0x1000 of the first memory is cached by the second accelerator card and sends a CXL sniffing packet to the DCOH of the second accelerator card. The second multiplexer module of the second accelerator card receives the CXL sniffing packet, forwards it to the second device consistency module, and simultaneously copies it to the test response module. At this time, the operand of the test response module is 4. This operand 4 is written to address 0 of the fourth memory (not shown), and the operand is cleared to 0. The second device consistency module determines that the cached state of address 0x1000 in the internal first memory is modified, and because the test response module has performed 4 operations, the cache line data corresponding to address 0x1000 of the first memory is 4. The second device consistency module of the second accelerator card sends the cache line data to the first device consistency module of the first accelerator card.

[0078] The first device consistency module of the first accelerator card returns data 4 to the test request module. The test request module writes the returned data to address 0 of the second memory, shifts the data left by 8 bits to obtain data 0x400, and writes it to address 0x1000 of the first memory through the first device consistency module. The test request module of the first accelerator card repeats the above operation after an interval of 100ns, obtaining returned data 0x406, writing it to address 1 of the second memory, shifting 0x406 left by 8 bits to obtain 0x40600, and writing it to address 0x1000 of the first memory. After repeating this 8 times, a stop test message is sent to the second accelerator card. At this time, the data at address 7 of the second memory of the first accelerator card is read through the host's JTAG, as shown in Table 1. The data at address 4 of the second accelerator card is read through the host's JTAG, as shown in Table 2. The data in the two tables correspond one-to-one, indicating that the cache consistency function between the accelerator cards is normal. The host reads the third memory of the second accelerator card. Partial address data of the third memory is shown in Table 3. It can be seen that when the first accelerator card modifies the data at address 0x1000 of the first memory, the second accelerator card can retrieve the modified data. The read latency is significantly higher than that of reading from the internal cache. The cache of the second accelerator card improves the efficiency of the read operation.

[0079] Table 1 Second Memory Record

[0080] Table 2 Fourth Memory Record

[0081] Table 3 Third Memory Record

[0082] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the cache consistency verification method described in the above embodiments.

[0083] Since the embodiments of the computer program product part correspond to the embodiments of the cache consistency verification method part, please refer to the description of the embodiments of the cache consistency verification method part for the embodiments of the computer program product part, and will not be repeated here.

[0084] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the cache consistency verification method described in the above embodiments.

[0085] Since the embodiments of the computer-readable storage medium portion correspond to the embodiments of the cache consistency verification method portion, the embodiments of the storage medium portion are described in the description of the embodiments of the cache consistency verification method portion, and will not be repeated here.

[0086] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0087] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0088] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0089] The cache consistency verification system and method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A cache consistency verification system, characterized in that, include: A first accelerator card, a second accelerator card, and a host are provided. The first accelerator card is connected to the second accelerator card, and the host is connected to both the first and second accelerator cards. The first accelerator card includes a first memory, a first device consistency module, and a test request module. The second accelerator card includes a second device consistency module and a test response module. The test request module is used to control the first device consistency module to write first data to the first memory according to a preset address; and to send the preset address to the test response module. A read operation is initiated to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module; The third data is reported to the host; The test response module is used to initiate a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it. The second device consistency module is controlled to modify the cached first data to the second data; the first data and the second data are then reported to the host. The host is used to verify the cache consistency function of the first accelerator card and the second accelerator card based on the received reported data.

2. The cache consistency verification system according to claim 1, characterized in that, The test request module and the test response module are configured based on programmable logic devices.

3. The cache consistency verification system according to claim 1 or 2, characterized in that, The host is also used for: Write the preset address and test start command into the register of the test request module; The test request module is also used for: Upon receiving the test start command, a write operation is initiated to the first device consistency module according to the preset address; A test start data packet is generated using the preset address and the test start command, and the test start data packet is sent to the test response module; Wait for a preset time, and when the wait ends, initiate a read operation to the first device consistency module according to the preset address, and report the third data sent by the first device consistency module to the host; The first device consistency module is used for: When a write operation initiated by the test request module based on the preset address is detected, preset first data is written to the first memory based on the preset address; When a read operation initiated by the second device consistency module based on the preset address is detected, the first data is sent to the second device consistency module, and the cache information of the second device consistency module is recorded; When a read operation initiated by the test request module based on the preset address is detected, if the cache information has been recorded, a sniffing data packet containing the preset address is sent to the second device consistency module so that the second device consistency module returns the second data based on the preset address. Based on the data corresponding to the preset address in the first memory and the data returned by the second device consistency module, determine the latest third data corresponding to the preset address, and send the third data to the test request module; the test response module is further configured to: Upon receiving the test start data packet, a read operation is initiated to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it. Record the first data, and then control the second device consistency module to read the cached data in the cache according to the preset address and use it as the data to be modified; The modified data is obtained by incrementing the data to be modified by one, and the operation count is incremented by one; wherein the initial value of the operation count is zero; A write operation is initiated on the second device consistency module according to the preset address and the modified data, so that the second device consistency module modifies the cached data; Determine whether a sniffing data packet sent by the first device consistency module has been received; If the sniffing data packet is not received, the process proceeds to the step of controlling the second device consistency module to read cached data from the cache according to the preset address; If the sniffing data packet is received, the second device consistency module is controlled to read the second data in the cache according to the preset address, record the second data and the number of operations, clear the number of operations to zero, and proceed to the step of initiating a read operation to the second device consistency module according to the preset address; The host is reported the first data, the second data, and the number of operations.

4. The cache consistency verification system according to claim 3, characterized in that, The first accelerator card also includes a first bus interface and a second memory. The test request module is connected to the first bus interface and the second memory. The first bus interface is connected to the host. The second accelerator card also includes a second bus interface and a third memory. The test response module is connected to the second bus interface and the third memory. The second bus interface is connected to the host. The test request module is also used to record the third data into the second memory; The test response module is also used to record the first data and the second data into the third memory; The host is also configured to access the second memory and the third memory respectively through the first bus interface and the second bus interface to obtain the third data recorded by the test request module and the first data and the second data recorded by the test response module.

5. The cache consistency verification system according to claim 4, characterized in that, The host is also configured to write the preset address and the test start command into the register of the test request module via the first bus interface.

6. The cache consistency verification system according to claim 3, characterized in that, The first accelerator card also includes a first multiplexer and a first high-speed interconnect module. The first device consistency module and the test request module are connected to the first multiplexer, and the first multiplexer is connected to the first high-speed interconnect module. The second accelerator card also includes a second multiplexer and a second high-speed interconnect module. The second device conformance module and the test response module are connected to the second multiplexer, and the second multiplexer is connected to the second high-speed interconnect module. The first high-speed interconnect module is connected to the second high-speed interconnect module via a high-speed interconnect link; The first multiplexer is used for: Upon receiving the test start data packet, the test start data packet is sent to the second acceleration card through the first high-speed interconnect module; The second multiplexer is used for: Upon receiving the test start data packet, the test start data packet is sent to the test response module; Upon receiving the sniffing data packet, the sniffing data packet is sent to the test response module and the second device consistency module, respectively.

7. The cache consistency verification system according to claim 3, characterized in that, The test response module is also used for: When a read operation is initiated to the second device consistency module, a timer is started, and the timer is stopped when the data returned by the second device consistency module is received, so as to obtain the latency information of the second device consistency module in response to the read operation; The host is reported the first data, the second data, the number of operations, and the latency information.

8. The cache consistency verification system according to claim 7, characterized in that, The test request module is also used for: The third data is shifted left by a preset number of bits to obtain the fourth data; The first device consistency module is controlled to write fourth data to the first memory according to a preset address; Wait for a preset time, and when the wait ends, initiate a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest sixth data corresponding to the preset address from the first memory and the second device consistency module; Report the fourth data and the sixth data to the host; When the number of left shift and write operations reaches a preset number, a test stop command is sent to the test response module; The test response module is also used for: A read operation is initiated to the second device consistency module according to the preset address, so that the second device consistency module reads the fourth data from the first device consistency module according to the preset address and caches it. The second device consistency module modifies the cached fourth data to the fifth data; Report the fourth and fifth data to the host; Upon receiving the test stop command, the control of the second device consistency module to modify cached data is stopped.

9. The cache consistency verification system according to claim 8, characterized in that, The host is also used for: The system determines whether the reported data meets preset conditions. If it does, the cache consistency function of the first and second acceleration cards is deemed to be normal. The preset conditions include: the third and sixth data reported by the test request module are consistent with the second and fifth data reported by the test response module, respectively; the fourth data reported by the test request module is consistent with the fourth data reported by the test response module; the number of operations reported by the test response module is the same as the difference between the first and second data; and the latency for the second device consistency module to read data from the first device consistency module is greater than the latency for the second device consistency module to read data from its own cache.

10. A cache consistency verification method, characterized in that, An application is provided in a cache consistency verification system, which includes a first accelerator card, a second accelerator card, and a host. The first accelerator card is connected to the second accelerator card, and the host is connected to both the first and second accelerator cards. The first accelerator card includes a first memory, a first device consistency module, and a test request module. The second accelerator card includes a second device consistency module and a test response module. The method includes: The test request module controls the first device consistency module to write first data to the first memory according to a preset address; The test request module sends the preset address to the test response module; The test response module initiates a read operation to the second device consistency module according to the preset address, so that the second device consistency module reads the first data from the first device consistency module according to the preset address and caches it; The test response module controls the second device consistency module to modify the cached first data to the second data; The test response module reports the first data and the second data to the host; The test request module initiates a read operation to the first device consistency module according to the preset address, so that the first device consistency module reads the latest third data corresponding to the preset address from the first memory and the second device consistency module; The test request module reports the third data to the host. The host verifies the cache consistency function of the first accelerator card and the second accelerator card based on the received reported data.

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