System, method and switch chip for monitoring register reads
By using the CPU's built-in buffer memory and defining registers as cacheable, combined with a monitoring module to achieve synchronous updates of cached data, the problem of low processing efficiency caused by the CPU accessing non-cacheable registers is solved, thereby improving the CPU's processing efficiency and data consistency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU CENTEC COMM CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, register address types are generally defined as Non-Cacheable, which means that CPU access operations must actually operate on the target address, occupying a long time for the CPU and resulting in low CPU processing efficiency.
By using a built-in buffer memory in the CPU and defining the addresses of registers as cacheable, and by using a monitoring module to monitor the behavior of the buffer memory and the state changes of the registers, synchronous updates and consistency of cached data can be achieved, reducing the number of times the target register is directly accessed.
It significantly reduces CPU processing time, improves CPU processing efficiency, and ensures data consistency, avoiding software misjudgments and control delays caused by cache inconsistency.
Smart Images
Figure CN122489377A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of switching chip technology, specifically relating to a system, method and switching chip for register reading based on monitoring. Background Technology
[0002] The accelerator processing unit (APU) is primarily used for batch processing of large datasets, including data transmission, computation, storage, and retrieval. During operation, the APU needs to adjust its operating parameters based on real-time status changes. Therefore, the on-chip CPU actively reads the accelerator's real-time status and adjusts the APU's operating parameters accordingly to meet application requirements. The CPU achieves these functions by accessing the APU's registers. This access operation is initiated by the CPU, sent to the system bus via internal buffer memory, and then forwarded to the target register based on the target address information. Finally, the system bus returns the target register's status information to the CPU.
[0003] Currently, register address types are generally defined as Non-Cacheable, meaning they cannot be cached. When the CPU accesses a Non-Cacheable address, read / write operations must actually operate on the target address; caching is not allowed during the access process. The CPU must wait for a response from the actual target address register before proceeding with subsequent operations. If this register is far from the CPU, the access time will be long. If the target address module cannot respond to the current CPU read / write operation in a timely manner, the CPU must also wait for its return and cannot execute subsequent operations. Therefore, this operation method consumes a significant amount of CPU time, resulting in low CPU processing efficiency. Summary of the Invention
[0004] The purpose of this application is to provide a system and method for register reading based on monitoring, in order to solve the problem that in the prior art, the address type of registers is generally defined as Non-Cacheable, and the CPU access operation must actually operate on the target address, which occupies a long time of CPU time and leads to low CPU processing efficiency.
[0005] To achieve the above objectives, the first aspect of this application provides a system for register reading based on monitoring, including a CPU, a target module, and a monitoring module that communicate via a system bus. The CPU has a built-in buffer memory, the target module has multiple built-in registers, each of the registers has a continuous field with consistent function, the buffer memory has a cache space that corresponds one-to-one with the addresses of the multiple registers, and the address of each register is defined by the CPU as cacheable.
[0006] The CPU is used to initiate read / write operation requests for the target register, determine whether there is cached data in the cache space corresponding to the target register in the buffer memory, and read / write the cached data in the cache space when cached data exists.
[0007] The monitoring module is used to monitor the CPU's operation of the buffer memory, and write the updated cached data into the target register when the cached data in the buffer memory is updated.
[0008] In one or more embodiments, the CPU is further configured to read and write the target register via the system bus and write the cached data in the target register into the corresponding cache space when there is no cached data in the cache space corresponding to the target register in the buffer memory.
[0009] In one or more embodiments, the monitoring module is further configured to monitor the state of the register and initiate a write operation request to the CPU when the state of the target register is updated;
[0010] The CPU is also configured to, upon receiving the write operation request, access the target register via the system bus and write the cached data in the target memory into the corresponding cache space in the buffer memory.
[0011] In one or more embodiments, the monitoring module monitors the CPU's operation of the buffer memory via a bus interface protocol.
[0012] In one or more embodiments, the starting addresses of the plurality of registers are aligned, and the field length of each of the registers matches the length of a cache line of the buffer memory.
[0013] In one or more embodiments, the monitoring module is used to initiate a read operation request to the CPU when the cached data in the buffer memory is updated;
[0014] The CPU is also used to read the updated cached data and feed it back to the monitoring module when it receives the read operation request;
[0015] The monitoring module is also used to write the updated cached data fed back by the CPU into the corresponding target register.
[0016] To achieve the above objectives, a second aspect of this application provides a method for register reading based on monitoring, applied to a system including a CPU, a target module, and a monitoring module communicating via a system bus. The CPU has a built-in buffer memory, the target module has a plurality of built-in registers, each of the registers having a continuous field with consistent function, the buffer memory having a cache space corresponding one-to-one with the addresses of the plurality of registers, and the address of each register is defined by the CPU as cacheable.
[0017] The method includes:
[0018] The CPU initiates a read / write operation request for the target register;
[0019] Determine whether there is cached data in the cache space corresponding to the target register in the buffer memory;
[0020] If so, read or write the cached data in the cache space corresponding to the target register;
[0021] When the monitoring module detects an update to the cached data in the buffer memory, it writes the updated cached data into the target register.
[0022] In one or more embodiments, if there is no cached data in the cache space corresponding to the target register, the method further includes:
[0023] The CPU reads and writes the target register through the system bus, and writes the cached data in the target register into the corresponding cache space.
[0024] In one or more embodiments, it further includes:
[0025] When the monitoring module detects an update in the state of the target register, it writes the updated cached data in the target register into the corresponding cache space in the buffer memory.
[0026] Specifically, it includes:
[0027] When the monitoring module detects an update in the state of the target register, it sends a write operation request to the CPU.
[0028] In response to the write operation request, the CPU accesses the target register through the system bus and writes the cached data in the target memory into the corresponding cache space in the buffer memory.
[0029] In one or more embodiments, the step of the monitoring module writing the updated cached data to the target register when it detects an update in the cached data in the buffer memory includes:
[0030] When the monitoring module detects that the cached data in the buffer memory has been updated, it sends a read operation request to the CPU.
[0031] In response to the read operation request, the CPU reads the updated cached data and sends it back to the monitoring module;
[0032] The monitoring module writes the updated cache data fed back by the CPU into the corresponding target register.
[0033] To achieve the above objectives, a third aspect of this application provides a switching chip, including the system described in any of the above embodiments.
[0034] The advantages of this application, which differ from existing technologies, are:
[0035] This application defines the addresses of all registers as cacheable, and the address of each register corresponds to a cache space of the CPU's built-in buffer memory. The cached data of the registers can be written to the corresponding cache space. When the cached data of the target register is in the buffer memory, the CPU only needs to perform read and write operations on the cached data in the buffer memory, without directly operating the target register. At the same time, the monitoring module can ensure the data consistency between the buffer memory and the registers, which significantly reduces the CPU processing time and effectively improves the CPU's processing efficiency.
[0036] The monitoring module of this application can synchronously update the cached data in the register when the CPU updates the cached data in the buffer memory, ensuring data consistency and reducing the CPU processing time.
[0037] The monitoring module of this application can synchronously update the cached data in the buffer memory when the state of the target register changes due to its own internal logic, thereby ensuring data consistency and reducing CPU processing time. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a flowchart of register reading in existing technology;
[0040] Figure 2This is a schematic diagram of one implementation of the system for register reading based on monitoring, as described in this application;
[0041] Figure 3 This is a flowchart illustrating one implementation method of the register reading method based on monitoring in this application;
[0042] Figure 4 yes Figure 3 A flowchart illustrating one embodiment corresponding to S300;
[0043] Figure 5 yes Figure 3 A flowchart of one embodiment corresponding to S400. Detailed Implementation
[0044] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.
[0045] The on-chip CPU needs to obtain the real-time status of the accelerator processing unit and other components in a timely manner to quickly adjust the accelerator's operating parameters to meet application requirements. This operation generally requires the CPU to actively read the register status in the accelerator processing unit, then process it through software operations, and finally modify the operating parameter configuration register in the accelerator processing unit to notify it to adjust its operating mode or computation method accordingly.
[0046] The following is a schematic diagram illustrating the process of reading a traditional register, such as... Figure 1 As shown, Figure 1 This is a flowchart of register reading in existing technology. For example... Figure 1 As shown, the CPU first initiates a read / write operation request, which is then sent to the system bus after passing through the internal cache memory. The system bus then accesses the target register on the operation accelerator processing unit based on the target address. Finally, the status information of the target register is returned to the CPU via the same route.
[0047] The addresses accessible by the CPU are mainly divided into two categories based on whether they can be cached: cacheable addresses and non-cacheable addresses. When the CPU accesses a cacheable address, the data result of the read / write operation can be cached in the CPU's cache, greatly saving the time of subsequent CPU accesses. However, when the CPU accesses a non-cacheable address, the read / write operation must actually operate on the target address; caching is not allowed during the access, and the CPU must wait for a response from the actual target address register before continuing the operation. If this register is far from the CPU, the access time will be longer. If the target address module cannot respond to the current CPU read / write operation in time, the CPU must also wait for its return and cannot execute subsequent operations. Therefore, the above operation mode consumes a lot of CPU time, resulting in lower CPU processing efficiency.
[0048] In addition, there is currently a problem of inconsistency between the data in the cached address and the data in the register. When the two are inconsistent, if the CPU reads an incorrect status value from the cache, it will cause software misjudgment. If the CPU's configuration write operation remains in the cache and cannot be written to the register in time, it will cause control delay or failure.
[0049] To this end, the applicant has developed a novel system for register reading based on monitoring. Please refer to [link / reference]. Figure 2 , Figure 2 This is a schematic diagram of a system implementation based on monitoring to read registers, as described in this application.
[0050] like Figure 2 As shown, the system includes a CPU 21, a target module 22, and a monitoring module 23 that communicate via a system bus 20. The CPU 21 has a built-in cache memory 210, and the target module 22 has multiple registers 220, each register 220 having a continuous field with consistent function. The cache memory 210 has a cache space 211 that corresponds one-to-one with the addresses of the multiple registers 220.
[0051] In this context, the address of each register 220 is defined by CPU21 as cacheable.
[0052] As is understandable, the address of the cache space 211 inside the cache corresponds one-to-one with the address of the register 220. The address of the register 220 is defined as the cache address, so the cached data in each register 220 can be written into the corresponding cache space 211.
[0053] At the same time, the functions of each field in register 220 remain consistent. When CPU 21 reads or writes to the register, all fields can be executed simultaneously without having to operate separately because of the different functions of different fields, thus improving processing efficiency.
[0054] In one implementation, the starting addresses of the multiple registers 220 can be aligned, and the field length of each register 220 matches the length of a cache line of the buffer memory 210, so that cached data can be completely written into the registers 220 and the cache space 211 of the buffer memory 210.
[0055] The start address alignment of multiple registers 220 means that the start address can be a multiple of the length of the cache line. For example, the cache line is usually 64 bytes, and the start address of register 220 can be a multiple of 64, so that each register 220 can maintain a length of 64 bytes, as shown in the table below.
[0056]
[0057] In one implementation, the target module 22 may be specifically an accelerator processing unit.
[0058] The steps for reading register 220 in this embodiment are described in detail below.
[0059] Specifically, firstly, CPU21 initiates a read / write operation request for target register 220. After the request is initiated, it first determines whether there is cached data in the cache space 211 corresponding to target register 220.
[0060] When cached data exists, CPU21 can directly read and write the cached data in the cache space 211 corresponding to the target register 220, thereby greatly saving the time CPU21 spends reading and writing register 220.
[0061] Furthermore, the monitoring module 23 is used to monitor the behavior of the CPU 21 in operating the buffer memory 210.
[0062] In one implementation, the monitoring module 23 can achieve the above-mentioned monitoring purpose through a bus interface protocol. For example, the monitoring module 23 can access protocol interfaces such as ACE and CHI. The external access ports of the above-mentioned bus interface protocols provide various operation parameters required for hardware consistency. Based on the processing of signals from this interface, the monitoring function of CPU 21 operating the cache can be realized. For example, the interface will indicate whether there is a cache read / write operation, the specific address of the operation, the data size, and other information. Based on the above information, the monitoring module 23 can determine whether there is a read / write access to the target module 22 in the current operation of CPU 21.
[0063] When CPU21 writes to cached data in cache space 211, the cached data is updated. The monitoring module 23 can determine the target register 220 of the current operation of CPU21 through the status of the interface signal, and write the updated cached data to the target register 220.
[0064] Specifically, when the cached data in the buffer memory 210 is updated, the monitoring module 23 can send a read operation request to the CPU 21. When the CPU 21 receives the read operation request, it reads the updated cached data and sends it back to the monitoring module 23. The monitoring module 23 writes the updated cached data sent back by the CPU 21 into the corresponding target register 220.
[0065] Based on the above scheme, when there is cached data in the cache space 211 of the buffer memory 210, the CPU 21 only needs to read and write the internal cached data through the monitoring module 23, without directly accessing the target register 220. The monitoring module 23 achieves data consistency between the buffer memory 210 and the target register 220, which significantly reduces the processing time of the CPU 21 and improves the processing efficiency.
[0066] Furthermore, when there is no cached data in the cache space 211 corresponding to the target register 220, the CPU 21 can also directly read and write the target register 220 through the system bus 20 and write the cached data in the target register 220 into the corresponding cache space 211 to improve subsequent access efficiency.
[0067] Since the state of the target module 22 also changes due to internal logic, rather than solely due to the operation of the CPU 21, in order to ensure data consistency between the register 220 and the buffer memory 210, the monitoring module 23 in this embodiment is also used to monitor the state of the register 220 and to send a write operation request to the CPU 21 when the state of the target register 220 is updated.
[0068] Specifically, when the monitoring module 23 detects a change in the state of the target register 220, it can send a write operation request to the CPU 21. When the CPU 21 receives the write operation request, it can access the target register 220 through the system bus 20 and write the cached data in the target memory into the corresponding cache space 211 in the buffer memory 210, thereby achieving data consistency between the two.
[0069] Based on the system of the above embodiments, the addresses of all registers 220 are defined as cacheable. At the same time, the address of each register 220 corresponds to a cache space 211 of the buffer memory 210 built into the CPU 21. The cached data of the register 220 can be written to the corresponding cache space 211. When the buffer memory 210 contains cached data of the target register 220, the CPU 21 only needs to perform read and write operations on the cached data in the buffer memory 210, without directly operating the target register 220. At the same time, the monitoring module 23 can ensure the data consistency between the buffer memory 210 and the register 220, significantly reducing the processing time of the CPU 21 and effectively improving the processing efficiency of the CPU 21.
[0070] This application also provides a method for register reading based on monitoring. This method can be applied to systems described in any of the above embodiments. For details, please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a flowchart illustrating one implementation of the method for register reading based on monitoring in this application.
[0071] like Figure 3 As shown, the method includes:
[0072] S100: The CPU initiates a read / write operation request for the target register.
[0073] S200. Determine whether there is cached data in the cache space corresponding to the target register in the buffer memory.
[0074] When cached data exists, the methods include:
[0075] S300a: The CPU reads and writes cached data in the cache space corresponding to the target register.
[0076] When no cached data exists, the methods include:
[0077] The S300b CPU reads and writes the target register through the system bus and writes the cached data in the target register into the corresponding cache space.
[0078] Furthermore, in S300a, after the CPU writes data into the cache space corresponding to the target register, the method also includes:
[0079] When the cached data in the buffer memory of the S400 monitoring module is updated, the updated cached data is written to the target register.
[0080] When the CPU writes cached data to the buffer memory, the monitoring module can write the updated cached data to the target register.
[0081] Specifically, please refer to Figure 4 , Figure 4 yes Figure 3 A flowchart of one embodiment corresponding to S400.
[0082] like Figure 4 As shown, the method by which the monitoring module writes the updated cached data to the target register includes:
[0083] S401. When the monitoring module detects that the cached data in the buffer memory has been updated, it sends a read operation request to the CPU.
[0084] S402. In response to a read operation request, the CPU reads the updated cached data and sends it back to the monitoring module.
[0085] S403, the monitoring module writes the updated cache data fed back by the CPU into the corresponding target register.
[0086] Based on the above scheme, when the CPU updates the cached data in the buffer memory, the cached data in the register can be updated synchronously, ensuring data consistency.
[0087] Furthermore, the methods also include:
[0088] When the monitoring module detects an update in the state of the target register, it writes the updated cached data in the target register into the corresponding cache space in the buffer memory.
[0089] When the state of the target register changes due to its internal logic, the monitoring module can write the updated cached data into the corresponding cache space.
[0090] Specifically, please refer to Figure 5 , Figure 5 yes Figure 3 A flowchart of one embodiment corresponding to S500.
[0091] like Figure 5 As shown, the steps by which the monitoring module writes the updated cached data to the corresponding cache space include:
[0092] S501. When the monitoring module detects an update in the state of the target register, it sends a write operation request to the CPU.
[0093] S502. In response to a write operation request, the CPU accesses the target register through the system bus and writes the cached data in the target memory into the corresponding cache space in the buffer memory.
[0094] Based on the above method, when the state of the target register changes due to its internal logic, the cached data in the buffer memory can be updated synchronously, ensuring data consistency.
[0095] It should be noted that the above descriptions of the systems for register reading based on monitoring in various embodiments of this application also apply to the method for register reading based on monitoring in this application, and will not be repeated here.
[0096] This application also provides a switching chip that includes a system for register reading based on monitoring, as described in any of the above embodiments.
[0097] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0098] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A system for register reading based on monitoring, characterized in that, The system includes a CPU, a target module, and a monitoring module that communicate via a system bus. The CPU has a built-in buffer memory, and the target module has multiple built-in registers. Each register has a continuous field with consistent function. The buffer memory has a cache space that corresponds one-to-one with the addresses of the multiple registers, and the address of each register is defined as cacheable by the CPU. The CPU is used to initiate read / write operation requests for the target register, determine whether there is cached data in the cache space corresponding to the target register in the buffer memory, and read / write the cached data in the cache space when cached data exists. The monitoring module is used to monitor the CPU's operation of the buffer memory, and write the updated cached data into the target register when the cached data in the buffer memory is updated.
2. The system according to claim 1, characterized in that, The CPU is also configured to read and write the target register via the system bus and write the cached data in the target register into the corresponding cache space when there is no cached data in the cache space corresponding to the target register in the buffer memory.
3. The system according to claim 1, characterized in that, The monitoring module is also used to monitor the state of the register and to send a write operation request to the CPU when the state of the target register is updated. The CPU is also configured to, upon receiving the write operation request, access the target register via the system bus and write the cached data in the target memory into the corresponding cache space in the buffer memory.
4. The system according to claim 1, characterized in that, The monitoring module monitors the CPU's operation of the buffer memory via a bus interface protocol.
5. The system according to claim 1, characterized in that, The starting addresses of the multiple registers are aligned, and the field length of each register matches the length of a cache line of the buffer memory.
6. The system according to claim 1, characterized in that, The monitoring module is used to initiate a read operation request to the CPU when the cached data in the buffer memory is updated. The CPU is also used to read the updated cached data and feed it back to the monitoring module when it receives the read operation request; The monitoring module is also used to write the updated cached data fed back by the CPU into the corresponding target register.
7. A method for register reading based on monitoring, characterized in that, The system is applied to a system including a CPU, a target module, and a monitoring module that communicate via a system bus. The CPU has a built-in buffer memory, the target module has a plurality of built-in registers, each of the registers having a continuous field with consistent function, the buffer memory has a cache space that corresponds one-to-one with the addresses of the plurality of registers, and the address of each of the registers is defined by the CPU as cacheable. The method includes: The CPU initiates a read / write operation request for the target register; Determine whether there is cached data in the cache space corresponding to the target register in the buffer memory; If so, the CPU reads and writes cached data in the cache space corresponding to the target register; When the monitoring module detects an update to the cached data in the buffer memory, it writes the updated cached data into the target register.
8. The method according to claim 7, characterized in that, If no cached data exists in the cache space corresponding to the target register, the method further includes: The CPU reads and writes the target register through the system bus, and writes the cached data in the target register into the corresponding cache space.
9. The method according to claim 7, characterized in that, Also includes: When the monitoring module detects an update in the state of the target register, it writes the updated cached data in the target register into the corresponding cache space in the buffer memory. Specifically, it includes: When the monitoring module detects an update in the state of the target register, it sends a write operation request to the CPU. In response to the write operation request, the CPU accesses the target register through the system bus and writes the cached data in the target memory into the corresponding cache space in the buffer memory.
10. The method according to claim 7, characterized in that, When the monitoring module detects an update to the cached data in the buffer memory, the step of writing the updated cached data to the target register includes: When the monitoring module detects that the cached data in the buffer memory has been updated, it sends a read operation request to the CPU. In response to the read operation request, the CPU reads the updated cached data and sends it back to the monitoring module; The monitoring module writes the updated cache data fed back by the CPU into the corresponding target register.
11. A switching chip, characterized in that, Includes the system described in any one of claims 1 to 6.