A method and system for automated generation and verification of test cases for FPGA EDA software
By automating the generation and verification of test cases for FPGA EDA software, the problems of time-consuming and error-prone manual test case writing are solved, achieving an efficient, accurate and comprehensive test case generation and verification process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU SINO MICROELECTRONICS TECH CO LTD
- Filing Date
- 2026-05-14
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional manual test case writing and verification processes for FPGA EDA software are time-consuming, error-prone, and lack comprehensiveness. Existing automated methods have failed to effectively address the issues of efficiency, accuracy, and comprehensiveness in test case generation and verification for FPGA EDA software.
The system employs a parameter file configuration module, a logic parameter combination module, a statement generation model, a parameter conversion module, and an automated verification module to automatically generate and verify test cases for FPGA EDA software. This includes logic parameter combination, test case set generation, tool runtime parameter conversion, and result statistics, thus achieving an automated testing process.
It improves the efficiency, accuracy, and comprehensiveness of test case generation and verification, reduces human error, and ensures the efficiency and coverage of verification.
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Figure CN122489429A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a method and system for automating the generation and verification of test cases for FPGA EDA software. Background Technology
[0002] A Field-Programmable Gate Array (FPGA) is a special type of digital circuit whose hardware logic functions can be configured and reconfigured by the user as needed. FPGA EDA software accurately and efficiently maps the design intent expressed by engineers in hardware description languages (such as Verilog and VHDL) onto the physical structure of an FPGA chip composed of programmable logic units.
[0003] As the functionality and complexity of FPGA EDA software increase, the number and complexity of required test cases also rise. Traditional manual test case development and verification processes for FPGA EDA software functionality are as follows: Figure 1 As shown, the process includes the following steps: manually writing test case sets; manually running the EDA software; manually writing .tb files; manually running simulation verification; and manually compiling results. Manually writing and verifying test cases for the FPGA EDA software is time-consuming, error-prone, and difficult to guarantee comprehensiveness. Using automated test case generation and verification is key to ensuring the efficiency, accuracy, and comprehensiveness of verification.
[0004] With the upgrading of FPGAs, the demand for supporting EDA development software is increasing. To ensure the accuracy and stability of the EDA development software's functions, it is necessary to write targeted and comprehensive test case sets for testing and verification. At the same time, as the functions of FPGA EDA software are iteratively updated, the ability to efficiently, accurately, and comprehensively generate and test test cases will directly affect the development cycle of FPGA EDA software.
[0005] Some existing technologies, such as patent CN202410634394.X "An EDA Software Testing Method, Apparatus and Storage Medium", use YAML files to define test cases and test processes, mainly to enable rapid and flexible combinations of test cases and processes. CN202010130642.9 "A Method and System for Supporting Automated Testing and Recording of EDA Software", on the other hand, uses full-process testing of tens of thousands of different circuits with random configurations. Each round of testing has different configuration information, ensuring that different circuits have different configuration items each time they are executed, thereby maximizing the identification of problems in the software. Summary of the Invention
[0006] Based on the above problems, the purpose of this invention is to provide a method and system for automated generation and verification of test cases for FPGA EDA software, which can realize automated test case generation and verification, and ensure the efficiency, accuracy and comprehensiveness of verification.
[0007] The technical solution adopted by this invention to achieve its objective is a method for automatically generating and verifying test cases for FPGA EDA software, comprising the following steps:
[0008] S1, Configuration parameter file;
[0009] S2. The parameter file is traversed by the logic parameter combination module to traverse all logic combinations and perform combinations between different logic parameters; the algorithm for traversing and combining is an existing technology and will not be described here.
[0010] S3. Use the statement generation model to generate a test case set based on logical parameter information;
[0011] S4. The parameter conversion module converts the logical parameter combination information into the parameter information required for the verification process.
[0012] S5. Input the test case set and parameter information into the automated verification module to automatically run the verification process;
[0013] S6. The results statistics module automatically performs the results statistics process.
[0014] Furthermore, the parameter file describes all the logic contained in the test cases to be generated. Although there are many combinations of logic parameters, the combinations between different logic parameters can be automatically implemented by the logic parameter combination module; only the logic types need to be listed in the parameter file.
[0015] Furthermore, in step S5, the automatic verification process specifically refers to the automatic execution of automated running commands, including EDA software, generating tb, and simulation equivalence verification. In step S4, the parameter information required for the verification process includes the parameters required for the operation of tools such as EDA software, generating tb, and simulation equivalence verification.
[0016] This invention also provides an automated test case generation and verification system for FPGA EDA software, comprising:
[0017] The logic parameter combination module is used to combine different logic parameters in a parameter file;
[0018] The statement generation model module is used to generate a test case set based on logical parameter information.
[0019] The parameter conversion module is used to convert logical parameter combinations into parameter information required for the verification process.
[0020] The automated verification module is used to automatically run the verification process based on the input test case set and parameter information;
[0021] The results statistics module is used to automatically perform results statistics.
[0022] Furthermore, the parameter file describes all the logic contained in the test cases to be generated.
[0023] Furthermore, the automated verification process specifically refers to the automated execution of commands including EDA software, tb generation, and simulation equivalence verification; the required parameter information for the verification process includes the parameters required for the operation of tools including EDA software, tb generation, and simulation equivalence verification.
[0024] The beneficial effects of this invention are as follows:
[0025] This invention improves upon the traditional manual development of test cases and verification processes for FPGA EDA software. It adds a parameter file describing all logic types included in the test cases; a logic parameter combination module automatically covers all logic parameter combinations; a statement generation model automatically generates all test cases; a parameter conversion module converts logic parameter combination information into parameters required for EDA software, test case generation, simulation equivalence verification, and other tools; an automated verification module automatically runs the verification process, including EDA software, test case generation, and simulation equivalence verification; and a result statistics module automatically compiles verification results. After these improvements, only the parameter file needs to be configured; all other operations are automated, significantly improving the efficiency, accuracy, comprehensiveness, and coverage of test case generation and verification. Attached Figure Description
[0026] Figure 1 A test case and verification flowchart illustrating the functionality of traditional manually written FPGA EDA software;
[0027] Figure 2 This is a schematic diagram of the automated generation and verification process of test cases in Embodiment 1 of the present invention;
[0028] Figure 3 This is the search tree constructed for the Shift Register in Embodiment 1 of the present invention;
[0029] Figure 4 This is a schematic diagram of the system structure in Embodiment 2 of the present invention;
[0030] Figure 5 This is a schematic diagram of the automated case generation and verification process using the system of Embodiment 2 of the present invention. Detailed Implementation
[0031] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0032] Example 1
[0033] Figure 2 This paper illustrates a specific implementation of the method for automatically generating and verifying test cases in the FPGA EDA software of the present invention. Taking the example of generating all logic combinations of a single Shift Register connected to a single Block RAM and automatically testing all cases, the steps of this implementation are described as follows:
[0034] S1, Configuration parameter file, describes all the logical types included in the test case.
[0035] The parameter file configuration required for this embodiment includes Shift Register and Block RAM, and the corresponding parameter configuration contents are as follows:
[0036] Table 1
[0037]
[0038] Table 2
[0039]
[0040] S2. The parameter file is traversed by the logic parameter combination module to traverse all logic combinations and perform combinations between different logic parameters.
[0041] Taking the recursive backtracking algorithm as an example, a search tree is built through depth-first search (DFS), elements are selected and recursively processed, and backtracking is performed after the target combination length is reached to try other choices.
[0042] For the Shift Register, construct a search tree from Table 1, such as... Figure 3 As shown.
[0043] The elements are selected sequentially and recursively using a depth-first search (DFS): Shift Register -> 8-Bit -> Rising edge clock -> Concatenation-based, and the results are saved as a dict structure: {Shift_Register:[8-Bit,Rising edge clock,Concatenation-based]}. Then, other choices are tried by backtracking until all possible combinations are traversed.
[0044] Similarly, all possible combinations of Block RAM can be obtained. Here are two examples to illustrate this:
[0045] {Block_RAM:[Read first, Pipeline, Single-port]}
[0046] {Block_RAM:[Write first, No_Pipeline, Simple Dual-Port]}
[0047] By combining all possible combinations of the Shift Register and Block RAM, we can obtain all logical combinations of a single Shift Register connecting to a single Block RAM. These logical combinations are stored using a dictionary structure. Two examples are provided below for illustration:
[0048] {Shift_Register:[8-Bit,Rising edge clock,Concatenation-based], BlockRAM:[Read first,Pipeline,Single-port]}
[0049] {Shift_Register:[32-Bit,Falling edge clock,For-loop based], BlockRAM:[Write first,No_Pipeline,Simple Dual-Ports]}
[0050] S3. The combined parameter information is used as input parameters for the statement generation model. The statement generation model combines these logical parameters to generate test cases representing the logical combinations. All these logical combination test cases form the test case set. Since different FPGA EDA function test points require different logical combination test cases, it is necessary to establish a statement generation model by introducing an industry-standard language (such as the IEEE Standard for Verilog Hardware Description Language) that includes all logical statement definitions. Using this model, statements representing different logic can be generated. Therefore, even if the test case structure logic differs, parameters representing different logical structures can be passed to the statement generation model, which can then generate statements representing those different logical structures.
[0051] The actual statement generation model is extremely complex to establish. For ease of explanation, we will only use Shift Register as an example for a brief explanation:
[0052] Step S301: Introduce the Shift Register statement from the industry language standard. An example of a Shift Register logical type 1 statement is as follows:
[0053] Logical type 1:
[0054] 8-Bit: "parameter WIDTH = 8;"
[0055] 32-Bit: "parameter WIDTH = 32;"
[0056] Step S302: Convert the logical type into a data structure. Here, we take the Class data structure as an example:
[0057] Class Shift Register:
[0058] Logical type 1:
[0059] 8-Bit: "parameter WIDTH = 8;"
[0060] 32-Bit: "parameter WIDTH = 32;"
[0061] Logical type 2:
[0062] Rising edge clock: "posedge clk"
[0063] Falling edge clock: "negedge clk"
[0064] Logical type 3:
[0065] Concatenation-based:
[0066] $Logical type 1
[0067] reg [WIDTH-1:0] shreg;
[0068] always @($logical type 2)
[0069] begin
[0070] if (clken)
[0071] shreg = {shreg[WIDTH-2:0], SI};
[0072] end
[0073] assign SO = shreg[WIDTH-1];”
[0074] For-loop based:
[0075] $Logical type 1
[0076] integer i;
[0077] always @($logical type 2)
[0078] begin
[0079] if (clken)
[0080] begin
[0081] for (i = 0; i < WIDTH-1; i = i+1)
[0082] shreg[i+1] <= shreg[i];
[0083] shreg[0] <= SI;
[0084] end
[0085] end
[0086] assign SO = shreg[WIDTH-1]; ”
[0087] Step S303: Based on the parameter information obtained after combination in step S2, extract statements from the data structure in step S302 and combine them.
[0088] Taking one of the combinations as an example: { Shift Register: [8-Bit, Rising edge clock, Activehigh clock enable, Concatenation-based], Block RAM: [Read first, Pipeline, Single-port]}
[0089] Extract statements from the Class class based on the corresponding parameter information:
[0090] Logical type 1:
[0091] 8-Bit: "parameter WIDTH = 8;"
[0092] Logical type 2:
[0093] Rising edge clock: "posedge clk"
[0094] Logical type 3:
[0095] Concatenation-based:
[0096] $1
[0097] reg [WIDTH-1:0] shreg;
[0098] always @($2)
[0099] begin
[0100] if ($3)
[0101] shreg = {shreg[WIDTH-2:0], SI};
[0102] end
[0103] assign SO = shreg[WIDTH-1];"
[0104] Combining statements yields the case design:
[0105] Concatenation-based:
[0106] parameter WIDTH = 8;
[0107] reg [WIDTH-1:0] shreg;
[0108] always @( posedge clk)
[0109] begin
[0110] if (clken)
[0111] shreg = {shreg[WIDTH-2:0], SI};
[0112] end
[0113] assign SO = shreg[WIDTH-1];
[0114] To obtain the final case study, add a case name (e.g., CASE_1) and a top module (e.g., top_1) to your case design. (Only the content required for the example is listed here.)
[0115] Following the above process, generate corresponding cases for all combined parameter information to obtain the test case set.
[0116] S4, the parameter conversion module, converts the logical combination parameter information corresponding to each test case into the parameters required for the operation of EDA software, tb generation, simulation equivalence verification and other tools.
[0117] The logic combination parameter information for this embodiment is shown in the following table:
[0118] Table 3
[0119]
[0120] S5. Input the test case set and parameter information into the automated verification module, and automatically run the automated operation commands, including EDA software, tb generation, simulation equivalence verification and other tools.
[0121] The automated execution command for this example is as follows:
[0122] EDA tools –source CASE_1 –top_module top_1
[0123] EDA tools – source CASE_2 – top_module top_2
[0124] …
[0125] S6. The results statistics module runs the automated results statistics command, automatically performing the results statistics process. This completes the entire process.
[0126] Collect the result files and log files from the run, extract them, and create a table. An example of the table content is provided here:
[0127] Table 4
[0128]
[0129] The tools for generating .tb files, performing simulation equivalence verification, and statistical analysis are all existing technologies and will not be described further here.
[0130] Example 2
[0131] Figure 4 This invention illustrates a specific implementation of the FPGA EDA software test case automated generation and verification system, including:
[0132] The logic parameter combination module is used to combine different logic parameters in a parameter file, which describes all the logic contained in the test cases to be generated.
[0133] The statement generation model module is used to generate a test case set based on logical parameter information.
[0134] The parameter conversion module is used to convert logical parameter combination information into parameters required for the operation of tools such as EDA software, tb generation, and simulation equivalence verification.
[0135] The automated verification module is used to automatically run commands for tools such as EDA software, tb generation, and simulation equivalence verification based on the input test case set and parameter information.
[0136] The results statistics module is used to run automated commands and automatically perform results statistics.
[0137] The specific process for automating test case generation and verification using the above system is as follows: Figure 5 As shown, the specific details of the process are as described in Example 1.
Claims
1. A method for test case automatic generation and verification of FPGA EDA software, characterized in that, Includes the following steps: S1, Configuration parameter file; S2. The parameter file is traversed by the logic parameter combination module to traverse all logic combinations and perform combinations between different logic parameters. S3. Use the statement generation model to generate a test case set based on logical parameter information; S4. The parameter conversion module converts the combined logical parameter information into the parameter information required for the verification process. S5. Input the test case set and parameter information into the automated verification module to automatically run the verification process; S6. The results statistics module automatically performs the results statistics process.
2. The method of claim 1, wherein the method further comprises: The parameter file describes all the logic contained in the test cases that need to be generated.
3. The method of claim 1, wherein the method further comprises: In step S5, the automatic verification process specifically refers to the automatic execution of automated running commands, including EDA software, generating tb, and simulation equivalence verification; in step S4, the parameter information required for the verification process includes the parameters required for the operation of tools such as EDA software, generating tb, and simulation equivalence verification.
4. A test case automatic generation and verification system for FPGA EDA software, characterized in that, include: The logic parameter combination module is used to combine different logic parameters in a parameter file; The statement generation model module is used to generate test case sets based on logical parameter information. The parameter conversion module is used to convert logical parameter combinations into parameter information required for the verification process. The automated verification module is used to automatically run the verification process based on the input test case set and parameter information; The results statistics module is used to automatically perform results statistics.
5. The FPGA EDA software test case automatic generation and verification system according to claim 4, wherein: The parameter file describes all the logic contained in the test cases that need to be generated.
6. The FPGA EDA software test case automatic generation and verification system according to claim 4, wherein: The automated verification process specifically involves automatically running automated commands, including EDA software, generating tb files, and performing simulation equivalence verification. The required parameters for the verification process include the parameters required for the operation of the tools, including EDA software, generating tb files, and performing simulation equivalence verification.