Memory channel address multiplexing apparatus, processor and electronic device

Abstract

This invention discloses a memory channel address multiplexing device, processor, and electronic device. The device includes a memory channel input port and an address calculation multiplexer. The memory channel input port is used to connect to the request queues corresponding to the mapped physical hash indices of each memory channel. The address calculation multiplexer is used to calculate the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the current mapped physical hash index corresponding to the current address request, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index. It is also used to calculate the NoC physical address of the current mapped physical hash index based on the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index, which can improve the availability of subsequent cache processing.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a memory channel address multiplexing device, processor and electronic device. Background Technology

[0002] With the increasing number of memory chips used in AI (Artificial Intelligence) chips, such as HBM (High Bandwidth Memory) or GDDR (Graphics Double Data Rate Synchronous Dynamic Random Access Memory, or VRAM), the demand for memory capacity is growing. Improving the yield and reliability of memory systems has become an increasingly urgent issue. These memory chips constitute multi-channel memory systems, with each channel operating independently. This means that even if some channels are defective, others can still be used.

[0003] In the field of AI chips, from the perspective of operator development friendliness, the memory seen by the software is a contiguous and affinity-free address space to avoid performance issues such as address imbalance. Address affinity is generally achieved by evenly distributing address requests across memory channels using address hashing algorithms. Simultaneously, the address hash mapper typically needs to multiplex address access requests corresponding to multiple physical hash indices onto a small number of AXI (Advanced eXtensible Interface) bus output ports. When the total number of NoC master ports (NoC master ports facing the target device) on the NoC (Network-on-Chip) is less than the number of physical hash indices, port address multiplexing is required to multiplex the addresses of memory channels (one memory channel can be called a slot) corresponding to multiple physical hash indices into the address space of the NoC master ports. In scenarios where memory channels are masked, some memory channels may be disabled due to masking, and the actual number of input paths that need to be multiplexed (corresponding to the number of available memory channels) will dynamically change, for example, from 4 memory channels to 3 or 2 memory channels. Figure 1 This is a schematic diagram illustrating the effect of address mapping using a conventional fixed-ratio multiplexing circuit in existing technology. For example, such as... Figure 1 As shown, the number of inputs to each multiplexer is the same as the number of memory channels within the memory channel group. Assuming slot-1 is masked, this means the physical hash index corresponding to the second memory channel group is masked. In this case, if a simple interleave algorithm is used to directly calculate the output address offset based on the input offset and the number of memory channels included in the memory channel group, a large number of holes will be generated in the output address space.

[0004] In other words, in the scenario of memory channel shielding, the number of effective input memory channels (slots) of the multiplexer is variable. Traditional fixed ratio multiplexing circuits (such as fixed 4:1 multiplexers) cannot handle this dynamic change, which causes the output address access request to have a hole in the output address space, which in turn makes it difficult for downstream cache circuits to handle. For example, prefetching a hole address will cause a functional error. Summary of the Invention

[0005] This invention provides a memory channel address multiplexing device, processor, and electronic device that can ensure the continuity of the output address of the memory channel, thereby meeting the caching requirements of the subsequent cache circuit and improving the availability of the subsequent cache processing.

[0006] According to one aspect of the present invention, a memory channel address multiplexing device is provided, comprising a memory channel input port and an address calculation multiplexer, wherein: The memory channel input port is communicatively connected to the address calculation multiplexer and is used to connect the request queue corresponding to the mapped physical hash index of each memory channel; The address calculation multiplexer is used to calculate the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the current mapped physical hash index corresponding to the current address request, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index. The address calculation multiplexer is also used to calculate the NoC physical address of the current mapped physical hash index based on the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index.

[0007] According to another aspect of the present invention, a processor is provided, the processor including the memory channel address multiplexing device described in any embodiment of the present invention.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device including the processor described in the embodiments of the present invention.

[0009] This invention provides a memory channel address multiplexing device by using memory channel input ports and an address calculation multiplexer. The device connects to the request queues corresponding to the mapped physical hash indices of each memory channel through the memory channel input ports. The address calculation multiplexer calculates the output base address and output address offset of the valid mapped physical hash indices within the current mapped physical hash index based on the current mapped physical hash index of the current memory channel, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index. Furthermore, the device calculates the NoC physical address of the current mapped physical hash index based on the output base address and output address offset. This memory channel address multiplexing device can adaptively adjust the NoC main port address based on the number of input paths at the memory channel input ports according to the masking situation, thereby ensuring the continuity of the memory channel output addresses, meeting the caching requirements of subsequent cache circuits, and improving the availability of subsequent cache processing.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram illustrating the effect of address mapping using a traditional fixed-ratio multiplexing circuit in existing technology. Figure 2 This is a schematic diagram of the structure of a memory channel address multiplexing device provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the layout structure of a physical hash index space provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of another physical hash index space layout structure provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure of a multi-channel memory system provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the structure of a memory channel address multiplexing device provided in Embodiment 2 of the present invention; Figure 7 This is a schematic diagram of another memory channel address multiplexing device provided in Embodiment 2 of the present invention; Figure 8 This is a schematic diagram illustrating the calculation of the output address offset by a memory channel address multiplexing device according to Embodiment 2 of the present invention; Figure 9 This is a schematic diagram illustrating the effect of an adaptive calculation of multiple memory channel address multiplexing mapping provided in Embodiment 2 of the present invention. Figure 10 This is a schematic diagram illustrating the effect of adaptive calculation of multiple memory channel address multiplexing mapping provided by another memory channel address multiplexing device in Embodiment 2 of the present invention; Figure 11 This is a schematic diagram of the structure of a processor provided in Embodiment 3 of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0014] It should be noted that the terms "first," "second," and "third," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] Currently, many types of memory chips can provide multiple memory channels for AI chips. Memory chips may include, but are not limited to, HBM chips or multiple GDDR6 (Graphics Double Data Rate, version 6) chips.

[0016] Taking HBM chips as an example, HBM chips are essentially a type of memory chip designed for high-bandwidth and low-latency scenarios, and are widely used in AI training servers and high-performance computing technologies. HBM chips can be integrated into AI chips. Each AI chip can integrate one or more HBM chips.

[0017] For HBM chips, the core hierarchical structure from top to bottom is: Stack, Channel, Bank Group (BG), Bank, Row / Column, and Cell. A Channel, also known as a physical memory channel or memory channel, is abbreviated as CH. An HBM chip by default includes eight independent memory channels, each with independent commands and addresses, a 128-bit independent data width, and an independent bank array. Each memory channel contains an independent controller, physical layer circuitry, and particle-side circuitry. Multiple memory channels operate in parallel to provide high bandwidth. The complete parallelism and non-interference between memory channels are the core source of HBM's high bandwidth. A memory channel can include multiple Bank Groups, and different Bank Groups can activate different rows in parallel to improve parallelism and reduce conflicts. A Bank is the smallest truly independently operating memory unit. Each Bank has its own row buffer and contains a memory cell array (composed of Rows and Columns), a set of Sense Amplifiers Arrays, and independent row / column decoders and control logic. Only one row can be opened in the same bank at a time, but different banks can be opened in parallel. A row is the smallest unit of activation, consisting of multiple columns. Once opened, the entire row enters the row buffer. A column can be understood as selecting data from the row buffer, where the sum of the column address and the burst length is the actual transmission block.

[0018] In the field of AI chips, from the perspective of operator development friendliness, the memory seen by the software is a contiguous and affinity-free address space to avoid performance issues such as address imbalance. Address affinity is generally achieved by evenly distributing address requests across memory channels using address hashing algorithms. In some cases, certain memory channels need to be masked due to defects or faults. Directly disabling masked faulty memory channels would result in "holes" in the physical channel space. Performing hash operations directly with some memory channels disabled would lead to uneven address request mapping, overloading some memory channels and severely impacting memory access functionality.

[0019] Therefore, after receiving an external address request initiated by the master device, the memory channel address mapping device can sequentially skip the masked physical memory channels from the virtual hash index space, thereby uniformly mapping the external address request to the actually available physical memory channels. Specifically, in response to the external address request, the memory channel address mapping device can read the relevant masked physical memory channel information and hash matrix register information to obtain basic information about the masked physical memory channels (such as the number of masked physical memory channels) and the register array information referenced for generating the virtual hash index. Based on a preset hash algorithm and the information read above, it generates a continuous virtual hash value index V for the external address request in the virtual hash index space. Further, the memory channel address mapping device traverses and maps the generated virtual hash index to the physical hash index in the physical hash index space corresponding to the physical memory channel. During the mapping process, if the physical hash index mapped by the virtual hash index is not the physical hash index of the masked physical memory channel, the memory channel address mapping device can traverse each virtual hash index sequentially according to the order of the virtual hash index and the physical hash index and map them sequentially to the corresponding sequentially arranged physical hash index. If the physical hash index mapped by the virtual hash index is a physical hash index that masks the physical memory channel, the memory channel address mapping device can skip the physical hash index that masks the physical memory channel for the current virtual hash index, and traverse the subsequent physical hash indices in the order of the physical hash indices until an unmasked physical hash index of an available physical memory channel is found for mapping.

[0020] Therefore, the aforementioned memory channel address mapping device can find the real usable physical hash index by skipping the physical hash index of the masked physical memory channel based on the virtual hash index and the physical hash index of the masked physical memory channel. This achieves order-preserving mapping from a continuous virtual hash index space to a non-contiguous physical hash index space. In other words, by skipping the physical hash index of the masked physical memory channel, the real usable physical hash index is found, so that the physical hash index still maintains its original order after the mapping process. This adaptive address mapping capability, which can handle any number and any position of masked memory channels, maximizes the parallel access performance of high-bandwidth memory.

[0021] It should be noted that the port naming in this embodiment of the invention is from the perspective of the NoC (NoC) side. Specifically, the NoC master port can refer to the port of the NoC facing the target device, such as a memory controller. Corresponding to the NoC master port is the NoC slave port, which can specifically refer to the port of the NoC facing the initiating device, such as a processor core and DMA (Direct Memory Access). In this embodiment of the invention, "output port" or "current channel output port" refers to the NoC master port connected to the output side of the address multiplexing device; out_port_idx is the port number of this NoC master port. Furthermore, in this embodiment of the invention, "memory channel group" and "Wrap" are the same concept, and "input path" and "slot" are the same concept.

[0022] In this embodiment of the invention, the memory channel address multiplexing device and the memory channel address mapping device are different functional units. The memory channel address mapping device maps external address requests to the physical hash index space; the memory channel address multiplexing device, as a downstream unit of the memory channel address mapping device, multiplexes the address requests corresponding to the mapped physical hash indexes to the NoC main port address space and generates continuous, hole-free output addresses. Where there is no conflict, the memory channel address mapping device can be implemented by other modules in the same chip, or it can be implemented independently; this embodiment of the invention does not impose any limitations on this.

[0023] Example 1 Figure 2 This is a schematic diagram of the structure of a memory channel address multiplexing device provided in Embodiment 1 of the present invention, as shown below. Figure 2 As shown, the structure of this memory channel address multiplexing device includes a memory channel input port 10 and an address calculation multiplexer 20, wherein: Memory channel input port 10 is communicatively connected to address calculation multiplexer 20, used to connect the request queues corresponding to the mapped physical hash indices of each memory channel; address calculation multiplexer 20 is used to calculate the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the current mapped physical hash index corresponding to the current address request, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index; address calculation multiplexer 20 is also used to calculate the NoC physical address of the current mapped physical hash index based on the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index.

[0024] Among them, memory channel input port 10 serves as the input port of the memory channel address multiplexing device, and can connect to the request queue corresponding to the mapped physical hash index of each memory channel. The mapped physical hash index can be a physical hash index with a mapping relationship after the external address request generates a continuous virtual hash index in the virtual hash index space and further performs mapping processing in the physical hash index space.

[0025] The address calculation multiplexer 20 can calculate the address of the external address request corresponding to the mapped physical hash index in the physical hash index space, and then multiplex it to the specific physical address in the physical address space on the NoC, ensuring that the address of the mapped physical hash index is reused continuously without gaps in the physical address space on the NoC. The current address request can be the external address request that needs mapping processing. The mapped physical hash index, also known as the physical hash index with a mapping relationship to the virtual hash index, is the target physical hash index mapped by the virtual hash index in the physical hash index space. The current mapped physical hash index can be the physical hash index in the physical hash index space of the memory channel that the current address request maps to through the corresponding virtual hash index. The physical hash index space can be the set of physical hash indices corresponding to the physical memory channels identified by the hash index structure. A physical hash index refers to the hash value index in the physical hash index space. Masking the associated physical hash index information can mask some information associated with the physical hash index, such as including but not limited to masking the physical hash index and masking the valid tag sequence corresponding to the physical hash index. The valid tag sequence can store and record the valid information of the masked physical hash index. The address offset of the current mapped physical hash index can be the address offset of the current address request within the current mapped physical hash index, that is, the address offset of the current address request in the physical hash index space. A valid mapped physical hash index can be any mapped physical hash index within the current mapped physical hash index that is not masked.

[0026] Specifically, the output base address of the valid mapped physical hash index in the current mapped physical hash index can be the base address calculated in the physical address space of the valid mapped physical hash index on the NoC, specifically the base address of the valid mapped physical hash index at the NoC main port. The output address offset of the valid mapped physical hash index in the current mapped physical hash index can be the offset within the base address space of the valid mapped physical hash index on the NoC, specifically the offset within the base address space of the valid mapped physical hash index at the NoC main port.

[0027] In this embodiment of the invention, a memory channel address multiplexing device (Mux) can be connected between the physical hash layer of the memory channel and the NoC main port. Each NoC main port can be configured with a memory channel address multiplexing device placed in front of it. Optionally, the NoC main port can be understood as the port of the NoC facing the target device, which can be used to access the memory channel. The memory channel address multiplexing device connects to the request queue corresponding to the mapped physical hash index of each memory channel through the memory channel input port 10. The number of input paths of the memory channel input port 10 is the maximum number of supported memory channels, such as the number of memory channels within a group of memory channels in the physical hash index space.

[0028] In an optional embodiment of the present invention, the layout configuration information of the physical hash index space may include the number of memory channel groups, the number of channel group access ports, and the number of memory channels within a memory channel group. The number of memory channel groups is the total number of memory channel groups. The number of channel group access ports can be the number of NoC main ports accessing a group of memory channel groups. For example, a channel group access port count of 2 indicates that a group of memory channel groups can be accessed through 2 NoC main ports. The number of memory channels within a memory channel group is the total number of memory channels included in a memory channel group.

[0029] Figure 3 This is a schematic diagram of the layout structure of a physical hash index space provided in Embodiment 1 of the present invention. Figure 4 This is a schematic diagram of another physical hash index space layout structure provided in Embodiment 1 of the present invention. In a specific example, such as Figure 3 and Figure 4 As shown, the number of memory channel groups can be abbreviated as W, the number of channel group access ports can be abbreviated as P, and the number of memory channels within a memory channel group can be abbreviated as C. For example, taking HBM as an example, HBM uses 4 memory channels as a group. If there are a total of 4 HBMs, and each HBM has 16 memory channels, and 4 memory channels form a memory channel group (Wrap), then there are a total of 16 memory channel groups across the 4 HBMs, and the value of W is 16. Assuming each memory channel group has P NoC master ports on the NoC, these P NoC master ports on the NoC are the P channel group access ports, which are essentially NoC master ports. This means that the master device can access the memory channel group from any one of the P NoC master ports. For example... Figure 3As shown, each layer of each P dimension in the physical hash index space represents a NoC main port, and each group of C dimensions (4 memory channels) represents a memory channel group. Each memory channel has a unique identifier in the physical hash index space; for example, 0 represents the first memory channel of the first memory channel group on the first NoC main port, and w+3 represents the first memory channel of the fourth memory channel group on the second NoC main port. Figure 3 and Figure 4 As shown, the total number of main ports in the memory channel group is P. W is the sum of the NoC master ports P0-Pn of all channel groups. For example... Figure 4 As shown, each NoC master port Pn can be configured with a memory channel address multiplexing device.

[0030] like Figure 3 and Figure 4 As shown, the CPW of the physical hash index space represents the memory architecture parameters of the chip. For example, CPW=[4,2,8] can represent 8 memory channel groups, each with 2 NoC main ports and 4 memory channels; CPW=[4,2,16] can represent 16 memory channel groups, each with 2 NoC main ports and 4 memory channels. Figure 3 and Figure 4 The physical hash index space adopts a layout of CPW=[4,2,16]. Any memory channel can be uniquely identified by coordinates or a linear memory channel number. For example, the coordinate identifier can be (ci,wi), which indicates that the memory channel ci is located within the memory channel group wi. The linear memory channel identifier can be: ch_idx=wi C+ci. Where ch_idx represents the linear memory channel number, wi represents the memory channel group identifier, and ci represents the identifier of the memory channel within memory channel group wi. In addition, the number of masked physical memory channels in the physical hash index space can be counted as N. Masked physical memory channels can include faulty memory channels and redundant memory channels. Redundant memory channels can be currently unused and in an idle state, which can be used to replace faulty memory channels. Furthermore, a masked physical memory channel list, Mask_CH_List, can be configured for masked physical memory channels. Mask_CH_List can use linear memory channel identifiers, with values ​​ranging from [0, C...]. W-1].

[0031] like Figure 3 and Figure 4As shown, in the CPW layout mode, these physical hash indices are arranged in the physical hash index space according to a certain pattern, with the memory channel group index W as the lowest dimension and the memory channel indices within the memory channel group as the highest dimension. Regardless of whether a memory channel is masked, each memory channel has P indices in the physical hash index space. If any one or more memory channels are masked, several holes will be created in the physical hash index space, resulting in a discontinuous physical hash index space. The total number of physical hash indices included in the physical hash index space is phy_hash_idx_count = C. P W. The CPW layout mode can balance memory access bandwidth at the memory channel level / port level, allowing the master device to obtain maximum bandwidth.

[0032] Correspondingly, when considering linear address access scenarios, in the CPW layout mode, linear address access requests are first hashed on the memory channel group dimension (W), then on the port dimension (P), and finally on the memory channel dimension (C) within the memory channel group. This layout allows for obtaining the bandwidth of the entire memory channel group with smaller linear accesses.

[0033] For example, such as Figure 3 As shown, assuming the 0th memory channel of Wrap-3 (i.e., the 4th memory channel group) is masked, its two corresponding indices "3 and w+3" in the physical hash index space will also be masked. Figure 4 As shown, assuming the first memory channel of Wrap-0 (i.e., the first group of memory channels) is masked, its two corresponding indices "2w and 3w" in the physical hash index space will also be masked. The formula for the physical hash index of any memory channel can be: given the memory channel coordinates (ci, wi), its physical hash index at the first NoC main port is: s_0 = ci W The physical hash index of the second NoC main port is P+wi: s_1=s_0+W. If P>=2, the physical hash indices of other NoC main ports are deduced sequentially. Given a linear channel number ch_idx, its range is [0,C]. W-1], then its physical hash index on the first NoC main port is: The physical hash index of the linear channel number ch_idx on the second NoC main port is: s_1 = s_0 + W. If P >= 2, the physical hash indices of the other NoC main ports are calculated sequentially. Here, (ch_idx%C) represents converting the linear channel number ch_idx to the channel number ci within the memory channel group, and (ch_idx / C) represents the memory channel group number wi. Therefore, the physical hash index of the linear channel number ch_idx on the first NoC main port is converted to: s_0 = ci. W P+wi.

[0034] Figure 5 This is a schematic diagram of a multi-channel memory system provided in Embodiment 1 of the present invention. For example, Figure 5 As shown, when the memory system supports prefetching of the subsequent cache, the output address request cannot have holes in the output address space; otherwise, the downstream cache circuitry will have difficulty processing it, for example, prefetching a hole address will cause a functional error. In this case, after the virtual hash index of the external address request is mapped to the corresponding mapped physical hash index, each mapped physical hash index constitutes a request queue and is connected to the memory channel input port 10 of the memory channel address multiplexing device. Accordingly, the memory channel address multiplexing device can sequentially map each mapped physical hash index connected to the memory channel input port 10 to the port address output of the SoC (System on a Chip) through the address calculation multiplexer 20 to determine the specific output address of the mapped physical hash index in the SoC's NoC network.

[0035] When the memory channel address multiplexing device further maps the mapped physical hash index to the port address of the SoC, for the current mapped physical hash index corresponding to the current address request that needs to be mapped, the memory channel address multiplexing device can obtain the layout configuration information of the physical hash index space and the associated information of the masked physical hash index through the address calculation multiplexer 20 to determine the layout information of the masked physical hash index in the physical hash index space. Based on this, the address calculation multiplexer 20 obtains the address offset of the current mapped physical hash index, thereby determining the address offset of the masked physical hash index and the valid mapped physical hash index within the physical hash index space. Further, by excluding the address offset information of the masked physical hash index in the physical hash index space, the address calculation multiplexer 20 can obtain the address offset of the valid mapped physical hash index in the physical hash index space, and then calculate the output address offset of the valid mapped physical hash index in the current mapped physical hash index. Simultaneously, the address calculation multiplexer 20 can also calculate the output base address of the current mapped physical hash index based on the information obtained above through the NoC's internal routing mechanism.

[0036] Furthermore, the address calculation multiplexer 20 calculates the NoC physical address of the entire current mapped physical hash index based solely on the output base address and output address offset of the valid mapped physical hash indexes within the current mapped physical hash index. That is, by using the address calculation multiplexer 20 to calculate the output base address and output address offset of the current mapped physical hash index, the mapping information of the masked physical hash index on the NoC main port can be removed, thus ensuring that the address space of the current mapped physical hash index reused in the NoC is continuous and without gaps.

[0037] It is understandable that when the mapped physical hash index is reused in the NoC address space without any gaps, the subsequent cache structure can successfully implement the cache prefetch function in the continuously distributed address space according to the prefetch strategy, thereby ensuring the availability of subsequent cache processing and meeting the cache requirements of subsequent cache circuits.

[0038] This invention provides a memory channel address multiplexing device, which uses memory channel input ports and an address calculation multiplexer. The device connects to the request queues corresponding to the mapped physical hash indices of each memory channel via the memory channel input ports. The address calculation multiplexer calculates the output base address and output address offset of the valid mapped physical hash indices within the current mapped physical hash index based on the current mapped physical hash index of the current memory channel, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index. Furthermore, the device calculates the NoC physical address of the current mapped physical hash index using the address calculation multiplexer based on the output base address and output address offset. This memory channel address multiplexing device can adaptively adjust the multiplexing ratio and port order to calculate the NoC main port address based on the memory channel masking situation, ensuring the continuity of the memory channel output addresses and thus meeting the caching requirements of subsequent cache circuits and improving the availability of subsequent cache processing.

[0039] Example 2 Figure 6 This is a schematic diagram of a memory channel address multiplexing device provided in Embodiment 2 of the present invention. The embodiments of the present invention are based on the above embodiments and are further specified. In the embodiments of the present invention, a specific implementation of the address calculation multiplexer is given.

[0040] Correspondingly, such as Figure 6As shown, the address calculation multiplexer 20 may include an output port calculation module 210, a memory channel detection module 220, a control status register 230, an address multiplexing module 240, and an address calculation module 250. Specifically: the output port calculation module 210 is communicatively connected to the memory channel input port 10, the memory channel detection module 220, and the address calculation module 250, and is used to calculate the current channel output port corresponding to the current mapped physical hash index and the output base address of the valid mapped physical hash index in the current mapped physical hash index, based on the current mapped physical hash index and the layout configuration information of the physical hash index space; the control status register 230 is communicatively connected to the memory channel detection module 220 and is used to store the masked physical hash index. The memory channel detection module 220 is also communicatively connected to the address multiplexing module 240, and is used to calculate memory channel shielding information based on the current channel output port corresponding to the current mapped physical hash index, the shielded physical hash index association information, and the layout configuration information of the physical hash index space; the address multiplexing module 240 is also communicatively connected to the address calculation module 250, and is used to calculate the output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the memory channel shielding information and the address offset of the current mapped physical hash index; the address calculation module 250 is used to calculate the NoC physical address of the current mapped physical hash index based on the output address offset of the valid mapped physical hash index in the current mapped physical hash index and the output base address.

[0041] The output port calculation module 210 can be used to calculate the current channel output port of the current mapped physical hash index, and can also further calculate the output base address of the current mapped physical hash index based on the current channel output port of the previous mapped physical hash index. Specifically, the output port calculation module 210 can determine the currently processed mapped physical hash index from the request queue corresponding to the mapped physical hash index of each memory channel connected to the memory channel input port, and then calculate the current channel output port corresponding to the current mapped physical hash index based on the layout configuration information CPW of the physical hash index space. The current channel output port corresponding to the current mapped physical hash index can be the NoC main port Px converted from the current mapped physical hash index in the physical hash index. The output port calculation module 210 can calculate the base address of the NoC main port Px corresponding to the current mapped physical hash index based on the current channel output port corresponding to the current mapped physical hash index and the NoC routing table. There is a preset mapping relationship between the port identifier Pn of the NoC main port and its NoC base address, i.e., the NoC routing table. Simultaneously, the current channel output port corresponding to the current mapped physical hash index can also be used to calculate the output address offset of the current mapped physical hash index.

[0042] The control status register 230 can be used to store masked physical hash index association information. The memory channel detection module 220 can read the masked physical hash index association information stored in the control status register 230, and, based on the layout configuration information CPW of the physical hash index space, combine it with the current channel output port corresponding to the current mapped physical hash index calculated by the output port calculation module 210 to comprehensively calculate various types of memory channel masking information. The memory channel masking information can be result information and processing information related to memory channel masking, such as, but not limited to, the number of masked physical memory channels and the number of valid mapped physical hash indices after excluding masked physical memory channels. The memory channel masking information calculated by the memory channel detection module 220 can be further sent to the address multiplexing module 240.

[0043] Correspondingly, the address multiplexing module 240 obtains the memory channel masking information calculated by the memory channel detection module 220, and can also receive the address offset of the current address request's current mapped physical hash index in the physical hash index space calculated and output by the memory channel address mapping device. That is, when mapping the virtual hash index of the current address request to the corresponding current mapped physical hash index, the memory channel address mapping device can calculate the address offset `offset_in` of the current address request in the physical hash index space according to relevant parameters and calculation methods. This address offset represents the address offset of the current address request within the corresponding physical hash index. In other words, a physical hash index corresponding to a memory channel can also include multiple address offsets. For example... Figure 3 or Figure 4 As shown, the physical hash index of the memory channel marked "0" can include multiple address offsets. Correspondingly, the physical hash index of the memory channel marked "0" can establish a mapping relationship with the virtual hash indices of multiple external address requests. Further, the address multiplexing module 240 calculates the output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the memory channel masking information and the address offset of the current mapped physical hash index.

[0044] Finally, the output address offset of the valid mapped physical hash index in the current mapped physical hash index calculated by the address multiplexing module 240 is sent to the address calculation module 250 as offset_out, and the output base address of the valid mapped physical hash index in the current mapped physical hash index calculated by the output port calculation module 210 is also sent to the address calculation module 250 as BASE_ADDR. Optionally, the address calculation module 250 can calculate the NoC physical address pa_out of the current mapped physical hash index based on the formula: pa_out = BASE_ADDR + offset_out.

[0045] In an optional embodiment of the present invention, such as Figure 6 As shown, the memory channel detection module 220 may include a valid input channel number detection module 221 and a port sorting module 222, wherein: the valid input channel number detection module 221 is communicatively connected to the address multiplexing module 240 and the control status register 230, and is used to calculate the number of valid input memory channels of the current channel output port according to the masked physical hash index association information; the port sorting module 222 is communicatively connected to the address multiplexing module 240 and the control status register 230, and is used to calculate the port sorting result according to the masked physical hash index association information and the layout configuration information of the physical hash index space; the address multiplexing module 240 is used to calculate the output address offset of the valid mapped physical hash index in the current mapped physical hash index according to the number of valid input memory channels, the port sorting result and the address offset of the current mapped physical hash index.

[0046] Specifically, the memory channel detection module 220 can be further divided into a valid input path detection module 221 and a port sorting module 222. The valid input path detection module 221 calculates the valid input path for the current address request. Specifically, it obtains the number of masked physical hash indices based on the masked physical hash index association information, and then determines the number of masked physical memory channels based on the number of masked physical hash indices. Simultaneously, the valid input path detection module 221 determines the theoretical total number of input paths for the current channel output port, and then subtracts the number of masked physical memory channels from the theoretical total number of input paths for the current channel output port to obtain the valid input memory channel count for the current channel output port.

[0047] The port sorting module 222 can determine the number and position of the masked physical hash indexes based on the masked physical hash index association information, and thus determine the skip count based on the number and position of the masked physical hash indexes. Simultaneously, the port sorting module 222 can calculate the basic sorting of the current mapped physical hash index within the set of all physical hash indices mapped to the current channel output port based on the layout configuration information of the physical hash index space. Then, by subtracting the skip count from the basic sorting, the port sorting result of the current mapped physical hash index can be obtained.

[0048] Correspondingly, the number of valid input memory channels at the current channel output port and the port sorting result of the current mapped physical hash index can be used as all types of memory channel masking information calculated by the memory channel detection module 220 and sent to the address multiplexing module 240. The address multiplexing module 240 can then specifically calculate the output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the number of valid input memory channels, the port sorting result, and the address offset of the current mapped physical hash index.

[0049] Figure 7 This is a schematic diagram of another memory channel address multiplexing device provided in Embodiment 2 of the present invention. In a specific example, such as Figure 6 and Figure 7 As shown, the output port calculation module can sequentially calculate the output port number `out_port_idx` for each memory channel's corresponding mapped physical hash index. Each output port number `out_port_idx` identifies a NoC master port, which can access a group of memory channels (Wrap). The effective input path detection module reads the masked physical hash index association information `masked_indices` and `masked_enable` from the control status register. `masked_indices` represents the masked physical hash indices, specifically ordered in ascending order; `masked_enable` represents the valid marker sequence of the masked physical hash indices. The effective input path detection module calculates the effective input memory channel count `effective_slot_num` based on the read masked physical hash index association information and the received output port number `out_port_idx`. Simultaneously, the effective input path detection module can calculate the output base address `BASE_ADDR` corresponding to the mapped physical hash index based on the output port number `out_port_idx`. This output base address can be used as the output base address corresponding to the effective mapped physical hash index within the mapped physical hash index. Optionally, the effective input path detection module can be implemented based on a popcount (Population Count Circuit, a digital circuit used to calculate the number of 1s in an input binary vector) circuit, and this embodiment of the invention does not limit this.

[0050] like Figure 7As shown, the port sorting module can use the set of all physical hash indices mapped to the output port as the base sorting rank_base, and calculate the number of physical hash indices skipped on the output port skipped by reading the masked physical hash index association information masked_indices and masked_enable from the control status register. Then, the port sorting result rank_p is calculated based on rank_base and skip_p.

[0051] like Figure 7 As shown, the address multiplexing module can be a variable-input multiplexer that can receive the effective input memory channel number effective_slot_num and the port sorting result rank_p, as well as the address offset offset_in of the mapped physical hash index of the external address request calculated by the memory channel address mapping device, and finally calculate the output address offset offset_out of the effective mapped physical hash index in the mapped physical hash index. Address calculation module ( Figure 7 "in The module can calculate the NoC physical address pa_out that maps the physical hash index based on BASE_ADDR and offset_out.

[0052] In an optional embodiment of the present invention, the output port calculation module 210 is further configured to: perform modulo operation on the current mapping physical hash index and the number of memory channel groups, calculate the product between the modulo result and the number of access ports of the channel group, and obtain a first calculation result; calculate the quotient of the current mapping physical hash index and the number of memory channel groups, perform modulo operation on the calculated quotient value and the number of access ports of the channel group, and obtain a second calculation result; calculate the sum of the first calculation result and the second calculation result to obtain the current channel output port corresponding to the current mapping physical hash index; and determine the output base address corresponding to the current mapping physical hash index based on the current channel output port corresponding to the current mapping physical hash index.

[0053] Specifically, assuming the number of memory channels within a memory channel group is C, the number of memory channel groups is W, the number of channel group access ports is P, and the current mapping physical hash index is p_hash_idx, then when calculating the current channel output port and output base address, the output port calculation module 210 can perform a modulo operation between the current mapping physical hash index p_hash_idx and the number of memory channel groups W: p_hash_idx%W. Further, it calculates the product of this modulo result and the number of channel group access ports P to obtain the first calculation result: (p_hash_idx%W). P. Simultaneously, the output port calculation module 210 can calculate the quotient of the current mapped physical hash index p_hash_idx and the number of memory channel groups W: p_hash_idx / W. The calculated quotient is then modulo-divided by the number of channel group access ports P to obtain a second calculation result: (p_hash_idx / W)%P. Finally, the first and second calculation results are added together to obtain the current channel output port corresponding to the current mapped physical hash index. Based on the layout configuration information CPW of the physical hash index space and the above-mentioned output port calculation method, the specified NoC main port can be calculated for any given mapped physical hash index.

[0054] In an optional embodiment of the present invention, such as Figure 6 and Figure 7 As shown, the effective input path detection module 221 can also be used to: determine the masked physical hash index and the effective tag sequence of the masked physical hash index according to the masked physical hash index association information; wherein, the effective tag sequence is used to record the validity of the register of the masked physical hash index; traverse and calculate the channel output port of each of the masked physical hash indices; when it is determined that the channel output port of the currently traversed masked physical hash index is consistent with the current channel output port of the currently mapped physical hash index, update the count of the masked physical hash index; after the channel output port of each of the masked physical hash indices has been traversed, calculate the difference between the number of memory channels in the memory channel group and the count of the masked physical hash index to obtain the number of effective input memory channels.

[0055] The masked physical hash index is the physical hash index corresponding to the masked physical memory channel. The masked physical memory channel is the physical memory channel that is being masked; it is usually a defective or faulty physical memory channel, and can also be called a masked memory channel. The valid tag sequence for the masked physical hash index can be a bit sequence, where each bit represents the validity of the register corresponding to the masked physical hash index of a certain record.

[0056] Specifically, the valid input path detection module 221 can determine the masked physical hash indexes `masked_indices` and the valid tag sequence `masked_enable` based on the masked physical hash index association information. The masked physical hash indexes `masked_indices` can be used to store records of the masked physical hash indices in ascending order. Assuming the number of masked physical hash indices is `masked_idx_cnt`, and there are a total of `MAX_MASK_INDICES` register sequences for storing the masked physical hash indices, then the value range of `masked_idx_cnt` is [0, `MAX_MASK_INDICES-1`]. `masked_indices` values ​​outside the range of `masked_idx_cnt` will be ignored and controlled by the valid tag sequence `mask_enable`. In the valid tag sequence `mask_enable`, each bit represents whether a corresponding `masked_indices[i]` is valid. `mask_enable` has a total of `MAX_MASK_INDICES` bits. In mask_enable, all bits that are greater than or equal to masked_idx_cnt will be 0. For example, assuming MAX_MASK_INDICES=16 and masked_idx_cnt=4, then mask_enable[15:0]={12'b0,4'b1111}, with the high 12 bits being 0.

[0057] Furthermore, the effective input path detection module 221 iterates through and calculates the channel output ports of each masked physical hash index. The channel output port of each masked physical hash index can be calculated using the method described above for calculating the current channel output port. The effective input path detection module 221 sequentially determines whether the channel output port of the currently iterated masked physical hash index is consistent with the current channel output port of the currently mapped physical hash index. If it is determined that the channel output port of the currently iterated masked physical hash index is consistent with the current channel output port of the currently mapped physical hash index, the count of the masked physical hash index can be updated by incrementing the count by 1. After the channel output ports of the masked physical hash indexes are traversed, the difference between the number of memory channels C in the memory channel group and the count of the masked physical hash index is calculated to obtain the effective input memory channel count, effective_slot_num. In summary, the specific calculation rules for the effective input memory channel count, effective_slot_num, are related to the layout configuration of the physical hash index space. Specifically, it is the number of memory channels C in the memory channel group (also known as the number of input paths of the port) minus the number of masked physical hash indices corresponding to the channel output port.

[0058] In an optional embodiment of the present invention, such as Figure 6 and Figure 7 As shown, the port sorting module 222 can also be used to: calculate the sorting information of the current mapped physical hash index in the set of all physical hash indexes mapped to the current channel output port; calculate the number of times the masked physical hash index is skipped in the current mapped physical hash index; calculate the difference between the sorting information of the current mapped physical hash index in the set of all physical hash indexes mapped to the current channel output port and the number of skips, and obtain the port sorting result.

[0059] The port sorting module 222 can calculate the sorting information of the current mapped physical hash index in the set of all physical hash indices mapped to the current channel output port as rank_base. Simultaneously, the port sorting module 222 can calculate the number of times the masked physical hash index is skipped in the current mapped physical hash index. For example, assuming C=4, the physical hash index set [1,33,65,97] is mapped to the memory channel address multiplexing device, and the memory channel corresponding to physical hash index 65 is masked. Assuming the current mapped physical hash index corresponding to the current address request is 97, then the sorting information rank_base of the current mapped physical hash index in the set of all physical hash indices mapped to the current channel output port is rank_base=3. Since the current mapped physical hash index is 97, 97>65, the number of times the masked physical hash index is skipped in the current mapped physical hash index is skip_p=1. Furthermore, the port sorting module 222 calculates the difference between the sorting information rank_base of the current mapped physical hash index in the set of all physical hash indices mapped to the current channel output port and the skip count skip_p, obtaining the port sorting result rank_p = rank_base – skip_p. That is, the port sorting result is specifically the result of sorting the current mapped physical hash index in the set of all physical hash indices mapped to the current channel output port, and then deducting the physical hash indices that are mapped to the current channel output port but are blocked.

[0060] In an optional embodiment of the present invention, the port sorting module 222 may also be used to: calculate the total number of main ports of the memory channel group based on the number of access ports of the channel group and the number of memory channel groups in the physical hash index space; calculate the quotient between the current mapping physical hash index and the total number of main ports of the memory channel group to obtain the basic sorting information of the current mapping physical hash index in the set of physical hash indices mapped to the current channel output port.

[0061] Optionally, the port sorting module 222 can calculate the product between the number of access ports P of the physical hash index space channel group and the number of memory channel groups W to obtain the total number of master ports of the memory channel group: total_master_port_cnt, that is, total_master_port_cnt=P W. Therefore, the total number of master ports in the memory channel group is a constant, and the number of memory channel address multiplexing devices is the same as the total number of master ports in the memory channel group. Further, the port sorting module 222 calculates the quotient between the current mapped physical hash index p_hash_idx and the total number of master ports in the memory channel group total_master_port_cnt, obtaining the basic sorting information rank_base of the current mapped physical hash index in the set of all physical hash indices mapped to the current channel output port. That is, rank_base = p_hash_idx / total_master_port_cnt.

[0062] In an optional embodiment of the present invention, the port sorting module 222 may also be used to: initialize the skip count to 0; traverse each of the masked physical hash indices, and if it is determined that the current masked physical hash index is less than or equal to the current mapped physical hash index, calculate the channel output port of the current masked physical hash index; if it is determined that the channel output port of the current masked physical hash index is consistent with the current channel output port of the current mapped physical hash index, increment the skip count by unit.

[0063] The port sorting module 222, for the current address request's current mapped physical hash index p_hash_idx and its corresponding current channel output port out_port_idx, calculates how many masked physical hash indices should be skipped from the set of all masked physical hash indices mapped to the same current channel output port. The rule for calculating the skip count is that the elements of the set are less than or equal to the current mapped physical hash index. Specifically, the port sorting module 222 initializes the skip count to 0, traverses each masked physical hash index masked_indices, and performs the following steps: determines the validity of masked_indices[i] through the valid tag sequence mask_enable of the masked physical hash index. If masked_indices[i] is valid and masked_indices[i] is greater than the current mapped physical hash index p_hash_idx, then skip_p does not increment; if masked_indices[i] is valid and masked_indices[i] is less than or equal to the current mapped physical hash index p_hash_idx, then calculates the channel output port of the current masked physical hash index. If the channel output port of the currently masked physical hash index is the same as the current channel output port out_port_idx of the currently mapped physical hash index, then skip_p increments by 1 each time; otherwise, it does not increment, thus obtaining the final skip_p.

[0064] It should be noted that the calculation process of rank_base and rank_p mentioned above can generally be implemented using popcount in hardware. Specifically, skip_p can use mask_enable to mask out invalid masked_indices.

[0065] In an optional embodiment of the present invention, the address multiplexing module 240 may also be used to: calculate the product of the address offset of the current mapped physical hash index and the number of valid input memory channels to obtain a third calculation result; calculate the sum of the third calculation result and the port sorting result to obtain the output address offset of the valid mapped physical hash index in the current mapped physical hash index.

[0066] Figure 8 This is a schematic diagram illustrating the calculation of the output address offset by a memory channel address multiplexing device according to Embodiment 2 of the present invention. In a specific example, such as... Figure 8As shown, the address multiplexing module 240 receives the address offset_in from the current mapped physical hash index, combines it with the effective input channel number detection module 221's calculated effective input memory channel number effective_slot_num and the port sorting result rank_p calculated by the port sorting module 222, calculates the output address offset_out of the effective mapped physical hash index in the current mapped physical hash index according to the core mapping formula, and sends the request to the NoC main port. Specifically, the address multiplexing module 240 calculates the product of the address offset of the current mapped physical hash index and the effective input memory channel number to obtain the third calculation result: offset_in. effective_slot_num. Further, the address multiplexing module 240 calculates the sum of the third calculation result and the port sorting result rank_p to obtain the output address offset_out of the effective mapped physical hash index in the current mapped physical hash index. That is, the core mapping formula for the address offset_out is: offset_out = offset_in eff_slots + rank_p. Here, eff_slots is short for effective_slot_num, which is the number of effective input memory channels.

[0067] In an optional embodiment of the present invention, the address calculation module 250 may further be used to: calculate the product of the output address offset of the effective mapped physical hash index in the current mapped physical hash index and the hash granularity to obtain a fourth calculation result; calculate the sum of the fourth calculation result and the output base address of the current mapped physical hash index to obtain the NoC physical address of the current mapped physical hash index.

[0068] Specifically, since the physical hash index space is generally measured in units of hash granularity (HASH_UNIT), and the address offset (offset_in) calculated and output by the memory channel address mapping device is also measured in units of hash granularity (HASH_UNIT), and the address calculation module 250 needs to convert the NoC physical address of the current mapped physical hash index to a Byte address when calculating it, the address calculation module 250 can first calculate the product of the output address offset (offset_out) of the effective mapped physical hash index in the current mapped physical hash index and the hash granularity (HASH_UNIT), to obtain the fourth calculation result: offset_out. HASH_UNIT. The fourth calculation result is the address offset in bytes. Further, the address calculation module 250 calculates the sum of the fourth calculation result and the output base address BASE_ADDR of the current mapped physical hash index, and then the NoC physical address of the current mapped physical hash index can be obtained: pa_out = BASE_ADDR+(offset_out HASH_UNIT). HASH_UNIT is the Hash (hash) granularity, which is a power of 2. Therefore, offset_out HASH_UNIT can also be equivalently expressed as offset_out << LSB (shift left by LSB bits), where LSB = log2(HASH_UNIT).

[0069] Figure 9 FIG. 8 is a schematic diagram showing the effect of the memory channel address multiplexing device provided in the second embodiment of the present invention for adaptively calculating the multiplexing mapping of multiple memory channel addresses. Figure 10 FIG. 9 is another schematic diagram showing the effect of the memory channel address multiplexing device provided in the second embodiment of the present invention for adaptively calculating the multiplexing mapping of multiple memory channel addresses. In a specific example, such as Figure 9 and Figure 10 shown, taking CPW = [4, 2, 4] as an example, after a certain memory channel is masked, the multiplexing situations of the input ports of the memory channel address multiplexing device are inconsistent, and the memory channel address multiplexing device needs to be able to adaptively and automatically process. In Figure 9 , the number of effective input memory channels effective_slot_num = 4, and the memory channel address multiplexing device can implement 4-to-1 multiplexing (4to1); in Figure 10 , the number of effective input memory channels effective_slot_num = 3, and the memory channel address multiplexing device can implement 3-to-1 multiplexing (3to1). As Figure 9 shown, for the memory channel group 0 (wrap-0), this memory channel group is not masked, and the Mux of the two NoC master ports P0 and P1 is 4to1 multiplexing. As Figure 10 shown, since the memory channel CH_5 of the memory channel group 1 (wrap-1) is masked, the corresponding physical hash index 33 / 49 is masked. Therefore, for the memory channel group 1, due to the masking reason, the Mux of its NoC master ports P2 and P3 degrades to 3to1 multiplexing mode. It can be seen that the memory channel address multiplexing device provided by the embodiment of the present invention can adaptively process this type of address space multiplexing with variable number of input paths, so that there are no holes in the address space output by the multiplexer, and the downstream cache can perform prefetching.

[0070] In summary, the memory channel address multiplexing device provided in this embodiment of the invention can adaptively adjust the port multiplexing ratio and port sorting according to the memory channel masking situation. Specifically, it automatically detects the masked physical hash index information included in the current mapped physical hash index and calculates the number of valid input memory channels for the current channel output port of the current mapped physical hash index. Simultaneously, the memory channel address multiplexing device calculates the port sorting result based on the layout configuration information of the physical hash index space. Then, based on the number of valid input memory channels, the port sorting result, and the address offset of the current mapped physical hash index, it calculates the output address offset of the valid mapped physical hash index in the current mapped physical hash index, ensuring that the address offset is continuous without gaps. This guarantees that the final calculated complete output address is spatially continuous and without address gaps, making subsequent cache prefetching possible.

[0071] It should be noted that all information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant regions.

[0072] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0073] Example 3 Figure 11 This is a schematic diagram of the structure of a processor provided in Embodiment 3 of the present invention. Figure 11 As shown, the processor may include the memory channel address multiplexing device provided in any embodiment of the present invention.

[0074] Optionally, a memory channel address multiplexing device includes a memory channel input port and an address calculation multiplexer, wherein: the memory channel input port is communicatively connected to the address calculation multiplexer and is used to connect to the request queues corresponding to the mapped physical hash indices of each memory channel; the address calculation multiplexer is used to calculate the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the current mapped physical hash index corresponding to the current address request, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index; the address calculation multiplexer is also used to calculate the NoC physical address of the current mapped physical hash index based on the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index.

[0075] In an alternative embodiment of the present invention, an electronic device is also provided, which includes the processor described above.

[0076] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the embodiments of the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in the embodiments of the present invention can be achieved, and this is not limited herein.

[0077] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory channel address multiplexing device, characterized in that, Includes memory channel input ports and address calculation multiplexers, wherein: The memory channel input port is communicatively connected to the address calculation multiplexer and is used to connect the request queue corresponding to the mapped physical hash index of each memory channel; The address calculation multiplexer is used to calculate the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the current mapped physical hash index corresponding to the current address request, the layout configuration information of the physical hash index space, the associated information of the masked physical hash index, and the address offset of the current mapped physical hash index. The address calculation multiplexer is also used to calculate the on-chip network NoC physical address of the current mapped physical hash index based on the output base address and output address offset of the valid mapped physical hash index in the current mapped physical hash index.

2. The apparatus according to claim 1, characterized in that, The address calculation multiplexer includes an output port calculation module, a memory channel detection module, a control status register, an address multiplexing module, and an address calculation module, wherein: The output port calculation module is communicatively connected to the memory channel input port, the memory channel detection module, and the address calculation module. It is used to calculate the current channel output port corresponding to the current mapping physical hash index and the output base address of the valid mapping physical hash index in the current mapping physical hash index according to the layout configuration information of the current mapping physical hash index and the physical hash index space. The control status register is communicatively connected to the memory channel detection module and is used to store the shielded physical hash index association information; The memory channel detection module is also communicatively connected to the address multiplexing module, and is used to calculate memory channel shielding information based on the current channel output port corresponding to the current mapped physical hash index, the shielded physical hash index association information, and the layout configuration information of the physical hash index space; The address multiplexing module is communicatively connected to the address calculation module and is used to calculate the output address offset of the valid mapped physical hash index in the current mapped physical hash index based on the memory channel masking information and the address offset of the current mapped physical hash index. The address calculation module is used to calculate the NoC physical address of the current mapped physical hash index based on the output address offset and output base address of the valid mapped physical hash index in the current mapped physical hash index.

3. The apparatus according to claim 2, characterized in that, The memory channel detection module includes a valid input path detection module and a port sorting module, wherein: The effective input channel number detection module is communicatively connected to the address multiplexing module and the control status register, and is used to calculate the number of effective input memory channels of the current channel output port based on the masked physical hash index association information; The port sorting module is communicatively connected to the address multiplexing module and the control status register, and is used to calculate the port sorting result based on the shielded physical hash index association information and the layout configuration information of the physical hash index space; The address multiplexing module is used to calculate the output address offset of the valid mapping physical hash index in the current mapping physical hash index based on the number of valid input memory channels, the port sorting result, and the address offset of the current mapping physical hash index.

4. The apparatus according to claim 3, characterized in that, The layout configuration information of the physical hash index space includes the number of memory channels within a memory channel group, the number of memory channel groups, and the number of access ports for the channel groups. The output port calculation module is also used for: The current mapping physical hash index is moduloed with the number of memory channel groups, and the product of the modulo result and the number of access ports of the channel group is calculated to obtain the first calculation result; Calculate the quotient of the current mapping physical hash index and the number of memory channel groups, and perform modulo operation on the calculated quotient value and the number of access ports of the channel group to obtain a second calculation result; Calculate the sum of the first calculation result and the second calculation result to obtain the current channel output port corresponding to the current mapping physical hash index; The output base address corresponding to the current mapping physical hash index is determined based on the current channel output port corresponding to the current mapping physical hash index.

5. The apparatus according to claim 4, characterized in that, The effective input path detection module is also used for: The masked physical hash index and the valid tag sequence of the masked physical hash index are determined based on the masked physical hash index association information; wherein, the valid tag sequence is used to record the validity of the register of the masked physical hash index; Iterate through and calculate the channel output ports of each of the aforementioned masked physical hash indices; If it is determined that the channel output port of the currently traversed masked physical hash index is consistent with the current channel output port of the currently mapped physical hash index, update the count of the masked physical hash index. After traversing the channel output ports of each of the masked physical hash indices, the difference between the number of memory channels in the memory channel group and the count of the masked physical hash index is calculated to obtain the number of effective input memory channels.

6. The apparatus according to claim 4, characterized in that, The port sorting module is also used for: Calculate the sorting information of the current mapped physical hash index in the set of all physical hash indices mapped to the current channel output port; Calculate the number of times the masked physical hash index is skipped in the current mapped physical hash index; The difference between the sorting information of the current mapping physical hash index in the set of physical hash indices mapped to the current channel output port and the number of skips is calculated to obtain the port sorting result.

7. The apparatus according to claim 6, characterized in that, The port sorting module is also used for: The total number of main ports of the memory channel group is calculated based on the number of access ports of the channel group and the number of memory channel groups in the physical hash index space; Calculate the quotient between the current mapping physical hash index and the total number of main ports in the memory channel group to obtain the basic sorting information of the current mapping physical hash index in the set of physical hash indices mapped to the output port of the current channel.

8. The apparatus according to claim 6, characterized in that, The port sorting module is also used for: Initialize the skip count to 0; Traverse each of the masked physical hash indices, and if it is determined that the current masked physical hash index is less than or equal to the current mapped physical hash index, calculate the channel output port of the current masked physical hash index; If it is determined that the channel output port of the currently masked physical hash index and the current channel output port of the currently mapped physical hash index are consistent, the skip count is incremented by unit.

9. The apparatus according to claim 3, characterized in that, The address multiplexing module is also used for: Calculate the product of the address offset of the current mapped physical hash index and the number of valid input memory channels to obtain the third calculation result; The sum of the third calculation result and the port sorting result is calculated to obtain the output address offset of the valid mapped physical hash index in the current mapped physical hash index.

10. The apparatus according to claim 2, characterized in that, The address calculation module is also used for: The fourth calculation result is obtained by multiplying the output address offset of the effective mapped physical hash index in the current mapped physical hash index with the hash granularity; The NoC physical address of the current mapping physical hash index is obtained by summing the fourth calculation result with the output base address of the current mapping physical hash index.

11. A processor, characterized in that, The processor includes the memory channel address multiplexing device according to any one of claims 1-10.

12. An electronic device, characterized in that, The electronic device includes at least one processor as described in claim 11.

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