Request processing methods, apparatus, electronic devices, storage media and products

Abstract

This disclosure proposes a request processing method, apparatus, electronic device, storage medium, and product. It includes: if the shared depth between a new page table traversal request and a preceding page table traversal request is greater than or equal to a target depth, and the preceding page table traversal request has not obtained page table entry information, the new page table traversal request is placed in a waiting state and waiting information is determined; if the preceding page table traversal request obtains page table entry information, a broadcast message containing the page table entry information is generated; if a match is successful, the waiting state of the new page table traversal request is released, and page table traversal is performed from the next level below the target level; if the waiting time of the new page table traversal request is greater than or equal to the target time, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level. This avoids multiple requests repeatedly reading the same page directory, thereby reducing memory bandwidth waste, lowering multi-level page table processing latency, and preventing the new page table traversal request from being blocked indefinitely when the preceding page table traversal request abnormally stalls.

Description

Technical Field

[0001] This disclosure relates to the field of request processing technology, and in particular to a request processing method, apparatus, electronic device, storage medium, and product. Background Technology

[0002] In the relevant page table traversal request processing scheme, when multiple translation lookaside buffers (TLBs) miss a request, each page table traversal request performs a complete multi-level page table read operation. Even if multiple requests share the page directory, each request will still repeatedly access off-chip storage to read the same upper-level page, resulting in wasted memory bandwidth and increased page table traversal processing latency. Summary of the Invention

[0003] This disclosure provides a request processing method, apparatus, electronic device, storage medium, and product to address problems in the related art.

[0004] A first aspect of this disclosure provides a request processing method, the method comprising: Obtain the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, wherein the shared depth is the number of levels of the shared page directory; If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request has not obtained the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request is determined to be in a waiting state, and the waiting information of the new page table traversal request is determined. The target depth threshold is 1, and the waiting information includes at least the identifier of the waiting preceding page table traversal request and the target level corresponding to the shared depth. In response to the prior page table traversal request obtaining page table entry information of the target level corresponding to the shared depth and / or page table entry information of any upper level of the target level corresponding to the shared depth, a broadcast message containing the page table entry information is generated, and the broadcast message is sent to the new page table traversal request. If the broadcast message matches the waiting information of the new page table traversal request, the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. Obtain the waiting time corresponding to the new page table traversal request that is in a waiting state; In response to the waiting time being greater than or equal to the target duration threshold, the waiting state of the new page table traversal request is released, and a page table traversal is initiated from the original page table level based on the new page table traversal request.

[0005] In one embodiment, obtaining the shared depth between a new page table traversal request and preceding page table traversal requests in the page table traversal request queue includes: The virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request; The page table indexes at each level of the new page table traversal request are compared with the page table indexes at each level of the preceding page table traversal requests in the page table traversal request queue. The shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue is determined based on the number of the largest page table levels with the same page table indexes.

[0006] In one embodiment, the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request, including: Obtain the first process identifier carried by the new page table traversal request and the second process identifier carried by the previous page table traversal request; If the first process identifier and the second process identifier are the same, the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request.

[0007] In one embodiment, after obtaining the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, the method provided in this disclosure further includes: If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request obtains the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request performs page table traversal from the next level below the target level corresponding to the shared depth based on the page table entry information.

[0008] In one embodiment, the method provided in this disclosure further includes: When an exception occurs during the page table traversal process of the preceding page table traversal request, a broadcast message containing exception information is generated and the broadcast message is sent to the new page table traversal request. If the exception type of the exception information does not affect the validity of the target level corresponding to the shared depth, then the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. If the anomaly type of the anomaly information affects the validity of the target level corresponding to the shared depth, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request.

[0009] A second aspect of this disclosure provides a request processing apparatus, the apparatus comprising: The acquisition unit is used to acquire the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, wherein the shared depth is the number of levels of the shared page directory; The determining unit is configured to, if the shared depth is greater than or equal to the target depth threshold and the preceding page table traversal request has not obtained the page table entry information of the target level corresponding to the shared depth, determine the new page table traversal request as a waiting state and determine the waiting information of the new page table traversal request, wherein the target depth threshold is 1 and the waiting information includes at least the identifier of the waiting preceding page table traversal request and the target level corresponding to the shared depth; The generation unit is configured to, in response to the prior page table traversal request, obtain page table entry information of the target level corresponding to the shared depth and / or page table entry information of any upper level of the target level corresponding to the shared depth, generate a broadcast message containing the page table entry information, and send the broadcast message to the new page table traversal request. The release unit is used to release the waiting state of the new page table traversal request if the broadcast message successfully matches the waiting information of the new page table traversal request, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. The second acquisition unit is used to acquire the waiting time corresponding to the new page table traversal request that is in a waiting state; The traversal unit is used to release the waiting state of the new page table traversal request in response to the waiting time being greater than or equal to the target time threshold, and to initiate page table traversal from the original page table level based on the new page table traversal request.

[0010] A third aspect of this disclosure provides an electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this disclosure.

[0011] A fourth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this disclosure.

[0012] A fifth aspect of this disclosure provides a computer program product including a computer program that, when executed by a processor, implements the methods described in the first aspect of this disclosure.

[0013] In summary, this disclosure proposes a request processing method, which includes: obtaining the shared depth between a new page table traversal request and a preceding page table traversal request in the page table traversal request queue, wherein the shared depth is the level of the shared page directory; if the shared depth is greater than or equal to a target depth threshold, and the preceding page table traversal request has not obtained page table entry information corresponding to the target level of the shared depth, then the new page table traversal request is determined to be in a waiting state, and the waiting information of the new page table traversal request is determined, wherein the target depth threshold is 1; in response to the preceding page table traversal request obtaining page table entry information, generating a process containing the page table entry. The system broadcasts information and sends the broadcast message to the new page table traversal request. If the broadcast message matches the waiting information of the new page table traversal request, the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. The system obtains the waiting time corresponding to the new page table traversal request in the waiting state. In response to the waiting time being greater than or equal to the target time threshold, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request.

[0014] According to the solution provided in this disclosure, the sharing depth is determined by the level of the shared page directory between the new page table traversal request and the preceding page table traversal request. When the sharing depth reaches a threshold and the preceding page table traversal request has not read the corresponding level page table entry, the new request is placed in a waiting state. After the preceding page table traversal request reads the page table entry, a broadcast message is sent. Upon successful matching, the waiting request is awakened and the already obtained upper-level page table entry is reused to directly perform page table traversal from the next level below the target level. The waiting time corresponding to the new page table traversal request in the waiting state is obtained. In response to the waiting time being greater than or equal to the target time threshold, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request. This avoids multiple requests repeatedly reading the same page directory, thereby reducing memory bandwidth waste, reducing multi-level page table processing latency, and preventing the new page table traversal request from being blocked indefinitely when the preceding page table traversal request is stuck or abnormally stalled.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0017] Figure 1 A flowchart illustrating a request processing method provided in an embodiment of this disclosure; Figure 2 A schematic diagram of a request processing system provided in an embodiment of this disclosure; Figure 3 A timing diagram for request processing provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of a request processing device provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the hardware composition structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0018] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0019] To facilitate a better understanding of the technical solutions described in the embodiments of this disclosure by those skilled in the art, the technical terms in the embodiments of this disclosure are explained as follows before introducing the embodiments of this disclosure.

[0020] The Memory Management Unit (MMU) is a hardware module within the processor responsible for translating virtual addresses into physical addresses. It includes sub-components such as a Translation Lookaside Buffer (TLB), a Page Table Walk (PTW) module, a hierarchy detection unit, a Stall status control unit, and a broadcast transmission unit. It can handle concurrent memory access requests caused by TLB misses, reduce duplicate memory accesses through a page directory sharing and reuse mechanism, and achieve multi-process address space isolation by relying on Address Space Identifiers (ASIDs). It also manages the Miss Status Holding Register (MSHR) hardware entries to achieve concurrent page table traversal request scheduling and exception handling.

[0021] TLB is a high-speed cache hardware built into the MMU, used to cache the mapping relationship between the translated virtual address and the corresponding physical address. When the processor initiates a memory access, it will first check the TLB. If a valid mapping is found, the physical address will be output directly. When no match is found, a TLB miss signal is triggered, and the PTW module starts the complete page table traversal process.

[0022] PTW accesses memory level by level by level using the L4, L3, L2, and L1 indexes derived from the virtual address, and implements logic such as shared depth computing, Stall wait management, normal page table entry broadcasting, abnormal broadcast distribution, skip-level traversal, and full re-traversal of the root page table.

[0023] MSHR is a hardware register array in the MMU used to cache TLB miss requests. It can be divided into two categories: ordinary entries and stall entries. Each entry independently stores the request virtual address, four-level page table index, ASID, wait information, cached shared page table entries, and wait timer value, and can accommodate multiple concurrent page table traversal requests at the same time.

[0024] ASID, or process identifier, is used to distinguish the independent virtual address space corresponding to processes in different operating systems.

[0025] In related technologies, in heterogeneous computing architectures, such as CPU-GPU collaboration and AI-accelerated architectures, there is a problem of repeated upper-level page table lookups during the page table traversal (PTW) stage in multi-level page table scenarios. Specifically, when multiple TLB misses request access to different virtual addresses of the same process, these requests often share the same page directory (such as the L2 page directory). However, in existing PTW processing mechanisms, each request independently traverses from the original page table level, resulting in the same page directory being read repeatedly, causing wasted memory bandwidth and increased PTW processing latency.

[0026] The above solution has the following drawbacks: 1. Repeated upper-level page table lookups incur significant overhead: When multiple requests share the same page directory, each request reads that page directory independently, leading to repeated memory accesses and PTW processing delays. For example, 100 TLBmiss requests accessing different pages of the same process require each request to independently read the L2, L3, and L4 page tables, even if these page table entries are identical.

[0027] 2. Inability to utilize intermediate result dependencies between requests: The page table traversal results of a lookahead page table traversal request cannot be reused by subsequent requests, which must start traversing from the beginning.

[0028] 3. Low MSHR resource utilization: Each request occupies an MSHR entry independently. Even if multiple requests share the same page directory, it is impossible to reduce MSHR resource consumption or speed up processing by sharing intermediate results.

[0029] 4. Lack of coordination in page directory access: In the existing PTW module, each request accesses the page directory independently and out of order, lacking a unified coordination mechanism, resulting in fragmented memory access patterns and the inability to utilize DRAM line buffer locality.

[0030] 5. Prefetch requests exacerbate redundant overhead: TLB misses generated by hardware prefetching also initiate page table traversals independently, further amplifying the problem of repeated page directory reads.

[0031] To address the shortcomings of related technologies, this disclosure uses the level of the shared page directory between the new page table traversal request and the preceding page table traversal request as the sharing depth. When the sharing depth reaches a threshold and the preceding page table traversal request has not read the corresponding level page table entry, the new request is placed in a waiting state. After the preceding page table traversal request reads the page table entry, a broadcast message is sent. Upon successful matching, the waiting request is awakened and the already obtained upper-level page table entry is reused to directly perform page table traversal from the next level below the target level. The waiting time corresponding to the new page table traversal request in the waiting state is obtained. In response to the waiting time being greater than or equal to the target time threshold, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request. This avoids multiple requests repeatedly reading the same page directory, thereby reducing memory bandwidth waste, reducing multi-level page table processing latency, and preventing the new page table traversal request from being blocked indefinitely when the preceding page table traversal request is stuck or abnormally stalled.

[0032] The present disclosure will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0033] The request processing method provided in this disclosure can be applied to processor memory management address translation scenarios, such as PTW hardware page table traversal scenarios of the built-in MMU of CPU / GPU / AI accelerator. The execution body of the method can be the page table traversal PTW hardware module in the memory management unit MMU, or it can be the processor chip hardware circuit integrating PTW logic.

[0034] like Figure 1 As shown, Figure 1 This is a flowchart illustrating a request processing method provided in an embodiment of this disclosure. The request processing method provided in this embodiment includes the following steps: Step 101: Obtain the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue. The shared depth is the number of levels in the shared page directory. In one embodiment, the page table traversal request queue is used to store all page table traversal requests in the PTW module within the MMU that have not yet completed address translation. The queue contains multiple preceding page table traversal requests, which are requests that entered the queue earlier than the current new page table traversal request and are currently performing multi-level page table read translation.

[0035] In one embodiment, a new page table traversal request refers to a page table traversal request that the processor kernel queries the TLB for a valid mapping when accessing a virtual address.

[0036] In one embodiment, the page directory refers to the L4 root page directory, L3 third-level page directory, and L2 second-level page directory in a four-level page table architecture. L1 is the bottom-level leaf page directory. The L4, L3, and L2 page directories are used to store the physical base address of the next-level page table, and L1 is used to store the physical memory address of the final accessed data.

[0037] In one embodiment, the shared depth represents the number of page directory levels that the new page table traversal request and the preceding page table traversal request continuously index from the shallowest L4 root directory. The larger the shared depth value, the more page directory levels that the new page table traversal request and the preceding page table traversal request can reuse.

[0038] In one embodiment, since the address spaces of different processes are isolated from each other, before obtaining the shared depth, it is necessary to verify the process identifiers carried by the new page table traversal request and the previous page table traversal request. The shared depth will only be determined if the process identifiers of the two (the aforementioned new page table traversal request and the previous page table traversal request) are consistent. If the process identifiers of the two are inconsistent, it means that the new page table traversal request and the previous page table traversal request belong to mutually isolated address spaces, that is, there is no shareable page directory.

[0039] In one embodiment, the virtual addresses of new page table traversal requests and previous page table traversal requests can be parsed separately to obtain four index segments: L4, L3, L2, and L1. The indexes are compared layer by layer from the L4 level, and the total number of consecutively perfectly matched page directory levels is counted as the shared depth.

[0040] Step 102: If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request has not obtained the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request is determined to be in a waiting state, and the waiting information of the new page table traversal request is determined. The target depth threshold is 1. In one embodiment, a target depth threshold of 1 indicates that the two pages at least share an L4 page directory; if the shared depth is 0, it means that the L4 indexes do not match, i.e. there is no shared page directory, and the new page table traversal request directly and independently traverses all levels of page tables from the original page table level.

[0041] In one embodiment, the shared depth corresponds to the target level, which is the deepest level in the continuously matched page directory. For example, when the shared depth is 2, the target level is L3, which means that the L4 and L3 indexes are completely consistent.

[0042] In one embodiment, if the advance page table traversal request fails to obtain the target level page table entry information, it means that the PTW traversal engine has not yet read complete and valid page table entry data for that level from off-chip storage resources, and the ready flag bit for that level in the MSHR entry is invalid.

[0043] In one embodiment, the waiting state refers to the suspended processing state, such as the Stand state, set for the new page table traversal request when the PTW module manages MSHR entries.

[0044] In one embodiment, the waiting information includes at least the identifier of the waiting anticipating page table traversal request, the target level corresponding to the shared depth (i.e., which anticipating page table traversal request the new page table traversal request needs to wait for), and the page table entry information corresponding to which level of the anticipating page table traversal request is being waited for.

[0045] In one embodiment, a new page table traversal request can be set to a waiting state by setting up an independent Stall queue to store waiting requests and corresponding waiting information, i.e., a separate Stall queue; alternatively, the waiting state can be marked by using the internal status bits of the page table traversal request queue entries to store the waiting information in the entry storage space, i.e., the status field of the MSHR entry, thus setting the new page table traversal request to a waiting state.

[0046] In one embodiment, the Stall queue uses a first-in, first-out (FIFO) structure, and each entry contains: a request identifier, the MSHR entry ID to be waited for, the page table to be waited for, and the wait start time.

[0047] Step 103: In response to the previous page table traversal request, page table entry information is obtained, a broadcast message containing page table entry information is generated, and the broadcast message is sent to the new page table traversal request; In one embodiment, each time the advance page table traversal request completes the reading and verification of page table entries at any level, it is determined that page table entry information has been obtained. That is, obtaining page table entry information may include obtaining page table entry information of the target level corresponding to the shared depth, and obtaining page table entry information of any upper level of the target level corresponding to the shared depth. For example, if the target level is L3, this may include obtaining page table entry information of L4 level and page table entry information of L3 level.

[0048] In one embodiment, page table entry information may include the physical address of the page table entry (i.e., the location of the page table entry in memory), the content of the page table entry (the physical base address of the next-level page table, access permissions, valid flags, etc.), the virtual page number range corresponding to the page table entry (calculated from the page directory index), the page level of the page table entry (L4 / L3 / L2 / L1), and the process address space identifier (ASID) to which the page table entry belongs.

[0049] In one embodiment, the broadcast message is sent to all requests that are in a waiting state, and is not limited to a single new page table traversal request, but can simultaneously match multiple requests waiting for the same preceding page table traversal request.

[0050] In one embodiment, whenever the PTW module successfully retrieves page table entries at any level (L4 / L3 / L2 / L1) from memory, it encapsulates the above page table entry information into a broadcast message and sends it down to match the waiting information stored in the MSHR stall entry.

[0051] Step 104: If the broadcast message matches the waiting information of the new page table traversal request, the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. In one embodiment, the process of matching the broadcast message with the waiting information of the new page table traversal request includes: if the preceding page table traversal request identifier, page table level, and ASID in the broadcast message are all consistent with the preceding page table traversal request identifier, target level, and ASID stored in the waiting information, then the match is determined to be successful.

[0052] For example, the following matching logic is performed on all pending requests in the MSHR: the VPN prefix in the broadcast message is matched with the request VPN prefix stored in the MSHR entry using TCAM; the page level of the broadcast message is equal to the current expected level of the MSHR entry; it is determined whether the ASID of the broadcast message is consistent with the ASID of the request; if the match is successful and the request has not yet obtained the page table information for that level, the page table entry content in the broadcast message is written into the MSHR entry corresponding to the request, marking that the page table information for that level is ready.

[0053] In one embodiment, page table traversal from the next level below the target level means that the new page table traversal request directly reuses all page directory data from L4 to the target level, without repeatedly accessing storage resources to read the upper-level page table, and only traversing down to the remaining lower-level page directory, reducing the number of DRAM memory accesses and lowering address translation latency.

[0054] In one embodiment, if the broadcast message level does not match the waiting information, the broadcast message is ignored, the new page table traversal request remains in a waiting state, and the broadcast message at the corresponding target level is continuously listened for.

[0055] Step 105: Obtain the waiting time corresponding to the new page table traversal request that is in a waiting state; In one embodiment, the waiting time refers to the number of hardware cycles during which a new page table traversal request remains in a waiting state.

[0056] In one embodiment, each new page table traversal request in a waiting state is independently bound to a set of hardware wait counters. The hardware wait counters start accumulating from zero when the request enters the waiting state and are reset to zero when the request exits the waiting state.

[0057] In one embodiment, the current cumulative waiting time can be collected in real time by reading the hardware counter value bound to each new page table traversal request that is in a waiting state.

[0058] Step 106: In response to the waiting time being greater than or equal to the target duration threshold, release the waiting state of the new page table traversal request, and initiate page table traversal from the original page table level based on the new page table traversal request.

[0059] In one embodiment, the target duration threshold is a pre-configured upper limit of hardware cycles, which can be configured according to processor design requirements, such as 1000 processor cycles.

[0060] In one embodiment, the original page table level is the lookup level when entering the PTW. Taking the original page table level as the root page table level as an example, the root page table is the shallowest level L4 root page directory in the four-level page table architecture, which is the starting level of the complete page table traversal process. Initiating page table traversal from the root page table means independently re-completing the reading of all page table entries at the L4, L3, L2, and L1 levels.

[0061] In one embodiment, the waiting state of a new page table traversal request can be released by clearing the waiting state bit marked in the Stall queue or MSHR entry; alternatively, the waiting state of a new page table traversal request can be released by clearing the waiting information stored in the request.

[0062] In one embodiment, if a separate Stall queue is used to store waiting requests, the request will be removed from the Stall queue after it times out; if MSHR entries are reused to mark the waiting status, only the waiting flag in the entry is cleared, and the request is still retained in the page table traversal request queue for independent traversal.

[0063] In one embodiment, by obtaining the waiting time corresponding to the new page table traversal request that is in a waiting state; in response to the waiting time being greater than or equal to the target time threshold, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request, it is possible to avoid the new page table traversal request being blocked indefinitely when the preceding page table traversal request is stuck or abnormally stalled, which would cause the MMU translation channel resources to be exhausted and the processor memory access to be blocked.

[0064] By using the shared page directory level of the new page table traversal request and the preceding page table traversal request as the shared depth, when the target depth threshold is met and the preceding page table traversal request has not read the page table entry information of the target level, the new request is put into a waiting state. After the preceding page table traversal request reads the page table entry information, a broadcast message is sent. After a successful match, the waiting state of the new page table traversal request is released and the already obtained page table entry information is reused. There is no need to repeatedly read the shared page directory. This can solve the problems of repeated access to off-chip storage, memory bandwidth consumption, and high translation latency when TLB miss requests are processed in parallel. It also reduces the memory access overhead in the multi-level page table traversal process and improves the overall throughput of MMU address translation.

[0065] In one embodiment, obtaining the shared depth between a new page table traversal request and preceding page table traversal requests in the page table traversal request queue includes: The virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request; In one embodiment, the new page table traversal request carries the complete virtual address to be translated.

[0066] In one embodiment, the virtual address refers to the logical address used by the processor core when accessing storage resources. All program execution is based on the virtual address to complete read and write operations. The physical address is the actual addressing address of the off-chip storage medium. The MMU needs to complete the conversion from virtual address to physical address through multi-level page tables.

[0067] In one embodiment, taking the aforementioned four-level page table architecture as an example, the levels from shallow to deep are L4 root page directory, L3 page directory, L2 page directory, and L1 leaf page directory. The virtual address is segmented according to a fixed bit width, and each segment of data corresponds to a page table index of a level. It should be noted that "shallow" here refers to the page directory level that is accessed earlier in the page table addressing process and is closer to the start of the virtual address translation. It corresponds to the higher-level directory that is read earlier in the addressing order, and only requires fewer rounds of memory access to obtain the page table entry of this level. In contrast, "deep" here refers to the lower-level page table level that is accessed later in the addressing process and requires multiple jumps through upper-level directories before it can be read. The L1 leaf page directory is the deepest level, and its stored content is the final physical page address.

[0068] In one embodiment, page table indexes at each level are used to address the location of the next-level page directory in the storage resource. The indexes of the page directories (L4, L3, L2) point to the base address of the secondary page directory, and the indexes of the bottom-level L1 leaf page directory point to the physical address corresponding to the target data.

[0069] In one embodiment, the virtual address parsing circuit in the page hierarchy detection unit can be used to parse the virtual address according to the preset address bit division rules to obtain four independent index data segments: L4 index, L3 index, L2 index, and L1 index.

[0070] The page table indexes at each level of the new page table traversal request are compared with the page table indexes at each level of the preceding page table traversal requests in the page table traversal request queue. The shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue is determined based on the number of the largest page table levels with the same page table indexes.

[0071] In one embodiment, the page table index comparison follows a hierarchical order from shallow to deep, starting from the top-level L4 root page directory index and matching layer by layer. Only when the current level index is completely consistent will the comparison of the index at a deeper level continue. Once a mismatch is found in an index at a certain level, the comparison of the subsequent deeper levels is terminated.

[0072] For example, for a new page table traversal request and a previous page table traversal request, if the L4 index is the same, the L3 index is the same, the L2 index is the same, and the L1 index is different: three consecutive levels of page directories are matched, and the shared depth is 3; if the L4 index is the same, the L3 index is the same, and the L2 index is different: two consecutive levels of page directories are matched, and the shared depth is 2; if only the L4 index is the same and the L3 index is different: one consecutive level of page directories is matched, and the shared depth is 1; if the L4 index does not match: there are no consecutive matching page directories, and the shared depth is 0.

[0073] In one embodiment, index comparison can be performed by the page hierarchy comparison circuit in the page hierarchy relationship detection unit. It can simultaneously complete the index matching of new page table traversal requests and multiple previous page table traversal requests, and batch calculate the shared depth between multiple sets of requests, which can reduce the processing delay caused by serial comparison.

[0074] In one embodiment, a Page Dependency Table (PDT) can be used to quickly filter out preceding page table traversal requests with a shared depth greater than or equal to 1. Only preceding page table traversal requests that match the PDT are indexed and compared, skipping those with no possible matches, thus reducing the hardware computation overhead of index comparison. The PDT is a dedicated hardware table implemented using a TCAM or Content Addressable Memory (CATM). Each entry stores the VPN prefix of the request, the mask of the acquired tier, the waiting tier, and the dependency count. New requests quickly determine whether a dependency is hit by looking up the table (rather than traversing it).

[0075] In one embodiment, the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request, including: Obtain the first process identifier carried by the new page table traversal request and the second process identifier carried by the previous page table traversal request; In one embodiment, the process identifier is a unique identification number assigned to each operating system process to distinguish between mutually isolated process address spaces.

[0076] In one embodiment, the first process identifier is the process identifier carried inside the new page table traversal request where the TLB was not hit, corresponding to the application process that initiated this memory access operation.

[0077] In one embodiment, the second process identifier is the process identifier carried by the preceding page table traversal request and residing in the page table traversal request queue.

[0078] In one embodiment, the first process identifier of the new page table traversal request can be obtained by querying the MSHR entry, and at the same time, the second process identifier of the previous page table traversal request pre-stored in the PDT can be queried.

[0079] In one embodiment, the new page table traversal request and the previous page table traversal request can also be directly parsed to obtain the first process identifier carried by the new page table traversal request and the second process identifier carried by the previous page table traversal request.

[0080] If the first process identifier and the second process identifier are the same, the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request.

[0081] In one embodiment, the fact that the first process identifier and the second process identifier are the same indicates that the new page table traversal request and the previous page table traversal request belong to the same process, and the two share the same set of multi-level page tables, and there is a possibility of page directory reuse.

[0082] In one embodiment, if the first process identifier and the second process identifier are different, it is determined that the two belong to completely isolated address spaces. The multi-level page tables of the two processes are independent of each other and there is no reusable page directory. Therefore, the new page table traversal request needs to complete the hierarchical page table traversal independently. It can complete the L4, L3, L2, L1 level page table traversal independently, or it can complete the L3, L2, L1 level page table traversal independently, or it can complete the L2, L1 level page table traversal independently.

[0083] In one embodiment, the virtual address is stored in the MSHR entry corresponding to the new page table traversal request. After the process identifier verification is passed, the complete virtual address can be read directly from the MSHR entry, and then the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request.

[0084] This embodiment first extracts the process identifiers bound to the new page table traversal request and the previous page table traversal request and performs consistency verification. Only when the process identifiers of the two are consistent is the virtual address of the new page table traversal request read and the subsequent shared depth calculated. By using process identifiers to achieve hardware isolation of the address spaces of different processes, the page directory is erroneously reused across processes, which can ensure the correctness of the address translation logic. At the same time, it can also filter out previous page table traversal requests that have no possibility of sharing in advance, reduce invalid virtual address resolution and index comparison operations, and thus reduce the hardware computing overhead of the PTW module.

[0085] In one embodiment, after obtaining the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, the request processing method further includes: If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request obtains the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request performs page table traversal from the next level below the target level corresponding to the shared depth based on the page table entry information.

[0086] In one embodiment, a shared depth greater than or equal to a target depth threshold indicates that the new page table traversal request and the preceding page table traversal request share at least one level of page directory.

[0087] In one embodiment, if the advance page table traversal request obtains the page table entry information corresponding to the target level of the shared depth, it means that the PTW traversal engine has read and verified the valid page table entry information of that level from the off-chip storage resources, and the bit position inside the corresponding MSHR entry used to mark the level as ready is in a valid state.

[0088] In one embodiment, page table entry information is stored in the MSHR storage entry corresponding to the preceding page table traversal request, and can be directly copied to the storage area of ​​the new page table traversal request via a hardware path without having to re-access off-chip storage.

[0089] In one embodiment, it can be determined that the anticipatory page table traversal request has obtained the target level page table entry information by reading the level ready mask in the MSHR entry and finding that the bit corresponding to the target level in the mask is 1; alternatively, it can be determined that the anticipatory page table traversal request has obtained the target level page table entry information by reading the broadcast message buffer and finding that the broadcast message buffer contains the page table entry information corresponding to the anticipatory page table traversal request and the target level.

[0090] For example, with a target depth threshold of 1, the L4, L3, and L2 indexes of the new page table traversal request and the previous page table traversal request all match, and the shared depth corresponds to the target level of L2. The previous page table traversal request has read and cached the L4, L3, and L2 page table entry information. The new page table traversal request directly reuses the complete L4, L3, and L2 page table entry information, skips the memory access and read operations of the L4, L3, and L2 page tables, and directly starts the page table traversal from the next level L1 of the target level L2.

[0091] In one embodiment, if the shared depth is less than the target depth threshold, that is, the new page table traversal request and the preceding page table traversal request do not have a shared page directory, the new page table traversal request enters MSHR normally and initiates page table traversal independently, that is, it needs to search down level by level from the original page table level until the leaf level page table entry is obtained.

[0092] This embodiment directly reuses existing page table data for skip-level traversal when the new page table traversal request and the preceding page table traversal request meet the sharing conditions and the preceding page table traversal request has already cached the complete page table entries of the shared level. This eliminates the need to repeatedly read the shared page directory, reduces request waiting time and the number of off-chip storage accesses, and lowers the overall latency of MMU address translation.

[0093] In one embodiment, the request processing method further includes: When an exception occurs during the page table traversal process of the preceding page table traversal request, a broadcast message containing exception information is generated and the broadcast message is sent to the new page table traversal request. In one embodiment, exceptions may include invalid page table entries, permission errors, memory read timeouts, physical address out of bounds, bus transmission check errors, and other exceptions.

[0094] In one embodiment, the exception information may include, but is not limited to, the page table level corresponding to the location where the exception occurred, the exception type code, the identifier of the preceding page table traversal request that triggered the exception, and the identifier of the target level corresponding to the shared depth.

[0095] If the exception type of the exception information does not affect the validity of the target level corresponding to the shared depth, then the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. In one embodiment, the exception type of the exception information does not affect the validity of the target level corresponding to the shared depth, indicating that the page table entry information obtained by the advance page table traversal request can be reused.

[0096] In one embodiment, by parsing the anomaly occurrence level recorded in the anomaly information, if the anomaly occurrence level is located below the target level corresponding to the shared depth, it can be determined that the anomaly type of the anomaly information does not affect the validity of the target level corresponding to the shared depth; if the anomaly occurrence level is equal to or shallower than the target level corresponding to the shared depth, it can be determined that the anomaly type of the anomaly information affects the validity of the target level corresponding to the shared depth.

[0097] In one embodiment, the shared-level page table entry verification flags cached within the MSHR entry can also be read. If the shared target-level page table entry verification flag is valid and only the lower-level directory is abnormal, it can be determined that the type of the abnormal information does not affect the validity of the target level corresponding to the shared depth. If the shared target-level page table entry verification flag becomes invalid, it can be determined that the type of the abnormal information affects the validity of the target level corresponding to the shared depth.

[0098] In one embodiment, the exception type may include lower-level page directory exception and shared target level exception; wherein, lower-level page directory exception includes invalid L1 page table entry, access denied to lower-level directory, lower-level directory address out of bounds, etc.; shared target level exception includes corrupted L4 / L3 / L2 shared page directory entry, invalid shared level access permission, illegal shared directory physical address, etc.

[0099] If the anomaly type of the anomaly information affects the validity of the target level corresponding to the shared depth, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request.

[0100] This embodiment generates a broadcast message containing exception information when an exception occurs during the page table traversal of the preceding page table traversal request, and sends the broadcast message to the new page table traversal request. If the exception type of the exception information does not affect the validity of the target level corresponding to the shared depth, the waiting state of the new page table traversal request is released, allowing the new page table traversal request to perform page table traversal from the next level below the target level corresponding to the shared depth based on the page table entry information. If the exception type of the exception information affects the validity of the target level corresponding to the shared depth, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request. This approach balances page directory reuse performance and translation correctness, retains upper-level directory reuse for lower-level faults to reduce memory access, and forces a full-process retraversal for shared-level faults, thus avoiding memory access exceptions caused by illegal page directory reuse.

[0101] In one embodiment, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a request processing system provided in an embodiment of the present disclosure, including the processing flow after a TLB miss request inside the MMU is sent to the PTW module. Specifically, the TLB miss request generated by the MMU is first input to the page table hierarchy relationship detection unit in the PTW module. The page table hierarchy relationship detection unit performs the shared depth calculation between the new page table traversal request and the previous page table traversal requests in the MSHR (the aforementioned page table traversal request queue) and outputs it to the Stall state control unit. The Stall state control unit has two processing branches: if it determines that waiting is required, it sends the new request to the MSHR stall entry to enter the stall state; if it determines that it can be processed normally, it sends the request to the PTW traversal engine. After the PTW traversal engine accesses the storage resources to retrieve the page table entry information, it transmits the page table entry information to the broadcast sending unit. The broadcast sending unit generates a broadcast message and sends it to the broadcast matching logic / update wake-up stall entry. The broadcast matching logic / update wake-up stall entry will synchronously perform matching update operations on the MSHR stall entry, MSHR ordinary entry 1, MSHR ordinary entry 2 up to MSHR entry N. When a stall entry matches a corresponding broadcast message or triggers a timeout, it will return to the PTW traversal engine through the timeout or broadcast wake-up path to continue completing the page table traversal.

[0102] In one embodiment, when a new PTW request (including regular demand requests and hardware prefetch requests) enters the PTW module, the following process is executed: 1. Hierarchical relationship detection: Extract the virtual address of the new request and calculate its page table indexes at each level (L2 index, L3 index, L4 index, etc.). The dependency relationship is quickly determined by querying the Page Table Dependency Table (PDT), rather than traversing the MSHR. The dependency relationship is determined based on the matching of the index fields of the virtual address at the corresponding page table level. 2. Sharing relationship determination: Based on the hierarchical relationship detection results, determine the sharing depth between the new request and existing requests: Sharing L4 page directories: sharing depth is level 1 (shallowest); Sharing L4 page directories and L3 page directories: sharing depth is level 2; Sharing L4 page directories, L3 page directories, and L2 page directories: sharing depth is level 3; Sharing the same L4 page directory, L3 page directory, L2 page directory, L1 leaf page, or the same TLB cache line: sharing depth is level 4 (deepest). 3. Stall Decision: The Stall state control unit determines whether to place a new request into the Stall state based on the sharing depth and the status of existing requests: If there is an existing request with a sharing depth ≥ 1 (i.e., sharing at least the same page), and that existing request has not yet obtained the page table information for the corresponding sharing level (i.e., the request is still waiting or traversing and has not yet completed reading the page table for that level), then the new request is placed into the Stall state, waiting for the broadcast result of the existing request; if there is an existing request with a sharing depth ≥ 1, but that request has already obtained the page table information for the corresponding level (i.e., the page table entries for that level have been retrieved from memory), then the new request does not need to be Stalled and can directly reuse the page table information of the existing request; if there is no existing request with a sharing depth ≥ 1, then the new request normally enters the MSHR and independently initiates page table traversal. 4. Stall State Record: For requests entering the Stall state, the Stall state control unit records them (through a separate Stall queue or the status field of the MSHR entry) and associates them with the index of the MSHR entry it is waiting for and the identifier of the page table level it is waiting for.

[0103] In one embodiment, a broadcast message is simultaneously sent to the Stall status control unit. The Stall status control unit traverses the Stall status records (either through a separate Stall queue or the status field of an MSHR entry), checking whether the MSHR entry that each Stall request is waiting for has been updated by this broadcast (i.e., the entry has received the page table information of the page table level it is waiting for). If a match is detected, the Stall status is determined based on the unstall condition.

[0104] In one embodiment, when a Stall request receives a broadcast update for the MSHR entry it is waiting for, the Stall release circuit performs the following judgment: checking whether the request and the existing request it is waiting for still share the lowest-level common page. Specifically, it calculates whether, based on the currently acquired page table information level, it can be determined that the two requests no longer share lower-level pages. For example, if the two requests share the L2 page directory but not the L1 page table entries, then after the L2 page directory information is broadcast, they begin to diverge at the L1 level. At this time, the "lowest-level common page" is the L2 level, and the Stall can be released once the broadcast information reaches the L2 level.

[0105] In one embodiment, when a Stall request is terminated, the request is removed from the Stall status record (or the status field of the MSHR entry is updated), and the following operations are performed: If the request has already obtained all page table information from the root page table to the shared hierarchy via broadcast, then it directly uses this information to initiate a lower-level page table request (i.e., traversing from the next level after the shared hierarchy), without having to start from the root page table again. If the request has only obtained page table information for a portion of the hierarchy, then it continues to initiate page table requests downwards from the deepest level that has been obtained.

[0106] In one embodiment, when multiple broadcast messages arrive simultaneously, a priority arbitration mechanism is used, with broadcasts at deeper levels (such as L1 page entries) having higher priority because they contain more specific information; broadcasts at the same level are processed in chronological order.

[0107] In one embodiment, when the Stall state record capacity reaches its limit (whether it is a separate Stall queue or the state field of an MSHR entry), newly arriving requests, even if they meet the Stall conditions, will not enter the Stall state but will be processed directly as independent requests (Fallback), ensuring that the system will not be blocked due to the Stall state record being full.

[0108] In one embodiment, such as Figure 3 As shown, Figure 3A timing diagram for request processing provided in this embodiment includes: a timing diagram of the interaction between two page table traversal requests (Request 1 and Request 2) and the PTW module, MSHR, broadcast unit, and memory. Specifically, Request 1 initiates a PTW request, the PTW module allocates an MSHR entry for Request 1 and records its status, then the PTW module initiates an operation to read the L4 page directory from memory, memory returns the L4 page directory of Request 1, and the broadcast unit broadcasts the L4 page directory returned by Request 1; then Request 2 initiates a PTW request, the PTW module allocates an MSHR entry for Request 2 and records its status, and through hierarchy detection, it detects that Request 2 and Request 1 share the L2 page directory, controlling Request 2 to enter the stall state and store the MSHR; PTW The module continues to initiate a read operation on the L3 page directory of request 1 from memory. Memory returns the L3 page directory of request 1, and the broadcast unit broadcasts the L3 page directory returned by request 1. The PTW module then reads the L2 page directory of request 1 from memory. Memory returns the L2 page directory of request 1, and the broadcast unit broadcasts the L2 page directory returned by request 1. MSHR matches this L2 page directory to request 2, which is in a waiting state, and request 2 reuses this L2 page directory. The PTW module then initiates read operations on the L1 page table entries of request 1 and request 2 from memory respectively. Memory returns the corresponding L1 page table entries for both requests. The broadcast unit simultaneously broadcasts the L1 page table entries returned by each of the two requests. Finally, the page table entry lookup for request 1 is completed, and the page table entry lookup for request 2 is completed.

[0109] The following example illustrates the complete workflow of the request processing method in this application: Assume there are two TLB miss requests: Request 1 (virtual address VA_1) and Request B (virtual address VA_2). Both belong to the same process, share the L2 page directory (i.e., have the same L2 index), but have different L1 page table indexes.

[0110] 1. Request 1 first enters the PTW module, normally allocates MSHR entries, and initiates page table traversal: read L4 page table - read L3 page table - read L2 page table - read L1 page table.

[0111] 2. After request 2, the system enters the PTW module. The page hierarchy detection unit finds that request 2 and request 1 share the same L2 page directory (the L2 indexes are the same).

[0112] 3. The Stall state control unit checks the status of request A: Request 1 has not yet obtained the L2 page directory (it is still being traversed), so it puts request 2 into the Stall state and records that it is waiting for request 1 to broadcast the L2 page directory.

[0113] 4. After the PTW module completes the reading of the L2 page entry for request 1, the broadcast sending unit broadcasts the L2 page entry information to all MSHR entries and Stall status records.

[0114] 5. The broadcast receiving and matching unit matches the MSHR entry (itself) of request 1 and the Stall status record of request 2. The MSHR entry of request 1 is updated normally; the Stall status record of request 2 is marked as having received the L2 page entry.

[0115] 6. The Stall determination circuit detects that Request 2 has received a page table entry from the shared hierarchy (L2), and Request 2 and Request 1 no longer share the same page table after the L2 hierarchy (the L1 indexes are different), so it releases the Stall state of Request 2.

[0116] 7. After Request2 is released from the Stall status record (or the status field of the MSHR entry is updated), it can directly use the already obtained L2 page table entry to initiate a read request for the L1 page table entry without having to retrace L4, L3, and L2.

[0117] 8. After the L1 page table entry of request 2 is read, the page table is returned normally, and the address translation is further completed.

[0118] Through the above process, request 2 saves a total of 3 memory accesses (L4, L3, L2), significantly reducing PTW processing latency and memory bandwidth usage.

[0119] This disclosure provides a specific request processing method, including: In summary, the solution provided in this public disclosure is as follows: The sharing depth is determined by the level of the shared page directory between the new page table traversal request and the preceding page table traversal request. When the sharing depth reaches a threshold and the preceding page table traversal request has not read the corresponding level of page table entries, the new request is put into a waiting state. After the preceding page table traversal request reads the page table entries, a broadcast message is sent. If a match is successful, the waiting request is woken up and the already obtained upper-level page table entries are reused to directly start page table traversal from the next level below the target level. The waiting time corresponding to the new page table traversal request in the waiting state is obtained. In response to the waiting time being greater than or equal to the target time threshold, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request. This avoids multiple requests repeatedly reading the same page directory, thereby reducing memory bandwidth waste, reducing multi-level page table processing latency, and preventing the new page table traversal request from being blocked indefinitely when the preceding page table traversal request is stuck or abnormally stalled.

[0120] To implement the request processing method provided in this disclosure, this disclosure also provides a request processing apparatus, such as... Figure 4 As shown. Figure 4 This is a schematic diagram of a request processing apparatus provided in an embodiment of the present disclosure. The request processing apparatus 400 includes: The first acquisition unit 401 is used to acquire the sharing depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, wherein the sharing depth is the number of levels of the shared page directory; The determining unit 402 is configured to determine the new page table traversal request as a waiting state and determine the waiting information of the new page table traversal request if the shared depth is greater than or equal to the target depth threshold and the preceding page table traversal request has not obtained the page table entry information of the target level corresponding to the shared depth. The target depth threshold is 1, and the waiting information includes at least the identifier of the waiting preceding page table traversal request and the target level corresponding to the shared depth. The generation unit 403 is configured to, in response to the prior page table traversal request, obtain page table entry information of the target level corresponding to the shared depth and / or page table entry information of any upper level of the target level corresponding to the shared depth, generate a broadcast message containing the page table entry information, and send the broadcast message to the new page table traversal request. Release unit 404 is used to release the waiting state of the new page table traversal request if the broadcast message successfully matches the waiting information of the new page table traversal request, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. The second acquisition unit 405 is used to acquire the waiting time corresponding to the new page table traversal request that is in a waiting state; Traversal unit 406 is used to release the waiting state of the new page table traversal request in response to the waiting time being greater than or equal to the target time threshold, and to initiate page table traversal from the original page table level based on the new page table traversal request.

[0121] In one embodiment, the first acquisition unit 401 is specifically used for: The virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request; The page table indexes at each level of the new page table traversal request are compared with the page table indexes at each level of the preceding page table traversal requests in the page table traversal request queue. The shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue is determined based on the number of the largest page table levels with the same page table indexes.

[0122] In one embodiment, the first acquisition unit 401 is specifically used for: Obtain the first process identifier carried by the new page table traversal request and the second process identifier carried by the previous page table traversal request; If the first process identifier and the second process identifier are the same, the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request.

[0123] In one embodiment, the request processing apparatus 400 further includes a traversal unit, which is used to: If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request obtains the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request performs page table traversal from the next level below the target level corresponding to the shared depth based on the page table entry information.

[0124] In one embodiment, the release unit 404 is specifically used for: When an exception occurs during the page table traversal process of the preceding page table traversal request, a broadcast message containing exception information is generated and the broadcast message is sent to the new page table traversal request. If the exception type of the exception information does not affect the validity of the target level corresponding to the shared depth, then the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. If the anomaly type of the anomaly information affects the validity of the target level corresponding to the shared depth, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request.

[0125] It should be noted that the request processing apparatus provided in the above embodiments is only illustrated by the division of the above program modules. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the request processing apparatus can be divided into different program modules to complete all or part of the processing described above. In addition, the request processing apparatus provided in the above embodiments and the request processing method embodiments provided in this disclosure belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0126] Figure 5 This is a schematic diagram of the hardware composition structure of the electronic device provided in the embodiments of this disclosure, such as... Figure 5 As shown, the electronic device 500 includes at least one processor 502; and a memory 501 communicatively connected to the at least one processor 502; wherein the memory 501 stores instructions executable by the at least one processor 502, the instructions being executed by the at least one processor 502 to implement the steps of the request processing method of the present disclosure embodiments.

[0127] Optionally, the electronic device may specifically be a request processing device in the embodiments of this application, and the electronic device may implement the corresponding processes implemented by the request processing device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0128] It is understood that the electronic device also includes a communication interface 503. Various components in the electronic device are coupled together via a bus system 504. It is understood that the bus system 504 is used to implement communication between these components. In addition to a data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 The general designated all buses as Bus System 504.

[0129] It is understood that memory 501 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 501 described in this embodiment of the invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0130] The methods disclosed in the above embodiments can be applied to or implemented by processor 502. Processor 502 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the hardware of processor 502 or by instructions in software form. Processor 502 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 502 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, specifically memory 501. Processor 502 reads information from memory 501 and, in conjunction with its hardware, completes the steps of the aforementioned methods.

[0131] In an exemplary embodiment, the electronic device may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), FPGAs, general-purpose processors, controllers, MCUs, microprocessors, or other electronic components to perform the aforementioned method.

[0132] This disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, which are used to cause a computer to execute the steps of the request processing method of the embodiments of the present invention.

[0133] Optionally, the computer-readable storage medium can be applied to the request processing apparatus in the embodiments of this application, and the computer instructions cause the computer to execute the corresponding processes implemented by the request processing apparatus in the various methods of the embodiments of this application. For the sake of brevity, they will not be described in detail here.

[0134] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the request processing method provided in this embodiment of the invention.

[0135] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0136] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0137] In addition, in the various embodiments of the present invention, each functional unit can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0138] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0139] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0140] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A request processing method, characterized in that, include: Obtain the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, wherein the shared depth is the number of levels of the shared page directory; If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request has not obtained the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request is determined to be in a waiting state, and the waiting information of the new page table traversal request is determined. The target depth threshold is 1, and the waiting information includes at least the identifier of the waiting preceding page table traversal request and the target level corresponding to the shared depth. In response to the prior page table traversal request obtaining page table entry information of the target level corresponding to the shared depth and / or page table entry information of any upper level of the target level corresponding to the shared depth, a broadcast message containing the page table entry information is generated, and the broadcast message is sent to the new page table traversal request. If the broadcast message matches the waiting information of the new page table traversal request, the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. Obtain the waiting time corresponding to the new page table traversal request that is in a waiting state; In response to the waiting time being greater than or equal to the target duration threshold, the waiting state of the new page table traversal request is released, and a page table traversal is initiated from the original page table level based on the new page table traversal request.

2. The method according to claim 1, characterized in that, The step of obtaining the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue includes: The virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request; The page table indexes at each level of the new page table traversal request are compared with the page table indexes at each level of the preceding page table traversal requests in the page table traversal request queue. The shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue is determined based on the number of the largest page table levels with the same page table indexes.

3. The method according to claim 2, characterized in that, The process of parsing the virtual address of the new page table traversal request to obtain the page table indexes at each level of the new page table traversal request includes: Obtain the first process identifier carried by the new page table traversal request and the second process identifier carried by the previous page table traversal request; If the first process identifier and the second process identifier are the same, the virtual address of the new page table traversal request is parsed to obtain the page table indexes at each level of the new page table traversal request.

4. The method according to claim 1, characterized in that, After obtaining the shared depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, the method further includes: If the shared depth is greater than or equal to the target depth threshold, and the preceding page table traversal request obtains the page table entry information of the target level corresponding to the shared depth, then the new page table traversal request performs page table traversal from the next level below the target level corresponding to the shared depth based on the page table entry information.

5. The method according to claim 1, characterized in that, The method further includes: When an exception occurs during the page table traversal process of the preceding page table traversal request, a broadcast message containing exception information is generated and the broadcast message is sent to the new page table traversal request. If the exception type of the exception information does not affect the validity of the target level corresponding to the shared depth, then the waiting state of the new page table traversal request is released, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. If the anomaly type of the anomaly information affects the validity of the target level corresponding to the shared depth, the waiting state of the new page table traversal request is released, and page table traversal is initiated from the original page table level based on the new page table traversal request.

6. A request processing apparatus, characterized in that, include: The first acquisition unit is used to acquire the sharing depth between the new page table traversal request and the preceding page table traversal requests in the page table traversal request queue, wherein the sharing depth is the number of levels of the shared page directory; The determining unit is configured to determine the new page table traversal request as a waiting state and determine the waiting information of the new page table traversal request if the shared depth is greater than or equal to the target depth threshold and the preceding page table traversal request has not obtained the page table entry information of the target level corresponding to the shared depth. The target depth threshold is 1. The generation unit is configured to, in response to the prior page table traversal request obtaining page table entry information, generate a broadcast message containing the page table entry information, and send the broadcast message to the new page table traversal request; The release unit is used to release the waiting state of the new page table traversal request if the broadcast message successfully matches the waiting information of the new page table traversal request, so that the new page table traversal request can perform page table traversal from the next level below the target level corresponding to the shared depth according to the page table entry information. The second acquisition unit is used to acquire the waiting time corresponding to the new page table traversal request that is in a waiting state; The traversal unit is used to release the waiting state of the new page table traversal request in response to the waiting time being greater than or equal to the target time threshold, and to initiate page table traversal from the original page table level based on the new page table traversal request.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 5.

9. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 5.

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