A fully path physically transparent alignment architecture (PAA) and method supporting high-bit-width addressing
By adopting a Flat-High physical alignment architecture, the latency jitter and TLB knock-off issues caused by multi-level paging in high bit-width addressing environments are resolved. This achieves full-path physical consistency alignment between the processor and I/O devices, improves the performance of multi-core architectures and the flexibility of memory space, and supports zero-translation and zero-copy network throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 向海
- Filing Date
- 2026-05-13
- Publication Date
- 2026-07-31
AI Technical Summary
In high-bit-width addressing environments, the latency jitter and TLB knockdown overhead caused by multi-level paging in modern computer architectures become performance bottlenecks, especially with 64-bit and higher addressing widths, which cannot meet large-scale memory requirements and cause severe performance degradation during multi-core synchronization.
It adopts a Flat-High Physical Alignment Architecture (PAA), which eliminates or bypasses MMU page table lookups, introduces hardware-level Base-Limit verification circuits, realizes physical alignment between the processor and I/O devices, and achieves atomic-level synchronization between multiple cores through hardware broadcast protocol, eliminating the paging conversion of the I/O management unit.
It achieves full-path physical consistency alignment between processor cores and I/O devices, shortens the addressing path, eliminates TLB lookup latency, reduces multi-core synchronization overhead, ensures deterministic addressing and efficient memory space scaling, supports zero-translation zero-copy RDMA technology, and eliminates latency fluctuations caused by page table thrashing.
Smart Images
Figure CN122489455A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to computer architecture and processor design, specifically to an architecture that achieves physical consistency alignment of the entire computation and I / O path in a long mode or at least 64-bit addressing environment by eliminating, bypassing, or natively omitting paging hardware circuitry and introducing pipeline-level physical boundary checks. Background Technology
[0002] While early computers existed in non-paging modes, their small address space and weak isolation mechanisms made them unsuitable for the demands of modern large-scale memory. Modern architectures enforce multi-level paging in large memory environments, but the resulting multi-level page table traversal generates latency jitter and a "translation wall" effect, which have become core performance bottlenecks in high-bit-width computing scenarios (such as 64-bit, 128-bit, and higher). Furthermore, it can cause severe TLB shoot-down overhead during multi-core synchronization. Summary of the Invention
[0003] This invention proposes a "Flat-High" Physical Alignment Architecture (PAA):
[0004] Long-mode flat triggering: In a mode that supports at least 64-bit addressing capability, the page table (or multi-level page table) lookup logic of the MMU is bypassed by eliminating, not natively included, or completely bypassing by hardware switching.
[0005] Hardware-level physical fence: Introducing a hardware-level Base-Limit verification circuit, whose register bit width matches the processor address bit width.
[0006] Full-path I / O consistency: Synchronously cancels paging translation of the I / O Management Unit (IOMU), achieving physical alignment between the processor core and I / O devices.
[0007] Multi-core hardware consistency synchronization: Achieve atomic-level synchronization of Base-Limit parameters among multiple cores through a hardware broadcast protocol.
[0008] Instantaneous space reconfiguration: This feature enables extremely rapid scaling of physical memory space by updating hardware boundary registers using atomic instructions. Detailed Implementation
[0009] [System Initialization and Bypass Logic] Referring to FIG. 1, when the system sets the hardware switch 21, the processor core 20 enters the Flat 64 mode. In the bypass or disable design, the multi-level page table circuit 11 of the MMU unit is clock-gated, and the linear address is directly output to the bus. In the design that eliminates or does not originally include the page table mechanism, the linear address is directly output to the bus. Since the retrieval of the TLB 12 is eliminated, the physical path is shortened by about 3-5 clock cycles, achieving a deterministic instruction cycle.
[0010] [Hardware Verification Timing] Referring to FIG. 2, within the same cycle of the address output, the physical boundary checker 22 compares the values of ADDR and the Base-Limit register 41 (Base ≤ ADDR < Base + Limit) through the hardware logic circuit 40. If the verification fails, the hardware directly triggers a boundary violation exception without software intervention.
[0011] [Multi-Core Synchronization Mechanism] In the multi-core architecture, the present invention adopts the "physical domain barrier" technology based on the bus. When the boundary register of Core 0 is updated, the hardware broadcasts a synchronization signal to other cores through dedicated wires. This process does not occupy the data cache bandwidth and solves the performance degradation problem caused by multi-core TLB shootdown in the traditional architecture.
[0012] [IO Full Path Alignment] Referring to FIG. 3, the IOMMU 50 is reconstructed as a "bus monitor", and the checker 51 uses the same Base-Limit parameters as the CPU side. This enables technologies such as RDMA to achieve true "zero translation, zero copy" network throughput in the PAA architecture.
[0013] I. System Global Topology and Flat Mode Initialization
[0014] Referring to Figure 1 , in the bypass or disable design, in the physical implementation of the PAA architecture provided by the present invention, it is first required that the processor core 20 has an "asymmetric" startup path. After the system is powered on and reset, the processor defaults to the traditional compatible paging mode.
[0015] When the system monitor or host kernel identifies a high-value task (such as an AI Agent execution request), it sends a set signal to hardware switch 21 by executing a defined privileged configuration instruction (such as MOV TO PAA_CTRL_REG). At this time, the processor's internal instruction pipeline undergoes an "address rerouting": the traditional page table traversal unit is clock-gated to save power. The linear address signal skips all multi-level address mapping logic and is directly output to the internal bus.
[0016] Those skilled in the art should understand that this "bypass" is not only a logical omission, but also a direct conduction in the physical circuit.
[0017] In the design that eliminates or natively does not include a page table mechanism, the PAA architecture provided by this invention, in its physical implementation, directly outputs the linear address to the bus.
[0018] By eliminating TLB 12 lookup comparisons and L1 / L2 page table cache retrievals, the physical path from instruction decoding to address output is shortened by approximately 3-5 clock cycles. In financial backtesting scenarios handling massive amounts of small data packets, this cumulative performance gain is generational.
[0019] II. Pipeline Integration and Timing Guarantee of Hardware Boundary Checker
[0020] Reference Figure 1 and Figure 2 The physical boundary checker 22 designed in this invention is integrated within the processor's addressing pipeline or memory access path. In a preferred embodiment, the physical boundary checker 22 is deeply embedded in the processor's Memory Unit (LSU) as a hardware enclosure; however, those skilled in the art should understand that the physical location of the physical boundary checker 22 is not limited to the LSU, and it can also be integrated on any hardware physical node capable of intercepting and verifying the processor's output address signals, such as the instruction decoding unit, the periphery of the execution unit, the front end of the on-chip cache controller (CacheController), the on-chip network (NoC) routing node, or the bus interface unit (BIU).
[0021] To support complex cloud computing environments, the Base-Limit register set 41 is designed as a group of high-speed on-chip memory units integrated within the pipeline (e.g., implemented by a high-speed static random access array (SRAM), a register latch array, or a non-volatile on-chip memory medium). In an advanced embodiment, the register set 41 includes multiple pairs (e.g., 16 or 32 pairs) of base address and limit parameters to support the "logical aggregation" of non-contiguous physical memory regions.
[0022] Upon receiving the ADDR signal, hardware logic circuit 40 triggers all enabled register pairs in parallel. Its comparison logic employs a high-speed arithmetic comparator.
[0023] 1. Lower bound check: Comparator_GTE(ADDR, Base)
[0024] 2. Upper limit check: Comparator_LT(ADDR, Base + Limit)
[0025] The above two steps must be completed during the "addressing phase" before the processor accesses the L1 cache. If the address is within any valid [Base, Limit] window, the logic gate is opened; if all windows are missed, the hardware must force the "Valid" signal low before sending the data to prevent illegal data from polluting the bus. This "pre-validation" mode is the core of the architecture's security.
[0026] III. Atomic Implementation of Dynamic Memory Scaling and Hot-Swapping (Solving Memory Fragmentation and Elastic Allocation Scenarios)
[0027] In real-world operation, the workload of an AI Agent may experience sudden increases. Under the architecture of this invention, hot-swapping of memory no longer involves expensive software operations.
[0028] The steps of the implementation example are as follows:
[0029] 1. The OS finds an adjacent free physical block Delta in physical memory 30.
[0030] 2. The host program executes an atomic exchange instruction, directly modifying the value in the Limit register (Limit = Limit + Delta).
[0031] 3. Since processor 20 has eliminated, bypassed, or natively omitted page table translation logic, this boundary change skips the traditional physical address remapping process at runtime. It eliminates the overhead of traditional multi-core address cache refresh and achieves seamless hardware-level expansion in a single cycle without the need for memory barrier instructions. The agent can then seamlessly access the expanded space in the next clock cycle. This "nanosecond-level elasticity" is something that the traditional Linux kernel cannot achieve by modifying the VMA (virtual memory region) mapping.
[0032] IV. Coordination Protocol for Full-Path I / O Consistency
[0033] Referring to Figure 3, the elimination, bypassing, or native absence of page table translation features in IOMMU 50 is key to achieving full path transparency.
[0034] The system control plane (Root) refers to the management entity (such as a security monitor or hypervisor) running at the highest privilege level of the processor. It loads predefined physical memory boundary values (Base / Limit) into the hardware registers of each processor core by executing specific atomic instructions. The control plane is physically isolated from the executed tasks (such as AIAgents), ensuring that tasks cannot modify their own physical boundaries without authorization.
[0035] The system control plane (Root) assumes the functions of the hardware abstraction management layer. Unlike traditional software hypervisors that rely on software page tables for address remapping, the Root plane of this invention establishes physical boundaries solely by manipulating hardware registers. Once the physical boundaries are established, task addressing behavior is decoupled from the intervention of the software management plane, and security verification is autonomously performed by the hardware verification circuitry. This design achieves complete decoupling between management logic and execution paths.
[0036] In the PAA architecture, IOMMU 50 no longer functions as a traditional address translation entity, but rather as a dedicated bus security monitoring unit. When an external device, such as a network interface card, storage controller, graphics processing unit (GPU), neural network accelerator (NPU), or programmable logic array (FPGA), initiates a DMA request, its physical address A is directly sent to the verifier 51.
[0037] To prevent unauthorized peripherals from simulating legitimate address spaces, this invention introduces a hardware-level end-to-end domain ID. In an environment without page table mapping along the entire path, verifier 51 directly performs atomic-level bus permission interception or permission based on the domain ID carried in the external device request and the corresponding hardware Base-Limit parameter, enabling peripheral data to be delivered directly, without translation, and with zero copying to the specified boundaries of physical memory 30.
[0038] This design enables RDMA (Remote Direct Memory Access) technology to achieve true "zero overhead" under the PAA architecture. Data packets travel from the fiber optic cable to the network card, pass through IOMMU 51 checksum, and are finally stored in memory 30, all without any software intervention or kernel involvement.
[0039] V. Specific advantages of PAA architecture for financial and industrial control scenarios
[0040] In high-frequency trading (HFT) implementations, the PAA architecture operates in an environment without page table mapping throughout the entire path, fundamentally eliminating latency fluctuations caused by page table thrashing and address translation in traditional paging architectures. Since the addressing cycle is entirely fixed and deterministic by the hardware routing logic, algorithm engineers can accurately predict the physical execution time of each line of code at the bus level. This is crucial for eliminating tail latency in high-frequency trading systems and ensuring absolute latency determinism.
[0041] In power and industrial control implementations, memory regions locked by hardware base-limits can physically prevent agents from attempting to access unauthorized I / O ports. Even if the agent software is compromised, attackers cannot perform address out-of-bounds or unauthorized addressing in an environment without page table mapping throughout the entire path. This is because the boundary parameter configuration of hardware register set 41 is either forcibly fixed by hardware circuitry or can only be modified unidirectionally by the underlying monitor with the highest privilege level, thus completely blocking malicious attack flows at the physical bus level.
[0042] VI. Maintaining Global Consistency at Physical Boundaries in Multi-Core Architectures
[0043] Reference Figure 3 In one high-performance multi-core embodiment of the present invention, the processor system includes multiple independent execution cores (Core 0, Core 1... Core N). When a task (such as an AI Agent) is scheduled across cores or runs in parallel on multiple cores, it must be ensured that the Base-Limit register set 41 of all relevant cores remains absolutely synchronized.
[0044] 1. Hardware Broadcast Protocol This invention introduces an atomic-level synchronization mechanism based on the underlying system bus or on-chip network (NoC). When the management plane updates the Base-Limit register of a core, the hardware automatically triggers a "Boundary Update Broadcast." This signal is delivered to all cores involved in the computation within 1-2 clock cycles via a dedicated hardware connection (rather than a software interrupt).
[0045] 2. Physical Domain Barrier
[0046] To prevent "address tearing" (i.e., core A has updated its boundary while core B is still addressing at the old boundary) during boundary updates, this invention designs a physical domain barrier instruction. During register value updates, the address checkers 22 of all relevant cores temporarily enter a very short "locked state" until the hardware acknowledgment (ACK) signal returns, ensuring that the entire system completes the addressing logic switching at the same physical time point.
[0047] 3. Deep decoupling from cache coherency protocols
[0048] Unlike traditional virtual addressing architectures that require frequent TLB refreshes or rely on complex MESI protocols to maintain page table consistency, the PAA architecture of this invention completely decouples hardware synchronization at addressing boundaries from data cache consistency protocols. Because it operates in an environment without page table mapping along the entire path, the system does not involve any reading or writing of page table entries in memory. Therefore, boundary synchronization between multiple cores does not consume data cache bandwidth and does not produce any cascading effects of cache misses or cache line invalidations. This out-of-band hardware synchronization mechanism allows this architecture to maintain consistently low synchronization latency and hardware-level latency determinism even when scaling to ultra-large-scale multi-core processors or distributed computing clusters.
[0049] The accompanying diagram description paragraph:
[0050] Figure 1 shows a comparison of the PAA architecture according to an embodiment of the present invention with that of a traditional paging architecture in terms of address translation path.
[0051] Figure 2 illustrates the logic decision process of a hardware boundary checker according to an embodiment of the present invention.
[0052] Figure 3 illustrates a multi-core system-level full path alignment and hardware synchronization architecture according to an embodiment of the present invention.
[0053] [Supplementary Terms and Conditions in the Instruction Manual]
[0054] The I / O Management Unit (IOMMU) described in this invention is a functional hardware abstraction and belongs to the functional hardware definition. Those skilled in the art should understand that the I / O Management Unit has different names and industry standards in specific hardware ecosystems or microarchitecture implementations, and different technical names in different chip architectures or instruction set ecosystems. For example, in the ARM architecture, it is equivalent to the System Memory Management Unit (SMMU); in other heterogeneous architectures, it can also be called the Device Memory Management Unit (DMU) or DMA boundary isolator; in certain specific System-on-Chip (SoC), it can also be called the Peripheral Memory Management Unit (PMU) or DMA physical isolator. Any component that performs the above-mentioned non-paged Base-Limit boundary check on the external device DMA path through hardwired logic is considered the I / O Management Unit described in this invention and falls within the protection scope of this invention.
[0055] [Supplementary Clauses for Detailed Implementation – Regarding Alternative Manifestations of Addressing Structures]
[0056] Those skilled in the art will understand that the 'bypass multi-level page table conversion circuit' or 'disable paging mechanism' described in this invention includes two equivalent hardware architecture implementations:
[0057] 1. The first type is an asymmetric compatible architecture, in which the processor retains the traditional MMU and paging circuitry, but uses the hardware mode switch of this invention to physically reroute the signals or turn off the clock, making it inactive.
[0058] 2. The second type is Pure Native Physical Architecture, which means that the processor completely removes or does not contain traditional MMU page table (or multi-level page table) translation circuits, page table traversal units (Table Walker) and TLB cache in the microarchitecture design stage.
[0059] Regardless of whether the hardware circuit chooses to selectively bypass during operation or completely excludes the page table architecture during manufacturing, as long as it directly outputs physically aligned addresses and relies on hardware-level physical boundary security verification logic for spatial isolation in at least 64-bit high-width mode, it falls within the core protection scope of this invention.
[0060] 3. Similarly, the 'IOMMU internally disabled or bypassed IO page table translation logic' described in this invention also covers the pure native IOMMU architecture that completely does not contain or completely removes IO page table mapping circuitry during the hardware manufacturing or routing stage.
[0061] [Supplementary Clauses for Detailed Implementation – Regarding Alternative Manifestations of Storage Media]
[0062] Those skilled in the art will understand that the 'Base-Limit register group,' 'high-speed static random access memory array,' or 'on-chip memory cell' described in this invention are functional hardware descriptions. The physical implementation of the register group claimed in this invention is not limited to traditional static random access memory (SRAM) circuits.
[0063] With the evolution of semiconductor processes and new memory technologies, any on-chip high-bandwidth, low-latency storage medium used to store physical boundary parameters and capable of intra-cycle parallel retrieval by hardware address comparison circuits falls within the protection scope of this invention. This includes, but is not limited to: register files, latch arrays, magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), phase-change memory (PCM), or high-bandwidth distributed hardware register logic directly integrated on a 3D IC or chiplet interconnect bus. Its core technical feature lies in its memory access latency matching the processor's address verification clock cycle overhead.
Claims
1. A physical alignment computing system supporting high-bit-width addressing, characterized in that... Include: A processor core that supports long mode or has at least 64-bit addressing capability, the processor including a configuration structure or specific physical wiring for exempting, bypassing or natively not including a page table translation mechanism in the mode, so that the address signal is directly output as a physical address without going through page table lookup logic; Hardware physical boundary verification module, which is integrated into the processor addressing pipeline or memory access path; Verification mechanism: The module includes at least one pair of on-chip memory cells for storing the corresponding bit-width physical address as a Base register and a Limit register, which are used to perform physical boundary value comparison and verification of the address signal through hardware logic before the address signal reaches the bus or data buffer; Its characteristic is that the addressing and verification process does not generate any memory access overhead, and realizes the identity mapping between the computational address space and the physical memory space, that is, realizes physical identity addressing.
2. The system according to claim 1, characterized in that: The page table translation mechanism that the processor core exempts from, bypasses, or does not natively include is specifically a multi-level page table translation mechanism that includes a multi-level hierarchical topology.
3. The system according to claim 1, characterized in that... It also includes a Coordinating I / O Management Unit (IOMMU) module: The IOMMU internally excludes, bypasses, or natively does not contain I / O page table translation logic, and the verification logic inside the IOMMU shares the Base-Limit register group parameters on the processor core side, so as to realize direct boundary verification of external device DMA access in an environment without page table mapping throughout the entire path; Achieve full-path consistency alignment between processor core addressing and external device DMA access at the physical layer.
4. The system according to claim 1, characterized in that: The hardware physical boundary verification module supports updating register values through atomic privileged instructions, enabling dynamic scaling or hot-swapping of physical memory space through a single register write operation while skipping address translation logic and address remapping.
5. The system according to claim 1, characterized in that: The system comprises multiple processor cores, and each core synchronizes physical boundary parameters through a dedicated hardware broadcast protocol, achieving out-of-band hardware synchronization of multi-core addressing boundaries under conditions of no page table mapping along the entire path and free from interference from data cache consistency protocols.
6. A task execution method based on the architecture of claim 1, characterized in that: Load a single address space library operating system image (such as Unikernel) or a single privilege level binary image into a contiguous block of physical memory defined by the Base-Limit register; In non-paging mode, the processor directly executes the instructions and I / O requests in the image using physical pointers.