Equal-length differential trace constraints between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device.

Abstract

This invention discloses a differential routing constraint method for equal-length differential traces between the uplink port and the CPU Root Port, and between the downlink port and the CXL device of a CXL switch. The method includes: acquiring the differential link connection relationship and initial electrical parameters between the uplink port and the CPU Root Port, and between the downlink port and the CXL device; calculating routing constraints that meet signal integrity indicators, and performing PCB layout and routing accordingly; configuring differentiated internal equal-length constraints based on port roles, with the uplink port standard being stricter than the downlink port standard; setting differentiated delay compensation strategies based on the CXL protocol transaction types to be carried, with CXL.cache transactions having higher priority than CXL.mem and CXL.io transactions; using a programmable delay adjustment unit (PDAU) to adjust the differential link propagation delay according to the compensation strategy; acquiring environmental awareness data, calculating predicted delay drift values, and controlling PDAU compensation to maintain the equivalent total propagation delay. This application achieves differentiated fine-grained constraints, multi-transaction adaptive compensation, and dynamic environmental compensation, improving link signal integrity and robustness.

Description

Technical Field

[0001] This invention relates to equal-length differential trace constraints between the uplink port and CPU Root Port of a CXL Switch, and between the downlink port and CXL devices, and particularly to the field of high-speed digital circuit design and PCB interconnection technology. Background Technology

[0002] CXL (Compute Express Link), a high-speed cache coherent interconnect protocol built on the PCIe physical layer, boasts a SerDes rate of 64 GT / s (PAM4 modulation) and a baseband frequency of 32 GHz in CXL 3.0. In a typical motherboard deployment of a CXL Switch ASIC, two key high-speed differential interconnect links exist: uplink (CXLSwitch uplink port → CPU Root Port) and downlink (CXL Switch downlink port → CXL devices, such as CXL memory expansion cards, GPUs, accelerators, etc.). The signal integrity of these two types of links directly determines the overall performance of the CXL Fabric.

[0003] In high-speed differential signal transmission, length equalization control of the differential pair (P / N lines) is a core requirement for ensuring signal quality. The fundamental goal of length equalization control is to ensure that the time difference between the signal arrival at the receiver is below the allowable skew threshold. For current high-speed CXL signals, the requirements for internal length equalization error are already extremely stringent.

[0004] Existing technologies have the following significant drawbacks regarding the equal-length differential trace constraints between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device:

[0005] The equal-length constraint for uplink and downlink ports uses a uniform, one-size-fits-all standard, failing to consider the fundamental differences in topology, load characteristics, and signal integrity margins between the two types of links. Uplink ports typically have shorter traces and lighter loads, while downlink ports have longer traces and heavier loads. This uniform standard results in the underutilization of more stringent controls achievable with uplink ports, while downlink ports may be difficult to implement due to overly stringent constraints under long-trace conditions.

[0006] Equal length constraints only focus on physical length matching, ignoring the relative delay matching between different links. In a multi-port CXLSwitch, differences in trace length between different downlink ports, and between uplink and downlink ports, may cause deviations in the response timing of cache-consistent transactions.

[0007] The equal-length routing strategy does not consider the impact of differentiated latency requirements for CXL multi-protocol transactions (CXL.io / CXL.mem / CXL.cache). CXL.cache consistency transactions are most sensitive to latency. The existing strategy uses "shortest path + serpentine routing" to achieve physical length matching, without considering the impact of the additional latency introduced by routing on transactions of different protocols.

[0008] There is a lack of compensation mechanisms for delay drift caused by temperature changes and voltage fluctuations. The dielectric constant of the PCB dielectric changes with temperature, and the temperature difference of the dielectric along different trace paths causes deviations in the originally matched delay under different temperature conditions. Existing equal-length constraints are static and cannot compensate for delay drift caused by such environmental changes. Summary of the Invention

[0009] This invention provides a differential routing constraint with equal length between the uplink port and the CPU Root Port of a CXL Switch, and between the downlink port and the CXL device, to overcome the shortcomings of existing technologies that apply equal length constraints to uplink and downlink ports in a one-size-fits-all manner, lack relative delay matching, fail to consider the differential delay requirements of multi-protocol transactions, and cannot compensate for delay drift caused by environmental changes.

[0010] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0011] This invention discloses a differential routing constraint for equal-length differential traces between the uplink port and the CPU Root Port, and between the downlink port and a CXL device of a CXL switch. The constraint includes obtaining the differential link connection relationship and initial electrical parameters between the uplink port and the CPU Root Port, and between the downlink port and at least one CXL device of the CXL switch; calculating differential routing constraints that satisfy preset signal integrity indicators based on the differential link connection relationship and initial electrical parameters; performing routing layout and winding operations of the differential links on a printed circuit board (PCB) according to the differential routing constraints to complete physical interconnection; configuring differentiated internal equal-length constraints for the uplink port and downlink port respectively according to their port roles, wherein the constraint standard for the uplink port is stricter than that for the downlink port; setting differentiated delay compensation strategies for the differential links according to the CXL protocol transaction types to be carried by the differential links, wherein the delay compensation priority for CXL.cache transactions is higher than that for CXL.mem and CXL.io transactions; and utilizing the CXL... The programmable delay adjustment unit (PDAU) in the switch adjusts the propagation delay of the differential link according to the differentiated delay compensation strategy; it acquires the environmental awareness data when the CXLSwitch is working, calculates the predicted delay drift value of the differential link based on the environmental awareness data, and controls the PDAU to perform compensation in order to maintain the equivalent total propagation delay of the differential link.

[0012] Furthermore, configuring differentiated internal equal-length constraints for the uplink and downlink ports respectively includes: configuring a first threshold for the internal equal-length constraint for the uplink port and a second threshold for the internal equal-length constraint for the downlink port, wherein the first threshold is less than the second threshold.

[0013] Furthermore, the differentiated latency compensation strategy includes: for differential links intended to carry CXL.cache transactions, configuring a zero-additional-latency path compensation strategy to prohibit serpentine routing in PCB traces to achieve internal equal-length matching; for differential links intended to carry CXL.mem transactions, configuring a restricted serpentine routing compensation strategy to allow serpentine routing of limited length in PCB traces.

[0014] Furthermore, the PDAU is implemented using a digitally controlled delay line (DCDL), and its adjustment step and adjustment range are configurable.

[0015] In one implementation, the adjustment step of the PDAU is 0.5ps, and the adjustment range is ±50ps.

[0016] Furthermore, the environmental sensing data includes temperature and voltage; the calculation of the predicted delay drift value based on the environmental sensing data includes: calculating the temperature drift delay based on the temperature and the dielectric constant temperature coefficient, and calculating the voltage drift delay based on the voltage and the voltage-delay sensitivity coefficient.

[0017] Furthermore, the step of calculating the predicted delay drift value based on environmental perception data and controlling the PDAU for compensation includes: performing an exponentially weighted moving average filter on the acquired raw environmental perception measurement value sequence to obtain a smooth value sequence; calculating the discrete first-order difference of the smooth value sequence to obtain a rate of change sequence; dynamically determining a trigger threshold based on the statistical characteristics of the rate of change sequence within a preset time window; and only performing the calculation of the predicted delay drift value and controlling the PDAU to adjust when the absolute value of the current value of the rate of change sequence exceeds the trigger threshold.

[0018] Furthermore, the formula for the exponentially weighted moving average filter is as follows: ,in, The original measurement value at the current moment. The filtered value from the previous time step. The smoothing factor; the trigger threshold is determined by the formula Calculate, where, and These are the mean and standard deviation of the absolute values ​​of the rate of change within the preset time window, respectively. These are preset coefficients.

[0019] Furthermore, the PDAU compensation control also includes: setting a first threshold T_up for increasing the delay adjustment and setting a second threshold T_down for decreasing the delay adjustment, where T_up > T_down; calculating a comprehensive decision variable based on the current predicted delay drift value and the residual error after the last adjustment; and determining the current adjustment direction instruction for the PDAU according to the relationship between the comprehensive decision variable and the first threshold T_up and the second threshold T_down, as well as the state of the previous adjustment cycle, wherein the state includes increasing the delay, decreasing the delay, or maintaining the current delay.

[0020] As one implementation method, the rule for determining the adjustment direction command is as follows: if the previous state was "hold", then when the comprehensive decision variable is greater than T_up, the current command is to increase the delay; when the comprehensive decision variable is less than -T_down, the current command is to decrease the delay; otherwise, hold. If the previous state was "increase the delay", then only when the comprehensive decision variable is less than T_down, the current command changes to "hold"; otherwise, maintain the increase in delay. If the previous state was "decrease the delay", then only when the comprehensive decision variable is greater than -T_up, the current command changes to "hold"; otherwise, maintain the decrease in delay.

[0021] Furthermore, when multiple differential link channels simultaneously trigger PDAU adjustment requests, the control of PDAU for compensation also includes: obtaining the priority identifier of each channel and the absolute value of its requested delay adjustment amount; calculating the corresponding arbitration weighting value based on the priority of each channel and the absolute value of the delay adjustment amount; and scheduling the PDAU of each channel to perform adjustments sequentially within a set time budget according to the magnitude of the arbitration weighting value.

[0022] Furthermore, the arbitration weighted value Through formula Calculate, where, The priority of channel i, The absolute value of the delay adjustment requested. The largest among all channels to be adjusted , The priority is a preset weighting coefficient; The priority is determined based on the type of CXL protocol transaction to be carried by the differential link, where the channel carrying CXL.cache transactions has the highest priority.

[0023] Furthermore, the CXL protocol transaction types include CXL.cache transactions, CXL.mem transactions, and CXL.io transactions.

[0024] Furthermore, the equal-length differential routing constraints between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device, also include: configuring inter-group relative delay constraints for multiple differential links within a preset equal-length group, wherein the inter-group relative delay constraints are used to limit the maximum deviation between the propagation delays of each differential link within the equal-length group.

[0025] This application provides a constraint device for equal-length differential traces in a CXL switch, comprising: a parameter acquisition module configured to acquire differential link connection relationships and initial electrical parameters between the uplink port and the CPU Root Port of the CXL switch, and between the downlink port and at least one CXL device; a routing planning module configured to calculate differential trace routing constraints that satisfy preset signal integrity indicators based on the differential link connection relationships and initial electrical parameters, and generate PCB layout routing instructions based on the constraints; a constraint configuration module configured to configure differentiated internal equal-length constraints for the uplink port and downlink port according to port roles, and set differentiated delay compensation strategies for the differential links according to CXL protocol transaction types; a programmable delay adjustment unit (PDAU) disposed in the CXL switch, configured to adjust the propagation delay of the differential links according to the differentiated delay compensation strategies; an environment perception module configured to acquire environment perception data when the CXL switch is operating; and a compensation control module configured to calculate predicted delay drift values ​​based on the environment perception data, and control the PDAU to perform compensation to maintain the equivalent total propagation delay of the differential links.

[0026] This application provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the program, it implements a method for equal-length differential routing constraints between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device.

[0027] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a method for equal-length differential routing constraints between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device.

[0028] The beneficial effects achieved by this invention are as follows: By acquiring the link information of the uplink and downlink ports of the CXL Switch, differentiated internal equal-length constraints are configured for the uplink and downlink ports based on their roles. For example, a stricter standard is adopted for the uplink port, while a relatively lenient standard is adopted for the downlink port. This enables fine-grained management of the different link characteristics and signal integrity requirements of the uplink and downlink ports, solving the problem that a unified standard cannot simultaneously meet the high-performance requirements of the uplink port and the manufacturability of the downlink port. Furthermore, by setting differentiated delay compensation strategies according to the CXL protocol transaction types to be carried by the differential link, such as configuring a zero-additional-delay path for the CXL.cache transaction, which is most sensitive to delay, unnecessary additional delays introduced by traditional serpentine routing are avoided, satisfying the differentiated delay requirements of different protocol transactions. Furthermore, by acquiring environmental awareness data to calculate and predict delay drift values, and using the programmable delay adjustment unit (PDAU) in the CXL Switch for dynamic compensation, delay drift caused by environmental changes such as temperature and voltage can be compensated in real time, maintaining a constant equivalent total propagation delay of the differential link. Therefore, this application achieves a comprehensive upgrade from static unified constraints to differentiated fine constraints, from single physical matching to multi-transaction adaptive compensation, and from fixed design to dynamic environmental compensation, thereby comprehensively improving the signal integrity and robustness of the CXL Switch link. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0030] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0031] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0032] Example 1

[0033] Terminology Explanation:

[0034] "Uplink port" refers to the physical port on the CXL Switch used to connect to the CPU Root Port, and its differential pairs constitute the uplink.

[0035] "Downlink port" refers to the physical port on the CXL Switch used to connect at least one CXL device, and its differential pairs constitute the downlink.

[0036] "Internal equal length constraint" refers to the restriction imposed on the physical length difference between the P-line and N-line within the same differential pair, with the goal of controlling the time difference of the signal arrival at the receiving end.

[0037] "CXL protocol transaction type" refers to the type of data operation transmitted in CXL Fabric, which mainly includes CXL.cache consistency transactions that are extremely sensitive to latency, CXL.mem memory access transactions that are relatively sensitive to latency, and CXL.io configuration and I / O transactions that have a higher tolerance for latency.

[0038] The "Programmable Delay Adjustment Unit (PDAU)" is a circuit unit integrated into the CXL Switch ASIC SerDes channel that can finely adjust the propagation delay of a signal in a digitally controllable manner.

[0039] "Predicted delay drift value" refers to the expected change in signal propagation delay due to environmental changes, calculated based on environmental sensing data (such as temperature and voltage).

[0040] "Environmental sensing data" refers to measurement data that reflects the physical state of the CXL Switch's working environment, mainly including temperature data and voltage data.

[0041] "Digital Controlled Delay Line (DCDL)" refers to a circuit structure that uses digital control signals to precisely select or synthesize delay paths of different lengths.

[0042] like Figure 1 As shown, a constraint for equal-length differential traces between the uplink port and the CPU Root Port of a CXL Switch, and between the downlink port and the CXL device, includes:

[0043] S101: Obtain the differential link connection relationship and initial electrical parameters between the uplink port and the CPU Root Port of the CXL Switch, and between the downlink port and at least one CXL device;

[0044] S102: Based on the differential link connection relationship and initial electrical parameters, calculate the differential routing constraints that meet the preset signal integrity index;

[0045] S103: Based on the differential routing constraints, perform the routing layout and routing operation of the differential link on the printed circuit board (PCB) to complete the physical interconnection.

[0046] S104: Based on the port roles of the uplink and downlink ports, configure differentiated internal equal-length constraints for the uplink and downlink ports respectively, wherein the constraint standard for the uplink port is stricter than that for the downlink port;

[0047] S105: Based on the CXL protocol transaction type to be carried by the differential link, set a differentiated delay compensation strategy for the differential link, wherein the delay compensation priority of CXL.cache transactions is higher than that of CXL.mem and CXL.io transactions;

[0048] S106: Using the programmable delay adjustment unit (PDAU) set in the CXL Switch, the propagation delay of the differential link is adjusted according to the differentiated delay compensation strategy;

[0049] S107: Obtain environmental awareness data when the CXL Switch is working, calculate the predicted delay drift value of the differential link based on the environmental awareness data, and control the PDAU to compensate for it in order to maintain the equivalent total propagation delay of the differential link.

[0050] In this embodiment, the above steps work together to form a complete "role awareness-dynamic constraint-adaptive compensation" system. First (S101-S103), by acquiring and analyzing the link topology and electrical parameters, a design foundation is laid for subsequent fine-grained constraints. The core lies in steps S104 to S107: S104, based on the differences in port roles (uplink links are short, have light loads, and are sensitive to cache consistency latency, while downlink links are relatively long and have variable loads), configures stricter equal-length constraints (i.e., smaller allowable length differences) for uplink ports and relatively looser constraints for downlink ports. This optimizes the system at the source according to the physical characteristics and performance requirements of different links, solving the problem of unfulfilled uplink potential or overly difficult downlink design caused by "one-size-fits-all" constraints. S105 further delves into the business layer, identifying the differentiated sensitivities of different CXL protocol transactions to latency, configuring compensation strategies aimed at minimizing latency for high-priority CXL.cache transactions, and configuring strategies that allow for moderate increases in latency for other transactions, thus meeting the performance requirements of the protocol layer. S106 utilizes the chip's internal PDAU as the execution unit, translating the differentiated strategy set in S105 into actual delay adjustments. This upgrades the process from PCB physical routing compensation to in-chip programmable compensation, reducing the impact of external routing on signal quality. Finally, S107 introduces an environmental awareness and dynamic compensation closed loop. By monitoring environmental parameters in real time to predict delay drift, it drives the PDAU for reverse compensation, ensuring that the sum of the physical delay of the PCB traces and the adjustable delay of the PDAU remains constant. This effectively combats the disruption of signal timing stability caused by temperature and voltage fluctuations. These interconnected steps collectively achieve multi-dimensional, adaptive, high-precision length equalization and delay constraints for the CXL Switch high-speed differential link, from static design to dynamic operation, comprehensively improving the link's signal integrity, timing consistency, and environmental robustness.

[0051] Taking a specific application scenario as an example, in the motherboard design of an AI training server, the CXL Switch (ASIC) connects to the CPU0 Root Port via 16 uplinks and connects to 4 CXL memory expansion cards and 4 GPUs via 8 downlink ports. First (S101), the design tool obtains initial parameters such as the start and end points and expected speeds (e.g., 64 GT / s) of all 24 differential links. Next (S102), based on these parameters, it calculates the basic routing constraints (such as impedance control and spacing requirements) to meet 32GHz signal integrity. In the PCB layout stage (S103), components are placed and preliminary routing is performed according to these constraints. The key optimization is that for the 16 uplinks connecting the CPU (S104), an internal equal-length constraint of ≤1.5mil is configured in the PCB design rules; while for the 8 sets of downlinks connecting the expansion cards and GPUs, a relatively relaxed constraint of ≤2.5mil is configured. Simultaneously (S105), according to the business plan, some downlink channels carrying cache coherency traffic between the CPU and GPU are marked as "CXL.cache priority," adopting a "zero additional latency path" strategy and prohibiting PCB serpentine routing; channels mainly used for memory access are marked as "CXL.mem," allowing limited routing (e.g., ≤500mil); the remaining configuration channels are marked as "CXL.io." To implement these strategies (S106), a PDAU is integrated into the TX transmitter of each SerDes channel of the CXL Switch ASIC. After PCB manufacturing, the slight internal length difference that may exist in the "CXL.cache" channel is compensated by configuring the PDAU, rather than relying on PCB routing. During server operation (S107), the integrated temperature sensor detects that the temperature in the area near the GPU connector rises from 40°C to 75°C due to the GPU being fully loaded. The predictive model calculates that this temperature rise will cause the latency of the adjacent downlink to increase by about 2ps. The compensation control logic then drives the corresponding PDAU to decrease by 2ps, so that the total propagation latency of the link (PCB physical latency + PDAU compensation latency) is restored to the nominal value, thereby maintaining the stable timing of cache consistency transactions with the CPU.

[0052] In one embodiment, step S104, which involves configuring differentiated internal equal-length constraints for the uplink and downlink ports respectively, specifically includes: configuring a first threshold for the internal equal-length constraint for the uplink port and a second threshold for the internal equal-length constraint for the downlink port, wherein the first threshold is smaller than the second threshold. Furthermore, based on the above principles, this approach can achieve precise adaptation to the differences in uplink and downlink characteristics. Since the uplink port connects to the CPU, the link is short and extremely sensitive to cache coherency latency. Using a smaller first threshold (e.g., 1.5mil) can force more precise P / N line matching, controlling the arrival time difference of differential signals within a smaller range, thereby improving signal eye diagram quality, reducing bit error rate, and meeting the CPU's requirement for extremely low jitter. On the other hand, the downlink port connects to external devices, and the traces may be longer and pass through connectors. Overly strict constraints are difficult to implement in manufacturing. Using a relatively larger second threshold (e.g., 2.5mil) improves the feasibility and yield of PCB routing while ensuring basic signal integrity, avoiding the introduction of more impedance discontinuities due to excessive routing. This differentiated constraint achieves an optimal balance between performance and manufacturability.

[0053] In one embodiment, step S105, which involves setting a differentiated latency compensation strategy as mentioned above, specifically includes: for differential links intended to carry CXL.cache transactions, configuring a zero-additional-latency path compensation strategy to prohibit serpentine routing in PCB traces to achieve internal equal-length matching; for differential links intended to carry CXL.mem transactions, configuring a restricted serpentine routing compensation strategy to allow serpentine routing of limited lengths in PCB traces. Furthermore, based on the above principles, this approach can accurately meet the latency requirements of multi-protocol transactions. CXL.cache transactions (such as listening and consistency maintenance) are extremely sensitive to end-to-end latency; every additional picosecond of latency can affect the overall system performance. The zero-additional-latency path strategy prioritizes ensuring the shortest and most direct physical traces, fundamentally avoiding the additional propagation latency caused by serpentine routing, and providing the lowest-latency physical channel for critical consistency transactions. While CXL.mem transactions (such as memory read / write) are also latency-sensitive, they have a certain margin. The constrained serpentine routing strategy allows for the addition of a limited length of routing (e.g., total routing length not exceeding 500 mil) when equal-length matching is required. This satisfies the basic equal-length requirement while keeping the additional latency increase within a certain range, thus balancing signal integrity and access delay. This strategy differentiation ensures that high-priority transactions achieve optimal latency performance.

[0054] In one embodiment, the aforementioned PDAU is implemented using a Digital Controlled Delay Line (DCDL), whose adjustment step and range are configurable. Utilizing existing feature words, the PDAU, as the core component executing differentiated delay compensation strategies (S105) and dynamic environment compensation (S107), provides high-precision, digital delay adjustment capabilities through its DCDL implementation. By configuring different digital control words, the DCDL can precisely switch the connection combinations of internal delay units, thereby generating variable delay amounts. This configurability allows the same PDAU hardware to adapt to application scenarios with different precision requirements (through step adjustment) and different compensation ranges (through range adjustment). Furthermore, based on the above principles, this DCDL implementation provides high-precision, flexibly adjustable delay compensation capabilities, offering a hardware foundation for chip-level dynamic delay management.

[0055] As a specific implementation, the PDAU is adjusted in 0.5ps increments, with an adjustment range of ±50ps. This specific parameter allows the PDAU to precisely compensate for minute delay deviations caused by factors such as PCB manufacturing tolerances and temperature drift with an accuracy of 0.5ps, while its wide range of ±50ps is sufficient to cover the maximum delay drift that may be introduced by typical PCB trace length differences and environmental changes.

[0056] In one embodiment, the aforementioned environmental sensing data includes temperature and voltage; and the calculation of the predicted delay drift value based on the environmental sensing data specifically includes: calculating the temperature drift delay based on the temperature and the dielectric constant temperature coefficient, and calculating the voltage drift delay based on the voltage and the voltage-delay sensitivity coefficient. Utilizing existing feature words, temperature and voltage in the environmental sensing data are the main physical factors causing delay drift. Temperature changes alter the dielectric constant of the PCB dielectric, thus affecting signal propagation speed; voltage fluctuations affect the switching speed of the SerDes driver and receiver circuits. By combining the dielectric constant temperature coefficient of the dielectric material (e.g., approximately +200 ppm / °C for FR-4 material) and the measured temperature, the change in signal propagation speed due to temperature changes can be calculated, and then converted into delay drift. Similarly, by combining the voltage-delay sensitivity coefficient of the chip circuit (obtained through simulation or testing) and the measured voltage, the circuit delay change caused by power supply variations can be calculated. Superimposing both yields the comprehensive predicted delay drift value. Furthermore, based on the above principles, this calculation method can achieve quantitative prediction of time-delayed changes caused by environmental factors, providing accurate input basis for subsequent precise compensation.

[0057] In one embodiment, step S107, which involves calculating the predicted delay drift value based on environmental sensing data and controlling the PDAU for compensation, specifically includes: applying an exponentially weighted moving average filter to the acquired raw environmental sensing measurement sequence to obtain a smoothed value sequence; calculating the discrete first-order difference of the smoothed value sequence to obtain a rate of change sequence; dynamically determining a trigger threshold based on the statistical characteristics of the rate of change sequence within a preset time window; and only performing the calculation of the predicted delay drift value and controlling the PDAU to adjust when the absolute value of the current value of the rate of change sequence exceeds the trigger threshold. Using existing feature words, raw environmental sensing measurements (such as temperature sensor readings) often contain noise, and directly using them to drive the PDAU may lead to frequent and unnecessary adjustments, increasing power consumption and potentially introducing phase jitter. First, the raw sequence is smoothed using an exponentially weighted moving average (EWMA) filter to remove high-frequency noise, resulting in smoothed values ​​that better reflect the true trend. Then, the first-order difference of the smoothed value is calculated to obtain the rate of change of the environmental parameters. The key innovation lies in the triggering mechanism: instead of triggering expensive prediction model calculations and PDAU adjustments with every sampling, an adaptive threshold is dynamically generated based on the statistical characteristics (mean and standard deviation) of the recent (within a preset time window) rate of change. Only when the current rate of change significantly exceeds the "calm" range defined by historical noise levels (i.e., exceeding "mean + k times the standard deviation") is it considered a meaningful, non-noise-induced environmental change, and only then is the complete compensation process initiated. Furthermore, combining the above principles, this approach can significantly reduce false PDAU triggering and invalid adjustments caused by sensor noise, ensuring timely compensation while reducing system power consumption and avoiding unnecessary timing disturbances.

[0058] As a specific implementation method, the formula for this exponentially weighted moving average filter is: ,in, The original measurement value at the current moment. The filtered value from the previous time step. The smoothing factor; this trigger threshold is determined by the formula Calculate, where, and These are the mean and standard deviation of the absolute values ​​of the rate of change within the preset time window, respectively. These are preset coefficients. For example, a value could be taken as... Time window length ,coefficient .

[0059] In one embodiment, the operation of compensating for the aforementioned control of PDAU further includes: setting a first threshold for adjusting the delay. Set a second threshold for adjusting the delay. ,in Based on the current prediction delay drift value and the residual error after the last adjustment, calculate the comprehensive decision variable; and then, based on this comprehensive decision variable and the first threshold... and the second threshold Based on the relationship between the current PDAU setting and the state of the previous adjustment cycle, the current adjustment direction instruction for PDAU is determined. This state includes increasing delay, decreasing delay, or maintaining. Utilizing existing feature vocabulary, PDAU adjustment needs to prevent oscillations near the critical point. Asymmetric threshold ( The state memory mechanism and the current state together form a hysteresis comparator. The integrated decision variables incorporate the drift of the current forecast and the residual error not completely eliminated in the previous adjustment. The adjustment rule ensures that a significant deviation (exceeding...) is required to transition from the "hold" state to the "adjust" state. or ), while reverting from the "adjust" state to the "hold" state allows for smaller deviations (below ), or higher This asymmetric hysteresis property avoids the phenomenon where the prediction delay drift value is within a certain range. When there are minor fluctuations in the vicinity, the PDAU frequently switches between the "increase delay" and "hold" states, thereby enhancing the stability and anti-interference capability of the adjustment. Furthermore, based on the above principles, this method can effectively prevent the PDAU from oscillating under critical conditions, ensuring the steady-state accuracy and stability of the delay compensation loop.

[0060] As a specific implementation method, the rule for determining the adjustment direction instruction is as follows: if the previous state was maintained, then when the comprehensive decision variable is greater than... When the current instruction is to increase the delay; when the comprehensive decision variable is less than If the current instruction is to reduce delay, then maintain the current state; otherwise, maintain the current state. If the previous state was to increase delay, then only if the overall decision variable is less than the specified value... If the current instruction changes to hold, then hold and increase the delay; otherwise, hold and increase the delay. If the previous state was to decrease the delay, then only if the comprehensive decision variable is greater than... When the current instruction is in hold state, it is held; otherwise, the delay is reduced. For example, it can be set to... , .

[0061] In one embodiment, when multiple differential link channels simultaneously trigger PDAU adjustment requests, the operation of controlling PDAU compensation further includes: obtaining the priority identifier of each channel and the absolute value of its requested delay adjustment; calculating the corresponding arbitration weighting value based on the priority of each channel and the absolute value of the delay adjustment; and scheduling the PDAUs of each channel to perform adjustments sequentially within a set time budget according to the magnitude of the arbitration weighting value. Utilizing existing feature words, when temperature and voltage changes affect multiple channels, PDAU adjustment resources need reasonable arbitration. The priority identifier reflects the urgency of the transactions carried by the channel (e.g., the channel carrying the CXL.cache transaction has the highest priority). The arbitration weighting value integrates priority and adjustment amount: channels with higher priority gain a basic weight advantage; at the same time, channels with larger adjustment amounts are also reflected in the weight to avoid excessive delay in their adjustments. The scheduler determines the execution order based on the weighting value and sets the total adjustment time or step budget within a single scheduling cycle to prevent prolonged adjustments of individual channels from blocking other channels. Furthermore, based on the above principles, this approach ensures that high-priority critical transaction channels receive priority compensation when multiple channels compete for PDAU resources, while also taking into account the fairness of channels with large adjustment volumes. This achieves optimized scheduling of adjustment resources and guarantees the timing performance of the overall system.

[0062] As a specific implementation method, this arbitration weighting value Through formula Calculate, where, The priority of channel i, The absolute value of the delay adjustment requested. The largest among all channels to be adjusted , The preset weighting coefficients; this priority The priority is determined based on the type of CXL protocol transactions that the differential link is intended to carry, with the channel carrying CXL.cache transactions having the highest priority. For example, a CXL.cache channel can be defined. CXL.mem channel CXL.io channel and take .

[0063] In one embodiment, the above CXL protocol transaction types include CXL.cache transactions, CXL.mem transactions, and CXL.io transactions.

[0064] In one embodiment, the equal-length differential routing constraint method between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device, further includes configuring inter-group relative delay constraints for multiple differential links within a preset equal-length group. These inter-group relative delay constraints limit the maximum deviation between the propagation delays of each differential link within the equal-length group. Utilizing existing feature words, based on equal-length matching within a single differential pair, the inter-group relative delay constraints solve the problem of inconsistent signal arrival times between multiple parallel channels. For example, all differential pairs (Lanes) connected to the same CXL device are defined as an equal-length group, and the total propagation delay deviation between the longest and shortest traces within the group is constrained to not exceed a limit value (e.g., ±5ps). This ensures that data on different Lanes arrive essentially synchronously during multi-Lane parallel transmission, reducing the risk of parallel data parsing errors or timing chaos caused by channel skew, which is crucial for maintaining the reliability of high-speed bus parallel transmission. Furthermore, combining the above principles, this method can optimize the timing consistency between multiple channels at the system level, improving the overall signal quality and data transmission reliability of parallel links.

[0065] It should be noted that, in some optional implementations, the differentiated internal length equalization constraint based on port role can be specifically manifested as follows: the internal length equalization constraint threshold (first threshold) for the uplink port can be set to ≤1.5mil (corresponding to a propagation delay difference of approximately ≤0.18ps), and the internal length equalization constraint threshold (second threshold) for the downlink port can be set to ≤2.5mil (corresponding to a propagation delay difference of approximately ≤0.30ps). In other optional implementations, the specific limitation on "finite length" in the restricted serpentine winding compensation strategy can be set as follows: the total winding length does not exceed 500mil, and the winding pitch is not less than 3 times the linewidth, and the winding amplitude does not exceed 5 times the linewidth, in order to control the impedance discontinuity and reflection introduced by the winding. It should be noted that, in some optional implementations, to more accurately predict delay drift under non-uniform temperature fields, each differential trace path can be logically divided into multiple segments. Using measurements from multiple distributed temperature sensors, the local temperature at the center of each segment is calculated using a spatial interpolation algorithm (such as inverse distance weighting). The delay drift caused by temperature in each segment is then summed to obtain a more accurate predicted delay drift value for the entire path. In other optional implementations, for the optimization of the PCB traces themselves, an asymmetric, gradually curving serpentine winding structure can be used. Micro-protrusions (micro-ridges) on the inner arc side of the bends can be used to fine-tune local capacitance, thereby optimizing impedance continuity and fine-tuning delay at the picosecond level while achieving equal-length matching. Furthermore, a passive thermally actuated compensation strip made of metals with different coefficients of thermal expansion can be placed near the critical path close to the heat source. Its deformation causes the attached flexible reference ground trace to expand and contract, achieving passive temperature delay compensation. Inside the packaging substrate, a microbridge path switcher based on microelectromechanical systems (MEMS) can also be integrated. By electrostatically driving the gold microbridge to engage and disengage, a short path (for CXL.cache) and a long path (for CXL.io) can be switched, realizing protocol-aware dynamic path selection.

[0066] This application embodiment also provides a constraint device for equal-length differential traces in a CXL switch. The device includes: a parameter acquisition module configured to acquire the differential link connection relationship and initial electrical parameters between the uplink port and the CPU Root Port of the CXL switch, and between the downlink port and at least one CXL device; a routing planning module configured to calculate differential trace routing constraints that meet preset signal integrity indicators based on the differential link connection relationship and initial electrical parameters, and generate PCB layout routing instructions based on the constraints; a constraint configuration module configured to configure differentiated internal equal-length constraints for the uplink port and downlink port according to the port role, and set differentiated delay compensation strategies for the differential links according to the CXL protocol transaction type; a programmable delay adjustment unit (PDAU) disposed in the CXL switch, configured to adjust the propagation delay of the differential links according to the differentiated delay compensation strategy; an environment perception module configured to acquire environment perception data when the CXL switch is working; and a compensation control module configured to calculate the predicted delay drift value based on the environment perception data, and control the PDAU to perform compensation to maintain the equivalent total propagation delay of the differential links. This device achieves all the technical effects of the aforementioned method embodiments through the coordination of its various modules.

[0067] This application also provides an electronic device, which includes at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above method embodiments. The electronic device can be a server, workstation, personal computer, etc., in a wired or wireless network environment, and it is capable of executing the equal-length differential trace constraint method between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device, to achieve automated or semi-automated optimization control of the CXL Switch PCB design process.

[0068] This application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, can implement the steps in any of the above method embodiments. The storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A CXL switch uplink port and CPU root port, downlink port and CXL device equal length differential trace constraints, characterized in that, This includes obtaining the differential link connection relationship and initial electrical parameters between the uplink port and the CPU Root Port of the CXL Switch, and between the downlink port and at least one CXL device; Based on the differential link connection relationship and initial electrical parameters, calculate the differential routing constraints that satisfy the preset signal integrity index. Based on the differential routing constraints, the differential link routing layout and routing operations are performed on the printed circuit board (PCB) to complete the physical interconnection. Based on the port roles of the uplink and downlink ports, differentiated internal equal-length constraints are configured for the uplink and downlink ports respectively, wherein the constraint standard for the uplink port is stricter than that for the downlink port. Based on the CXL protocol transaction type to be carried by the differential link, a differentiated delay compensation strategy is set for the differential link, wherein the delay compensation priority of CXL.cache transactions is higher than that of CXL.mem and CXL.io transactions; Using the programmable delay adjustment unit (PDAU) in the CXL Switch, the propagation delay of the differential link is adjusted according to the differentiated delay compensation strategy; The system acquires environmental awareness data during the operation of the CXL Switch, calculates the predicted delay drift value of the differential link based on the environmental awareness data, and controls the PDAU to perform compensation in order to maintain the equivalent total propagation delay of the differential link.

2. The equal length differential pair of CXL Switch Upstream Port and CPU Root Port, Downstream Port and CXL Device of claim 1, wherein, The provision of differentiated internal equal-length constraints for the uplink and downlink ports includes: The internal equal-length constraint configured for the uplink port is a first threshold, and the internal equal-length constraint configured for the downlink port is a second threshold, wherein the first threshold is less than the second threshold.

3. The equal length differential pair of CXL Switch Upstream Port and CPU Root Port, Downstream Port and CXL Device of claim 2, wherein, The differentiated delay compensation strategy includes: For the differential link intended to carry CXL.cache transactions, configure a zero-addition-latency path compensation strategy to prohibit serpentine routing in PCB traces in order to achieve internal equal-length matching. For differential links intended to carry CXL.mem transactions, configure a restricted serpentine routing compensation strategy to allow serpentine routing of limited lengths in the PCB traces.

4. The equal length differential pair constraint between the CXL Switch Upstream Port and the CPU Root Port, the CXL Switch Downstream Port and the CXL Device of claim 1 or 3, wherein, The PDAU is implemented using a digitally controlled delay line (DCDL), and its adjustment step and adjustment range are configurable.

5. The equal-length differential trace constraint between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device as described in claim 4, is characterized in that... The adjustment step of the PDAU is 0.5ps, and the adjustment range is ±50ps.

6. The equal-length differential trace constraint between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device as described in claim 4, is characterized in that... The environmental sensing data includes temperature and voltage; The calculation of the predicted delay drift value based on environmental perception data includes: calculating the temperature drift delay based on the temperature and the dielectric constant temperature coefficient, and calculating the voltage drift delay based on the voltage and the voltage-delay sensitivity coefficient.

7. The equal-length differential trace constraint between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device as described in claim 4, is characterized in that... The process of calculating and predicting delay drift values ​​based on environmental perception data and controlling PDAU for compensation includes: The acquired raw environmental perception measurement value sequence is filtered by exponential weighted moving average to obtain a smooth value sequence. Calculate the discrete first-order difference of the smoothed value sequence to obtain the rate of change sequence; Based on the statistical characteristics of the rate of change sequence within a preset time window, the trigger threshold is dynamically determined; The calculation of the predicted delay drift value and the adjustment of the PDAU are only performed when the absolute value of the current value of the rate of change sequence exceeds the trigger threshold.

8. The equal-length differential trace constraint between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device as described in claim 7, is characterized in that... The formula for the exponentially weighted moving average filter is as follows: ,in, The original measurement value at the current moment. The filtered value from the previous time step. It is a smoothing factor; The trigger threshold is determined by the formula. Calculate, where, and These are the mean and standard deviation of the absolute values ​​of the rate of change within the preset time window, respectively. These are preset coefficients.

9. The equal-length differential trace constraint between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device, as described in claim 4 or 5, is characterized in that... The compensation of the controlled PDAU also includes: A first threshold T_up is set to increase the delay adjustment, and a second threshold T_down is set to decrease the delay adjustment, where T_up > T_down; Based on the current prediction delay drift value and the residual error after the last adjustment, calculate the comprehensive decision variables; Based on the relationship between the comprehensive decision variables and the first threshold T_up and the second threshold T_down, as well as the state of the previous adjustment cycle, the current adjustment direction instruction for PDAU is determined, and the state includes increasing delay, decreasing delay, or maintaining.

10. The equal-length differential trace constraint between the CXL Switch uplink port and the CPU Root Port, and between the downlink port and the CXL device as described in claim 9, is characterized in that... The rule for determining the adjustment direction command is as follows: If the previous state was "hold", then when the comprehensive decision variable is greater than T_up, the current instruction is to increase the delay; when the comprehensive decision variable is less than -T_down, the current instruction is to decrease the delay; otherwise, hold. If the previous state was "increase the delay", then only when the comprehensive decision variable is less than T_down, the current instruction changes to "hold"; otherwise, hold and increase the delay. If the previous state was to reduce latency, then the current instruction will switch to hold only if the overall decision variable is greater than -T_up; otherwise, it will hold to reduce latency.

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