Dma operation synchronization method and apparatus, electronic device, and medium
By setting a shared memory region and a write pointer synchronization identifier for the DMA ring buffer, the problems of high synchronization resource overhead and low efficiency in DMA operations are solved, and efficient and low-latency synchronization judgment is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MU XI LING ZHI KE JI (HANG ZHOU) YOU XIAN GONG SI
- Filing Date
- 2026-07-02
- Publication Date
- 2026-07-31
AI Technical Summary
Existing DMA operation synchronization methods suffer from high resource overhead and low efficiency, especially affecting system performance under high-frequency DMA operations, and making it difficult to accurately track the operation status.
A shared memory region is set up for the DMA circular buffer. By combining write pointers and barrier commands, the synchronization identifiers are shared and reused, reducing memory usage and resource overhead. The operation completion status is determined by unsigned surrounding subtraction.
It reduces the resource overhead of DMA operation synchronization, improves synchronization efficiency, reduces memory usage and interrupt overhead, and achieves low-latency synchronization judgment.
Smart Images
Figure CN122489459A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a DMA operation synchronization method, apparatus, electronic device, and medium. Background Technology
[0002] In high-performance computing systems, Direct Memory Access (DMA) technology is widely used for data transfer acceleration. Existing technologies typically employ the following synchronization methods to determine the completion status of DMA operations: (1) Based on an interrupt mechanism, the DMA controller sends an interrupt signal to the host device (Central Processing Unit, GPU) when the operation is completed. This method has at least the following drawbacks: large interrupt handling overhead, including context switching, interrupt service routine execution, etc.; a large number of interrupts generated by high-frequency DMA operations seriously affect the overall system performance; the interrupt latency is uncertain and difficult to meet low latency requirements. (2) Based on status register polling, the host device periodically reads the hardware status register of the DMA controller. This method has at least the following drawbacks: it requires access to hardware registers through the system bus, resulting in high access latency; it cannot accurately track the completion status of specific operations or commands; and it is difficult to distinguish the completion status of different operations when multiple concurrent DMA operations are performed. (3) Based on a fence (synchronization barrier) mechanism, a barrier command is inserted into the DMA command queue. This method suffers from at least the following drawbacks: maintaining a global atomic counter and assigning a unique identifier to each fence operation; requiring a separate memory region for each fence operation to write back its state; and lacking a direct correlation between the fence identifier and the actual execution state of the DMA queue. Therefore, reducing the resource overhead of DMA operation synchronization and improving its efficiency are urgent technical problems to be solved. Summary of the Invention
[0003] The purpose of this invention is to provide a DMA operation synchronization method, apparatus, electronic device, and medium that reduces the resource overhead of DMA operation synchronization and improves the efficiency of DMA operation synchronization.
[0004] According to a first aspect of the present invention, a DMA operation synchronization method is provided, comprising: A shared memory region is set up for the DMA ring buffer, which is a ring buffer in which DMA operation commands are written by the host device and read by the DMA device; DMA operation commands are sequentially written to the DMA ring buffer and the write pointer is updated. When DMA operation synchronization is required, the barrier command synchronization identifier is obtained based on the current write pointer value. The shared memory region address is used as the operation address of the barrier command. Then, the barrier command is inserted into the position pointed to by the current write pointer value in the DMA ring buffer and the write pointer is updated. The DMA device executes commands in the DMA circular buffer sequentially. When a barrier command is executed, the synchronization identifier corresponding to the barrier command is updated in the shared memory region. The host device obtains the target pointer and polls the shared memory region. It obtains the currently stored write pointer in the shared memory region, compares the target pointer with the currently stored write pointer, and determines whether the target pointer is located after the currently stored write pointer. If so, it is determined that the target DMA operation has not been completed; otherwise, it is determined that the target DMA operation has been completed.
[0005] Furthermore, the step of comparing the target pointer and the currently stored write pointer to determine whether the target pointer is located before the currently stored write pointer includes: Based on the current stored write pointer and the target pointer, perform an M-bit unsigned surrounding subtraction to obtain the corresponding difference, where M is the number of bits in the synchronization identifier; If the corresponding difference is in [0, 2] M-1 If the difference is within the range of [-1], then the target pointer is determined to be located before or coincide with the currently stored write pointer. If the corresponding difference is within [2], then the target pointer is determined to be located before or coincide with the currently stored write pointer. M ,2 M If the value is within the range of -1], then the target pointer is determined to be after the currently stored write pointer.
[0006] Furthermore, if the number of bits in the write pointer is less than or equal to the number of bits in the synchronization identifier, then the write pointer is directly used as the corresponding synchronization identifier. If the number of bits in the write pointer is greater than the number of bits in the synchronization identifier, then only the lower M bits of the write pointer will be used as the corresponding synchronization identifier.
[0007] Furthermore, M can take the value 32 or 64.
[0008] Furthermore, accessing shared memory regions is an atomic memory operation.
[0009] According to a second aspect of the present invention, a DMA operation synchronization device is provided, comprising: The configuration module, located in the host device, is used to set up a shared memory area for the DMA ring buffer, which is a ring buffer in which DMA operation commands are written by the host device and read by the DMA device. The command writing module, located in the host device, is used to sequentially write DMA operation commands to the DMA ring buffer and update the write pointer. When DMA operation synchronization is required, it obtains the barrier command synchronization identifier based on the current write pointer value, uses the shared memory region address as the operation address of the barrier command, and then inserts the barrier command into the position pointed to by the current write pointer value in the DMA ring buffer and updates the write pointer. The execution module, located in the DMA device, is used to execute commands in the DMA circular buffer in sequence. When a barrier command is executed, the synchronization identifier corresponding to the barrier command is updated to the shared memory area. The judgment module, located in the host device, is used to obtain the target pointer and poll the shared memory region, obtain the currently stored write pointer in the shared memory region, compare the target pointer and the currently stored write pointer, and determine whether the target pointer is after the currently stored write pointer. If so, it is determined that the target DMA operation has not been completed; otherwise, it is determined that the target DMA operation has been completed.
[0010] Furthermore, the determination module includes: The calculation unit is used to perform an M-bit unsigned wrap-around subtraction based on the currently stored write pointer and the target pointer to obtain the corresponding difference, where M is the number of bits of the synchronization identifier; The judgment unit is used to determine the corresponding difference in [0, 2]. M-1 When the target pointer is within the range of [-1], it is determined that the target pointer is located before or coincides with the currently stored write pointer, and the corresponding difference is within [2]. M ,2 M When the target pointer is within the range of -1], it is determined that the target pointer is after the currently stored write pointer.
[0011] Furthermore, if the number of bits in the write pointer is less than or equal to the number of bits in the synchronization identifier, then the write pointer is directly used as the corresponding synchronization identifier. If the number of bits in the write pointer is greater than the number of bits in the synchronization identifier, then only the lower M bits of the write pointer will be used as the corresponding synchronization identifier.
[0012] Furthermore, M can take the value 32 or 64.
[0013] Furthermore, accessing shared memory regions is an atomic memory operation.
[0014] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.
[0015] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.
[0016] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the DMA operation synchronization method, apparatus, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It possesses at least the following beneficial effects: This invention establishes a shared memory region for the DMA circular buffer. All barrier commands within the DMA circular buffer share this shared memory region, eliminating the need to set up a separate memory region for each barrier command, thus significantly reducing memory usage. Furthermore, this invention reuses the write pointer of the DMA circular buffer as the data for barrier commands. No additional counters are required, further reducing resource overhead. This invention requires only a single memory access to determine DMA operation synchronization, eliminating interrupt overhead and resulting in low latency, thus improving the efficiency of DMA operation synchronization. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 Here is a flowchart of the DMA operation synchronization method provided in Example 1; Figure 2 A flowchart for comparing the target pointer and the currently stored write pointer provided in Example 1; Figure 3 This is a schematic diagram of the DMA operation synchronization device provided in Embodiment 2; Figure 4 This is a schematic diagram of the judgment module structure provided in Embodiment 2; Figure 5 This is a schematic diagram of the electronic device structure provided in Embodiment 3; Figure 6 This is a schematic diagram of the structure of a computer-readable storage medium provided in Embodiment 4. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] Example 1 Example 1 provides a DMA operation synchronization method, such as Figure 1 As shown, it includes: Step S1: Set up a shared memory region for the DMA ring buffer, wherein the DMA ring buffer is a ring buffer in which the host device writes DMA operation commands and the DMA device reads DMA operation commands.
[0021] It should be noted that this embodiment of the invention supports creating independent fence operations for multiple independent DMA ring buffers. Each DMA ring buffer independently uses its corresponding shared memory region, supporting batch synchronization and concurrent detection. Only one shared memory region needs to be set for each DMA ring buffer, eliminating the need for a separate memory region for each barrier command, thus reducing resource overhead by over 90% and host device overhead by over 50%. DMA device refers to DMA hardware, specifically a DMA engine. The host device is responsible for reading, parsing, and processing the DMA ring buffer; specifically, the host device can be a CPU. The DMA device is responsible for writing or transferring data to the DMA ring buffer. Specifically, atomic counting units can be allocated in the shared memory region for the DMA ring buffer. Both the host device and the DMA device can perform atomic operations on these atomic counting units. Atomic operations are uninterrupted; therefore, accessing the shared memory region is an atomic memory operation, ensuring the safety of multi-threaded concurrency.
[0022] Step S2: Write DMA operation commands sequentially into the DMA ring buffer and update the write pointer. When DMA operation synchronization is required, obtain the barrier command synchronization identifier based on the current write pointer value, use the shared memory region address as the operation address of the barrier command, and then insert the barrier command into the position pointed to by the current write pointer value in the DMA ring buffer and update the write pointer.
[0023] It should be noted that the insertion position of the barrier command can be set according to specific application requirements. For example, after writing three consecutive DMA operation commands, a corresponding barrier command can be written; then after writing eight consecutive DMA operation commands, another corresponding barrier command can be written. The write pointer in the DMA circular buffer is updated accordingly for each command written, specifically incrementally. The write pointer points to the next area to be written in the DMA circular buffer. The write pointer naturally reflects the execution progress of the DMA queue. Setting the write pointer corresponding to the barrier command to the synchronization identifier corresponding to that barrier command can ensure the timing correctness of the DMA operation completion detection.
[0024] Step S3: The DMA device executes the commands in the DMA ring buffer in sequence. When the barrier command is executed, the synchronization identifier corresponding to the barrier command is updated in the shared memory area.
[0025] It should be noted that when a barrier command is executed, it indicates that the DMA operation commands preceding the barrier command have been completed. Upon execution of the barrier command, the synchronization identifier corresponding to the barrier command is updated in the shared memory region, and the DMA device continues to execute subsequent commands in the DMA circular buffer.
[0026] Step S4: The host device obtains the target pointer and polls the shared memory region to obtain the currently stored write pointer in the shared memory region. It compares the target pointer with the currently stored write pointer and determines whether the target pointer is located after the currently stored write pointer. If so, it is determined that the target DMA operation has not been completed; otherwise, it is determined that the target DMA operation has been completed.
[0027] It should be noted that the host device creates a polling object, which stores the write pointer and the target pointer currently stored in the shared memory region. The target pointer is the address where it is necessary to determine whether the corresponding DMA operation has been completed.
[0028] In this embodiment, a DMA ring buffer requires only one shared memory region. The same shared memory region is reused by multiple barrier commands, and the barrier commands are distinguished by their corresponding write pointers, thus realizing resource reuse and concurrency support.
[0029] As an example, in step S4, the target pointer and the currently stored write pointer are compared to determine whether the target pointer is located before the currently stored write pointer. Figure 2 As shown, it includes: Step S41: Perform an M-bit unsigned wrap-around subtraction based on the currently stored write pointer and the target pointer to obtain the corresponding difference, where M is the number of bits in the synchronization identifier.
[0030] It should be noted that performing M-bit unsigned surrounding subtraction based on the current storage write pointer and the target pointer means subtracting the target pointer from the current storage write pointer. If the difference is large enough, the corresponding difference is directly obtained; if it is not large enough, the current storage write pointer needs to be incremented by 2 first. M Then subtract the target pointer to get the corresponding difference, thus automatically limiting the difference to [0, 2]. M Within the range of [-1], that is, if it exceeds the range, it will circle once and will not generate an overflow exception.
[0031] Step S42: If the corresponding difference is in [0, 2] M-1 If the difference is within the range of [-1], then the target pointer is determined to be located before or coincide with the currently stored write pointer. If the corresponding difference is within [2], then the target pointer is determined to be located before or coincide with the currently stored write pointer. M ,2 M If the value is within the range of -1], then the target pointer is determined to be after the currently stored write pointer.
[0032] It should be noted that the address space of the M-bit shared memory region is divided into two intervals: [0, 2... M-1 -1] and [2] M ,2 M -1],[0,2 M-1 [-1] represents the interval where the operation has been completed, [2] M ,2 M [-1] represents the interval where the operation is not yet completed.
[0033] If the number of bits in the write pointer is less than or equal to the number of bits in the synchronization identifier, the write pointer is directly used as the corresponding synchronization identifier, and subsequently stored in the shared memory area as the corresponding synchronization identifier. If the number of bits in the write pointer is greater than the number of bits in the synchronization identifier, only the lower M bits of the write pointer are used as the corresponding synchronization identifier, and subsequently stored in the shared memory area as the corresponding synchronization identifier.
[0034] As an example, the number of bits in the synchronization identifier is equal to the number of bits in the write pointer, or the number of bits in the write pointer is twice the number of bits in the synchronization identifier. If the number of bits in the write pointer is twice the number of bits in the synchronization identifier, then the shared memory region only stores the lower M bits of the write pointer, where M is the number of bits in the synchronization identifier.
[0035] As a specific example, M is 32 bits, the synchronization identifier is 32 bits, the write pointer is 64 bits, and the shared memory region only stores the lower M bits of the write pointer. The M-bit shared memory region address space is divided into two intervals: [0, 2... M-1 -1] and [2] M ,2 M -1] are [0, 0x7FFF_FFFF] and [0x8000_0000, 0xFFFF_FFFF] respectively.
[0036] Taking the current storage write pointer as 150 and the target pointer as 100 as an example, a 32-bit unsigned wrap-around subtraction is performed based on the current storage write pointer and the target pointer: 150-100=50. 50 is in the range [0, 0x7FFF_FFFF]. Therefore, it is determined that the target pointer is located before the current storage write pointer, and thus the target DMA operation is determined to be complete.
[0037] Taking a current write pointer of 0x100 and a target pointer of 0xFFFF_FF00 as an example, a 32-bit unsigned wrap-around subtraction is performed based on the current write pointer and the target pointer: 0x100 - xFFFF_FF00 = 0x100 + 2 32 -xFFFF_FF000=0x200, 0x200 is in the range [0, 0x7FFF_FFFF], so it is determined that the target pointer is located before the current storage write pointer, and thus the target DMA operation is determined to be complete. It is understandable that in this example, there is a situation of wrapping around the 4GB boundary.
[0038] Taking a current write pointer of 50 and a target pointer of 100 as an example, a 32-bit unsigned wrap-around subtraction is performed based on the current write pointer and the target pointer: 50 - 100 = 50 + 2 32 -100 = 0xFFFF_FFCE. Since 0xFFFF_FFCE is in the range [0x8000_0000, 0xFFFF_FFFF], it is determined that the target pointer is after the write pointer of the current storage, and thus it is determined that the target DMA operation has not been completed. It is understandable that in this example, there is a situation of wrapping around the 4GB boundary.
[0039] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0040] The method described in Example 1 sets up a shared memory region for the DMA circular buffer. All barrier commands in the DMA circular buffer share this shared memory region, eliminating the need to set up a memory region for each barrier command, thus greatly reducing memory usage. Furthermore, this invention reuses the write pointer of the DMA circular buffer as the data for the barrier commands. No additional counters are required, further reducing resource overhead. Example 1 only requires a single memory access to determine DMA operation synchronization, eliminating interrupt overhead and resulting in low latency and improved efficiency of DMA operation synchronization.
[0041] Example 2 Example 2 provides a DMA operation synchronization device, such as Figure 3 As shown, it includes: The configuration module, located in the host device, is used to set up a shared memory region for the DMA ring buffer, which is a ring buffer in which DMA operation commands are written by the host device and read by the DMA device.
[0042] It should be noted that the configuration module of this embodiment supports creating independent fence operations for multiple independent DMA ring buffers. Each DMA ring buffer independently uses its corresponding shared memory region, supporting batch synchronization and concurrent detection. Only one shared memory region needs to be set for each DMA ring buffer, eliminating the need for a separate memory region for each barrier command, thus reducing resource overhead by over 90% and host device overhead by over 50%. DMA device refers to DMA hardware, specifically a DMA engine. The host device is responsible for reading, parsing, and processing the DMA ring buffer; specifically, the host device can be a CPU. The DMA device is responsible for writing or transferring data to the DMA ring buffer. Specifically, atomic counting units can be allocated in the shared memory region for the DMA ring buffer. Both the host device and the DMA device can perform atomic operations on these atomic counting units. Atomic operations are uninterrupted; therefore, accessing the shared memory region is an atomic memory operation, ensuring the safety of multi-threaded concurrency.
[0043] The command writing module, located in the host device, is used to sequentially write DMA operation commands to the DMA ring buffer and update the write pointer. When DMA operation synchronization is required, it obtains the barrier command synchronization identifier based on the current write pointer value, uses the shared memory region address as the operation address of the barrier command, and then inserts the barrier command into the position pointed to by the current write pointer value in the DMA ring buffer and updates the write pointer.
[0044] It should be noted that the insertion position of the barrier command can be set according to specific application requirements. For example, after writing three consecutive DMA operation commands, a corresponding barrier command can be written; then after writing eight consecutive DMA operation commands, another corresponding barrier command can be written. The write pointer in the DMA circular buffer is updated accordingly for each command written, specifically incrementally. The write pointer points to the next area to be written in the DMA circular buffer. The write pointer naturally reflects the execution progress of the DMA queue. Setting the write pointer corresponding to the barrier command to the synchronization identifier corresponding to that barrier command can ensure the timing correctness of the DMA operation completion detection.
[0045] The execution module, located in the DMA device, is used to execute commands in the DMA ring buffer in sequence. When a barrier command is executed, the synchronization identifier corresponding to the barrier command is updated in the shared memory area.
[0046] It should be noted that when the execution module reaches the barrier command, it indicates that the DMA operation commands preceding the barrier command have been completed. When the execution module reaches the barrier command, it updates the synchronization identifier corresponding to the barrier command in the shared memory region, and then continues to execute subsequent commands in the DMA circular buffer.
[0047] The judgment module, located in the host device, is used to obtain the target pointer and poll the shared memory region, obtain the currently stored write pointer in the shared memory region, compare the target pointer and the currently stored write pointer, and determine whether the target pointer is after the currently stored write pointer. If so, it is determined that the target DMA operation has not been completed; otherwise, it is determined that the target DMA operation has been completed.
[0048] It should be noted that the judgment module creates a polling object, which stores the write pointer and the target pointer currently stored in the shared memory region. The target pointer is the address where it is necessary to determine whether the corresponding DMA operation has been completed.
[0049] In this embodiment, a DMA ring buffer requires only one shared memory region. The same shared memory region is reused by multiple barrier commands, and the barrier commands are distinguished by their corresponding write pointers, thus realizing resource reuse and concurrency support.
[0050] As an example, such as Figure 4 As shown, the judgment module includes: The calculation unit is used to perform an M-bit unsigned wrap-around subtraction based on the currently stored write pointer and the target pointer to obtain the corresponding difference, where M is the number of bits of the synchronization identifier.
[0051] It should be noted that the calculation unit is specifically used to: subtract the target pointer from the currently stored write pointer; if the difference is large enough, the corresponding difference is obtained directly; if the difference is small enough, the currently stored write pointer needs to be incremented by 2. M Then subtract the target pointer to get the corresponding difference, thus automatically limiting the difference to [0, 2]. M Within the range of [-1], that is, if it exceeds the range, it will circle once and will not generate an overflow exception.
[0052] The judgment unit is used to determine the corresponding difference in [0, 2]. M-1 When the target pointer is within the range of -1], it is determined that the target pointer is located before or coincides with the currently stored write pointer, and the corresponding difference is within (2) M-1 -1,2 MWhen the target pointer is within the range of -1], it is determined that the target pointer is after the currently stored write pointer.
[0053] It should be noted that the decision unit can divide the M-bit shared memory region address space into two intervals: [0, 2... M-1 -1] and [2] M ,2 M -1],[0,2 M-1 [-1] represents the interval where the operation has been completed, [2] M ,2 M [-1] represents the interval where the operation is not yet completed.
[0054] The command writing module includes a synchronization identifier acquisition unit, which is used to directly use the write pointer as the corresponding synchronization identifier when the number of bits of the write pointer is less than or equal to the number of bits of the synchronization identifier, and subsequently directly store the write pointer as the corresponding synchronization identifier in the shared memory area; when the number of bits of the write pointer is greater than the number of bits of the synchronization identifier, only the lower M bits of the write pointer are used as the corresponding synchronization identifier, and subsequently only the lower M bits of the write pointer are used as the corresponding synchronization identifier in the shared memory area.
[0055] As an example, the number of bits in the synchronization identifier is equal to the number of bits in the write pointer, or the number of bits in the write pointer is twice the number of bits in the synchronization identifier. If the number of bits in the write pointer is twice the number of bits in the synchronization identifier, then the shared memory region only stores the lower M bits of the write pointer, where M is the number of bits in the synchronization identifier.
[0056] As a concrete example, M can be 32 or 64 bits, the synchronization identifier is 32 bits, the write pointer is 64 bits, and the shared memory region only stores the lower M bits of the write pointer. The M-bit shared memory region address space is divided into two intervals: [0, 2...]. M-1 -1] and [2] M ,2 M -1] are [0, 0x7FFF_FFFF] and [0x8000_0000, 0xFFFF_FFFF] respectively.
[0057] The device described in Embodiment 2 sets up a shared memory region for the DMA circular buffer. All barrier commands in the DMA circular buffer share this shared memory region, eliminating the need to set up a memory region for each barrier command, thus greatly reducing memory usage. Furthermore, this invention reuses the write pointer of the DMA circular buffer as the data for the barrier commands. No additional counter is required, further reducing resource overhead. Embodiment 1 requires only a single memory access to determine DMA operation synchronization, eliminating interrupt overhead and resulting in low latency and improved efficiency of DMA operation synchronization.
[0058] Example 3 This invention also provides an electronic device, such as... Figure 5 As shown, it includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the embodiments of the present invention.
[0059] Example 4 This invention also provides a computer-readable storage medium, such as... Figure 6 As shown, computer-executable instructions are stored thereon, which are used to execute the methods described in the embodiments of the present invention.
[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A DMA operation synchronization method, characterized in that, include: A shared memory region is set up for the DMA ring buffer, which is a ring buffer in which DMA operation commands are written by the host device and read by the DMA device; DMA operation commands are sequentially written to the DMA ring buffer and the write pointer is updated. When DMA operation synchronization is required, the barrier command synchronization identifier is obtained based on the current write pointer value. The shared memory region address is used as the operation address of the barrier command. Then, the barrier command is inserted into the position pointed to by the current write pointer value in the DMA ring buffer and the write pointer is updated. The DMA device executes commands in the DMA circular buffer sequentially. When a barrier command is executed, the synchronization identifier corresponding to the barrier command is updated in the shared memory region. The host device obtains the target pointer and polls the shared memory region. It obtains the currently stored write pointer in the shared memory region, compares the target pointer with the currently stored write pointer, and determines whether the target pointer is located after the currently stored write pointer. If so, it is determined that the target DMA operation has not been completed; otherwise, it is determined that the target DMA operation has been completed.
2. The method according to claim 1, characterized in that, The step of comparing the target pointer and the currently stored write pointer to determine whether the target pointer is located before the currently stored write pointer includes: Based on the current stored write pointer and the target pointer, perform an M-bit unsigned surrounding subtraction to obtain the corresponding difference, where M is the number of bits in the synchronization identifier; If the corresponding difference is in the range [0, 2 M-1 -1], it is determined that the target pointer is located before or coincides with the currently stored write pointer, if the corresponding difference is in the range [2 M , 2 M -1], it is determined that the target pointer is located after the currently stored write pointer.
3. The method according to claim 1, characterized in that, The process of obtaining the barrier command synchronization identifier based on the current write pointer value includes: If the number of bits in the write pointer is less than or equal to the number of bits in the synchronization identifier, then the write pointer is directly used as the corresponding synchronization identifier. If the number of bits in the write pointer is greater than the number of bits in the synchronization identifier, then only the lower M bits of the write pointer will be used as the corresponding synchronization identifier.
4. The method according to claim 3, characterized in that, The value of M is either 32 or 64.
5. The method according to claim 1, characterized in that, Accessing a shared memory region is an atomic memory operation.
6. A DMA operation synchronization device, characterized in that, include: The configuration module, located in the host device, is used to set up a shared memory area for the DMA ring buffer, which is a ring buffer in which DMA operation commands are written by the host device and read by the DMA device. The command writing module, located in the host device, is used to sequentially write DMA operation commands to the DMA ring buffer and update the write pointer. When DMA operation synchronization is required, it obtains the barrier command synchronization identifier based on the current write pointer value, uses the shared memory region address as the operation address of the barrier command, and then inserts the barrier command into the position pointed to by the current write pointer value in the DMA ring buffer and updates the write pointer. The execution module, located in the DMA device, is used to execute commands in the DMA circular buffer in sequence. When a barrier command is executed, the synchronization identifier corresponding to the barrier command is updated to the shared memory area. The judgment module, located in the host device, is used to obtain the target pointer and poll the shared memory region, obtain the currently stored write pointer in the shared memory region, compare the target pointer and the currently stored write pointer, and determine whether the target pointer is after the currently stored write pointer. If so, it is determined that the target DMA operation has not been completed; otherwise, it is determined that the target DMA operation has been completed.
7. The synchronization device according to claim 6, characterized in that, The judgment module includes: The calculation unit is used to perform an M-bit unsigned wrap-around subtraction based on the currently stored write pointer and the target pointer to obtain the corresponding difference, where M is the number of bits of the synchronization identifier; The judgment unit is used to determine the corresponding difference in [0, 2]. M-1 When the target pointer is within the range of [-1], it is determined that the target pointer is located before or coincides with the currently stored write pointer, and the corresponding difference is within [2]. M ,2 M When the target pointer is within the range of -1], it is determined that the target pointer is after the currently stored write pointer.
8. The synchronization device according to claim 6, characterized in that, The command writing module includes: The synchronization identifier acquisition unit is used to directly use the write pointer as the corresponding synchronization identifier when the number of bits of the write pointer is less than or equal to the number of bits of the synchronization identifier; and to use only the lower M bits of the write pointer as the corresponding synchronization identifier when the number of bits of the write pointer is greater than the number of bits of the synchronization identifier.
9. The synchronization device according to claim 8, characterized in that, The value of M is either 32 or 64.
10. The synchronization device according to claim 6, characterized in that, Accessing a shared memory region is an atomic memory operation.
11. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method as described in any one of claims 1-5.
12. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method as described in any one of claims 1-5.