Serial peripheral interface bus topology with multiplexed chip select addressing

Abstract

The examples described herein provide a method that includes determining whether a software request at a microcontroller unit (MCU) is pending, the software request being to read data from or write data to an SPI device. The method also includes, in response to determining that the software request is pending, having the MCU drive column select and row select signals using an SPI device address associated with the SPI device. The method further includes decoding the column select and row select signals by chip select decoder logic. The method further includes having the MCU perform an SPI transaction with one of a plurality of SPI devices, the SPI transaction being to read data from or write data to one of the SPI devices.

Description

Technical Field

[0001] This subject matter relates to vehicles, and more specifically to serial peripheral interface bus topologies with multiplexed chip select addressing. Background Technology

[0002] Serial Peripheral Interface (SPI) is a synchronous communication protocol used to transfer data between a command device (sometimes called a "master" device) and one or more responder devices (sometimes called "slave" devices). SPI typically operates with a simple four-wire configuration: Clock (SCLK), Master Output / Slave Input (MOSI), Master Input / Slave Output (MISO), and Slave Select (SS) (sometimes called "Chip Select" (CS)). SPI is known for its high speed and efficiency in transmitting data over short distances.

[0003] In vehicles, SPI is widely used for communication between microcontrollers and peripheral devices such as sensors, displays, and control modules. SPI is typically used with electronic control units (ECUs) in vehicles. ECUs are dedicated computing modules that manage various automotive systems, such as engine control, transmission, braking, and infotainment. SPI provides a reliable and efficient means of communication between the ECU's microcontroller and peripheral devices or other components. For example, the ECU can use SPI to interface with sensors (e.g., temperature sensors, pressure sensors, or position sensors), memory modules, or other subsystems that require fast and synchronous data exchange. SPI's simplicity and speed make it a useful choice for automotive applications that require low-latency communication. For example, SPI enables rapid data exchange with devices such as tire pressure monitoring systems, engine control sensors, or infotainment components, ensuring the real-time performance of critical automotive functions.

[0004] The desire to improve SPI communication remains. Summary of the Invention

[0005] In one embodiment, a method is provided. The method includes determining whether a software request is pending at a microcontroller unit (MCU), the software request being to read data from or write data to an SPI device, the SPI devices being selected from a plurality of SPI devices arranged in an SPI device matrix and electrically connected to the MCU. The method further includes, in response to determining that the software request is pending, having the MCU drive column select signals and row select signals using an SPI device address associated with the SPI device. The method further includes decoding the column select signals and row select signals by chip select decoder logic, wherein the chip select decoder logic is electrically connected to each of the plurality of SPI devices. The method further includes having the MCU perform an SPI transaction using an SPI device selected from the plurality of SPI devices, the SPI transaction being to read data from or write data to one of the SPI devices.

[0006] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include an MCU and multiple SPI devices forming an SPI bus.

[0007] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include having the SPI bus idle until it is determined whether a software request at the MCU is pending.

[0008] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include determining whether an SPI transaction is complete, and returning the SPI bus to an idle state in response to determining that the SPI transaction is complete.

[0009] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include an SPI bus that also includes a Master Output / Slave Input (MOSI) line, a Serial Clock (SCLK) line, a Master Input / Slave Output (MISO) line, and a Chip Select (CS) line.

[0010] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include an MCU electrically connected to a plurality of SPI devices at least via a chip select decoder logic.

[0011] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include the MCU being further electrically connected to a plurality of SPI devices at least via multiplexers and buffers.

[0012] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include buffers comprising an SCLK buffer and a MOSI buffer.

[0013] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include a multiplexer comprising a MISO multiplexer.

[0014] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include decoding column select signals and row select signals by chip select decoder logic, and determining which of a plurality of SPI devices is an SPI device based at least in part on the column select signals and row select signals.

[0015] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include configuring the chip select decoder logic based at least in part on the number of SPI devices among a plurality of SPI devices.

[0016] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include the chip selection decoder logic comprising a plurality of chip selection decoders and row address decoders.

[0017] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include the chip selection decoder logic comprising a plurality of chip selection decoders and reverse logic.

[0018] In addition to one or more features described herein, or as an alternative, other embodiments of the method may include the chip selection decoder logic comprising a plurality of chip selection decoders.

[0019] In another embodiment, a vehicle with communication circuitry is provided. The communication circuitry includes a microcontroller unit, a multiplexer, a buffer, chip select decoder logic, and an SPI device matrix having multiple Serial Peripheral Interface (SPI) devices, each of which is electrically connected to the MCU via the multiplexer, buffer, and chip select decoder logic, and each of the multiple SPI devices is selectively addressable by the MCU via the chip select decoder logic.

[0020] In addition to one or more features described herein, or as an alternative, other embodiments of the vehicle may include an MCU and multiple SPI devices forming an SPI bus, wherein the SPI bus also includes a master output / slave input (MOSI) line, a serial clock (SCLK) line, a master input / slave output (MISO) line, and a chip select (CS) line.

[0021] In addition to one or more features described herein, or as an alternative, other embodiments of the vehicle may include buffers including SCLK buffers and MOSI buffers, and wherein the multiplexer includes a MISO multiplexer.

[0022] In addition to one or more features described herein, or as an alternative, other embodiments of the vehicle may include a configuration of the chip selection decoder logic that is at least in part based on the number of SPI devices among a plurality of SPI devices.

[0023] In addition to one or more features described herein, or as an alternative, other embodiments of the vehicle may include chip selection decoder logic comprising a plurality of chip selection decoders.

[0024] In another embodiment, a communication circuit is provided. The communication circuit includes a microcontroller unit, a multiplexer, a buffer, chip select decoder logic, and an SPI device matrix including a plurality of Serial Peripheral Interface (SPI) devices, each of the plurality of SPI devices being electrically connected to the MCU via the multiplexer, buffer, and chip select decoder logic, and each of the plurality of SPI devices being selectively addressable by the MCU via the chip select decoder logic.

[0025] The above-described features and advantages, as well as other features and advantages, of this disclosure will become apparent when taken in conjunction with the accompanying drawings and the following detailed description. Attached Figure Description

[0026] Other features, advantages, and details appear only as examples in the following detailed description, which is described in detail with reference to the accompanying drawings, in which:

[0027] Figure 1 A vehicle with communication circuitry according to one or more embodiments is shown;

[0028] Figure 2 The illustration shows one or more embodiments. Figure 1 The circuit diagram of the communication circuit;

[0029] Figures 3A-3E Together, illustrations are provided according to one or more embodiments. Figure 1 The circuit diagram of the communication circuit; and

[0030] Figure 4A flowchart is shown for a method for a serial peripheral interface bus topology with multiplexed chip select addressing, according to one or more embodiments. Detailed Implementation

[0031] The following description is exemplary in nature only and is not intended to limit this disclosure, its application, or use. It should be understood that throughout the drawings, corresponding reference numerals denote the same or corresponding parts and features. As used herein, the term module refers to processing circuitry that may include application-specific integrated circuits (ASICs), electronic circuitry, processor (shared, dedicated, or grouped) and memory executing one or more software or firmware programs, combinational logic circuitry, and / or other suitable components that provide the described functionality.

[0032] As used herein, the term “controller” (e.g., automotive electronic controller) refers to a dedicated controller that includes a processor and memory, a general-purpose controller that includes control modules configured to perform control processes using the dedicated controller, a network of multiple different controllers that communicate with each other and each includes a processor and memory and are configured to cooperate in implementing control processes, and any similar configuration for implementing control processes.

[0033] One or more embodiments described herein relate to a serial peripheral interface bus topology with multiplexed chip select addressing.

[0034] In modern vehicles, the expectation for efficient and reliable communication between microcontrollers and peripheral devices is significant. The Serial Peripheral Interface (SPI) is a widely used synchronous communication protocol that facilitates data transfer between command devices (such as microcontrollers, also known as "MCUs") and multiple responder devices (including sensors, displays, and control modules). SPI is favored for its high-speed data transfer capabilities and simplicity, and typically operates in a four-wire configuration: Clock (SCLK) (also known as "SPI bus clock"), Master Output / Slave Input (MOSI) (also known as "SPI bus serial data, MCU output / SPI device input"), Master Input / Slave Output (MISO) (also known as "SPI bus serial data, MCU input / SPI device output"), and Slave Select (SS) (also known as "chip select" (CS)). In automotive applications, SPI plays a role in the operation of electronic control units (ECUs), which manage various systems such as engine control, transmission, and infotainment. SPI's ability to provide low-latency communication is extremely useful for the real-time performance of essential automotive functions.

[0035] Despite these advantages, traditional SPI configurations have several limitations, particularly in high-capacity ECUs (typically used in vehicles) that need to communicate with a large number of SPI devices. Typically, due to limitations in available SPI bus signal resources and total capacitive load, the microcontroller can only address a limited number of devices on the bus. This limitation often necessitates the use of multiple SPI buses, increasing the consumption of microcontroller I / O pins and potentially leading to inefficient resource utilization. Furthermore, the increased capacitive load associated with a large number of SPI devices can significantly reduce data transfer rates, impacting the overall system performance and efficiency, and consequently, the overall performance and efficiency of the vehicle.

[0036] The need for improved SPI communication is important for the efficient operation of vehicles, and therefore, it is desirable to provide a serial peripheral interface bus topology with multiplexed chip select addressing.

[0037] One or more embodiments address these and other drawbacks by introducing a circuit topology that enables efficient scaling of SPI communication in vehicles using multiple SPI devices. This topology utilizes a combination of digital multiplexer logic, decoder logic, and buffer logic to redistribute capacitive loads on the SPI bus signals. By employing a logic matrix addressing scheme, one or more embodiments allow the microcontroller to communicate with a large number of SPI devices using minimal I / O resources. This approach not only improves data transfer rates by reducing the capacitive load on each signal segment but also optimizes hardware design in terms of printed circuit board (PCB) area and bill of materials (BOM) cost. This scalable solution provides an effective and efficient alternative to traditional SPI methods, such as those using dedicated microcontrollers or complex programmable logic devices, thereby improving the overall efficiency and performance of SPI communication in automotive applications.

[0038] One or more embodiments provide a microcontroller unit that addresses a large number of SPI devices (e.g., 16 to 64 SPI devices) using a single standard SPI interface (4x inputs / outputs) and a minimum address control output. The SPI devices are addressed using column (COL_x) and row (ROW_x) control signals in a logic matrix, which can be extended to... Multiple decoders allow addressing of each SPI device without complex PCB signal routing. Multi-channel buffers copy and repair serial clock (SCLK) and MOSI data signals column-wise, up to [capacity missing]. Multiplexers allow multiple MISO data signals, up to [number missing]. This is a single input pin used to route data back to the MCU.

[0039] Figure 1A vehicle 100 with communication circuitry 102 is shown according to one or more embodiments. The vehicle 100 may be a car, truck, van, bus, motorcycle, boat, or any other type of vehicle. According to one embodiment, the vehicle 100 is a hybrid electric vehicle, such as a plug-in hybrid electric vehicle (PHEV) that is partially or fully powered by electricity. According to another embodiment, the vehicle 100 is an electric vehicle powered by electricity. A battery (not shown) is used to provide power to components of the vehicle 100, such as an electric motor (not shown), electrical components (not shown), etc., including combinations and / or multiple such components. According to one or more embodiments, the vehicle 100 includes an internal combustion engine (not shown) that provides electrical and / or mechanical energy for providing propulsion to the vehicle 100. According to one or more embodiments, the vehicle 100 is an autonomous or semi-autonomous vehicle. An autonomous vehicle is a vehicle with autonomous driving capabilities. A semi-autonomous vehicle is a vehicle with some autonomous features (e.g., self-parking, lane keeping, etc.) but lacks full autonomous control.

[0040] Communication circuitry 102 is located within vehicle 100 and is responsible for employing a logic matrix addressing scheme that enables the microcontroller to communicate with a large number of SPI devices using minimal I / O resources. To this end, the MCU uses a unique logical combination of "column" and "row" address signals to address any unique SPI device, and the MCU communicates with the addressed SPI device using a standard SPI interface (e.g., SCLK, MOSI, MISO, CS). Now refer to... Figure 2 Further features of the communication circuit 102 are described.

[0041] In particular, Figure 2 An illustration is provided according to one or more embodiments. Figure 1 The circuit diagram of the communication circuit 102 is shown. According to one or more embodiments, the communication circuit 102 is designed to facilitate efficient communication between the microcontroller unit (MCU) 202 and the SPI device matrix 204 of the SPI devices.

[0042] MCU 202 is electrically connected to SPI device matrix 204 via several components, including multiplexer (MUX) 206, buffer 208, and chip select (CS) decoder logic 210 configured and arranged as shown. MCU 202 transmits and receives signals via various lines: Master Output / Slave Input (MOSI) line 211, Serial Clock (SCLK) line 212, Master Input / Slave Output (MISO) line 213, and Chip Select (CS) line 214. MOSI line 211, SCLK line 212, MISO line 213, and CS line 214 together form an SPI interface for writing data to and / or reading data from SPI devices in SPI device matrix 204. According to one or more embodiments, the MOSI line 211, SCLK line 212, and MISO line 213 to / from MUX 206 and buffer 208 are arranged in columns. According to one or more embodiments, each row of SPI devices has a CS decoder logic 210 that routes a unique CS signal to each SPI device, each SPI device being addressable based on column and row address signals from MCU 202.

[0043] The SPI device matrix 204 is organized in a logic matrix, allowing the MCU 202 to communicate with a large number of SPI devices using minimal I / O resources. The MCU 202 addresses any unique SPI device in the SPI device matrix 204 using a unique logical combination of "column" and "row" address signals (e.g., via column select line 215 and row select line 216). The MCU 202 communicates with the addressed SPI devices in the SPI device matrix 204 using the SPI interface (e.g., SCLK line 212, MISO line 213, and CS line 214).

[0044] The MCU 202 also controls column select line 215 and row select line 216, which are used to address specific SPI devices within the SPI device matrix 204.

[0045] MUX 206 is responsible for multiplexing and re-driving MISO signals from the SPI device matrix 204 to the MCU 202, effectively managing the capacitive load and routing of these signals back to the MCU 202 via MISO line 213. According to one or more embodiments, MUX 206 utilizes digital multiplexer logic with address-selectable inputs and output strobes. The multiplexer output logic state is asserted based on the state of the addressed multiplexer input logic. MUX 206 re-drives the SPI bus MISO signals from multiple SPI devices, effectively distributing the total capacitive load of the SPI devices and routing them back to the MCU from a single multiplexer output.

[0046] The task of buffer 208 is to redrive the SCLK and MOSI signals from MCU 202 to the devices in SPI device matrix 204, distributing them to selected SPI devices via multiple outputs, as shown by SCLK line 217 and MOSI line 218. This distribution helps to distribute capacitive load and improve data transfer rate. According to one or more embodiments, buffer 208 utilizes a digital logic buffer with logic inputs driven from a common signal and multiple logic outputs. The logic state of the output matches the logic state of the input. Buffer 208 redrives the SPI bus SCLK signal (e.g., SCLK line 212) from the MCU and distributes it across the multiple outputs of the buffer (e.g., via SCLK line 217) to the SPI devices in SPI device matrix 204, thereby effectively distributing the total capacitive load of the SPI devices. According to one or more embodiments, buffer 208 redrives the SPI bus MOSI signal (e.g., MOSI line 211) from MCU 202 and distributes it across the multiple outputs of the buffer (e.g., via MOSI line 218) to the SPI devices in SPI device matrix 204, thereby effectively distributing the total capacitive load of the SPI devices.

[0047] CS decoder logic 210 provides a mechanism for selecting SPI devices in the SPI device matrix 204 as target devices from which to read data or to which to write data. CS decoder logic 210 decodes CS signals from MCU 202 and assigns them to the appropriate SPI devices within the SPI device matrix 204 via chip select line 220. CS decoder logic 210 ensures that the SPI devices as target devices are correctly addressed based on the column and row signals provided by MCU 202 via column select line 215 and row select line 216. According to one or more embodiments, CS decoder logic 210 utilizes digital decoder logic with address select inputs and output strobe control inputs. When a strobe is asserted, the addressed decoder output is asserted. CS decoder logic 210 re-drives the SPI bus CS signals (e.g., CS line 214) from MCU 202 and assigns them to the addressed SPI devices.

[0048] Decoding the row address signal into a CS decoder strobe is achieved through a decoder, discrete logic gates, or direct signal routing from the MCU 202. This combination enables hardware expansion utilizing this number of SPI devices. The hardware design of the communication circuit 102 can be optimized in terms of PCB area, BOM cost, and desired data transfer rate, with each signal segment having a low capacitive load, thus providing a scalable and efficient solution for SPI communication in automotive applications.

[0049] about Figures 3A-3E The features and functions of the components of the communication circuit 102 are further described.

[0050] In particular, Figures 3A-3E Together, they illustrate one or more embodiments. Figure 1 The circuit diagram of the communication circuit. Now describe it together. Figures 3A-3E .

[0051] Figure 3A A detailed view of a portion of the communication circuitry 102 is provided, highlighting the interaction between the MCU 202 and various components that facilitate SPI communication. These components include the MISO multiplexer 306, the SCLK buffer 308a, and the MOSI buffer 308b.

[0052] MCU 202 is depicted with several general purpose input / output (GPIO) lines for controlling column (COL_0, COL_1, COL_2) and row (ROW_0, ROW_1, ROW_2) address signals. These signals are used to select a specific SPI device within the SPI device matrix 204. SPI interface 302 (also referred to as the "SPI bus") is shown, consisting of Master Output / Slave Input (MOSI), Serial Clock (SCLK), Master Input / Slave Output (MISO), and Chip Select (CS) lines. SPI interface 302 facilitates data exchange (e.g., reading and writing data) between MCU 202 and the SPI devices of the SPI device matrix 204.

[0053] The MISO multiplexer 306, used as an example of MUX 206, is a multiplexer that manages MISO signals from multiple SPI devices, effectively reducing capacitive load and routing signals back to MCU 202. According to one or more embodiments, MISO multiplexer 306 is an 8:1 multiplexer, but in other embodiments it can be configured as other types of multiplexers. MISO multiplexer 306 is controlled by address inputs A0, A1, and A2, which determine the specific MISO signal to be routed.

[0054] The SCLK buffer 308a and MOSI buffer 308b are described. Figure 2Example of buffer 208. Each of SCLK buffer 308a and MOSI buffer 308b is configured as a 1:8 buffer according to one or more embodiments, but may be configured as other types of buffers in other embodiments. SCLK buffer 308a redrives the SCLK signal from MCU 202, distributing it across multiple outputs (Y0 to Y7), thereby distributing capacitive load and enhancing the data transfer rate to the SPI devices of SPI device matrix 204. Similarly, MOSI buffer 308b redrives the MOSI signal, distributing it across multiple outputs (Y0 to Y7) to ensure effective communication with the SPI devices of SPI device matrix 204. This configuration allows communication circuitry 102 to handle a large number of SPI devices while optimizing I / O resource usage and maintaining a high data transfer rate.

[0055] Ax (e.g., A0, A1, A2) represents address selection, Dx (e.g., D0, D1, D2, ..., D7) represents data input, Yx (e.g., Y1, Y2, Y3, ..., Y7) represents data output, and Gx (e.g., G0) represents output strobe active high. (For example, ) indicates that the output strobe is active low, GPO indicates general-purpose output, COL_x indicates the SPI device column address, ROW_x indicates the SPI device row address, and CS_xy indicates the SPI device chip selection at column "x" and row "y".

[0056] Figure 3B An SPI device matrix 204 is shown, illustrating the organization and interconnection of multiple SPI devices within the matrix. The SPI device matrix 204 is constructed in a logical grid, where each SPI device is represented by a block, such as SPI devices A0 320a, A1 320b, and A7 320c in the first column, SPI devices B0 321a, B1 321b, and B7 321c in the second column, and SPI devices H0 322a, H1 322b, and H7 322c in the last column. For simplicity, some SPI devices are omitted; however, it should be understood that in this embodiment, the SPI device matrix 204 supports 64 SPI devices. In other embodiments, a different number of SPI devices may be supported. Each SPI device is connected to a common SPI bus, including the SCLK, MOSI, MISO, and CS lines, as shown. These lines facilitate communication between the MCU 202 and the SPI devices 320a…322c.

[0057] A CS line (e.g., CS line 220) is uniquely assigned to each SPI device, allowing the MCU 202 to select and communicate with a specific SPI device within the SPI device matrix 204. SCLK, MOSI, and MISO lines are shared among the devices, supporting synchronous data transfer. This matrix configuration allows for efficient addressing and communication with a large number of SPI devices using minimal I / O resources from the MCU 202. This arrangement optimizes PCB area usage and reduces the overall capacitive load on the SPI bus, thereby improving data transfer rates and system performance. The logical arrangement of the SPI devices (e.g., SPI devices 320a…322c) in the SPI device matrix 204 provides a scalable solution for managing multiple devices in automotive and other high-capacity ECU applications.

[0058] Figure 3C , 3D And 3E presented Figure 2 Alternative embodiments of the chip-select decoder logic arrangement for the CS decoder logic 210 are shown. Each embodiment is capable of supporting a different number of SPI devices within the SPI device matrix 204. These figures illustrate various configurations of the CS decoder logic 210, demonstrating how the decoder can be adapted to accommodate different scales of SPI device integration. For example, Figure 3C The implementation supports up to 16 SPI devices using CS decoding for one or two rows. Figure 3D Supports up to 32 SPI devices using CS decoding for three to four rows, and Figure 3E It supports up to 64 SPI devices using CS decoding for rows five to eight. Each configuration employs a combination of digital logic to manage the distribution of chip select signals, ensuring that the MCU 202 can effectively address and communicate with SPI devices (e.g., SPI devices 320a…322c). The variations in these figures demonstrate the scalability and flexibility of the circuit design for communication circuitry 102, allowing for optimization based on the specific requirements of the application using communication circuitry 102.

[0059] exist Figure 3C The image depicts a first chip select decoder device 310a, characterized by two CS decoders: CS decoder 330a and CS decoder 330b. This configuration is designed to support a relatively small number of SPI devices (e.g., up to 16 SPI devices), wherein each CS decoder 330a, 330b is capable of processing a subset of the SPI devices. The CS decoders are located via... Figure 3A The column select line 215 receives the column address signal (e.g., Figure 3CThe signals are COL_0, COL_1, and COL_2 from the MCU 202 and the chip select signal (CS) from the MCU 202. These signals are used to generate an appropriate chip select output (e.g., Y[7:0]) to select the desired (e.g., target) SPI device. The output is then routed to the corresponding SPI device, thereby allowing the MCU 202 to select the desired SPI device and communicate with it.

[0060] Figure 3D A second chip select decoder arrangement 310b is shown, comprising four CS decoders (CS decoder 330a, CS decoder 330b, CS decoder 330c, and CS decoder 330d) and additional inversion logic 340. This arrangement is designed to accommodate a large number of SPI devices, with each CS decoder managing the addressing of a specific group of SPI devices. Inversion logic 340, including inverters 341a and 341b, manipulates row address signals (ROW_0, ROW_1) to ensure accurate decoding and selection of the SPI devices. CS decoders 330a-330d receive column address signals as shown and manipulated row address signals to generate the desired chip select output for the target SPI device.

[0061] exist Figure 3E The diagram shows a third chip select decoder arrangement 310c, characterized by eight CS decoders (CS decoder 330a, CS decoder 330b, CS decoder 330c, CS decoder 330d, CS decoder 330e, CS decoder 330f, CS decoder 330g, and CS decoder 330h) and a row address decoder 350. This arrangement is designed for a larger number of SPI devices than existing arrangements, with each CS decoder 330a-330h responsible for a specific subset of devices. The row address decoder 350 receives row address signals (ROW_0, ROW_1, ROW_2) and chip select signals (CS) from the MCU 202 and generates outputs (Y[7:0]) fed to the CS decoders 330a-330h, as shown. The CS decoders 330a-330h then use these outputs from the row address decoders 350, along with column address signals (COL_0, COL_1, COL_2), to generate appropriate chip select signals to select the target SPI device of the SPI device matrix 204. This arrangement provides a highly scalable solution for managing a large number of SPI devices within the SPI device matrix 204.

[0062] It should be understood that the chip selection decoder arrangement can be selected based on the number of SPI devices. According to one or more embodiments, combinations of chip selection decoder devices can be used and / or the chip selection decoder devices can be modified according to the number of SPI devices. For example, in the case of using 46 SPI devices, a third chip selection decoder device 310c can be used with a total of six CS decoders (e.g., CS decoders 330a-330f), where the remaining CS decoders (e.g., CS decoders 330g, 330h) are omitted. Other configurations and arrangements are possible in various embodiments.

[0063] Figure 4 A flowchart of a method 400 for a serial peripheral interface bus topology with multiplexed chip select addressing, according to one or more embodiments, is shown. Method 400 can be implemented using any suitable system or device. For example, method 400 and its steps can be used... Figure 1 , Figure 2 and Figures 3A-3E The method is implemented using communication circuits 102 (including combinations and / or multiple circuits thereof). Method 400 will now be described with reference to at least a portion of the foregoing figures, but is not limited thereto.

[0064] In operation 402, the method begins with the SPI bus in an idle state. During this state, the chip select (CS) signal is not asserted, and no SPI traffic occurs within the communication circuit 102. This ensures that the bus is inactive and ready for any new communication requests.

[0065] In Operation 404, it is determined whether a software request is pending, and whether the request is sent to an SPI device (e.g., ...). Figure 3B The SPI bus remains idle if no request is detected (operation 404 "No"). However, if a request is present (operation 404 "Yes"), method 400 proceeds to operation 406.

[0066] In operation 406, the microcontroller unit (e.g., MCU 202) drives the column (COL_x) select signal (e.g., column select line 215) and the row select signal (ROW_x) (e.g., row select line 216) to logic high or low, corresponding to the address of the specific SPI device to be accessed for reading or writing data. This operation enables the selection of the correct SPI device for communication with MCU 202.

[0067] In operation 408, it is determined whether the multiplexer (e.g., MUX 206, MISO multiplexer 306) and chip select decoder (e.g., chip select decoder 330a-33h) have successfully decoded the COL_x and ROW_x address signals. If decoding is unsuccessful (operation 408 "No"), method 400 returns to operation 406. If decoding is successful (operation 408 "Yes"), method 400 proceeds to operation 410.

[0068] In operation 410, MCU 202 communicates with the selected SPI device specified in operation 404 (e.g., Figure 3B The SPI device (A0 320a... SPI device H7 322c) performs an SPI transaction. During this transaction, the clock selection signal is asserted, and the MCU 202 and the SPI device (e.g., Figure 3B This operation involves exchanging data between one of the SPI devices A0 320a…SPI devices H7 322c. This operation involves writing and / or reading data specified by an initial software request (Operation 404).

[0069] In operation 412, it is determined whether the SPI transaction has been completed. If the transaction has not yet been completed (operation 412 "No"), data exchange continues at operation 410. Once the transaction is completed (operation 412 "Yes"), method 400 proceeds to operation 414.

[0070] In operation 414, the SPI bus transitions back to an idle state. This involves de-asserting the chip select signal and ensuring there is no SPI traffic, thereby effectively resetting the SPI bus for future communication requests.

[0071] It may also include additional processes, and it should be understood that, Figure 4 The processes described herein are illustrative, and other processes may be added, or existing processes may be removed, modified, or rearranged without departing from the scope of this disclosure. It should also be understood that... Figure 4 The process described herein can be implemented as programming instructions stored on a non-transitory computer-readable storage medium, which, when executed by a processor of a computing system, cause the processor to perform the process described herein.

[0072] Table 1 below shows a possible example of SPI device addressing:

[0073]

[0074] Table 1

[0075] Table 2 below shows a possible example of SPI device address mapping:

[0076]

[0077] Table 2

[0078] One or more embodiments offer significant technical benefits, particularly in the context of automotive applications. For example, one or more embodiments described herein provide an innovative circuit topology that enables efficient extension of SPI communication, allowing a microcontroller to address a large number of SPI devices with minimal I / O resources. This is achieved by using digital multiplexer logic, decoder logic, and buffer logic, which together redistribute the capacitive load on the SPI bus signals. By employing a logic matrix addressing scheme, one or more embodiments enhance data transfer rates by reducing the capacitive load on each signal segment. This not only optimizes hardware design in terms of PCB area and BOM cost but also provides a scalable and cost-effective solution compared to existing methods, such as those using dedicated microcontrollers or complex programmable logic devices.

[0079] In the context of vehicle 100, one or more embodiments improve the operation of vehicle 100 by facilitating more efficient and reliable communication between the microcontroller and peripheral devices. This is particularly beneficial for high-capacity ECUs that utilize communication with a large number of SPI devices. The ability to address up to 64 SPI devices using a single SPI interface and minimal I / O utilization of the MCU significantly reduces the consumption of microcontroller I / O pins. This efficient use of resources allows for the integration of more features and functions within the vehicle's electronic systems without compromising performance.

[0080] Furthermore, the reduced capacitive load on each signal segment enables faster signal rise and fall times, which in turn allows for higher SPI transmission rates. This improvement in data transmission speed is useful for real-time performance in certain automotive functions, such as engine control, transmission, and infotainment systems. By ensuring fast and synchronous data exchange, one or more embodiments enhance the overall efficiency and performance of vehicle systems, thereby contributing to improved functionality and user experience. In summary, the described embodiments provide a robust and scalable solution for managing SPI communication in automotive applications, offering technological advantages.

[0081] It should be understood that one or more embodiments described herein can be implemented in conjunction with any other type of computing environment now known or developed in the future.

[0082] The terms “a” and “an” do not indicate a limitation of quantity, but rather that at least one of the referenced items is present. Unless the context clearly indicates otherwise, the term “or” means “and / or”. Throughout the specification, the reference to “aspect” means that a particular element described in connection with that aspect (e.g., a feature, structure, step, or characteristic) is included in at least one aspect described herein, and may or may not be present in other aspects. Furthermore, it should be understood that the described elements may be combined in any suitable manner in the aspects.

[0083] When an element, such as a layer, film, region, or substrate, is referred to as being “on” another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly” on another element, there are no intermediate elements present.

[0084] Unless otherwise stated herein, all test standards are the most recent standards in force up to the date of filing of this application, or, if priority is claimed, the date of filing of the earliest priority application in which a test standard appears.

[0085] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0086] While the foregoing disclosure has been described with reference to exemplary embodiments, those skilled in the art will understand that various changes can be made and elements can be substituted with equivalents without departing from its scope. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of this disclosure without departing from the basic scope of this disclosure. Therefore, it is intended that this disclosure be limited to the specific embodiments disclosed, but will include all embodiments falling within its scope.

Claims

1. A method comprising, Determine whether a software request at the microcontroller unit (MCU) is pending, the software request being to read data from or write data to a Serial Peripheral Interface (SPI) device, the SPI device being selected from a plurality of SPI devices arranged in an SPI device matrix and electrically connected to the MCU; In response to determining that the software request is pending, the MCU drives the column select signal and the row select signal using the SPI device address associated with the SPI device; The column select signal and the row select signal are decoded by chip select decoder logic, wherein the chip select decoder logic is electrically connected to each of the plurality of SPI devices; and The MCU performs SPI transactions with SPI devices selected from the plurality of SPI devices, wherein the SPI transactions are either reading data from the SPI devices or writing data to one of the SPI devices.

2. The method according to claim 1, wherein the MCU and the plurality of SPI devices form an SPI bus.

3. The method of claim 2, wherein the SPI bus is idle before determining whether a software request at the MCU is pending.

4. The method according to claim 3, further comprising: Determine whether the SPI transaction is complete; and In response to determining that the SPI transaction is complete, the SPI bus is returned to the idle state.

5. The method according to claim 2, wherein the SPI bus further comprises a master output / slave input (MOSI) line, a serial clock (SCLK) line, a master input / slave output (MISO) line, and a chip select (CS) line.

6. The method of claim 5, wherein the MCU is electrically connected to the plurality of SPI devices at least via the chip select decoder logic.

7. The method of claim 6, wherein the MCU is further electrically connected to the plurality of SPI devices at least via a multiplexer and a buffer.

8. The method of claim 7, wherein the buffer comprises an SCLK buffer and a MOSI buffer.

9. The method of claim 7, wherein the multiplexer comprises an MISO multiplexer.

10. A vehicle, comprising, The communication circuit includes, Microcontroller unit (MCU); Multiplexer; buffer; Chip selection decoder logic; and A Serial Peripheral Interface (SPI) device matrix, comprising a plurality of SPI devices, each of which is electrically connected to the MCU via the multiplexer, the buffer, and the chip select decoder logic, and each of the plurality of SPI devices being selectively addressable by the MCU via the chip select decoder logic.

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