Bus address generation method, apparatus, and device

Abstract

This application provides a bus address generation method, apparatus, and device. The method includes: determining a processing data segment based on an input address; wherein the input address consists of a first lookup table address, the number of hops for inter-chip transmission, and a data offset, and the processing data segment consists of 20'h0, a second lookup table address, and the number of hops for inter-chip transmission; acquiring multiple segment information, effective bit count, and alignment parameters; wherein any segment information consists of start position information and length information; determining an extraction position in the processing data segment based on the start position information of each segment information, and extracting a continuous data segment corresponding to the length information starting from the extraction position; concatenating the continuous data segments to obtain a concatenated segment; and obtaining a bus address based on the data offset, the concatenated segment, the effective bit count, and the alignment parameters. The method of this application enables flexible and reconfigurable address generation, allowing the final bus address to cover a large address space with a limited table entry configuration, suitable for the broadcast characteristics of the bus.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, and device for generating bus addresses. Background Technology

[0002] As the core communication hub, the bus plays a crucial role in connecting various components such as processors, memory, and input / output devices. Its performance and flexibility directly determine its operating efficiency and scalability.

[0003] With the rapid development of information technology, the demand for data processing has exploded, and the types and quantities of components and the complexity of data interaction are constantly increasing, which puts forward higher requirements for bus address generation.

[0004] The existing rules for generating bus addresses are relatively simple, such as only transforming the high-order bits of the input address, or obtaining a one-to-one mapping by simply looking up a table.

[0005] Existing bus address generation methods lack flexibility, with relatively fixed input and output address relationships; furthermore, lookup tables can only be statically configured, making it impossible to modify address generation rules while the bus is in operation. Summary of the Invention

[0006] To address one of the aforementioned technical deficiencies, this application provides a bus address generation method, apparatus, and device.

[0007] The first aspect of this application provides a method for generating a bus address, the method comprising: The processing data segment is determined based on the input address; wherein, the input address consists of the first lookup table address, the number of hops for inter-chip transmission, and the data offset, and the processing data segment consists of 20'h0, the second lookup table address, and the number of hops for inter-chip transmission; 20'h0 is a 20-bit hexadecimal number with a value of 0; Multiple segment information, effective number of bits, and alignment parameters are obtained based on the first lookup table address; each segment information consists of start position information and length information. Based on the starting position information of each segment, the extraction position is determined in the processed data segment, and the continuous data segment corresponding to the length information is extracted from the extraction position. The consecutive data segments are spliced ​​together to obtain the spliced ​​segment; The bus address is obtained based on the data offset, splice segment, significant bits, and alignment parameters.

[0008] A second aspect of this application provides a bus address generation apparatus, the apparatus comprising: The determination module is used to determine the processing data segment based on the input address; wherein, the input address consists of a first lookup table address, the number of hops for inter-chip transmission, and a data offset, and the processing data segment consists of 20'h0, a second lookup table address, and the number of hops for inter-chip transmission; 20'h0 is a 20-bit hexadecimal number with a value of 0; The acquisition module is used to obtain multiple segment information, effective number of bits, and alignment parameters based on the first lookup table address; wherein, any segment information consists of start position information and length information; The extraction module is used to determine the extraction position in the processed data segment based on the starting position information of each segment information, and extract the continuous data segment corresponding to the length information starting from the extraction position; The splicing module is used to splice together consecutive data segments to obtain a spliced ​​segment; The generation module is used to obtain the bus address based on the data offset, splice segment, significant number of bits, and alignment parameters.

[0009] A third aspect of this application provides an electronic device, including a bus and a processor.

[0010] The address of the bus is generated by the method described in the first aspect above.

[0011] This application provides a bus address generation method, apparatus, and device. The method includes: determining a processing data segment based on an input address; obtaining multiple segment information, significant bit length, and alignment parameters based on a first lookup table address; determining an extraction position in the processing data segment based on the start position information of each segment information, and extracting a continuous data segment corresponding to the length information starting from the extraction position; concatenating the continuous data segments to obtain a concatenated segment; and obtaining the bus address based on the data offset, the concatenated segment, the significant bit length, and the alignment parameters. The method of this application enables flexible and reconfigurable address generation, allowing the final bus address to cover a large address space with a limited table entry configuration, suitable for the broadcast characteristics of the bus. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A flowchart illustrating a bus address generation method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a high-performance processor provided in an embodiment of this application; Figure 3 A schematic diagram of the architecture of a scalar processor provided for an embodiment of this application; Figure 4A schematic diagram of a synchronization unit provided in an embodiment of this application; Figure 5 A schematic diagram of the architecture of a vector processor provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a vector operation unit provided in an embodiment of this application; Figure 7 A schematic diagram of another vector processor architecture provided in an embodiment of this application; Figure 8 This is a schematic diagram of a bus address generation device provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0014] In the process of developing this application, the inventors discovered that existing bus address generation rules are relatively simple, such as only transforming the high-order bits of the input address or obtaining a one-to-one mapping simply by looking up a table. Existing bus address generation methods lack flexibility, the input and output address relationships are relatively fixed, and the lookup table can only be statically configured, making it impossible to modify the address generation rules while the bus is operating.

[0015] To address the aforementioned problems, this application provides a bus address generation method, apparatus, and device. The method includes: determining a processing data segment based on an input address; obtaining multiple segment information, significant bit length, and alignment parameters based on a first lookup table address; determining an extraction position within the processing data segment based on the start position information of each segment information, and extracting a continuous data segment corresponding to the length information starting from the extraction position; concatenating the continuous data segments to obtain a concatenated segment; and obtaining the bus address based on the data offset, the concatenated segment, the significant bit length, and the alignment parameters. This method enables flexible and reconfigurable address generation, allowing the final bus address to cover a large address space with a limited table entry configuration, suitable for the broadcast characteristics of the bus.

[0016] See Figure 1 This embodiment provides a bus address generation method, the implementation process of which is as follows: 101. Determine the data segment to be processed based on the input address.

[0017] The input address consists of the first lookup table address (lut_addr), the number of hops for inter-chip transmission (hop_cnt), and the data offset (offset). For example, the structure of the input address is {lut_addr, hop_cnt, offset}.

[0018] The first lookup table address (lut_addr), the number of hops for inter-chip transfer (hop_cnt), and the data offset (offset) in the input address are the inputs to the bus address generation method provided in this embodiment, and are processed as known parameters. How the first lookup table address (lut_addr), the number of hops for inter-chip transfer (hop_cnt), and the data offset (offset) are determined is irrelevant to the implementation of the bus address generation method provided in this embodiment, and therefore is not specifically limited thereto.

[0019] If the first lookup address (lut_addr) has a bit width of 13 bits, the hop count for inter-chip transmission has a bit width of 15 bits, the data offset has a bit width of 24 bits, then the input address can be 52 bits.

[0020] It should be noted that the bit width (such as 13 bits) involved in this embodiment and subsequent embodiments are just examples. The actual implementation shall be based on the actual situation, such as adjusting the bit width according to the algorithm requirements and the total number of chips in the Internet.

[0021] After obtaining the input address, the processing data segment (data_to_process) can be obtained through step 101.

[0022] The processing data segment (data_to_process) consists of 20'h0, the second lookup table address (new_lut_addr), and the number of hops for inter-chip transmission (hop_cnt). For example, the structure of the processing data segment (data_to_process) is {20'h0, new_lut_addr, hop_cnt}.

[0023] In the data_to_process segment, 20'h0 is a 20-bit hexadecimal number with a value of 0. This notation is the syntax of hardware description languages ​​(such as Verilog).

[0024] The second lookup address (new_lut_addr) in the data segment (data_to_process) is obtained by looking up a table, such as by using the first lookup address (lut_addr) as an index to look up a LUT (look up table).

[0025] The number of hops (hop_cnt) for inter-chip transfers in the data segment (data_to_process) is the same as the number of hops (hop_cnt) for inter-chip transfers in the input address.

[0026] If the second lookup table address (new_lut_addr) is 13 bits, the number of hops in the inter-chip transfer (hop_cnt) is 15 bits, and the 20 bits of 20'h0 are added, then the data segment (data_to_process) can be 48 bits.

[0027] It should be noted that both the first lookup table address (lut_addr) and the second lookup table address (new_lut_addr) are lookup table addresses, each with a bit width of 13 bits. The first and second bits are used only to represent different lookup table addresses. The first lookup table address (lut_addr) represents the lookup table address in the input address, which serves as known data in the bus address generation method provided in this embodiment. The second lookup table address (new_lut_addr) represents the lookup table address in the processed data segment, which is obtained through a table lookup.

[0028] The first lookup address (lut_addr) is used to obtain the concatenated segment later, and the second lookup address (new_lut_addr) can be considered as part of the high-order address translation.

[0029] The second lookup address (new_lut_addr) is part of the data segment (data_to_process) and carries some address translation functions.

[0030] 102. Obtain multiple segment information, significant number of bits, and alignment parameters based on the first lookup table address.

[0031] Each segment information (segement_info) consists of a start position information and a length information.

[0032] If the bit width of any segment information (segement_info) is M bits, then the start position information is located in the lower S bits of any segment information, and the length information is located in the higher (MS) bits of any segment information.

[0033] Where M and S are positive integers, and M > S.

[0034] In practical implementation, S≥ L is the bit width of the data-to-process segment. S should be sufficient to cover all bits of the data-to-process segment.

[0035] In practice, the multiple segment information (segement_info), significant digits (oe_len), and alignment parameter (extend) in step 102 can be obtained by looking up a table, such as by looking up a LUT (look up table).

[0036] For example, a table (such as a LUT table) records the correspondence between an index and multiple (such as N) segment information (segement_info), significant bit length (oe_len), and alignment parameter (extend). In step 102, the first lookup address (lut_addr) in the input address is used as an index to search for the N segment information (segement_info), significant bit length (oe_len), and alignment parameter (extend) corresponding to the first lookup address (lut_addr) in the table (such as a LUT table).

[0037] If the obtained N segment information (segment_info) are denoted as segment_info 0 segment_info 1 ..., segment_info (N-1) Each segment of information has a bit width of Mbit.

[0038] Each segment information (segement_info) is divided into two parts: low S bits and high (MS) bits.

[0039] For any segment information (segement_info), the start position information is located in the lower S bits of any segment information, and the length information is located in the higher (MS) bits of any segment information.

[0040] Use any segment information (segement_info) as segement_info n For example, segment_info n [S-1:0] is segment_info n The 0th to S-1st positions are segment_info n The lower S bits represent the start position information; segment_info n [M-1:S] indicates that the length information is segment_info n The S to M-1th positions are segement_info n The high (MS) bits represent length information.

[0041] Where n is the sequence number of the segment information (segement_info), 0≤n≤N-1.

[0042] If the length of the data segment (data_to_process) is 48 bits, then S should satisfy S≥ Its value should be large enough to cover all bits of the data segment (data_to_process). Provided that S satisfies the above constraints, the larger the value of M, the greater the upper limit of the bit width of a single consecutive data segment retrieved.

[0043] Additionally, the effective number of bits (oe_len) is the offset effective length, representing the effective number of bits in the data offset contained within the final generated address. The effective number of bits (oe_len) satisfies the following relationship: 0 ≤ oe_len ≤ W(offset), where W(offset) is the bit width of the data offset.

[0044] The alignment parameter (extend) indicates whether the output address has been modified to be aligned to twice the width of the input data. The alignment parameter (extend) is a 1-bit control signal; for example, extend=1 indicates that the output address is aligned to 1024 bits.

[0045] 103. Based on the starting position information of each segment, determine the extraction position in the processed data segment, and extract the continuous data segment corresponding to the length information starting from the extraction position.

[0046] For example, N segment information (segment_info) are segment_info 0~(N-1) Let n represent the sequence number of the segment information (segement_info), 0≤n≤N-1. Then in step 103, for any segment information (segement_info), such as segment_info... n According to segment_info n The starting position, such as Bn, is obtained from the lower S bits, based on segment_info. n If the length of the high (MS) bits is obtained, such as Cn, then the Bn-th bit is determined in the processing data segment (data_to_process) obtained in step 101, and a continuous data segment Dn of Cn bits is extracted from the high bits starting from the Bn-th bit.

[0047] 104. The consecutive data segments are spliced ​​together to obtain the spliced ​​segment.

[0048] After obtaining N consecutive data segments corresponding to N segment information (segement_info) in step 103, the consecutive data segments are concatenated from largest to smallest according to the sequence number of the segment information (segement_info) to obtain the concatenated segment (addr_origin).

[0049] For example, N segment information (segement_info) are segement_info 0 segement_info 1 , ..., segment_info n , ..., segment_info N-1 The corresponding continuous data segments are D0, D1, ..., Dn, ..., DN-1, and the spliced ​​segment (addr_origin) is {DN-1, ..., Dn, ..., D1, D0}.

[0050] In step 104, based on the starting position and length information of the N segment information (segement_info) obtained in step 103, N consecutive data segments are extracted from the processed data segment (data_to_process), and the N consecutive data segments are concatenated in descending order of their sequence number n to obtain the concatenated segment (addr_origin).

[0051] 105. The bus address is obtained based on the data offset, splice segment, effective bits, and alignment parameters.

[0052] For example, the bus address is {concatenation segment [bus address bit width - 4 - effective number of bits - 1: 0], {data offset [effective number of bits - 1: 3], (!extend&data offset[2]), x'h0}, y'h0}.

[0053] Where, ! is the negation operator, & is the bitwise AND operator, the concatenation segment [bus address bit width - 4 - effective bits - 1: 0] is the 0th bit of the concatenation segment to the 4th bit width - 1 - effective bits of the bus address, the data offset [effective bits - 1: 3] is the 3rd bit of the data offset to the 1st bit width - 1, and the data offset [2] is the 2nd bit of the data offset; x and y are both bit numbers, x'h0 is a hexadecimal number with a bit width of x bits and a value of 0; y'h0 is a hexadecimal number with a bit width of y bits and a value of 0.

[0054] In this embodiment and subsequent embodiments, the variables are defined with the most significant byte first and the least significant byte last. For example, the variables for bus addresses are all defined with the most significant byte first and the least significant byte last.

[0055] x and y determine the number of low-order zeros. The number of low-order zeros is related to the bus data width. For example, taking an input offset aligned to 128 bits, 2 4 *8=128, therefore y=4, and the output address is aligned to 512 bits, 512 / 128=4=2 2 Therefore, x=2, that is, x=2, y=4, so the bus address is {segment[bus address bit width-4-effective number of bits-1:0], {data offset[effective number of bits-1:3], (!extend&data offset[2]), 2'h0}, 4'h0}.

[0056] Wherein, 2'h0 is a 2-bit hexadecimal number with a value of 0; 4'h0 is a 4-bit hexadecimal number with a value of 0.

[0057] The following example uses x=2 and y=4. The data offset is the input address in step 101, such as 24 bits.

[0058] The splicing segment (addr_origin) is obtained in step 104, the effective number of bits (oe_len) and the alignment parameter (extend) are obtained in step 102. If the bit width of the bus address is A, then the bus address output_addr is {addr_origin[A-4-oe_len-1:0], {offset[oe_len-1:3], (!extend&offset[2]), 2'h0}, 4'h0}.

[0059] addr_origin[A-4-oe_len-1:0] represents the 0th to the A-4-oe_len-1th bits of the concatenation segment (addr_origin), which is a total of (A-4-oe_len) bits.

[0060] offset[oe_len-1:3] represents the 3rd to oe_len-1th bits of the data offset, totaling (oe_len-3) bits.

[0061] offset[2] represents the second bit of the data offset, which is 1 bit.

[0062] !extend&offset[2] means that the alignment parameter (extend) is inverted and then a bitwise AND operation is performed with offset[2]. !extend&offset[2] is 1 bit.

[0063] {offset[oe_len-1:3],(!extend&offset[2]) ,2'h0} is formed by concatenating offset[oe_len-1:3],(!extend&offset[2]) ,2'h0, and its bit width is (oe_len-3)+1+2=oe_len bit.

[0064] The output_addr is formed by concatenating addr_origin[A-4-oe_len-1:0], {offset[oe_len-1:3], (!extend&offset[2]), 2'h0}, and 4'h0. Therefore, the bit width of the bus address is (A-4-oe_len) + (oe_len) + 4 = A bit.

[0065] In this way, the bus address output_addr can be aligned to bit A.

[0066] The bit width of the bus address (e.g., A) is related to the total address space of the system. It can address all address spaces. For example, if the bit width of the bus address (e.g., A) is 32 bits, or 512 bits, or 1024 bits, it can be obtained through step 105.

[0067] In this way, the bus address (output_addr) output by the bus address generation method provided in this embodiment will be aligned.

[0068] The bus address generation method provided in this embodiment realizes the conversion from the input address to the high-order bits of the output address. The conversion relationship can be achieved through software configuration of the index and the correspondence between multiple segment information (segment_info), effective bit length (oe_len), and alignment parameter (extend). The converted address is composed of a concatenated segment (addr_origin) and a data offset (offset). The segment information (segment_info) allows for flexible variation in the high-order bits of the output bus address (output_addr), the effective bit length (oe_len) specifies the effective bit length of the data offset (offset) from the input address in the low-order bits of the output bus address (output_addr), and the alignment parameter (extend) controls the address alignment.

[0069] The correspondence between the index and multiple segment information (segement_info), effective number of bits (oe_len), and alignment parameter (extend) can be implemented based on RAM. The RAM read / write interface supports arbitration, and the default address generation logic has priority in reading. The software configuration requests to insert the address generation logic into RAM after a read, ensuring that the correspondence between the index and multiple segment information (segement_info), effective number of bits (oe_len), and alignment parameter (extend) is updated in real time without affecting the read result of the address generation logic.

[0070] It should be noted that the bus involved in this embodiment and subsequent embodiments can be an existing bus or a custom bus. For example, a custom bus that includes information such as data, addr, mask (marker, such as marking which bytes in data are valid), extend, and burst (burst type, such as indicating whether this transmission is a burst transmission and burst mode (such as increment, cycle, etc.)). This custom bus can use valid (issued by the master device) / ready (issued by the slave device) handshake, supports broadcast and burst operations, and has the characteristics of high efficiency, large bandwidth and good scalability.

[0071] The bus address generation method provided in this embodiment can realize flexible and reconfigurable address generation in the bus, improving the flexibility and reconfigurability of bus addresses.

[0072] The bus address generation method provided in this embodiment can enable the output address to cover a large address space with a limited table entry configuration, which is suitable for the broadcast characteristics of the bus.

[0073] The bus address generation method provided in this embodiment transforms the input address using multiple segmentation information, significant bit length, and alignment parameters to generate the address corresponding to each frame of data, making the address of each frame of data software controllable. The segmentation information, significant bit length, and alignment parameters can also be modified in real time by software to achieve reconfigurability of the output bus address.

[0074] The bus address generation method provided in this embodiment can be applied to the generation of bus output address mapping in data diffusion and broadcasting scenarios in scientific computing (Molecular Dynamics simulation).

[0075] In a practical implementation, the input address in step 101 can be sent by a high-performance processor. This high-performance processor includes scalar processors and vector processors.

[0076] The connection between scalar processors and vector processors can be as follows: Figure 2 As shown.

[0077] In this architecture, scalar processors and vector processors share data storage. However, vector processors can only access the data storage and are executed solely by scalar processors.

[0078] A connection is established between scalar processors and vector processors. For example, scalar processors and vector processors can be connected via a dedicated instruction channel.

[0079] In addition, a high-performance processor may include two registers: one for the scalar processor and the other for the vector processor. The vector processor can read and write its corresponding register, while the scalar processor can read and write both its corresponding register and the register corresponding to the vector processor.

[0080] Scalar processors can read and write the registers of vector processors.

[0081] The scalar processor establishes a connection with global memory.

[0082] (a) Scalar Processor Scalar processors can provide Figure 3 The scalar processor shown includes: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0083] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0084] 1. Instruction Fetch Unit The instruction fetch unit is used to fetch and dispatch instructions.

[0085] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0086] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetching. It also receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially searches for one or more instructions from the qualified instructions, performs decoding and related checks, and dispatches the qualified instructions in sequence. At most, it dispatches one program control unit instruction and one synchronization unit instruction at a time. In addition, it can dispatch one or more scalar arithmetic unit instructions and one or more memory access unit instructions at a time.

[0087] 2. Register renaming unit The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0088] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to the arithmetic reserved stack unit, and stores them in one or more of the following: the program control unit, and the synchronization unit.

[0089] For example, the register renaming unit in a scalar processor is used to receive instructions dispatched by the instruction fetch unit and rename registers and special vector registers, decode instruction conditions, generate pipeline congestion signals, and simultaneously receive data from execution units (such as scalar arithmetic units, memory access units, program control units, and synchronization units) to write back registers, special vector registers, condition registers, and status flag registers and write them back to the corresponding registers.

[0090] Scalar processors support out-of-order write-back, resulting in high execution efficiency. They also distribute instructions to the arithmetic stack, storage stack, program control unit, or synchronization unit.

[0091] The register renaming unit bandwidth can be 6 bits, during which multiple (e.g., 4) input instructions can be valid at the same time.

[0092] There can be multiple condition registers, which are located in the register renaming unit.

[0093] The instructions for the scalar arithmetic unit and memory access unit support reading and writing condition registers.

[0094] The instructions for the synchronization unit support reading the condition register.

[0095] The program control unit's jump and function call instructions support reading the condition register.

[0096] When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

[0097] In other words, the condition register is not renamed; when a read / write request occurs, a dispatch blocking mechanism is triggered to wait. The conditions register read / write rules are as follows: Reading rules: (1) All instructions in the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0098] (2) The scalar arithmetic unit also supports read condition register instruction operations.

[0099] (3) The jump and function call instructions of the program control unit support reading condition register operations.

[0100] Write the rules: (1) The scalar arithmetic unit supports write condition register instructions.

[0101] (2) Scalar arithmetic unit logic instructions and comparison instructions support the option to write to the condition register.

[0102] When a previously issued instruction to write to the condition register has not yet finished executing, and another instruction to read or write to the same condition register enters, the pipeline becomes congested, generating a condition execution block signal, and waits for the previous condition register to finish writing.

[0103] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0104] Each of the following physical registers can be one of the following: scalar physical register, vector physical register, condition register, or flag register.

[0105] Any logic register can be one of the following: scalar logic register or vector logic register.

[0106] For example, a register renaming unit contains one or more physical registers, such as multiple 512-bit special vector registers, multiple condition registers, and a status flag register.

[0107] Among them, the special vector register is renamed, while the condition register and status flag register are not renamed.

[0108] There are multiple logic registers, such as scalar logic registers and multiple vector logic registers.

[0109] In addition, the mapping relationship between logical registers and physical registers is maintained by a register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by a special vector register mapping table.

[0110] 1) Register Map Table Initially, all entries in the register map table corresponding to logical register indices have a mapped physical register value of 0. When an instruction is executed, or when an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries in the register map table corresponding to the allocated logical register indices is updated to the identifier of the relevant physical register.

[0111] For example, the register map table, with a depth of 32 bits and a width of 6 bits, stores the mapping relationship between all logical registers and all physical registers. Initially, the register map table is invalid, and all entries mapping physical registers are 0. When a physical register is allocated to a logical register, the entry in the register map table corresponding to the logical register index is changed to the ID of that physical register.

[0112] It should be noted that the register map table is only updated when an instruction is actually executed. If the conditional execution instruction is not executed, the register map table will not be updated. In addition, the register map table will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register map table to ensure that the interrupt can return normally.

[0113] 2) Special Vector Register Mapping Table Initially, the mapped vector physical registers for all entries corresponding to vector logical register indices in the special vector register map are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logical register indices in the special vector register map is updated to the identifier of the relevant vector physical register.

[0114] For example, the special vector register map table, with a depth of 4 bits and a width of 3 bits, stores the mapping relationship between all vector logic registers and all vector physical registers. Initially, the special vector register map table is invalid, and all entries mapping to vector physical registers are 0. When a vector physical register is allocated to a vector logic register, the entry in the special vector register map table corresponding to the vector logic register index is changed to the ID of that vector physical register.

[0115] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0116] 3. Operations retain stack units The operation-reserved stack unit is the issue queue of scalar operation units.

[0117] The arithmetic stack is used to receive instructions, dispatch and rename information from the register renaming unit and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution.

[0118] The stack space is reserved for operations and is also used to decode input instructions and store instruction type information.

[0119] In other words, the arithmetic reserve stack is the dispatch queue of the scalar arithmetic unit. The arithmetic reserve stack receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions onto the scalar arithmetic unit for execution. The arithmetic reserve stack decodes the input instructions and stores the instruction type information.

[0120] In practice, the depth of the operation reserve stack can be flexibly adjusted, such as a depth of 8. Multiple scalar operation units share one operation reserve stack unit.

[0121] The rules for issuing and receiving instructions that reserve stack space are as follows: (1) The output of the register renaming unit enters the operation reserve stack unit.

[0122] (2) When there is any free scalar arithmetic unit, it will fetch instructions and operands from the arithmetic reserve stack and execute them.

[0123] (3) The principle of fetching instructions from the operation reserved stack is to fetch executable instructions that can be sent from the operation reserved stack in the order from front to back.

[0124] (4) Whether it is possible to send a value based on the values ​​of all source registers or special vector registers or condition registers and status flag registers is ready to be determined.

[0125] (5) If there are multiple instructions that can be sent, send the oldest instruction first according to the order of instructions.

[0126] (6) If any scalar arithmetic unit is blocked, it can no longer receive new instructions.

[0127] (7) If the instruction previously sent to any scalar arithmetic unit was a division instruction, a new division instruction can only be sent to it after the division result is calculated and the calculation completion En signal is returned.

[0128] 4. Store and retain stack units The storage-reserved stack unit is the issue queue for memory access units.

[0129] The storage reserve stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0130] The storage reserve stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and to save the read address operand.

[0131] The register renaming unit is also used to calculate the address after the instruction has obtained the address, decode the address, and save the decoded information.

[0132] The register renaming unit is also used to detect when the existence source register of any instruction is ready and the address decoding is complete, and then issue it to the memory access unit for execution.

[0133] In practice, the depth of the memory reservation stack unit can be flexibly adjusted, such as 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the issue queue for memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit obtains the address, it can calculate the address and decode the address, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready in the memory reservation stack unit and the address decoding is complete, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checks, address comparison checks, and address forward checks.

[0134] The rules for storing and reserving stack cells for sending and receiving instructions are as follows: (1) The output of the register renaming unit enters the memory retention stack unit.

[0135] (2) Once the source operand for the calculation address is ready, calculate the memory access address and store it in the memory reservation stack.

[0136] (3) Address-independent instructions: can be out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions can all be sent out of order. Write instructions after write instructions need to be ordered (cannot be sent to different memory access units at the same time). Even if the address-independent write instructions are written after write instructions, the order still needs to be maintained.

[0137] (4) Address-related instructions: The order of reading instructions followed by writing instructions, writing instructions followed by reading instructions, writing instructions followed by writing instructions, and reading instructions followed by reading instructions must be guaranteed.

[0138] (5) When addresses are unrelated but are located in the same memory space as all instructions that have not been successfully sent (i.e. instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level), they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0139] (6) Only one memory access instruction located in the same memory space but with unrelated addresses can be sent at the same time. Two or more memory access instructions cannot be sent at the same time.

[0140] (7) Address correlation judgment principle: whether addresses are related is: if they are located in different storage spaces, they are not related; if they are located in the same storage space, the address correlation is judged based on the data granularity.

[0141] 5. Scalar Operation Unit In a practical implementation, there can be one or more scalar operation units.

[0142] For example, a scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0143] The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform operations on the data based on the instructions, and write the operation result back to the register renaming unit.

[0144] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the arithmetic stack, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0145] The following are some example instructions. In actual implementation, the instructions are not limited to these, nor is it limited to including all of them.

[0146] Instructions at execution level 1 include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point max / min instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction instructions, and Rounding instructions.

[0147] Instructions with an execution level of three include: fixed-point multiplication instructions, fixed-to-floating-point conversion instructions, bit filtering instructions, count instructions, and floating-point addition and subtraction instructions.

[0148] Instructions that support bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0149] The execution cycle of a division instruction is indeterminate and depends on the data of the divisor and dividend. Upon completion, the instruction generates a DivEn instruction, indicating its completion and outputting the result to the register file. No new division instructions can be input during the execution of a division instruction, but other scalar computation unit instructions can be input. The output result of the division is multiplexed with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar computation unit instructions, the division outputs its result and simultaneously outputs the DivEn flag. This DivEn flag is output to the arithmetic reserve stack, indicating that Div instructions can continue to be output to the current scalar computation unit. 6. Memory access unit In a practical implementation, there can be one or more memory access units.

[0150] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0151] The memory access unit is used to receive instructions, data, and register information sent by the memory-reserved stack unit, and to read and write the data based on the instructions and register information.

[0152] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0153] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0154] 7. Program Control Unit In practice, there is only one program control unit.

[0155] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0156] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0157] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0158] 8. Synchronization Unit In practice, there is only one synchronization unit.

[0159] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0160] like Figure 4 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0161] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0162] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0163] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0164] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Output) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0165] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate execution-level signals affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0166] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit): The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0167] The query vector processor execution status function supports option B.

[0168] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. Reading / writing the FIFO will wait until success, or the result of reading / writing the FIFO will be written back to the register whether it is successful or not.

[0169] Write register file stack functionality, including special vector register write or register write.

[0170] The function allows reading and writing scalar registers, including reading and writing immediate indexes or register indexes.

[0171] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0172] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0173] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full, and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0174] 9. Production line control unit The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0175] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0176] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0177] In addition, scalar processors can also perform conditional execution decoding in practical applications. For example, when performing conditional execution decoding, a scalar processor checks the preset bits of the instruction to determine the execution condition. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. Here, a null instruction represents an empty instruction or an invalid instruction.

[0178] If a read / write operation is active in the condition register, pipeline blocking is triggered, waiting for the condition register write operation to complete before the read operation can proceed. There is no bypass for condition register reads and writes.

[0179] Taking two condition registers, namely condition register 0 and condition register 1, with the preset bits [29:28] as an example, when the scalar processor performs conditional execution decoding, it judges the execution conditions of the input instruction based on the [29:28] bits of the instruction set encoding. If the conditions are met, a valid instruction is output; otherwise, a null instruction is output.

[0180] In this instruction, bits [29:28] being 00 indicates that condition register 0 is 1 and the instruction is executed; bits [29:28] being 01 indicates that condition register 1 is 1 and the instruction is executed; bits [29:28] being 10 indicates that condition register 0 is 0 and the instruction is executed without conditions; and bits [29:28] being 11 indicates that the instruction is executed without conditions. If the conditions are not met, the instruction is invalid and an empty instruction is output.

[0181] In other words, if bits 29 and 28 of the instruction are 00 (i.e., bits [29:28] are 00), it means that the instruction will be executed when the condition register 0 is 1 (i.e., when the condition register 0 == 1 is met, the instruction is a valid instruction and a valid instruction will be output), otherwise it will not be executed (i.e., the condition is not met and an empty instruction will be output).

[0182] If bits 29 and 28 of the instruction are 01 (i.e., bits [29:28] are 01), it means that the instruction will be executed when condition register 1 is 1 (i.e., when the condition condition 1 == 1 is met, the instruction is a valid instruction and a valid instruction will be output), otherwise it will not be executed (i.e., the condition is not met and an empty instruction will be output).

[0183] Bits 29 and 28 of the instruction are 10 (i.e., bits [29:28] are 10), indicating that the instruction is executed when the condition register is 0. Here, "condition register 0" means to invert, that is, when condition register 0 is 1, the inverted value is 0, and the instruction is not executed; when condition register 0 is 0, the inverted value is 1, and the instruction is executed (i.e., when the condition 0 == 0 is met, the instruction is valid and a valid instruction is output), otherwise the instruction is not executed (i.e., the condition is not met, and a null instruction is output).

[0184] Bits 29 and 28 of the instruction are 11 (i.e., bits [29:28] are 11), indicating unconditional execution (i.e., the condition is always met, the instruction is a valid instruction, and a valid instruction is output).

[0185] If there is a read / write dependency in the condition register, pipeline blocking is triggered, and the read operation is performed only after the condition register has been written. There is no bypass for condition register read / write operations.

[0186] This scalar processor achieves synchronization between the scalar processor and the vector processor through a synchronization unit, thereby enabling efficient instruction execution.

[0187] (ii) Vector Processor See Figure 5 The vector processor includes: a vector program control unit, multiple functional units, a register file stack, and scalar registers.

[0188] In addition, the vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0189] 1. Vector Program Control Unit Vector program control unit, used for instruction fetching and instruction issuing.

[0190] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0191] The vector program control unit is also used to control instruction jumps.

[0192] The vector program control unit has scalar computation capabilities.

[0193] The vector program control unit interacts with the scalar register.

[0194] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0195] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0196] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0197] 2. Functional Units Functional units are used to perform functional processing according to instructions.

[0198] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0199] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0200] 1) Vector operation unit Any vector operation unit is used to perform vector operations according to instructions.

[0201] like Figure 6 As shown, any vector operation unit includes: a floating-point multiply-add subunit, a floating-point multiply-accumulate subunit, a floating-point arithmetic subunit, a tensor multiplication subunit, and an intermediate result register.

[0202] The floating-point multiply-accumulate subunit and the floating-point arithmetic subunit share one issue slot. Therefore, a maximum of 8 instructions from the vector operation unit can be issued per cycle.

[0203] The floating-point multiplication-accumulation subunit and the tensor multiplication subunit share a single launch slot.

[0204] The floating-point multiply-accumulate subunit is a functional unit that executes instructions related to floating-point multiply-accumulate operations. For example, instructions related to floating-point multiply-accumulate operations include integer and floating-point vector multiplication and accumulation, multiplication, addition, tensor calculation, etc.

[0205] Each vector operation unit has its own intermediate result register.

[0206] One floating-point multiply-accumulate subunit, one floating-point multiply-accumulate subunit, one tensor multiplication subunit, and one floating-point arithmetic subunit share an intermediate result register.

[0207] (1) Floating-point multiply-accumulate and floating-point multiply-accumulate subunits, which can perform integer and floating-point vector multiplication, multiply-accumulate and other operations. Supported types include, but are not limited to, int32, fp32, and fp64.

[0208] (2) The floating-point arithmetic subunit can perform integer and floating-point vector arithmetic operations, such as comparison, addition, subtraction, bitwise operations, etc. Supported types include, but are not limited to, int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, fp64.

[0209] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate and other operations. Supported types include, but are not limited to, int8, bf16, fp16 and tf32.

[0210] 2) Vector interleaving unit Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0211] The vector interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point and floating-point calculations. It also supports numerous customized instructions, including table lookup, horizontal calculation, sparse matrix calculation, precision conversion, and FIFO (First Input First Output) functions. It executes instructions such as data broadcasting, extraction, and internal interleaving.

[0212] Each vector interleaving unit has a set of private vector registers; therefore, the private vector registers of each vector interleaving unit correspond one-to-one with the vector interleaving units.

[0213] The vector interleaving unit includes: a decoder for the vector interleaving unit, multiple execution modules, and a selector.

[0214] The private vector register of a vector interleaving unit is shared by multiple vector interleaving units. The private vector register of a vector access unit is shared by multiple vector access units.

[0215] The decoder of the vector interleaving unit decodes the instructions generated by the vector program control unit to obtain the execution module identifier. The instructions are then sent to the execution module corresponding to the execution module identifier.

[0216] The execution module is used to execute instructions based on the execution module identifier.

[0217] The selector is used to select the execution result of the module and output the selected execution result.

[0218] 3) Vector Access Unit Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0219] The vector access unit is the memory access unit within the vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0220] The read / write instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and accumulation mode.

[0221] It supports multiple parameter configurations, with a maximum read / write instruction data width of up to 1024 bits. It executes instructions such as address calculation, load / store, etc.

[0222] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0223] 3. Register file stack The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0224] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0225] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data in the register file stack.

[0226] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0227] Taking other processing processors as examples, such as scalar processors, the synchronization unit of a scalar processor can write data to the register file, and the register file can also receive status information from the synchronization unit of the scalar processor to query whether the data has been written.

[0228] The depth of the register file heap is configurable.

[0229] Figure 7 A schematic diagram of a vector processor is shown, comprising four vector operation units, four vector interleaving units, and four vector access units.

[0230] When there are multiple execution modules in a vector interleaving unit, how should the vector registers be configured to achieve both iterative computation within a single unit and rapid transfer of computation results between different units before proceeding to the next step, resulting in good performance and flexibility? This requires both shared private vector registers for relatively simple tasks and registers corresponding one-to-one with each vector interleaving unit for more complex tasks. For example, if there are multiple execution modules in the interleaving unit and multiple output results are selected, multiple vector registers are needed in coordination.

[0231] When there are multiple vector access units, since the functions of the vector access units are relatively simple, it is sufficient to set a common private vector register, thus saving hardware resources.

[0232] The vector processor provided in this embodiment supports the VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0233] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0234] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0235] Other processing units perform read or write operations on the vector register.

[0236] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0237] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0238] This high-performance processor achieves synchronization between the scalar processor and the vector processor through a synchronization unit, thereby enabling efficient instruction execution.

[0239] This embodiment provides a bus address generation method. The method involves: determining the data segment to be processed based on the input address; obtaining multiple segment information, significant bit length, and alignment parameters based on a first lookup table address; determining the extraction position in the data segment to be processed based on the starting position information of each segment; extracting continuous data segments corresponding to the length information starting from the extraction position; concatenating the continuous data segments to obtain a concatenated segment; and obtaining the bus address based on the data offset, the concatenated segment, the significant bit length, and the alignment parameters. This method enables flexible and reconfigurable address generation, allowing the final bus address to cover a large address space with a limited table entry configuration, suitable for the broadcast characteristics of the bus.

[0240] Based on the same inventive concept as the above method, this embodiment provides a bus address generation device, see [link to relevant documentation]. Figure 8 The device includes: The determination module 801 is used to determine the processing data segment based on the input address. The input address consists of a first lookup table address, the number of hops for inter-chip transmission, and a data offset. The processing data segment consists of 20'h0, a second lookup table address, and the number of hops for inter-chip transmission. 20'h0 is a 20-bit hexadecimal number with a value of 0.

[0241] The acquisition module 802 is used to obtain multiple segment information, significant number of bits, and alignment parameters based on the first lookup table address. Each segment information consists of start position information and length information.

[0242] The extraction module 803 is used to determine the extraction position in the processed data segment based on the starting position information of each segment information, and extract the continuous data segment corresponding to the length information starting from the extraction position.

[0243] The splicing module 804 is used to splice together consecutive data segments to obtain a spliced ​​segment.

[0244] The generation module 805 is used to obtain the bus address based on the data offset, splice segment, significant number of bits and alignment parameters.

[0245] If the bit width of any segment information is M bits, then the start position information is located in the lower S bits of any segment information, and the length information is located in the higher (MS) bits of any segment information.

[0246] Where M and S are positive integers, and M > S.

[0247] Where, S≥ .

[0248] Where L is the bit width of the processed data segment.

[0249] The bus address is {segmentation[bus address width - 4 - effective number of bits - 1: 0], {data offset[effective number of bits - 1: 3], (!extend&data offset[2]), x'h0}, y'h0}.

[0250] Where, ! is the negation operator, & is the bitwise AND operator, the concatenation segment [bus address bit width - 4 - effective bits - 1: 0] is the 0th bit of the concatenation segment to the 4th bit width - 1 - effective bits of the bus address, the data offset [effective bits - 1: 3] is the 3rd bit of the data offset to the 1st bit width - 1, and the data offset [2] is the 2nd bit of the data offset; x and y are both bit numbers, x'h0 is a hexadecimal number with a bit width of x bits and a value of 0; y'h0 is a hexadecimal number with a bit width of y bits and a value of 0.

[0251] The device provided in this embodiment may further include a processor connected to a bus. The processor can send an input address to the bus, and the input address can be processed by the determination module 801 to obtain a processing data segment. The processor may be a high-performance processor, implemented as follows: Figure 2-7 The high-performance processor shown is described in detail in the bus address generation method embodiment, and will not be repeated here.

[0252] The apparatus provided in this embodiment can realize flexible and reconfigurable address generation, so that the final bus address covers a large address space with a limited table entry configuration, which is suitable for the broadcast characteristics of the bus.

[0253] Based on the same inventive concept as the above method, this embodiment provides an electronic device, which is as follows: Figure 9 As shown, it includes: a bus and a processor 901.

[0254] The bus address is determined by... Figure 1 The bus address generation method provided in this embodiment is shown.

[0255] For example, the processing data segment is determined based on the input address. The input address consists of a first lookup table address, the number of hops for inter-chip transfer, and a data offset. The processing data segment consists of 20'h0, a second lookup table address, and the number of hops for inter-chip transfer. 20'h0 is a 20-bit hexadecimal number with a value of 0.

[0256] Multiple segment information, significant number of bits, and alignment parameters are obtained based on the first lookup table address. Each segment information consists of start position information and length information.

[0257] Based on the starting position information of each segment, the extraction position is determined in the processed data segment, and the continuous data segment corresponding to the length information is extracted from the extraction position.

[0258] The consecutive data segments are spliced ​​together to obtain the spliced ​​segment.

[0259] The bus address is obtained based on the data offset, splice segment, significant bits, and alignment parameters.

[0260] If the bit width of any segment information is M bits, then the start position information is located in the lower S bits of any segment information, and the length information is located in the higher (MS) bits of any segment information.

[0261] Where M and S are positive integers, and M > S.

[0262] Where, S≥ .

[0263] Where L is the bit width of the processed data segment.

[0264] The bus address is {segmentation[bus address width - 4 - effective number of bits - 1: 0], {data offset[effective number of bits - 1: 3], (!extend&data offset[2]), x'h0}, y'h0}.

[0265] Where, ! is the negation operator, & is the bitwise AND operator, the concatenation segment [bus address bit width - 4 - effective bits - 1: 0] is the 0th bit of the concatenation segment to the 4th bit width - 1 - effective bits of the bus address, the data offset [effective bits - 1: 3] is the 3rd bit of the data offset to the 1st bit width - 1, and the data offset [2] is the 2nd bit of the data offset; x and y are both bit numbers, x'h0 is a hexadecimal number with a bit width of x bits and a value of 0; y'h0 is a hexadecimal number with a bit width of y bits and a value of 0.

[0266] In addition, the processor 901 can be a high-performance processor, as implemented as... Figure 2-7The high-performance processor shown is described in detail in the bus address generation method embodiment, and will not be repeated here.

[0267] The electronic device provided in this embodiment has a computer program executed by a processor to achieve flexible and reconfigurable address generation, so that the final bus address covers a large address space under a limited table entry configuration, which is suitable for the broadcast characteristics of the bus.

[0268] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0269] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0270] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0271] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0272] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0273] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0274] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A bus address generation method, characterized in that, The method includes: The processing data segment is determined based on the input address; wherein, the input address consists of a first lookup table address, the number of hops for inter-chip transmission, and a data offset, and the processing data segment consists of 20'h0, a second lookup table address, and the number of hops for inter-chip transmission; 20'h0 is a 20-bit hexadecimal number with a value of 0. Multiple segment information, effective number of bits, and alignment parameters are obtained based on the first lookup table address; wherein, any segment information consists of start position information and length information; Based on the starting position information of each segment, the extraction position is determined in the processed data segment, and the continuous data segment corresponding to the length information is extracted from the extraction position. The consecutive data segments are spliced ​​together to obtain the spliced ​​segment; The bus address is obtained based on the data offset, splice segment, significant bits, and alignment parameters.

2. The method according to claim 1, characterized in that, If the bit width of any segment information is M bits, then the start position information is located in the lower S bits of the segment information, and the length information is located in the higher (MS) bits of the segment information. Where M and S are positive integers, and M > S.

3. The method according to claim 2, characterized in that, The S≥ ; Where L is the bit width of the processed data segment.

4. The method according to claim 1, characterized in that, The bus address is {concatenation segment [bus address bit width - 4 - effective number of bits - 1: 0], {data offset [effective number of bits - 1: 3], (!extend&data offset [2]), x'h0}, y'h0}; Where, ! is the negation operator, & is the bitwise AND operator, the concatenation segment [bus address bit width - 4 - effective bits - 1: 0] is the 0th bit of the concatenation segment to the 4th bit width - 1 - effective bits of the bus address, the data offset [effective bits - 1: 3] is the 3rd bit of the data offset to the 1st bit width - 1, and the data offset [2] is the 2nd bit of the data offset; x and y are both bit numbers, x'h0 is a hexadecimal number with a bit width of x bits and a value of 0; y'h0 is a hexadecimal number with a bit width of y bits and a value of 0.

5. A bus address generation device, characterized in that, The device includes: The determination module is used to determine the processing data segment based on the input address; wherein, the input address consists of a first lookup table address, the number of hops for inter-chip transmission, and a data offset, and the processing data segment consists of 20'h0, a second lookup table address, and the number of hops for inter-chip transmission; 20'h0 is a 20-bit hexadecimal number with a value of 0; The acquisition module is used to acquire multiple segment information, effective number of bits, and alignment parameters based on the first lookup table address; wherein, any segment information consists of start position information and length information; The extraction module is used to determine the extraction position in the processed data segment based on the starting position information of each segment information, and extract the continuous data segment corresponding to the length information starting from the extraction position; The splicing module is used to splice together consecutive data segments to obtain a spliced ​​segment; The generation module is used to obtain the bus address based on the data offset, splice segment, significant number of bits, and alignment parameters.

6. The apparatus according to claim 5, characterized in that, If the bit width of any segment information is M bits, then the start position information is located in the lower S bits of the segment information, and the length information is located in the higher (MS) bits of the segment information. Where M and S are positive integers, and M > S.

7. The apparatus according to claim 6, characterized in that, The S≥ ; Where L is the bit width of the processed data segment.

8. The apparatus according to claim 5, characterized in that, The bus address is {concatenation segment [bus address bit width - 4 - effective number of bits - 1: 0], {data offset [effective number of bits - 1: 3], (!extend&data offset [2]), x'h0}, y'h0}; Wherein, ! is the negation operator, & is the bitwise AND operator, the concatenation segment [bus address bit width - 4 - effective bits - 1: 0] is the 0th bit of the concatenation segment to the 4th bit width - 1 effective bits of the bus address, the data offset [effective bits - 1: 3] is the 3rd bit of the data offset to the 1st effective bits of the data offset, and the data offset [2] is the 2nd bit of the data offset; x and y are both bit numbers, x'h0 is a hexadecimal number with a bit width of x bits and a value of 0; y'h0 is a hexadecimal number with a bit width of y bits and a value of 0; and the variables of the bus address are all in high-order order, with low-order order.

9. The apparatus according to claim 5, characterized in that, The device also includes a processor; The processor is connected to the bus, and the processor sends an input address to the bus; wherein, the input address is processed by the determination module to obtain a processing data segment.

10. An electronic device, characterized in that, include: Bus and processor; The address of the bus is generated by the method described in any one of claims 1-4.

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