An instruction processing method, a terminal device, and a storage medium

Abstract

This application relates to the field of instruction processing technology, and provides an instruction processing method, terminal device, and storage medium. The method includes: if a current instruction exists, a universal asynchronous transceiver sends an interrupt signal; upon receiving the interrupt signal, the controller stops the currently running main program and begins running an interrupt routine. When running the interrupt routine, the controller first determines the priority of the current instruction. If the current instruction is a low-priority instruction, the interrupt routine does not process the current instruction, and the controller directly exits the interrupt routine and continues running the main program, which then processes the current instruction. If the current instruction is a high-priority instruction, the interrupt routine processes the current instruction. This application's controller first determines the priority of the current instruction in the interrupt routine, and does not perform substantive processing on low-priority instructions, thereby shortening the execution time of the interrupt routine, avoiding prolonged occupation of the interrupt context, and reducing blocking of other interrupts.

Description

Technical Field

[0001] This application belongs to the field of instruction processing technology, and in particular relates to an instruction processing method, terminal device and storage medium. Background Technology

[0002] During controller operation, if a user command is received, the controller will initiate an interrupt service routine. Within this routine, the controller parses, processes, and responds to the user command. However, this interrupt routine takes a long time to execute, potentially blocking responses to other interrupts and impacting the overall system real-time performance. This is especially problematic in scenarios with multiple commands arriving consecutively or high-load communication, where prolonged occupation of the interrupt context can easily lead to system timing irregularities or data loss. Summary of the Invention

[0003] This application provides an instruction processing method, a terminal device, and a storage medium, which can solve the problem of system abnormalities caused by long interrupt program execution time.

[0004] In a first aspect, embodiments of this application provide an instruction processing method, including: In response to the controller receiving an interrupt signal from the universal asynchronous transceiver, the controller stops the main program that is running and runs an interrupt routine, wherein the interrupt routine is not a program in the main program, and the interrupt signal is generated by the universal asynchronous transceiver after receiving the instruction data of the current instruction; If the controller determines through the interrupt routine that the current instruction is a low-priority instruction, the controller exits the interrupt routine; The controller continues to execute the main program, and the controller processes the current instruction through the main program to obtain the processing result of the current instruction.

[0005] In this application, if a current instruction exists, the universal asynchronous transceiver sends an interrupt signal. Upon receiving the interrupt signal, the controller stops the currently running main program and begins running the interrupt routine. When running the interrupt routine, the controller does not immediately process the current instruction. Instead, it first determines the priority of the current instruction. If the current instruction is a low-priority instruction, the interrupt routine does not process it, and the controller exits the interrupt routine directly. The controller then continues running the main program, which processes the current instruction. This application's controller first determines the priority of the current instruction within the interrupt routine. For low-priority instructions, no substantial processing is performed, and the interrupt routine exits immediately. This shortens the execution time of the interrupt routine, avoids prolonged occupation of the interrupt context, reduces blocking of other interrupts, and improves the overall real-time response capability of the system. Because the interrupt routine execution logic is simplified and does not involve complex data parsing or processing, it reduces the possibility of prolonged interrupt occupation in high-load or multi-instruction-arrival scenarios, effectively avoiding system timing disorders or data loss problems, and improving the stability of communication processing. Furthermore, by dividing instruction processing into an interrupt judgment stage and a main program execution stage, asynchronous processing of low-priority instructions is achieved, improving the utilization efficiency of system resources and the flexibility of instruction processing.

[0006] In one possible implementation of the first aspect, the instruction data stores the instruction code of the current instruction; Before the controller exits the interrupt routine, the method executed by the controller based on the interrupt level further includes: Query the global character corresponding to the instruction code of the current instruction, wherein the mapping relationship between different instruction codes and global characters is stored in advance; Set the value of the global flag to the global character; The instruction data is cached in the data cache module.

[0007] In this application, if the current instruction is a low-priority instruction, the interrupt routine will not process the current instruction, and the main program needs to process the current instruction. The interrupt routine updates the global flag bit, and after the main program reads the global flag bit, it can process the current instruction, thus avoiding the main program from missing the current instruction.

[0008] In one possible implementation of the first aspect, before the controller processes the current instruction through the main program to obtain the processing result of the current instruction, the method executed by the controller through the main program includes: Read the global character of the global flag bit; If it is determined that the global character does not match the initial character, the instruction data is read from the data cache module, and the instruction data includes the current instruction.

[0009] In one possible implementation of the first aspect, after the controller runs the interrupt routine, the method executed by the controller through the interrupt routine further includes: Read the instruction data, wherein the instruction data includes the instruction code of the current instruction; The priority of the current instruction is determined by querying a preset priority mapping table, which stores the mapping relationship between different instruction codes and priorities. If the priority of the instruction code of the current instruction is determined to be low priority, then the current instruction is determined to be a low priority instruction. If the priority of the instruction code of the current instruction is determined to be high priority, then the current instruction is determined to be a high priority instruction.

[0010] In this application, a preset priority mapping table is stored in advance. The interrupt level can be determined by the preset priority mapping table to determine the priority of the current instruction. This eliminates the need for complex procedures, simplifies the priority judgment steps, and improves the system response speed.

[0011] In one possible implementation of the first aspect, after the controller stops the running main program in response to receiving an interrupt signal from the universal asynchronous transceiver, and after the controller runs the interrupt routine, the method further includes: If the controller determines that the current instruction is a high-priority instruction through the interrupt routine, the controller processes the current instruction through the interrupt routine to obtain the processing result of the current instruction; The controller exits the interrupt routine; The controller continues to execute the main program.

[0012] In this application, if the current instruction is a high-priority instruction, the high-priority instruction is processed directly in the interrupt routine without waiting for the main program to poll or switch tasks, thus ensuring the response speed of the high-priority instruction. After the interrupt routine exits, the main program continues to execute, and the processing of non-critical commands is not affected. This decouples the "immediate processing" of high-priority instructions from the "asynchronous delayed processing" of low-priority tasks, ensuring both real-time performance and maintaining high system throughput.

[0013] In one possible implementation of the first aspect, the controller processes the current instruction through the interrupt routine to obtain the processing result of the current instruction, including: The controller parses the current instruction through the interrupt routine to determine the target function required to execute the current instruction; The controller calls the target function through the interrupt routine to process the current instruction and obtain the processing result of the current instruction.

[0014] In one possible implementation of the first aspect, the interrupt signal is generated after the universal asynchronous transceiver receives the instruction data of the current instruction and stores the instruction data in the data register.

[0015] In this application, the invention utilizes the inherent preemptive characteristic of serial port hardware receive interrupt. The interrupt signal is generated after the general asynchronous transceiver receives the current instruction data and stores it in the data register, without relying on software scheduling.

[0016] In a second aspect, embodiments of this application provide a terminal device, including: a memory, a controller, and a computer program stored in the memory and executable on the processor, wherein the controller executes the computer program to implement the instruction processing method described in any one of the first aspects above.

[0017] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the instruction processing method described in any one of the first aspects above.

[0018] Fourthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute the instruction processing method described in any one of the first aspects. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the instruction processing procedure provided in an embodiment of this application; Figure 2 This is a flowchart illustrating an embodiment of the instruction processing method provided in this application; Figure 3 This is a flowchart illustrating a method for determining the priority of instructions according to an embodiment of this application; Figure 4 This is a flowchart illustrating the execution method of an interrupt routine provided in an embodiment of this application; Figure 5This is a flowchart illustrating a method for processing high-priority instructions according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0021] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0022] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0023] Currently, after receiving instructions, the controller processes each instruction in the order of receipt time, resulting in critical instructions not receiving priority responses and making it difficult to meet the hard real-time requirements of industrial sites for instructions such as emergency stops and safety reporting.

[0024] If an interrupt service routine exists, the controller will start the terminal service routine to process the instruction after receiving it. Data is processed directly in the interrupt service routine. Although the response is timely, the interrupt processing time is too long and will block other interrupts, affecting the overall real-time performance and stability of the system. It is not suitable for complex command parsing scenarios.

[0025] Based on this, refer to Figure 1 As shown, this application proposes an instruction processing method, which includes: After receiving instruction data from an external module, the Universal Asynchronous Receiver Transmitter (UART) stores the instruction data in its data register.

[0026] UART sends interrupt signals to the controller via a hardware serial port.

[0027] After receiving an interrupt signal, the controller stops the main program that is running and starts running the interrupt routine.

[0028] The operations performed by the interrupt routine include: first, determining whether the current instruction is a high-priority instruction.

[0029] If the current instruction is a high-priority instruction, the current instruction is processed through the interrupt routine; If the current instruction is a low-priority instruction, the controller exits the interrupt routine and continues to run the main program, which then processes the low-priority current instruction.

[0030] The following combination Figure 2 The instruction processing method of the embodiments of this application will be described in detail.

[0031] Figure 2 A schematic flowchart of the instruction processing method provided in this application is shown, with reference to... Figure 2 The method is described in detail below: S101, in response to the controller receiving an interrupt signal sent by the universal asynchronous transceiver, the controller stops the main program that is running and runs an interrupt routine, wherein the interrupt routine is not a program in the main program, and the interrupt signal is generated by the universal asynchronous transceiver after receiving the instruction data of the current instruction.

[0032] In this embodiment, the universal asynchronous transceiver (UAST) receives the instruction data of the current instruction and stores the instruction data in the data register; the UAST sends an interrupt signal to the controller via a hardware serial port. The controller receives the interrupt signal via the hardware serial port. In this application, the generation and transmission of the interrupt signal are both handled by hardware, without involving complex software processing, thus improving the instruction response speed.

[0033] In this embodiment, when the device starts up, the system needs to be initialized, specifically including: initializing the global flag bit; setting the value of the global flag bit to an initial character, the initial character indicating that there are no low-priority instructions to be processed; initializing the data register of the universal asynchronous transceiver, clearing the data register so that there is no historical instruction data in the data register; and enabling the serial port to receive hardware interrupts, that is, enabling the hardware serial port to receive interrupt signals.

[0034] In this embodiment, the interrupt routine is a program segment that is automatically triggered by the serial port hardware receiving an interrupt signal. The interrupt routine runs in the interrupt context of the controller, has a very high priority, and can interrupt the execution of the main program.

[0035] The main program is a program segment that runs continuously in the main loop after the controller is powered on. The main program runs in the task context and has a lower priority than the interrupt routine. The main program can parse load-bearing and time-consuming instructions without interfering with the processing of high-priority instructions.

[0036] S102, if the controller determines through the interrupt routine that the current instruction is a low-priority instruction, the controller exits the interrupt routine.

[0037] In this embodiment, an interrupt routine is executed, and the priority of the current instruction can be determined by the degree of interruption. That is, the interrupt routine includes a process for determining the priority of the current instruction.

[0038] High-priority commands require immediate response; failure to do so may damage the equipment or affect user experience. Low-priority commands do not require immediate response. High-priority commands may include emergency stop commands and safety status reporting commands. Low-priority commands may include commands to query equipment temperature and commands to retrieve historical data.

[0039] In one approach, the process of determining the priority of the current instruction may include: finding the security level and control category corresponding to the current instruction; finding the level parameter value corresponding to the security level and the category parameter value corresponding to the control category; weighting the level parameter value and the category parameter value to obtain the priority value of the current instruction; finding the level discrimination interval where the priority value lies, and determining the priority corresponding to the level discrimination interval where the priority value lies as the priority of the current instruction. For example, if the priority value is 4, if the priority interval where the priority value lies corresponds to a high priority, then the current instruction is a high-priority instruction; if the priority interval where the priority value lies corresponds to a low priority, then the current instruction is a low-priority instruction.

[0040] In another way, such as Figure 3 As shown, the process of determining the priority of the current instruction may include: S1021, Read the instruction data, wherein the instruction data includes the instruction code of the current instruction.

[0041] In this embodiment, if the universal asynchronous transceiver stores instruction data in the data register, then when the interrupt routine is executed, it needs to read the instruction data from the data register.

[0042] An instruction code is a short number or byte value that uniquely identifies different instructions.

[0043] S1022, query the preset priority mapping table to determine the priority corresponding to the instruction code of the current instruction. The preset priority mapping table stores the mapping relationship between different instruction codes and priorities.

[0044] In this embodiment, the priorities of different instructions are distinguished in advance, and a mapping relationship between instruction code and instruction type (high priority or low priority) is established to obtain a preset priority mapping table.

[0045] For example, the instruction code for an emergency stop command is 0x01, and 0x01 has a high priority; the instruction code for equipment temperature is 0x02, and 0x02 has a low priority.

[0046] In one implementation, the preset priority mapping table is automatically updated.

[0047] Specifically, if the number of times the same instruction is processed reaches a preset number within a preset time period, the priority of that instruction will be raised to high priority.

[0048] Specifically, query the processor's load status. If the load status exceeds the preset value (e.g., 80%), low-priority instructions may be delayed for a long time under high load. If the low-priority instruction is related to security or task continuity (e.g., device heartbeat, mode hold instructions), then the priority of the instruction is raised from low priority to high priority.

[0049] S1023, if it is determined that the priority of the instruction code of the current instruction is low priority, then the current instruction is determined to be a low priority instruction.

[0050] S1024, if it is determined that the priority of the instruction code of the current instruction is high priority, then the current instruction is determined to be a high priority instruction.

[0051] In this embodiment, if the interrupt routine determines that the current instruction is a low-priority instruction, the interrupt routine will not process the current instruction, and the controller will directly stop the execution of the interrupt routine.

[0052] S103, the controller continues to execute the main program, and the controller processes the current instruction through the main program to obtain the processing result of the current instruction.

[0053] In this embodiment, if the current instruction is a low-priority instruction, the controller executes the main program. That is, the current instruction does not need to be executed immediately. Instead, the current instruction can be processed through the instruction processing flow in the main program during the execution of the main program, thereby realizing the asynchronous processing of low-priority instructions.

[0054] In this application, if a current instruction exists, the universal asynchronous transceiver sends an interrupt signal. Upon receiving the interrupt signal, the controller stops the currently running main program and begins running the interrupt routine. When running the interrupt routine, the controller does not immediately process the current instruction. Instead, it first determines the priority of the current instruction. If the current instruction is a low-priority instruction, the interrupt routine does not process it, and the controller exits the interrupt routine directly. The controller then continues running the main program, which processes the current instruction. This application's controller first determines the priority of the current instruction within the interrupt routine. For low-priority instructions, no substantial processing is performed, and the interrupt routine exits immediately. This shortens the execution time of the interrupt routine, avoids prolonged occupation of the interrupt context, reduces blocking of other interrupts, and improves the overall real-time response capability of the system. Because the interrupt routine execution logic is simplified and does not involve complex data parsing or processing, it reduces the possibility of prolonged interrupt occupation in high-load or multi-instruction-arrival scenarios, effectively avoiding system timing disorders or data loss problems, and improving the stability of communication processing. Furthermore, by dividing instruction processing into an interrupt judgment stage and a main program execution stage, asynchronous processing of low-priority instructions is achieved, improving the utilization efficiency of system resources and the flexibility of instruction processing.

[0055] In one possible implementation, since low-priority instructions need to be processed when the main program is executed, and the priority of the current instruction is determined by the interrupt routine, when the interrupt routine determines that the current instruction is a low-priority instruction, in order to let the main program know that there is a low-priority instruction that needs to be processed, the interrupt routine can set a global flag bit, so that the main program can determine whether there is a low-priority instruction that needs to be processed based on the global flag bit.

[0056] Therefore, as Figure 4 As shown, if the controller determines through the interrupt routine that the current instruction is a low-priority instruction, the method executed by the controller based on the interrupt level before exiting the interrupt routine further includes: S201, query the global character corresponding to the instruction code of the current instruction, wherein the mapping relationship between different instruction codes and global characters is stored in advance.

[0057] In this embodiment, the instruction data contains the instruction code of the current instruction. Global characters corresponding to different instruction codes are pre-stored to obtain the mapping relationship between instruction codes and global characters.

[0058] S202, set the value of the global flag bit to the global character.

[0059] In this embodiment, if the initial character of the global flag is 0x00 and the global character corresponding to the instruction code of the current instruction is 0x02, then the global flag is set to 0x02.

[0060] S203, the instruction data is cached in the data cache module.

[0061] In this embodiment, since the interrupt routine does not process low-priority current instructions, in order for the main program to read the instruction data of the current instruction, the interrupt routine needs to cache the instruction data in the data cache module to temporarily store the instruction data.

[0062] In one possible implementation, the controller continues to execute the main program by: S301, Read the global character of the global flag bit.

[0063] S302, if it is determined that the global character does not match the initial character, the instruction data is read from the data cache module, and the instruction data includes the current instruction.

[0064] After reading the instruction data, the controller processes the current instruction through the main program to obtain the processing result of the current instruction.

[0065] Specifically, the main program can call the corresponding function to process the current instruction and obtain the processing result. For example, if the current instruction is to query the device temperature, the main program can call the temperature sensor to read the device temperature measured by the sensor. Specifically, the main program performs complete protocol parsing on the instruction data, including frame header, frame trailer, data length, and checksum verification operations to ensure the validity and integrity of the instruction. After successful verification, the main program calls the corresponding function to process the current instruction and obtain the processing result. After processing, the main program clears the corresponding flag bits and sends the processing result (response data packet) back to the host computer or main control device via the UART peripheral.

[0066] In one possible implementation, if the interrupt routine determines that the current instruction is a high-priority instruction, the interrupt routine needs to process the current instruction directly. Thus, as... Figure 5 As shown, after step S101, the above method may further include: S401, if the controller determines that the current instruction is a high-priority instruction through the interrupt routine, the controller processes the current instruction through the interrupt routine to obtain the processing result of the current instruction.

[0067] In this embodiment, the controller parses the current instruction through an interrupt routine to determine the target function required to execute the current instruction; the controller then calls the target function through the interrupt routine to process the current instruction and obtain the processing result of the current instruction.

[0068] S402, the controller exits the interrupt routine.

[0069] S403, the controller continues to execute the main program.

[0070] For high-priority instructions, if the interrupt routine fails to process the instruction and no result is obtained, it will retry and continue to process the high-priority instruction until the preset number of retries is reached. If no result is obtained after the retry, an exception message will be output so that the user can determine that the instruction has not been processed.

[0071] In this application, if the current instruction is a high-priority instruction, the high-priority instruction is processed directly in the interrupt routine without waiting for the main program to poll or switch tasks, thus ensuring the response speed of the high-priority instruction. After the interrupt routine exits, the main program continues to execute, and the processing of non-critical commands is not affected. This decouples the "immediate processing" of high-priority instructions from the "asynchronous delayed processing" of low-priority tasks, ensuring both real-time performance and maintaining high system throughput.

[0072] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0073] This application also provides a terminal device, see [link to relevant documentation] Figure 6 The terminal device 500 may include: at least one processor 510 (i.e., a controller), a memory 520, and a computer program stored in the memory 520 and executable on the at least one processor 510. When the processor 510 executes the computer program, it implements the steps in any of the above method embodiments, for example... Figure 2 Steps S101 to S103 in the illustrated embodiment.

[0074] For example, a computer program may be divided into one or more modules / units, one or more of which are stored in memory 520 and executed by processor 510 to complete this application. The one or more modules / units may be a series of computer program segments capable of performing specific functions, which describe the execution process of the computer program in terminal device 500.

[0075] Those skilled in the art will understand that Figure 6 This is merely an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, buses, etc.

[0076] The processor 510 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0077] The memory 520 can be an internal storage unit of the terminal device or an external storage device, such as a plug-in hard drive, a smart media card (SMC), a secure digital (SD) card, or a flash card. The memory 520 is used to store the computer program and other programs and data required by the terminal device. The memory 520 can also be used to temporarily store data that has been output or will be output.

[0078] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0079] The instruction processing method provided in this application can be applied to terminal devices such as computers, tablets, laptops, netbooks, and personal digital assistants (PDAs). This application does not impose any restrictions on the specific type of terminal device.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0081] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0082] In the embodiments provided in this application, it should be understood that the disclosed terminal devices, apparatuses, and methods can be implemented in other ways. For example, the terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, apparatuses, or units, and may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0085] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by one or more processors, it can implement the steps of the various method embodiments described above.

[0086] Similarly, as a computer program product, when the computer program product is run on a terminal device, it enables the terminal device to implement the steps in the above-described method embodiments.

[0087] The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0088] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An instruction processing method, characterized by, include: In response to the controller receiving an interrupt signal from the universal asynchronous transceiver, the controller stops the main program that is running and runs an interrupt routine, wherein the interrupt routine is not a program in the main program, and the interrupt signal is generated by the universal asynchronous transceiver after receiving the instruction data of the current instruction; If the controller determines through the interrupt routine that the current instruction is a low-priority instruction, the controller exits the interrupt routine; The controller continues to execute the main program, and the controller processes the current instruction through the main program to obtain the processing result of the current instruction.

2. The instruction processing method as described in claim 1, characterized in that, The instruction data stores the instruction code of the current instruction; Before the controller exits the interrupt routine, the method executed by the controller based on the interrupt level further includes: Query the global character corresponding to the instruction code of the current instruction, wherein the mapping relationship between different instruction codes and global characters is stored in advance; Set the value of the global flag to the global character; The instruction data is cached in the data cache module.

3. The instruction processing method as described in claim 2, characterized in that, Before the controller processes the current instruction through the main program and obtains the processing result of the current instruction, the methods executed by the controller through the main program include: Read the global character of the global flag bit; If it is determined that the global character does not match the initial character, the instruction data is read from the data cache module, and the instruction data includes the current instruction.

4. The instruction processing method as described in claim 1, characterized in that, After the controller runs the interrupt routine, the method executed by the controller through the interrupt routine further includes: Read the instruction data, wherein the instruction data includes the instruction code of the current instruction; The priority of the current instruction is determined by querying a preset priority mapping table, which stores the mapping relationship between different instruction codes and priorities. If the priority of the instruction code of the current instruction is determined to be low priority, then the current instruction is determined to be a low priority instruction. If the priority of the instruction code of the current instruction is determined to be high priority, then the current instruction is determined to be a high priority instruction.

5. The instruction processing method according to any one of claims 1 to 4, characterized in that, In response to the controller receiving an interrupt signal from the universal asynchronous transceiver, the controller stops the running main program, and after the controller runs the interrupt routine, the method further includes: If the controller determines that the current instruction is a high-priority instruction through the interrupt routine, the controller processes the current instruction through the interrupt routine to obtain the processing result of the current instruction; The controller exits the interrupt routine; The controller continues to execute the main program.

6. The instruction processing method as described in claim 5, characterized in that, The controller processes the current instruction through the interrupt routine to obtain the processing result of the current instruction, including: The controller parses the current instruction through the interrupt routine to determine the target function required to execute the current instruction; The controller calls the target function through the interrupt routine to process the current instruction and obtain the processing result of the current instruction.

7. The instruction processing method as described in claim 1, characterized in that, The interrupt signal is generated after the universal asynchronous transceiver receives the instruction data of the current instruction and stores the instruction data in the data register.

8. The instruction processing method as described in claim 1, characterized in that, Before the controller stops its running main program and runs the interrupt routine in response to receiving an interrupt signal from the universal asynchronous transceiver, the method further includes: Initialize the global flags by setting their values ​​to the initial character; The data registers of the general asynchronous transceiver are initialized.

9. A terminal device, comprising a memory, a controller, and a computer program stored in the memory and executable on the controller, characterized in that, When the controller executes the computer program, it implements the instruction processing method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the instruction processing method as described in any one of claims 1 to 8.

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