Modular heterogeneous real-time processing platform and data collaboration method for airborne radar

Abstract

This invention discloses a modular heterogeneous real-time processing platform and data collaboration method for airborne radar, belonging to the field of airborne radar signal processing technology. The platform uses a central data board as a fixed carrier unit, and real-time processing sub-boards, RF sub-boards, and CPU core boards can be detachably connected via three types of functional sockets. The chassis has an RF interface opening area, with external interfaces formed by connectors built into the sub-boards. It supports switching between lightweight and enhanced computing dual-master control configurations, and the chassis heat dissipation structure can be globally reused. The method divides radar data into seven levels (L0-L6), supporting mixed hierarchical uploading based on range gate, beam direction, scanning sector, or target area. Combined with dual control logic, frame synchronization smoothing, and heterogeneous dynamic load scheduling, it achieves dynamic adaptation of transmission and processing strategies. This invention enables independent upgrades of multiple modules, reduces RF link loss, and improves platform adaptability and real-time processing efficiency.

Description

Technical Field

[0001] This invention relates to the field of airborne radar signal processing technology, and in particular to a modular heterogeneous real-time processing platform and data collaboration method for airborne radar. Background Technology

[0002] As a core component of avionics systems, airborne radar is characterized by long development cycles, high technical complexity, and frequent iterations of mission requirements. In the traditional airborne radar development process, the number of radio frequency channels, sampling rate, real-time processing scale, algorithm load, storage and display, and external interface configuration can only be determined based on estimated indicators in the early stages of the system. However, with the iteration of radar algorithms, functional expansion, accumulation of field test data, changes in mission modes, and adjustments to the overall technical specifications, the early predictions of radio frequency performance, real-time processing computing power, and complex computing capabilities are prone to deviation.

[0003] Traditional fixed-system airborne radars, once problems such as insufficient radio frequency channels, inadequate processing power, or the need to adjust radio frequency bands / interfaces occur, must simultaneously modify the chassis structure, external interfaces, chassis openings, cooling water platforms, connecting cables, and power systems. This directly leads to extended development cycles, increased costs of structural modifications, and heightened risks of multi-module integration. While some existing modular radar platforms employ a backplane + daughterboard architecture, they still suffer from significant drawbacks: First, the RF interface is fixed to the chassis, requiring a complete chassis redesign for adjustments to the number of RF channels or interface type. Internal RF adapter links are long with high insertion loss, and RF front-end compatibility with different channel numbers is poor. Second, computing power upgrades require a complete replacement of the processing unit, hindering independent iteration of RF, real-time processing, and complex computing modules. Hardware upgrades are coarse-grained and costly. Third, data transmission uses a raw data full-upload mode, with each frame using a single processing depth level, failing to adapt to the echo characteristics differences across different ranges and scanning areas of airborne radar. This results in high bandwidth utilization and heavy load on the backend processor. Fourth, the fixed main control architecture cannot be flexibly configured based on task complexity, device power consumption, weight, and cost. Furthermore, the rigid boundaries of heterogeneous processing lead to low computing power utilization and difficulty in guaranteeing real-time performance under high load scenarios. Fifth, parameter adjustments take full effect in the next frame, making significant parameter changes prone to result jumps in processing outcomes and target tracking loss. Additionally, the output data lacks parameter version identification, resulting in poor backend data traceability.

[0004] Therefore, the industry urgently needs an airborne radar heterogeneous real-time processing platform with a stable overall structure, independently replaceable functional modules, on-demand upgradeable system capabilities, and an efficient data collaboration mechanism. Summary of the Invention

[0005] In view of this, this application provides a modular heterogeneous real-time processing platform and data collaboration method for airborne radar to address the shortcomings of existing technologies.

[0006] The first aspect of this application provides a modular heterogeneous real-time processing platform for airborne radar, comprising: The central data board, as the fixed support unit of the whole machine, integrates a general external interface, a power management module, a clock distribution module, a high-speed data conversion module, a low-speed control module, as well as a first function socket, a second function socket, and a third function socket. The real-time processing sub-board is detachably connected to the first functional socket and uses an FPGA chip or MPSoC chip to complete high-speed data access and real-time preprocessing. The radio frequency daughterboard is detachably connected to the second functional socket and is used to adapt to radar front-ends with different frequency bands, bandwidths, polarization methods, transceiver systems, or number of channels. The CPU core board can be detachably added to or replaced in the third functional socket for performing complex processing, task scheduling, data management, display and storage under the enhanced computing configuration; The chassis body, its shape, internal load-bearing structure, general external interface positions, mounting hole positions and heat sink positions are all fixed, and RF interface opening areas are set at the corresponding RF daughterboard positions; The platform supports switching between a lightweight main control configuration and an enhanced computing main control configuration. In the lightweight main control configuration, the internal ARM processing system of the MPSoC chip in the real-time processing subboard serves as the platform main control. In the enhanced computing main control configuration, the CPU core board is installed as the platform main control.

[0007] In one possible implementation of the first aspect, the RF daughterboard integrates an RF connector, which is exposed in the RF interface opening area and directly constitutes the external RF interface of the whole machine. The RF daughterboard connects to external RF signals through its integrated RF connector. The second functional socket integrates multiple analog-to-digital signal transmission channels and digital-to-analog signal transmission channels. The analog-to-digital and digital-to-analog signals between the RF daughterboard and the real-time processing daughterboard are transmitted through the second functional socket. When it is necessary to adjust the number of RF channels, the arrangement of RF connectors, or the form of RF interface, the adjustment can be completed by replacing the RF sub-board with a different configuration within the allowable range of the RF interface opening area, the size of the RF sub-board, and the pre-configured socket resources, power supply resources, clock resources, heat dissipation resources, and processing resources of the system.

[0008] In one possible implementation of the first aspect, when the real-time processing subboard uses an MPSoC chip, it includes a programmable logic (PL) side and a processing system (PS) side. The PL side undertakes high-speed real-time preprocessing functions in both the lightweight main control configuration and the enhanced computing main control configuration. The PS side, in a lightweight main control configuration, serves as the platform's main control, completing RF daughterboard configuration, system status monitoring, working mode management, and basic data processing. The PS side undertakes the underlying hardware control functions under the enhanced computing main control configuration, while the CPU core board, as the platform main controller, undertakes complex algorithm processing, task scheduling, data management, display and storage functions.

[0009] In one possible implementation of the first aspect, the first functional socket, the second functional socket, and the third functional socket are all composed of multiple high-speed connectors; The first functional socket is used to transmit power, clock, and low-speed control signals. It communicates with the real-time processing daughterboard via PCIe through a high-speed serial channel, and transmits ADC input signals from the RF daughterboard via LVDS and DAC output signals to the RF daughterboard via a high-speed serial channel. The second functional socket is used to transmit power, clock, and control I / O signals, enabling ADC / DAC signal transmission between the RF sub-board and the real-time processing sub-board; The third functional socket is used to transmit power, clock, and I / O signals, and enables PCIe communication with the CPU core board through a high-speed serial channel.

[0010] In one possible implementation of the first aspect, the position of the heat sink of the chassis remains fixed, and the heat-generating devices of each detachable sub-board are connected to the corresponding heat sink through a heat-conducting block, heat-conducting pad or heat spreader; when replacing CPU core boards, real-time processing sub-boards or RF sub-boards of different performance levels, they share the same chassis heat dissipation structure.

[0011] A second aspect of this application provides an airborne radar data coordination method for the platform, comprising the following steps: The real-time processing subboard divides radar data into multiple levels according to the processing depth of the data in the processing link, and completes the preprocessing of radar data of the corresponding level. Based on the current radar type, mission mode, and platform main control configuration, select the corresponding data level and upload it to the platform main control unit; The platform's main control unit, in conjunction with the system's operating status and user commands, writes back control parameters to the real-time processing sub-board. After the real-time processing sub-board receives and confirms the control parameters, the changes take effect in the next frame data processing cycle, adjusting the data preprocessing parameters, data upload level, and caching strategy.

[0012] In one possible implementation of the second aspect, the radar data is divided into seven levels, from L0 to L6, specifically: L0 level: Raw sampled data, which is the ADC output or the raw I / Q data or real sampled data after interface processing, generated by AD sampling, data alignment, frame synchronization and channel processing; L1 level: Distance gate data, which is data processed by pulse, channel and distance unit, generated by raw sampling, digital down-conversion, decimation filtering and distance gate division; L2 level: Pulse compressed data, which is multi-channel data after filtering, digital downconversion or frequency band division, generated by digital downconversion, FIR filtering, channelization, amplitude and phase correction and pulse compression. L3 level: Doppler spectral data, which is the spectral data after spectral estimation of a specified distance gate or channel, and generated by windowing, FFT, spectral averaging and amplitude calculation; Level L4: Basic parameter data, which are basic measurement parameters extracted from spectral data or distance gate data, generated through peak search, threshold detection, parameter estimation, and statistical averaging. Level L5: Structured feature data, which is target, environment or echo feature data for backend algorithms or display, generated through feature extraction, target or region aggregation and data packaging; Level L6: Displays compressed data, which is extracted, compressed, or reduced-dimensional data for real-time display or low-bandwidth transmission. It is generated through downsampling, grayscale or pseudo-color mapping, compression encoding, and frame rate control.

[0013] In one possible implementation of the second aspect, the platform main control unit uses dual control logic to write back control parameters to the real-time processing sub-board: First control logic: The user manually adjusts the radar operating parameters and processing parameters based on the detection results, echo quality, detection sensitivity, signal-to-noise ratio, and clutter conditions; Second control logic: The CPU core board automatically adjusts the radar operating parameters and processing parameters based on whether the processing time of each frame meets the preset real-time requirements; The adjustable parameters include radar operating bandwidth, pulse coherent accumulation time, number of FFT points, MTI switch, number of various CFAR elements, and CFAR calculation mode; The issued control parameters are accompanied by a specified effective frame number. The real-time processing sub-board completes the parameter switching within the pulse blanking region of the corresponding frame. Each frame output data carries the current parameter version tag. For parameter changes that exceed the corresponding parameter's set threshold, a multi-frame gradual transition mode is used to adjust the processing parameters step by step. After receiving and confirming the control parameters, the real-time processing sub-board returns status information to the platform's main control unit.

[0014] In one possible implementation of the second aspect, the real-time processing sub-board divides a single frame of radar data into multiple data sub-regions in terms of range gate, beam direction, scanning sector, or target area, and different data sub-regions within the same frame are mixed and uploaded according to different data levels. The data frame header carries a sub-region division identifier and a corresponding data level label, which the platform's main control unit parses and processes separately according to the data sub-regions.

[0015] In one possible implementation of the second aspect, under the enhanced computing main control configuration, the CPU core board monitors its own computing load and high-speed interconnect bandwidth utilization in real time. When the computing load or high-speed interconnect bandwidth utilization exceeds the preset threshold, a task offload command is sent to the real-time processing sub-board to offload some back-end processing algorithms to the real-time processing sub-board for execution, and the data upload level is upgraded simultaneously. When both the computing load and the high-speed interconnect bandwidth utilization rate are below the preset threshold, the corresponding processing task is revoked, and the data upload level drops back to the original level.

[0016] Its beneficial effects are as follows: 1. Decoupled architecture reduces iteration costs: The architecture adopts a "central data board + detachable sub-board" structure, strictly following the "three unchanged and four variable" design. RF, real-time processing and complex computing modules can be replaced and upgraded independently. The main control configuration can be switched without modifying the chassis, interface, heat dissipation and power supply structure, which greatly shortens the radar iteration cycle and reduces the risk of structural changes and joint debugging.

[0017] 2. Optimized RF interface to reduce link loss: An RF interface opening area is set up, and the RF daughterboard integrated connector is directly used as the external interface of the whole machine, eliminating redundant RF adapter cables and connectors built into the chassis, effectively reducing signal insertion loss, VSWR and assembly error; it supports flexible replacement of RF daughterboards with different number of channels and different interface forms, improving hardware versatility.

[0018] 3. Dual main control configuration to adapt to multiple scenario requirements: It distinguishes between two main control modes, namely lightweight and enhanced computing. The hardware configuration can be flexibly tailored according to the complexity of the task, power consumption, weight and cost. It can meet the needs of miniaturized and low-power scenarios, as well as support complex algorithm operations, avoiding over-design or insufficient computing power.

[0019] 4. Hierarchical collaboration and airspace optimization to improve transmission efficiency: Radar data is divided into 7 levels and selectively uploaded as needed, eliminating bandwidth waste caused by the full transmission of raw data; a new airspace regional hybrid hierarchical mechanism is added to adapt to the echo characteristics of different airspaces, further reducing the amount of transmitted data while ensuring the processing accuracy of key areas.

[0020] 5. Smooth parameter tuning and dynamic scheduling enhance real-time performance: Parameter switching adopts frame synchronization, version tagging and multi-frame gradual change mechanism to avoid target tracking loss and data jump caused by parameter mutation; it is equipped with heterogeneous dynamic load scheduling, which dynamically adjusts the computing power division boundary according to the system load, fully explores the potential of heterogeneous computing power, and improves real-time performance and system stability in high-load scenarios. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 This is a block diagram of the overall structure of the modular heterogeneous real-time processing platform provided in the embodiments of this application; Figure 2 This is a schematic diagram of the layout of the central data board functional socket and high-speed connector provided in the embodiments of this application; Figure 3 This is a block diagram showing the connection relationship and signal flow between the central data board and the three types of sub-boards provided in this application embodiment; Figure 4 This is a system architecture diagram of the enhanced computing master control configuration provided in the embodiments of this application; Figure 5 This is a system architecture diagram of the lightweight main control configuration provided in the embodiments of this application; Figure 6 This is a schematic diagram of the airborne radar data collaboration method provided in the embodiments of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0025] Example 1 This embodiment provides a complete introduction to the platform's hardware composition, component selection, interface protocols, power supply, clock, radio frequency, and heat dissipation system hardware architecture and basic working principles, corresponding to... Figure 1 , Figure 2 and Figure 3 .

[0026] Core component selection and hardware parameters (corresponding) Figure 1 ): Central Data Board: The only fixed load-bearing unit in the entire machine, with onboard power management module, high-precision clock distribution, high-speed SerDes conversion circuit, low-speed control circuit and three sets of function sockets; edge integration of all universal external interfaces: Gigabit Ethernet interface, RS485 serial port, LVDS synchronization / trigger interface, debugging interface, storage / display interface, and the interface standards remain unchanged.

[0027] Functional socket connectors: The first and second functional sockets use Panasonic AXK6A2337YG high-speed connectors, which can also be replaced with Samtec ADM series connectors to support GHz-level RF signal transmission; the third functional socket uses Foxconn QT series high-speed connectors. All sockets have sufficient pin resources to support synchronous transmission of power, clock, low-speed IO, and high-speed serial signals.

[0028] Real-time processing daughterboard: The main chip is Xilinx Zynq UltraScale+XCZU15EG (MPSoC), which integrates the programmable logic (PL) side and the ARM processing system (PS) side; the hardware is equipped with DDR4 memory, eMMC storage, and FLASH configuration chip; it is responsible for real-time preprocessing such as high-speed radar data acquisition, digital down-conversion, pulse compression, and FFT.

[0029] RF daughterboard: adopts dual LTC2209 (ADC analog-to-digital converter chip) + AD9154 (DAC digital-to-analog converter chip), and integrates SMA RF connector; natively supports 1 receive and 1 transmit RF channel, which can be expanded to 4 receive and 4 transmit through hardware configuration; adaptable to multi-band, multi-bandwidth, and multi-polarization radar front-end.

[0030] CPU core board: The main processor is Phytium D3000M, equipped with Linux operating system, algorithm driver, and data management software; responsible for complex signal processing, task scheduling, data fusion, display and storage.

[0031] Chassis body: The shape, internal load-bearing structure, mounting holes, and position of the heat sink are permanently fixed; an RF interface opening area is opened in the corresponding area of ​​the RF daughterboard, and the opening area size and installation tolerance are adapted to the outer contour of the RF daughterboard.

[0032] Working principle of power supply and clock system: The power management module of the central data board introduces the whole machine input voltage and configures independent power supply branches for the three sets of functional sockets. Each branch outputs multiple voltages of 3.3V, 5V and 12V. Each power supply branch integrates a self-resetting fuse (overcurrent protection) and a TVS diode (overvoltage protection) to achieve fault isolation. Short circuits and overvoltages on a single sub-board will not affect the normal operation of other modules.

[0033] The clock distribution module is equipped with a high-precision crystal oscillator and outputs two reference clocks, 33.333MHz and 200MHz. These clocks are synchronously distributed to the real-time processing sub-board, RF sub-board, and CPU core board through the on-board clock network. The global clock synchronization accuracy is better than ±10ns, which meets the timing requirements of high-speed signal processing for airborne radar.

[0034] Signal transmission link working principle (corresponding) Figure 2 and Figure 3 ): Low-speed signals: Power, global clock, and control I / O signals are uniformly distributed from the central data board to three functional sockets to realize full-module hardware control and status interaction.

[0035] RF Analog / Digital Signals: External RF signals are input via the SMA connector on the RF daughterboard, converted, and then sent to the LTC2209 for AD sampling. Four ADC digital signals are transmitted to the real-time processing daughterboard via the LVDS channel of the second function socket. The four DAC signals generated by the real-time processing daughterboard are fed back to the AD9154 on the RF daughterboard via the high-speed SerDes channel for digital-to-analog conversion and RF transmission. All ADC / DAC signals from the RF daughterboard and the real-time processing daughterboard are integrated within the function socket for transmission; no additional RF adapter cables are required in the chassis.

[0036] High-speed interactive signal: The real-time processing daughterboard and the CPU core board realize high-speed PCIe Gen3×4×2 serial communication through the third function socket, which is used for radar data uploading and control parameter writing back.

[0037] Working principle of the RF interface opening area: The SMA RF connector integrated into the RF daughterboard is directly exposed in the RF interface opening area of ​​the chassis, serving as the external RF interface for direct connection to external RF cables. When it is necessary to adjust the number of RF channels (from 1 transmit / receive to 4 transmit / receive), connector arrangement, or RF interface type, only the corresponding RF daughterboard needs to be replaced. As long as the daughterboard size, socket resources, power supply, clock, heat dissipation, and processing capacity are within the reserved range, there is no need to redesign the chassis body and central data board. This structure eliminates the traditional chassis-built-in RF adapters and cables, significantly reducing signal insertion loss, VSWR, and assembly errors, and simplifying internal wiring.

[0038] Working principle of heat dissipation system: The chassis cooling water platform is positioned in a fixed location. The main heat-generating chips (MPSoC, Phytium processor, RF transceiver chip) of the real-time processing daughterboard, RF daughterboard, and CPU core board are arranged in a pre-defined heat dissipation area and are tightly attached to the cooling water platform through thermal pads, thermal blocks, and heat spreaders. Regardless of the performance level of the daughterboard being replaced, the same chassis cooling structure can be used, eliminating the need for resimulation and redesign of the cooling system.

[0039] This embodiment also fully elaborates on the hardware division of labor, signal processing flow, and task boundaries for the enhanced computing main control configuration, adapting to 5~30MHz full-bandwidth radar signal processing scenarios (such as...). Figure 4 (As shown).

[0040] Architecture and task allocation: The entire device is equipped with a real-time processing daughterboard, an RF daughterboard, and a CPU core board. The Phytium D3000M CPU core board serves as the main controller for the entire device. The MPSoC is divided into PL side and PS side for collaborative operation. MPSoC-PL side: Dedicated to high-speed real-time preprocessing, including low-level signal processing such as AD data alignment, frame synchronization, digital downconversion, FIR filtering, channelization, amplitude and phase correction, pulse compression, and FFT spectrum estimation; MPSoC-PS side (ARM system): Only responsible for low-level hardware control, including RF daughterboard parameter configuration, turntable control, hardware status acquisition, and fault reporting, and does not participate in complex algorithm calculations.

[0041] Phytium D3000M CPU core board: runs the operating system and upper-layer software, and is responsible for system control, task scheduling, complex algorithm processing (Doppler processing, clutter suppression, CFAR detection, point convergence, target angle measurement), data management, human-computer interaction, image display and data storage.

[0042] The complete workflow is as follows: Signal reception stage: External RF signal → RF daughterboard SMA interface → RF frequency conversion → LTC2209 AD sampling → Second function socket LVDS channel → MPSoC-PL side; Real-time preprocessing stage: The PL side completes the raw data processing, digital down-conversion, and pulse compression to generate L2 level pulse compressed data; Data upload phase: According to the radar mission mode, the corresponding level data is uploaded to the CPU core board through the PCIe Gen3×4×2 channel; Complex processing stage: After receiving data, the CPU core board completes complex calculations such as Doppler processing, CFAR detection, and point aggregation. Parameter write-back stage: The CPU combines user instructions, the processing time per frame, and system load to generate control parameters and send them back to MPSoC; Status feedback phase: MPSoC receives parameters and performs handshake confirmation, which takes effect in the next frame period, and at the same time returns the hardware status to the CPU.

[0043] This configuration supports 5~30MHz wideband radar signal processing and is suitable for full-function operation modes of target detection radar and weather radar.

[0044] This embodiment also describes the architecture, task flow, bandwidth limitations, and application scenarios for a lightweight main control configuration (without installing a CPU core board), highlighting its advantages of lightweight design, low power consumption, and miniaturization (e.g., ...). Figure 5 (As shown).

[0045] Architecture and task allocation: The entire device only has a real-time processing daughterboard and an RF daughterboard installed; the third function socket is left unused and covered with a protective cover; the MPSoC's internal ARM processing system (PS side) serves as the sole controller for the entire device. MPSoC-PL side: It still undertakes all high-speed real-time preprocessing work, and its functions remain consistent with the enhanced configuration; MPSoC-PS side (ARM system): It combines hardware control, system main control, and basic signal processing, including RF configuration, status monitoring, turntable control, basic CFAR detection, spot aggregation, and simple data output.

[0046] Work restrictions and operating procedures: Bandwidth limitation: This configuration only supports narrowband radar signal processing of 5~10MHz. When the signal bandwidth exceeds 10MHz, the computing power cannot support it and it must be switched to an enhanced computing configuration. Data processing flow: After the radio frequency signal is sampled by the AD converter, the PL side performs preprocessing and generates L3 level Doppler spectrum data; it is then directly uploaded to the local ARM system, where the ARM performs simple target detection and data output. Control logic: The ARM system completes parameter adjustment and status management locally, eliminating cross-board high-speed parameter interaction and simplifying the process.

[0047] This configuration is designed for lightweight, low-power, and miniaturized airborne platforms, and is suitable for UAV-borne simple detection radars and small weather radars.

[0048] In this embodiment, the platform supports online, power-free switching between enhanced computing main control configuration and lightweight main control configuration, enabling the handover of control without physically disassembling the CPU core board. It is adaptable to various airborne scenarios, including low power consumption and fault tolerance, and specifically includes three operating modes: Normal master control mode: In the enhanced computing configuration, the CPU core board, as the system master control, undertakes all complex algorithms and task scheduling functions, while the real-time processing daughter board PS side is in standby mode, only responsible for low-level hardware control and status reporting; the CPU core board and MPSoC PS side maintain periodic heartbeat interaction through the PCIe link.

[0049] Low-power switching mode: When the system enters standby, cruise or light-load task phase, the CPU core board sends a master control handover command to the MPSoCPS side. After completing the current frame data processing and context handover, the CPU core board enters a low-power sleep state. The MPSoCPS side takes over the system master control, and the platform automatically switches to a lightweight master control configuration, maintaining only basic detection and data output capabilities, significantly reducing the overall power consumption.

[0050] Fault degradation mode: When the heartbeat interaction times out or the CPU core board goes offline abnormally, the real-time processing daughter board PS side automatically takes over the system master control within a single frame cycle. The platform seamlessly degrades to a lightweight master control configuration, maintaining uninterrupted RF configuration, basic signal processing and data output functions, avoiding the complete termination of the detection task due to master control failure in airborne scenarios; after the CPU core board returns to normal, it automatically completes the return of master control and task continuation.

[0051] Specifically, regarding the expansion capabilities of the RF interface opening area and modular RF daughterboard, the complete process and principle of upgrading a 1-receive-1-transmit channel to a 4-receive-4-transmit channel are explained.

[0052] Initial configuration: The platform is originally configured with a single-channel RF sub-board, implementing a 1-receive and 1-transmit RF channel. The RF connector is a single SMA interface, which is compatible with conventional single-channel airborne radar.

[0053] Expansion operation procedure: After power failure, the original single-channel RF daughterboard can be removed without disassembling the chassis, central data board, cables, or cooling water platform. Replace with a 4-receive, 4-transmit multi-channel RF daughterboard, and align the daughterboard connector with the second function socket to complete the connection. The four sets of SMA connectors on the multi-channel RF daughterboard are naturally exposed in the RF interface opening area, serving directly as the external RF interface of the whole machine; After power-on, MPSoC automatically identifies the new RF daughterboard channel configuration, completes parameter adaptation, and the expansion is complete.

[0054] Principle: Adjusting the number of RF channels only depends on hardware changes to the RF daughterboard. The chassis, central data board, interfaces, heat dissipation, and power supply are all reused, and all modifications are completed within the preset resource range.

[0055] Furthermore, to better illustrate the serialized development of multiple airborne radar products by replacing different sub-boards, based on the same chassis and the same central data board, the differentiated configurations are as follows.

[0056] Unified basic platform: The entire chassis, central data board, universal external interfaces, cooling platform, and installation structure remain completely unchanged, serving as a universal basic platform.

[0057] Differentiated configuration options: Small and lightweight airborne radar: equipped with a narrowband RF daughterboard and a basic MPSoC real-time processing daughterboard, without installing a CPU core board, adopting a lightweight main control configuration, used for small UAV reconnaissance and detection. Conventional airborne target radar: Equipped with a 4-receive 4-transmit bandwidth RF daughterboard + standard MPSoC + Phytium D3000M CPU core board, adopting an enhanced configuration, for routine detection of manned aircraft; Airborne meteorological radar: Equipped with a dedicated meteorological radio frequency sub-board, a high-bandwidth real-time processing sub-board, and a CPU core board, with optimized meteorological algorithm configuration, it is used for aviation meteorological observation.

[0058] Example 2 Based on the modular heterogeneous real-time processing platform for airborne radar provided in Embodiment 1 of this application, Embodiment 2 of this application also provides an airborne radar data collaboration method based on this platform, such as... Figure 6 As shown, it includes the following steps: The real-time processing subboard divides radar data into multiple levels according to the processing depth of the data in the processing link, and completes the preprocessing of radar data of the corresponding level. Based on the current radar type, mission mode, and platform main control configuration, select the corresponding data level and upload it to the platform main control unit; The platform's main control unit, in conjunction with the system's operating status and user commands, writes back control parameters to the real-time processing sub-board. After the real-time processing sub-board receives and confirms the control parameters, the changes take effect in the next frame data processing cycle, adjusting the data preprocessing parameters, data upload level, and caching strategy.

[0059] This embodiment, combining 7-level data hierarchy, dual control logic, different radar types, and host computer scenarios, fully illustrates the data collaboration closed-loop process and is the core implementation example of the method section of this embodiment.

[0060] Data grading basic rules: Radar data is divided into seven levels, L0 to L6, based on processing depth. The amount of data decreases sequentially from L0 (maximum) to L6 (minimum). The real-time processing sub-board generates data as needed based on the task and selectively uploads it, avoiding the uploading of all raw data.

[0061] Scenario-based operation flow: Scenario 1: Target Detection Radar Enhanced computing configuration (5~30MHz bandwidth): The search task involves the PL side generating L2 level pulse compression data and uploading it to the CPU; the CPU then performs Doppler processing, CFAR, point aggregation, and angle measurement. Once the target is locked during the tracking task, the PL side generates L3 level Doppler spectrum data and uploads it, reducing the amount of data transmitted and improving the real-time performance of tracking.

[0062] Lightweight configuration (5~10MHz bandwidth): The system generates L3-level Doppler spectrum data in a unified manner, and the on-board ARM system completes simple CFAR and spot aggregation, with a simple process and low latency.

[0063] Scenario 2: Weather Radar Enhanced computing configuration: Fixed upload of L2 level pulse compression data, with the CPU performing meteorological parameter inversion and meteorological product generation; Lightweight configuration: Directly generate L4 level basic parameter data and upload it to ARM, outputting basic meteorological observation results.

[0064] Scenario 3: External host computer scenario Regardless of the main control configuration, users can choose to upload L0-level raw sampling data or L1-level distance gate data to the host computer, which will then complete the entire offline analysis and algorithm debugging process. The platform is only responsible for data acquisition and forwarding.

[0065] In this embodiment, multi-dimensional sub-regional differentiated hierarchical uploading of single-frame data is supported to adapt to the echo characteristics differences of airborne radar at different distance gates, different beam directions, and different scanning sectors.

[0066] Region division can be performed according to range gate, beam direction, scanning sector, or target area: for example, on the range gate, the close-range strong clutter band is divided into the first data sub-region, and the long-range target detection band is divided into the second data sub-region; on the scanning sector, the key tracking sector is divided into the high-priority sub-region, and the remaining airspace is divided into the regular sub-region.

[0067] Within the same frame, different data sub-regions can have their data upload levels set independently: for example, L2-level pulse compression data is uploaded to near-field clutter areas for the CPU to perform fine clutter suppression; L4-level basic parameter data is uploaded to far-field open areas to compress the transmission volume; and L3-level Doppler spectrum data is uploaded to key target areas to ensure tracking accuracy. The data frame header carries sub-region division identifiers, the start and end positions of each region, and corresponding data level labels. The main control unit parses and processes the data in segments according to the data sub-regions.

[0068] This mechanism significantly reduces data transmission volume and backend computing load in non-critical areas while ensuring processing performance in critical areas. Compared with the unified grading mode for the entire frame, the overall bandwidth usage can be reduced by more than 30%.

[0069] Dual-control write-back closed-loop process: Manual control logic (first control logic): The operator manually issues adjustment commands based on the requirements of radar echo quality, signal-to-noise ratio, clutter intensity, and detection sensitivity; adjustable parameters include: radar operating bandwidth, pulse coherent accumulation time, number of FFT points, MTI switch, number of CFAR units, and CFAR calculation mode.

[0070] Automatic control logic (second control logic): The CPU core board monitors the processing time of each frame of data in real time and determines whether it meets the radar's preset real-time performance indicators; if the processing times out or the load is too high, it automatically lowers the data upload level and simplifies the preprocessing parameters to reduce the system load.

[0071] Response and Activation Mechanism: After receiving control parameters, the real-time processing sub-board immediately returns a handshake confirmation signal to the main control unit; the parameters do not take effect immediately, but wait for the next frame data processing cycle to load and execute them uniformly, ensuring radar frame synchronization and timing stability.

[0072] In this embodiment, the issuance and execution of control parameters adopt a strict frame synchronization mechanism, and the specific rules are as follows: Each set of control parameters issued by the platform's main control unit comes with a specified effective frame number. After the real-time processing sub-board receives the parameters and confirms them via handshake, it does not immediately modify the operating parameters. Instead, it completes the register configuration switch uniformly within the pulse blanking period of the specified frame to avoid data breaks and timing chaos caused by parameter changes in the middle of the pulse cycle.

[0073] Each output data frame header carries a current parameter version tag. The tag includes the version number of key parameters such as working bandwidth, FFT points, and CFAR configuration. The backend processing unit can match the corresponding algorithm logic according to the version tag to achieve traceability of data and processing parameters.

[0074] For large-scale adjustments exceeding the corresponding parameter thresholds (such as changing the FFT points from 1024 to 4096 or the operating bandwidth from 5MHz to 30MHz), the system automatically activates a multi-frame gradual transition mode: the parameter change is evenly distributed across N consecutive frames, with adjustments made frame by frame. This avoids jumps in processing results and loss of target tracking caused by a full switch in a single frame, ensuring the continuity of output data and tracking stability. Typically, the FFT point rate change threshold is set to 2 times, the bandwidth change threshold is set to 10MHz, and the number of gradual transition frames is set to 4.

[0075] In this embodiment, a dynamic load scheduling mechanism is adopted under the enhanced computing master control configuration to break the fixed heterogeneous processing division boundary and realize the elastic allocation of computing resources.

[0076] The CPU core board monitors its own CPU computing load rate and PCIe link bandwidth utilization rate in real time, using frames as the cycle, and presets high thresholds (such as 80%) and low thresholds (such as 40%).

[0077] When either the computational load or bandwidth utilization exceeds a high threshold, the CPU sends a task offload instruction to the real-time processing subboard, offloading some parallelizable back-end processing algorithms (such as CFAR detection, point aggregation, and amplitude-phase correction) to the PL side of the real-time processing subboard for execution. At the same time, the data upload level is upgraded from L2 / L3 to L4 / L5 to reduce the amount of data transmitted and reduce the computational pressure on the CPU side.

[0078] When both the computational load and bandwidth utilization are below the low threshold, the CPU reclaims the devolved processing tasks, the data upload level drops back to the original level, and the CPU performs more complex algorithm processing to ensure detection performance.

[0079] This mechanism can dynamically adjust the division of heterogeneous computing power according to the real-time load, make full use of the advantages of FPGA parallel computing, and improve the system's real-time processing capability and computing power utilization in high-load scenarios.

[0080] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computing software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0081] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0082] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A modular heterogeneous real-time processing platform for airborne radars, characterized in that, include: The central data board, as the fixed support unit of the whole machine, integrates a general external interface, a power management module, a clock distribution module, a high-speed data conversion module, a low-speed control module, as well as a first function socket, a second function socket, and a third function socket. The real-time processing sub-board is detachably connected to the first functional socket and uses an FPGA chip or MPSoC chip to complete high-speed data access and real-time preprocessing. The radio frequency daughterboard is detachably connected to the second functional socket and is used to adapt to radar front-ends with different frequency bands, bandwidths, polarization methods, transceiver systems, or number of channels. The CPU core board is detachably added to or replaced in the third functional socket for performing complex processing, task scheduling, data management, display and storage under the enhanced computing configuration; The chassis body, its shape, internal load-bearing structure, general external interface positions, mounting hole positions and heat sink positions are all fixed, and RF interface opening areas are set at the corresponding RF daughterboard positions; The platform supports switching between a lightweight main control configuration and an enhanced computing main control configuration. In the lightweight main control configuration, the internal ARM processing system of the MPSoC chip in the real-time processing subboard serves as the platform main control. In the enhanced computing main control configuration, the CPU core board is installed as the platform main control.

2. The modular heterogeneous real-time processing platform of claim 1, wherein, The RF daughterboard integrates an RF connector, which is exposed in the RF interface opening area and directly constitutes the external RF interface of the whole machine. The RF daughterboard connects to external RF signals through its integrated RF connector. The second functional socket integrates multiple analog-to-digital signal transmission channels and digital-to-analog signal transmission channels. The analog-to-digital and digital-to-analog signals between the RF daughterboard and the real-time processing daughterboard are transmitted through the second functional socket. When it is necessary to adjust the number of RF channels, the arrangement of RF connectors, or the form of RF interface, the adjustment can be completed by replacing the RF sub-board with a different configuration within the allowable range of the RF interface opening area, the size of the RF sub-board, and the pre-configured socket resources, power supply resources, clock resources, heat dissipation resources, and processing resources of the system.

3. The modular heterogeneous real-time processing platform of claim 1, wherein, When the real-time processing subboard uses an MPSoC chip, it includes a programmable logic (PL) side and a processing system (PS) side. The PL side undertakes high-speed real-time preprocessing functions in both the lightweight main control configuration and the enhanced computing main control configuration. The PS side, in a lightweight main control configuration, serves as the platform's main control, completing RF daughterboard configuration, system status monitoring, working mode management, and basic data processing. The PS side undertakes the underlying hardware control functions under the enhanced computing main control configuration, while the CPU core board, as the platform main controller, undertakes complex algorithm processing, task scheduling, data management, display, and storage functions.

4. The modular heterogeneous real-time processing platform according to claim 1, characterized in that, The first functional socket, the second functional socket, and the third functional socket are all composed of multiple high-speed connectors; The first functional socket is used to transmit power, clock, and low-speed control signals. It communicates with the real-time processing daughterboard via PCIe through a high-speed serial channel, and transmits ADC input signals from the RF daughterboard via LVDS and DAC output signals to the RF daughterboard via a high-speed serial channel. The second functional socket is used to transmit power, clock, and control I / O signals, enabling ADC / DAC signal transmission between the RF sub-board and the real-time processing sub-board; The third functional socket is used to transmit power, clock, and I / O signals, and enables PCIe communication with the CPU core board through a high-speed serial channel.

5. The modular heterogeneous real-time processing platform according to claim 1, characterized in that, The position of the heat sink in the chassis remains fixed, and the heat-generating components of each detachable sub-board are connected to the corresponding heat sink through heat-conducting blocks, heat-conducting pads, or heat spreaders; when replacing CPU core boards, real-time processing sub-boards, or RF sub-boards of different performance levels, they share the same chassis heat dissipation structure.

6. An airborne radar data collaboration method, implemented through a modular heterogeneous real-time processing platform for airborne radar as described in claim 1, characterized in that, Includes the following steps: The real-time processing subboard divides radar data into multiple levels according to the processing depth of the data in the processing link, and completes the preprocessing of radar data of the corresponding level. Based on the current radar type, mission mode, and platform main control configuration, select the corresponding data level and upload it to the platform main control unit; The platform's main control unit, in conjunction with the system's operating status and user commands, writes back control parameters to the real-time processing sub-board. After the real-time processing sub-board receives and confirms the control parameters, the changes take effect in the next frame data processing cycle, adjusting the data preprocessing parameters, data upload level, and caching strategy.

7. The airborne radar data coordination method according to claim 6, characterized in that, The radar data is divided into 7 levels, from L0 to L6, specifically: L0 level: Raw sampled data, which is the ADC output or the raw I / Q data or real sampled data after interface processing, generated by AD sampling, data alignment, frame synchronization and channel processing; L1 level: Distance gate data, which is data processed by pulse, channel and distance unit, generated by raw sampling, digital down-conversion, decimation filtering and distance gate division; L2 level: Pulse compressed data, which is multi-channel data after filtering, digital downconversion or frequency band division, generated by digital downconversion, FIR filtering, channelization, amplitude and phase correction and pulse compression. L3 level: Doppler spectral data, which is the spectral data after spectral estimation of a specified distance gate or channel, and generated by windowing, FFT, spectral averaging and amplitude calculation; Level L4: Basic parameter data, which are basic measurement parameters extracted from spectral data or distance gate data, generated through peak search, threshold detection, parameter estimation, and statistical averaging. Level L5: Structured feature data, which is target, environment or echo feature data for backend algorithms or display, generated through feature extraction, target or region aggregation and data packaging; Level L6: Displays compressed data, which is extracted, compressed, or reduced-dimensional data for real-time display or low-bandwidth transmission. It is generated through downsampling, grayscale or pseudo-color mapping, compression encoding, and frame rate control.

8. The airborne radar data coordination method according to claim 6, characterized in that, The platform's main control unit uses dual control logic to write back control parameters to the real-time processing sub-board: First control logic: The user manually adjusts the radar operating parameters and processing parameters based on the detection results, echo quality, detection sensitivity, signal-to-noise ratio, and clutter conditions; Second control logic: The CPU core board automatically adjusts the radar operating parameters and processing parameters based on whether the processing time of each frame meets the preset real-time requirements; The adjustable parameters include radar operating bandwidth, pulse coherent accumulation time, number of FFT points, MTI switch, number of various CFAR elements, and CFAR calculation mode; The issued control parameters are accompanied by a specified effective frame number. The real-time processing sub-board completes the parameter switching within the pulse blanking area of ​​the corresponding frame. Each frame output data carries the current parameter version tag. For parameter changes that exceed the corresponding parameter's set threshold, a multi-frame gradual transition mode is used to adjust the processing parameters step by step. After receiving and confirming the control parameters, the real-time processing sub-board returns status information to the platform main control unit.

9. The airborne radar data coordination method according to claim 7, characterized in that, The real-time processing sub-board divides a single frame of radar data into multiple data sub-regions based on the range gate, beam direction, scanning sector, or target area. Different data sub-regions within the same frame correspond to different data levels and are mixed and uploaded. The data frame header carries a sub-region division identifier and a corresponding data level label, which the platform's main control unit parses and processes separately according to the data sub-regions.

10. The airborne radar data coordination method according to claim 6, characterized in that, In the enhanced computing main control configuration, the CPU core board monitors its own computing load and high-speed interconnect bandwidth utilization in real time; When the computing load or high-speed interconnect bandwidth utilization exceeds the preset threshold, a task offload command is sent to the real-time processing sub-board to offload some back-end processing algorithms to the real-time processing sub-board for execution, and the data upload level is upgraded simultaneously. When both the computing load and the high-speed interconnect bandwidth utilization rate are below the preset threshold, the corresponding processing task is revoked, and the data upload level drops back to the original level.

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