Method and apparatus for transmitting serial data streams

Abstract

This application relates to methods and apparatus for transmitting serial data streams. Example apparatus includes: a filter circuit system (720) having a first output and a second output; a source follower circuit system (730) having a first input, a second input, and an output, the first input of the source follower circuit system being coupled to the first output of the filter circuit system, and the second input of the source follower circuit system being coupled to the second output of the filter circuit system; a resistor (740) having a first terminal and a second terminal; a load circuit system (460) having an input and an output, the input of the load circuit system being coupled to the output of the source follower circuit system and the first terminal of the resistor; and a combination circuit system (470) having a first input and a second input, the first input of the combination circuit system being coupled to the second terminal of the resistor, and the second input of the combination circuit system being coupled to the output of the load circuit system.

Description

Technical Field

[0001] This specification generally relates to transmitter circuit systems, and more specifically, to methods and apparatus for transmitting serial data streams. Background Technology

[0002] In a communication system, multiple devices exchange data by transmitting and receiving signals. Such devices comprise transmitter circuitry and receiver circuitry. The transmitter circuitry transmits signals across the communication channel to the receiver circuitry of another device. In a full-duplex communication system, multiple devices can simultaneously transmit signals along the communication channel. In operation, the transmitter circuitry of different devices uses additional circuitry to support simultaneous communication. Summary of the Invention

[0003] For a method and apparatus for transmitting a serial data stream, one example apparatus includes: a filter circuit system having a first output and a second output; a source follower circuit system having a first input, a second input, and an output, the first input of the source follower circuit system being coupled to the first output of the filter circuit system, and the second input of the source follower circuit system being coupled to the second output of the filter circuit system; a resistor having a first terminal and a second terminal; a load circuit system having an input and an output, the input of the load circuit system being coupled to the output of the source follower circuit system and the first terminal of the resistor; and a combination circuit system having a first input and a second input, the first input of the combination circuit system being coupled to the second terminal of the resistor, and the second input of the combination circuit system being coupled to the output of the load circuit system. Other examples are described.

[0004] For a method and apparatus for transmitting a serial data stream, one example apparatus includes: a receiver circuit system having an input; a transmitter circuit system having a first output, a second output, a third output, and a fourth output; and an echo cancellation circuit system including: a load circuit system having a first input, a second input, a first output, and a second output, the first input of the load circuit system coupled to the first output of the transmitter circuit system, the second input of the load circuit system coupled to the second output of the transmitter circuit system; and a combination circuit system having a first input, a second input, a third input, a fourth input, and an output, the first input of the combination circuit system coupled to the third output of the transmitter circuit system, the second input of the combination circuit system coupled to the fourth output of the transmitter circuit system, the third input of the combination circuit system coupled to the first output of the load circuit system, the fourth input of the combination circuit system coupled to the second output of the load circuit system, and the output of the combination circuit system coupled to the input of the receiver circuit system. Other examples are described.

[0005] For a method and apparatus for transmitting a serial data stream, an example apparatus includes: a first transmitter circuit system having an output; a communication channel having a first terminal and a second terminal, the first terminal of the communication channel being coupled to the output of the first transmitter circuit system; a second transmitter circuit system having a first output and a second output; an echo cancellation circuit system having a first input, a second input, and an output, the first input of the echo cancellation circuit system being coupled to the first output of the second transmitter circuit system, the second input of the echo cancellation circuit system being coupled to the second terminal of the communication channel and the second output of the second transmitter circuit system; and a receiver circuit system having an input coupled to the output of the echo cancellation circuit system. Other examples are described. Attached Figure Description

[0006] Figure 1 It is a block diagram of an example vehicle that includes an example Advanced Driver Assistance System (ADAS) system and an example In-vehicle Infotainment (IVI) system.

[0007] Figure 2 It includes example deserializer circuit systems and example serializer circuit systems. Figure 1 A block diagram of an example ADAS system.

[0008] Figure 3 It includes example serializer circuit systems and example deserializer circuit systems. Figure 1 A block diagram of an example IVI system.

[0009] Figure 4 It includes an example backward channel transmitter circuit system. Figure 2 and 3 A block diagram of an example of a serializer circuit system.

[0010] Figure 5 It includes an example forward channel transmitter circuit system. Figure 2 and 3 A block diagram of an example serializer circuit system.

[0011] Figure 6 It includes Figure 2 , 3 Block diagrams of example serializer and deserializer circuit systems of numbers 4 and 5, which may be referred to as serial-deserializer (SerDes) systems.

[0012] Figure 7 yes Figure 4 and 6 A block diagram of an example of a backward channel transmitter circuit system.

[0013] Figure 8 It includes an example AC coupler circuit system, an example filter circuit system, and an example source follower circuit system. Figure 4 , 5 Schematic diagrams of example backward channel transmitter circuit systems for 6 and 7.

[0014] Figure 9 yes Figure 8 A schematic diagram of an example AC coupler circuit system.

[0015] Figure 10 It means that it can be used. Figure 4 , 5 Flowcharts of example machine-readable instructions or example operations executed, instantiated, and / or performed in example implementations of the backward channel transmitter circuit systems of 6, 7, 8, and 9.

[0016] Figure 11A and 11B yes Figure 4 , 5 Graphs showing example operations of the backward channel transmitter circuit systems of 6, 7, and 8.

[0017] Figure 12 yes Figure 5 and 6 A block diagram of an example forward channel transmitter circuit system.

[0018] Figure 13 yes Figure 5 , 6A schematic diagram of an example of a forward channel transmitter circuit system of 12.

[0019] Figure 14 yes Figure 5 , 6 A schematic diagram of another example of the forward channel transmitter circuitry system of 12 and 13.

[0020] Figure 15 It means that it can be used. Figure 5 , 6 Flowcharts of example machine-readable instructions or example operations executed, instantiated, and / or performed in example implementations of the forward channel transmitter circuit systems of 1, 12, 13, and 14.

[0021] Figure 16 yes Figure 5 , 6 Graphs showing example operation of the forward channel transmitter circuit systems 12, 13, and 14.

[0022] The accompanying drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and this specification refer to the same or similar features and / or parts (functionally and / or structurally). Although the drawings show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be invisible, mixed, or irregular. Detailed Implementation

[0023] In a communication system, multiple devices exchange data by transmitting and receiving signals. Such devices comprise transmitter circuitry and receiver circuitry. The transmitter circuitry transmits signals across the communication channel to the receiver circuitry of another device. In a full-duplex communication system, multiple devices can simultaneously transmit signals along the communication channel. In operation, the transmitter circuitry of different devices uses additional circuitry to support simultaneous communication.

[0024] Transmitter circuitry uses driver circuitry to drive the communication channel. One type of driver circuitry is the source-series-terminated (SST) driver circuitry. An SST driver circuitry includes an inverter, a resistor-capacitor (RC) filter, a high-side transistor, a high-side resistor, a low-side transistor, and a low-side resistor. The inverter drives the RC filter by inverting the digital input signal. The RC filter controls the high-side and low-side transistors in response to the inverted digital input signal. The high-side transistor and resistor pull up the communication channel in response to a logic one (e.g., logic high) of the digital input signal, which is equivalent to an inverted logic zero (e.g., logic low). The low-side transistor and resistor pull down the communication channel in response to a logic zero (e.g., an inverted logic one) of the digital input signal.

[0025] In operation, the transconductance of the high-side transistor and the resistance of the high-side resistor are matched to the communication channel impedance. Similarly, the transconductance of the low-side transistor and the resistance of the low-side resistor are configured to match the communication channel impedance. However, return loss depends on the load parasitics of the communication channel as a response to the impedance matching between the high-side and low-side transistors. Furthermore, process variations between the high-side and low-side components create a mismatch between the rise and fall times of the transmitted signal. This mismatch leads to transmission distortion.

[0026] Another type of driver circuit system is the current-mode logic (CML) driver circuit system. A CML driver circuit system includes a resistor-capacitor (RC) filter for controlling a pair of transistors. The pair of transistors drives the communication channel by drawing current from a load resistor. For example, the transistors pull down the communication channel in response to drawing current through the load resistor. Alternatively, the load resistor pulls up the communication channel in response to a lack of current through the transistors.

[0027] In operation, the load resistor is configured to match the impedance of the communication channel. However, when the transistor pulls down the communication channel, the impedance matching changes through a change in the transistor's impedance in response to the magnitude of the absorbed current. This change in impedance of the CML driver circuitry in response to a non-ideal impedance match distorts the transmitted signal. Furthermore, the difference in impedance between the transistor and the load resistor creates a mismatch between the rise and fall times of the transmitted signal.

[0028] Some CML driver circuit systems contain multiple pairs of transistors coupled in parallel to drive a load resistor. These pairs of transistors perform feedforward equalization (FFE). During transmission logic one, the CML driver circuit system sequences the turn-off of each pair of transistors to form an amplitude gradient over time. This gradient of amplitude over time adds a high-frequency component to the transmitted signal, which can be attenuated by the communication channel, resulting in a steep attenuation. This gradient of the amplitude of the digital pulse used for transmission over time is called FFE.

[0029] In operation, a steep roll-off reduces bit errors in the receiver circuitry and improves inter-symbol interference (ISI). However, return loss is limited by the parasitic capacitance of multiple pairs of parallel transistors. To compensate for high-frequency return loss, some designs incorporate inductors between the load resistor and the communication channel. Such inductors increase the size of the system-on-chip (SoC) and the implementation cost of the freeform field (FFE). Furthermore, the sequencing of transistor current sinking during transistor pair turn-off increases the mismatch between rise and fall times in response to changes in pull-down impedance.

[0030] In both CML and SST driver circuit systems, the transition between the rising and falling edges is distorted due to the transition of high-side and low-side components from impedance matching. This distortion limits the linearity of the transmitter circuit system. In some designs, the limited linearity of the transmitter circuit system may restrict different signaling methods, such as pulse amplitude modulation (PAM) signaling. In full-duplex communication systems, CML and SST driver circuit systems may need to sink and supply current to support simultaneous communication. In such systems, the current from simultaneous communication may create a bias, thereby distorting the output impedance of the CML and SST driver circuit systems.

[0031] In full-duplex communication systems, some devices also include an echo cancellation circuitry, which removes the transmitted signal, such as the signal of the communication channel, from the main signal path. The echo cancellation circuitry provides the remainder of the communication signal to the receiver circuitry. In operation, this remainder represents data transmitted across the communication channel by another device. The echo cancellation circuitry improves signal integrity by reducing the contribution of the transmitted signal to the signal at the input of the receiver circuitry.

[0032] Some devices use a primary transmitter circuitry and a secondary transmitter circuitry to implement echo cancellation. The primary transmitter circuitry transmits signals by driving a communication channel. The secondary transmitter circuitry contains an internal termination circuitry that replicates the impedance of the communication channel. The secondary transmitter circuitry generates a copy of the signal transmitted by the primary transmitter circuitry in response to driving the internal termination circuitry.

[0033] However, impedance mismatch between the internal termination circuitry and the communication channel can degrade echo cancellation. For example, at relatively high frequencies, the impedance of the communication channel attenuates the signal strength. In such examples, the receiver circuitry amplifies the communication signal to compensate for the attenuation along the communication channel. The receiver circuitry may amplify a portion of the transmitted signal in response to impedance mismatch between the termination circuitry and the communication channel. Furthermore, process variations between the primary and secondary transmitter circuitries further increase the inaccuracy of echo cancellation.

[0034] The examples described herein include methods and apparatus for transmitting serial data streams. In some of the described examples, the apparatus supporting full-duplex communication includes a transmitter circuit system, an echo cancellation circuit system, and a receiver circuit system. In such examples, the transmitter circuit system further includes an AC coupler circuit system, a filter circuit system, a source follower circuit system, and a resistor. The transmitter circuit system drives the communication channel and generates a copy of the transmitted signal. In operation, the AC coupler circuit system sets the common-mode voltage of the digital input signal. Furthermore, the AC coupler circuit system can scale (e.g., attenuate, amplify, etc.) the digital input signal. For example, the AC coupler circuit system can scale multiple digital input signals to implement PAM signaling. The filter circuit system is a second-order filter that converts the AC-coupled digital signal into a sinusoidal signal. The source follower circuit system uses a positive feedback path to control the cross-coupled transistor, thereby reducing impedance loss caused by parasitic capacitance in the communication channel. The source follower circuit system includes additional capacitors to increase impedance matching across a larger bandwidth. Furthermore, the positive feedback path of the source follower circuit system compensates for the current during simultaneous communication to maintain output impedance and signal integrity. The source follower circuit system provides the load transistor current to drive the communication channel.

[0035] The echo cancellation circuit system further comprises an impedance matching circuit system and a combinational circuit system. The impedance matching circuit system is coupled to the output of the source follower circuit system. Advantageously, the positive feedback path of the source follower circuit system compensates for the additional load of the impedance matching circuit system. The impedance matching circuit system generates a copy of the transmitted signal in response to the scaling of the transmitted signal by the load resistor of the matching transmitter circuit system. The combinational circuit system subtracts the copy of the transmitted signal from the signal of the communication channel. Advantageously, the transmitter circuit system allows the echo cancellation circuit system to remove the transmitted signal from the signal of the communication channel without a copy transmitter. Advantageously, using the copy from the transmitter circuit system reduces mismatch in echo cancellation. Advantageously, using the copy from the transmitter circuit system reduces the system-on-chip (SoC) size of the echo cancellation circuit system in response to the elimination of the need for a secondary transmitter.

[0036] In other described examples, the transmitter circuitry includes multiple FFE segments, cross-coupled transistors, and load resistors. In such examples, the multiple FFE segments further include a capacitor divider, bias resistors, and transistor pairs. In operation, the capacitor divider divides the amplitude of the digital input signal to set the step weight of the amplitude of each FFE segment. The transistors draw current from the cross-coupled transistors in response to the step amplitude of the digital input signal.

[0037] Cross-coupled transistors isolate the capacitance of the plurality of FFE segments by forming a virtual ground. The virtual ground provides nodes (e.g., terminals) for current combination of the plurality of FFE segments without altering the voltage of the communication channel. The cross-coupled transistors draw current from a load resistor to pull down the communication channel. Alternatively, the load resistor pulls up the communication channel in response to a lack of current from the resistor. Advantageously, the cross-coupled positive feedback loop enables active impedance compensation and rise / fall time matching without compromising speed or FFE tunability.

[0038] Figure 1 This is a block diagram of an example vehicle 100 including an example Advanced Driver Assistance System (ADAS) 105 and an example In-vehicle Infotainment (IVI) system 110. The ADAS system 105 and IVI system 110 may be referred to as a flat panel display (FPD) link system, which can display media such as images, multimedia content, etc. In some examples, vehicle 100 may include one or more instances of ADAS system 105 or IVI system 110. For example, vehicle 100 may include one or more instances of ADAS system 105 but not IVI system 110. In another example, vehicle 100 may include one or more instances of IVI system 110 but not ADAS system 105. In yet another example, vehicle 100 may include one or more instances of ADAS system 105 and one or more instances of IVI system 110. Figure 1 In the example, vehicle 100 is shown as a system for traversing distances, such as a car, truck, etc. Alternatively, vehicle 100 may replace, be shown, or described as an alternative distributed display system, such as a ship, aircraft, spacecraft, workstation, control panel, etc.

[0039] Figure 1 The ADAS system 105 includes an example ADAS hub 115, a first example peripheral module 120, a second example peripheral module 125, a third example peripheral module 130, a fourth example peripheral module 135, and an example display 140. Alternatively, the ADAS system 105 may include any number of peripheral modules or displays.

[0040] ADAS system 105 is an example type of FPD link system that uses serialized and deserialized data to assist driving in vehicle 100. In some examples, ADAS system 105 uses serialized and deserialized media to alternatively implement data processing, storage, or display, such as safety systems, recording systems, etc. In some examples, ADAS system 105 is an example camera system that facilitates at least one of the storage, processing, or display of multimedia data (e.g., images, videos, etc.) from one or more sensors, such as cameras. In other examples, ADAS system 105 may facilitate at least one of the storage, processing, or display of alternative types of data from one or more alternative types of sensors (e.g., lidar, radar, ultrasound, etc.). Examples of ADAS system 105 combined... Figure 2 Further illustration and description.

[0041] ADAS hub 115 is communicatively coupled to peripheral modules 120, 125, 130, 135 and display 140. ADAS hub 115 uses full-duplex communication to transmit and receive data from peripheral modules 120, 125, 130, 135. In some examples, ADAS hub 115 uses low-voltage differential communication (LVDS) to communicate with peripheral modules 120, 125, 130, 135. Alternatively, ADAS hub 115 can use alternative types of communication to communicate with peripheral modules 120, 125, 130, 135, such as Display Serial Interface (DSI), Embedded Display Port (eDP), etc. ADAS hub 115 can perform at least one of the following: storage, processing, or display of data from peripheral modules 120, 125, 130, 135. Figure 1 In the example, the ADAS hub 115 uses a display 140 to display data from one or more of the peripheral modules 120, 125, 130, and 135. The ADAS hub 115 uses multiplexing to display the data on the display 140. Furthermore, the ADAS hub 115 can also store or process at least one of the data from the peripheral modules 120, 125, 130, and 135 to enable other functions of the vehicle 100, such as object recognition, time-of-flight calculation, etc. The example of the ADAS hub 115 is combined with... Figure 2 Further illustration and description.

[0042] Peripheral modules 120, 125, 130, and 135 are communicatively coupled to the ADAS central hub 115. Peripheral modules 120, 125, 130, and 135 contain at least one sensor for receiving information about the surrounding environment, such as images, video, time-of-flight measurements, beamforming data, etc. Peripheral modules 120, 125, 130, and 135 use communication channels 120A, 125A, 130A, and 135A to transmit the received sensor data to the ADAS central hub 115. In some examples, communication channels 120A, 125A, 130A, and 135A are coaxial connectors used to couple the ADAS central hub 115 to the peripheral modules 120, 125, 130, and 135. In this example, the ADAS hub 115 uses Power over Coaxial Cable (POC) to supply power to the peripheral modules 120, 125, 130, and 135 across communication channels 120A, 125A, 130A, and 135A. Alternatively, communication channels 120A, 125A, 130A, and 135A can be formed using different types of connectors, such as standard twisted pair (STP). Example combinations of peripheral modules 120, 125, 130, and 135 are provided. Figure 2 Further illustration and description.

[0043] exist Figure 1 In an example operation of the ADAS system 105, peripheral modules 120, 125, 130, and 135 generate video streams of the environment surrounding the vehicle 100. Peripheral modules 120, 125, 130, and 135 serialize the video stream data. Peripheral modules 120, 125, 130, and 135 use communication channels 120A, 125A, 130A, and 135A to transmit the serial data stream to the ADAS hub 115. Simultaneously, the ADAS hub 115 can use communication channels 120A, 125A, 130A, and 135A to transmit data to the peripheral modules 120, 125, 130, and 135. Communication between the ADAS hub 115 and the peripheral modules 120, 125, 130, and 135 can occur simultaneously. This type of multi-directional communication across communication channels 120A, 125A, 130A, and 135A is called full-duplex communication.

[0044] exist Figure 1In such example operation of the ADAS system 105, the ADAS hub 115 receives serial data streams from peripheral modules 120, 125, 130, and 135. The ADAS hub 115 deserializes the data streams to reconstruct the video streams captured by the peripheral modules 120, 125, 130, and 135. The ADAS hub 115 performs at least one of the following: video stream storage, processing, or display, for driver assistance. For example, in response to determining that a viewing angle corresponding to the peripheral module 135 is required, the ADAS hub 115 displays the video stream of the peripheral module 135 on a display 140. In another example, the ADAS hub 115 stores or processes the video streams of the peripheral modules 120, 125, 130, and 135 to detect safety hazards in the environment of the vehicle 100.

[0045] Example operation of ADAS system 105 Figure 2 Further description. Advantageously, the serialization and deserialization of data from peripheral modules 120, 125, 130, and 135 reduces the number of connections from vehicle 100 to ADAS hub 115. Advantageously, the serial data stream can accurately traverse relatively large distances across communication channels 120A, 125A, 130A, and 135A.

[0046] Figure 1 The IVI system 110 includes an example media source 145, an example IVI driver circuitry 150, a first example display driver 155, a first example display 160, a second example display 165, a second example display driver 170, and a third example display 175. Alternatively, the IVI system 110 may include any number of display drivers or displays.

[0047] IVI system 110 is an example type of FPD link system that uses media serialization and deserialization to provide infotainment on one or more displays (e.g., displays 160, 165, 175). In some examples, IVI system 110 is a dashboard with multiple displays for showing content. In other examples, IVI system 110 is a different display system with multiple displays for showing content, such as a broadcasting studio, workstation, etc. Figure 1 In the example, IVI system 110 includes media source 145, IVI driver circuitry 150, display drivers 155 and 170, and displays 160, 165, and 175. Alternatively, IVI system 110 may include any number of media sources, display drivers, or displays. The example of IVI system 110 combines... Figure 3 Further illustration and description.

[0048] In IVI system 110, media source 145 is coupled to IVI driver circuitry 150. Media source 145 supplies media to IVI driver circuitry 150 for display on one or more of displays 160, 165, and 175. In some examples, media source 145 is integrated into vehicle 100, such as a circuitry supporting data streaming or a memory storing media. In other examples, media source 145 represents a connection to external devices of vehicle 100, such as a wireless connection to a service hosting multimedia streaming.

[0049] IVI driver circuitry 150 is communicatively coupled to media source 145 and display driver 155. IVI driver circuitry 150 processes multimedia data from media source 145 for transmission to one or more of display drivers 155, 170. IVI driver circuitry 150 uses full-duplex communication to transmit data to and receive data from display driver 155. In some examples, IVI driver circuitry 150 uses LVDS to communicate with display driver 155. In such examples, IVI driver circuitry 150 communicates indirectly with display driver 170 via display driver 155. Such examples combine... Figure 3 Further illustration and description are provided. Alternatively, the IVI driver circuitry 150 may use alternative types of communication to communicate with the display driver 155, such as DSI, eDP, etc. An example of the IVI driver circuitry 150 is provided in conjunction with... Figure 3 Further illustration and description.

[0050] Display driver 155 is communicatively coupled to IVI driver circuitry 150, displays 160 and 165, and display driver 170. Display driver 155 interfaces with IVI driver circuitry 150 using a first communication channel 155A and a second communication channel 155B. Display driver 155 interfaces with display driver 170 using communication channels 155C and 155D. Figure 1 In the example, the first and second coaxial connectors form communication channels 155A and 155B between the IVI driver circuitry 150 and the display driver 155. Similarly, the third and fourth coaxial connectors form communication channels 155C and 155D between the display drivers 155 and 170. The display driver 155 uses multiplexing to display media on displays 160 and 165. In some examples, the display driver 155 decodes additional data from the IVI driver circuitry 150 to determine which of the displays 160 and 165 corresponds to the data. Although Figure 1 The display driver 155 is coupled to the displays 160 and 165, but the display driver 155 can be coupled to any number of displays. Example combination of display driver 155 Figure 3 Further illustration and description.

[0051] Display driver 170 is communicatively coupled to display driver 155 and display 175. In some examples, display driver 170 may be coupled to another instance of display driver 170 (similar to communication channels 155A, 155B, 155C, 155D of display driver 155). Display driver 170 interfaces with display driver 155 using communication channels 155C, 155D. Display driver 170 uses multiplexing to display multimedia data using display 175. Although Figure 1 The display driver 155 is coupled to the display 175, but the display driver 170 can be coupled to any number of displays.

[0052] exist Figure 1 In an example operation of the IVI system 110, a media source 145 supplies media for display on at least one of displays 160, 165, and 175. An IVI driver circuitry system 150 determines which of the displays 160, 165, and 175 displays the media from the media source 145. The IVI driver circuitry system 150 determines which of the display drivers 155 and 170 is coupled to said one or more of the displays 160, 165, and 175. The IVI driver circuitry system 150 generates an identifier specifying at least one of the following: said one or more of the display drivers 155 and 170 or said one or more of the displays 160, 165, and 175. The IVI driver circuitry system 150 combines identification data and the media from the media source 145. The IVI driver circuitry system 150 generates a serial data stream by serializing the combined data for transmission on at least one of communication channels 155A and 155B.

[0053] In this example operation of IVI system 110, display driver 155 receives a serial data stream representing media and identification data. Display driver 155 deserializes the serial data stream from communication channels 155A and 155B. Display driver 155 decodes the identification data to determine whether the media corresponds to any of displays 160 and 165. If display driver 155 determines that the media corresponds to one or more of displays 160 and 165, then display driver 155 displays the media on one or more of displays 160 and 165. If display driver 155 determines that the media does not correspond to one or more of displays 160 and 165, then display driver 155 regenerates the serial data stream by reserializing the combined media and identification data. Display driver 155 transmits serial data to display driver 170 via at least one of communication channels 155C and 155D. After receiving the serial data stream from communication channels 155C and 155D, display driver 155 deserializes the serial data stream. Display driver 170 decodes the identification data to determine whether the media corresponds to display 175. If display driver 170 determines that the identification data corresponds to display 175, then display driver 170 displays the media on display 175. In some examples, display drivers 155, 170 transmit serial data to IVI driver circuitry 150 along communication channels 155A, 155B, 155C, 155D. In such examples, simultaneous communication from display drivers 155, 170 can confirm the reception or display of media on one or more of displays 160, 165, 175.

[0054] Example operation of IVI system 110 Figure 3 Further description. Serialization and deserialization of media from media source 145 reduces the number of connections from vehicle 100 to displays 160, 165, and 175. Furthermore, the serial data stream can accurately traverse relatively large distances across communication channels 155A, 155B, 155C, and 155D.

[0055] Figure 2 It includes Figure 1 The ADAS central hub 115, peripheral modules 120 and 135, and display 140 Figure 1 A block diagram of an example ADAS system 105. Figure 2 The example ADAS hub 115 includes a first example power supply circuit system 205, a first example deserializer circuit system 210, a first example serializer circuit system 215, a second example power supply circuit system 220, a second example deserializer circuit system 225, a second example serializer circuit system 230, an example programmable circuit system 235, and an example display interface circuit system 240. Figure 2The example peripheral module 120 includes an example serializer circuit system 245, an example power regulator circuit system 250, and an example sensor 255.

[0056] The power supply circuit system 205 has outputs coupled to the communication channel 120A and the deserializer circuit system 210. In some examples, the power supply circuit system 205 has inputs coupled to a power storage device or an electronic control unit (ECU) supplying power. In other examples, the power supply circuit system 205 is located within the peripheral module 120. In such examples, the power supply circuit system 205 supplies power directly to the peripheral module 120. Alternatively, different methods of powering the peripheral module 120 may be used in the circuit system described herein.

[0057] The deserializer circuit system 210 has inputs and outputs. The inputs of the deserializer circuit system 210 are coupled to a communication channel 120A and a power supply circuit system 205. The outputs of the deserializer circuit system 210 are coupled to a serializer circuit system 215 and a programmable circuit system 235. In some examples, the deserializer circuit system 210 communicates with a peripheral module 120 along the communication channel 120A using a serial data stream. Examples of the deserializer circuit system 210 are combined... Figure 4 Further illustration and description.

[0058] Serializer circuitry 215 has inputs and outputs. The inputs of serializer circuitry 215 are coupled to deserializer circuitry 210 and programmable circuitry 235. The outputs of serializer circuitry 215 are configured to couple to additional communication channels. In some examples, as shown by dashed lines, ADAS hub 115 may include serializer circuitry 215 to connect ADAS system 105 to external circuitry. In such examples, serializer circuitry 215 can communicatively couple ADAS system 105 to another ADAS system, IVI system 110, storage medium, ECU, etc. In other examples, ADAS hub 115 may not include serializer circuitry 215.

[0059] The power supply circuit system 220 has outputs coupled to the communication channel 135A and the deserializer circuit system 225. In some examples, the power supply circuit system 220 has inputs coupled to a power storage device or ECU. In other examples, the power supply circuit system 220 is located within the peripheral module 135. In such examples, the power supply circuit system 220 supplies power directly to the peripheral module 135. Alternatively, different methods of powering the peripheral module 135 may be used in the circuit system described herein.

[0060] The deserializer circuit system 225 has inputs and outputs. The inputs of the deserializer circuit system 225 are coupled to a communication channel 135A and a power supply circuit system 220. The outputs of the deserializer circuit system 225 are coupled to a serializer circuit system 230 and a programmable circuit system 235. In some examples, the deserializer circuit system 225 communicates with a peripheral module 135 along the communication channel 135A using a serial data stream. Examples of the deserializer circuit system 225 are combined... Figure 4 Further illustration and description.

[0061] Serializer circuitry 230 has inputs and outputs. The inputs of serializer circuitry 230 are coupled to deserializer circuitry 225 and programmable circuitry 235. The outputs of serializer circuitry 230 are configured to couple to additional communication channels. In some examples, as shown by dashed lines, ADAS hub 115 may include serializer circuitry 230 to connect ADAS system 105 to external circuitry. In such examples, serializer circuitry 230 can communicatively couple ADAS system 105 to another ADAS system, IVI system 110, storage media, ECU, etc. In other examples, ADAS hub 115 may not include serializer circuitry 230.

[0062] Programmable circuit system 235 has a first input, a second input, and an output. The first input of programmable circuit system 235 is coupled to deserializer circuit system 210 and serializer circuit system 215. The second input of programmable circuit system 235 is coupled to deserializer circuit system 225 and serializer circuit system 230. The output of programmable circuit system 235 is coupled to display interface circuit system 240. In some examples, programmable circuit system 235 instantiates the circuit system in response to the execution of machine-readable instructions. In such examples, programmable circuit system 235 may be one of a central processing unit (CPU), graphics processing unit (GPU), multi-core processing unit (MCU), etc. Alternatively, programmable circuit system 235 may be an application-specific integrated circuit (ASIC) configured to store, process, or regulate at least one of the data from deserializer circuit systems 210 and 225.

[0063] The display interface circuitry 240 has inputs and outputs. The inputs of the display interface circuitry 240 are coupled to the programmable circuitry 235. The outputs of the display interface circuitry 240 are coupled to the display 140. In some examples, the display interface circuitry 240 represents a display driver used to convert data from the programmable circuitry 235 to drive the display 140. In some such examples, the display interface circuitry 240 may include ports and connectors dedicated to driving the display 140, such as a monitor port, a High Definition Multimedia Interface (HDMI) port, etc.

[0064] The serializer circuit system 245 has inputs and outputs. The input of the serializer circuit system 245 is coupled to sensor 255. The output of the serializer circuit system 245 is coupled to communication channel 120A and power regulator circuit system 250. In some examples, the serializer circuit system 245 communicates with ADAS hub 115 along communication channel 120A using a serial data stream. (Example combination of serializer circuit system 245) Figure 4 Further illustration and description.

[0065] exist Figure 2 In one example, deserializer circuitry 210 is communicatively coupled to serializer circuitry 245 via a full-duplex cable represented by communication channel 120A. In some examples, deserializer circuitry 210 and serializer circuitry 245 can receive data from or transmit data on communication channel 120A. In such examples, the inputs of deserializer circuitry 210 and the outputs of serializer circuitry 245 are bidirectional. Such examples combine... Figure 4 Further description.

[0066] The power regulator circuit system 250 has inputs and outputs. The inputs of the power regulator circuit system 250 are coupled to a communication channel 120A and a serializer circuit system 245. The outputs of the power regulator circuit system 250 are coupled to a sensor 255. The power regulator circuit system 250 receives power from a power supply circuit system 205. In some examples, such as in… Figure 2 In this example, the power regulator circuit system 250 receives power via communication channel 120A. In other examples, the power supply circuit system 205 can be coupled to the power regulator circuit system 250 via a separate connection, or positioned close to the peripheral module 120.

[0067] Sensor 255 has an input and an output. The input of sensor 255 is coupled to power regulator circuitry 250. The output of sensor 255 is coupled to serializer circuitry 245. In some examples, sensor 255 generates data corresponding to the surrounding environment. For example, in... Figure 1 In this embodiment, sensor 255 may be a camera positioned to capture a portion of the environment surrounding vehicle 100. In another example, sensor 255 may be an alternative type of sensor used to correspond to features of the environment surrounding vehicle 100, such as obstacles.

[0068] In example operation, power supply circuitry 205 supplies power to power regulator circuitry 250 via communication channel 120A. In some examples, such as when communication channel 120A is a coaxial connector, power supply circuitry 205 and power regulator circuitry 250 implement power on coaxial cable (POC). In such examples, power supply circuitry 205 supplies power (power input), and power regulator circuitry 250 receives power (power output). Based on the power from power supply circuitry 205, power regulator circuitry 250 supplies power to sensor 255 or more generally peripheral module 120. Similarly, power supply circuitry 220 can supply power to peripheral module 135 using communication channel 135A.

[0069] Sensor 255 generates data corresponding to the surrounding environment. In some examples, sensor 255 is a camera that generates multimedia data corresponding to the viewpoint of the surrounding environment. In another example, sensor 255 is a lidar device that generates time-of-flight data corresponding to potential obstacles in the surrounding environment. In yet another example, sensor 255 is a radar that generates beamforming data corresponding to the surrounding environment. Alternatively, sensor 255 may be an alternative type of sensor that generates alternative types of data. In such example operations, sensor 255 generates sensor data using multiple parallel data paths (also referred to as lines or paths). Serializer circuitry 245 serializes the data from the multiple parallel data paths to generate a serial data stream, the data rate of which is greater than the data rate of the parallel data paths from sensor 255. Serializer circuitry 245 transmits the serial data stream to deserializer circuitry 210 using a forward channel of communication channel 120A. This type of data in the serial data stream is referred to as forward channel data (DATA). FC_0 ).

[0070] In the example operation, the deserializer circuitry 210 receives a serial data stream after traversing communication channel 120A. Simultaneously, the deserializer circuitry 210 can use the backward channel of communication channel 120A to transmit a serial data stream to the serializer circuitry 245. This type of data is referred to as backward channel data (DATA). BC_0 In such examples, the data rate of the forward channel data is higher than that of the backward channel data to reduce interference. This type of multi-directional communication along communication channel 120A is called full-duplex communication. The deserializer circuitry 210 can use the backward channel of communication channel 120A to control the setting of sensor 255 or to verify the reception of data on the forward channel. Similarly, peripheral module 135 and deserializer circuitry 225 can use full-duplex communication along communication channel 135A to exchange forward and backward channel data (DATA). FC_N DATA BC_N ).

[0071] In example operation, deserializer circuitry 210 deserializes the forward channel data to generate multiple parallel data paths. In some examples, deserializer circuitry 210 can decode identification data based on the forward channel data. In such examples, in response to deserializer circuitry 210 decoding identification data corresponding to an external circuitry, serializer circuitry 215 can serialize and transmit the forward channel data to the external circuitry. Advantageously, serializer circuitry 215 allows ADAS system 105 to be coupled to another instance of ADAS system 105, IVI system 110, or an alternative type of data processing system.

[0072] In example operation, programmable circuitry system 235 processes, stores, or modulates at least one of the multiple parallel data paths for display 140. In some examples, programmable circuitry system 235 combines data from peripheral modules 120, 135 before displaying it. For example, programmable circuitry system 235 may stitch together video streams from peripheral modules 120, 135 to display a larger portion of the surrounding environment. In such examples, display interface circuitry system 240 constructs data from programmable circuitry system 235 to drive display 140. In some examples, display interface circuitry system 240 is at least one of column pixel driver or row pixel driver. Display 140 produces a perceptible representation of data from at least one of peripheral modules 120, 135.

[0073] Example operation of the serializer and deserializer system of ADAS system 105 Figure 4 , 5 Further described in section 6. Advantageously, the serialization and deserialization of data from peripheral modules 120 and 135 reduces the number of connections to the ADAS hub 115. Advantageously, the serial data stream can accurately traverse relatively large distances across communication channels 120A and 135A.

[0074] Figure 3 yes Figure 1 A block diagram of an example IVI system 110. Figure 3 The IVI system 110 includes Figure 1 Examples of media source 145, IVI driver circuitry 150, display drivers 155 and 170, and displays 160, 165 and 175. Figure 3 The example IVI driver circuit system 150 includes an example programmable circuit system 320 and an example serializer circuit system 330. Figure 3 The example display driver 155 includes an example deserializer circuit system 340, an example decoder circuit system 350, an example display interface circuit system 360, and an example serializer circuit system 370.

[0075] Programmable circuit system 320 has inputs and outputs. The inputs of programmable circuit system 320 are coupled to media source 145. The outputs of programmable circuit system 320 are coupled to serializer circuit system 330. In some examples, programmable circuit system 320 is instantiated in response to the execution of machine-readable instructions. In such examples, programmable circuit system 320 may be one of a CPU, GPU, MCU, etc. Alternatively, programmable circuit system 335 may be an ASIC configured to store, process, or regulate at least one of the following: data from media source 145.

[0076] Serializer circuit system 330 has an input, a first output, and a second output. The input of serializer circuit system 330 is coupled to programmable circuit system 320. The first output of serializer circuit system 330 is coupled to communication channel 155A. The second output of serializer circuit system 330 is coupled to communication channel 155B. In some examples, serializer circuit system 330 communicates with display driver 155 using a serial data stream along communication channels 155A and 155B. Examples of serializer circuit system 330 are combined. Figure 4 Further illustration and description. Different from... Figure 2 The serializer circuit system 245 and the serializer circuit system 330 exchange data using multiple serial data streams along communication channels 155A and 155B. In some examples, the serializer circuit system 330 may be shown and described as multiple instances of a single serializer circuit system 330 supporting communication channels 155A and 155B. For example, the serializer circuit system 330 may be divided into two instances of the serializer circuit system 330.

[0077] The deserializer circuit system 340 has a first input, a second input, and an output. The first input of the deserializer circuit system 340 is coupled to a communication channel 155A. The second input of the deserializer circuit system 340 is coupled to a communication channel 155B. The output of the deserializer circuit system 340 is coupled to a decoder circuit system 350. In some examples, the deserializer circuit system 340 communicates with the IVI driver circuit system 150 using a serial data stream along communication channels 155A and 155B. Examples of the deserializer circuit system 340 are combined... Figure 4 Further illustration and description. Different from... Figure 2The deserializer circuit systems 210 and 225, and the deserializer circuit system 340 use multiple serial data streams to exchange data along communication channels 155A and 155B. In some examples, the deserializer circuit system 340 can be shown and described as multiple instances supporting a single deserializer circuit system 340 in communication channels 155A and 155B. For example, the deserializer circuit system 340 can be divided into two instances of the deserializer circuit system 340, for example... Figure 2 The serializer circuit system 210, 225.

[0078] Decoder circuitry 350 has an input, a first output, and a second output. The input of decoder circuitry 350 is coupled to deserializer circuitry 340. The first output of decoder circuitry 350 is coupled to display interface 360. The second output of decoder circuitry 350 is coupled to serializer circuitry 370. In some examples, decoder circuitry 350 is implemented using a programmable circuitry or an ASIC. In such examples, decoder circuitry 350 is configured to route data from deserializer circuitry 340 to at least one of display interface 360 ​​or serializer circuitry 370 in response to a decoded portion of the data. Such a portion of the data from deserializer circuitry 340 may be referred to as identification data, used to identify one or more display media in displays 160, 165, and 175.

[0079] Display interface 360 ​​has an input, a first output, and a second output. The input of display interface 360 ​​is coupled to decoder circuitry 350. The first output of display interface 360 ​​is coupled to display 160. The second output of display interface 360 ​​is coupled to display 165. In some examples, display interface 360 ​​drives one or more of displays 160 and 165 in response to data from decoder circuitry 350. In some such examples, display interface 360 ​​may include ports and connectors dedicated to driving the displays, such as monitor ports, HDMI ports, etc. Figure 3 In the example, display interface 360 ​​drives displays 160 and 165. Alternatively, display driver 155 may include any number of display interfaces 360 for driving any number of displays (e.g., displays 160 and 165).

[0080] Serializer circuitry 370 has an input, a first output, and a second output. The input of serializer circuitry 370 is coupled to decoder circuitry 350. The first output of serializer circuitry 370 is coupled to communication channel 155C. The second output of serializer circuitry 370 is coupled to communication channel 155D. In some examples, serializer circuitry 370 communicates with display driver 170 using a serial data stream along communication channels 155C and 155D. Examples of serializer circuitry 370 are combined. Figure 4 Further illustration and description are provided. Similar to serializer circuit system 330, serializer circuit system 370 uses multiple serial data streams to exchange data along communication channels 155C, 155D. In some examples, serializer circuit system 370 may be shown and described as multiple instances of serializer circuit system 370 supporting one of communication channels 155C, 155D. For example, serializer circuit system 370 may be divided into two instances of serializer circuit system 370.

[0081] In example operation, programmable circuit system 320 receives multimedia data from media source 145. In some examples, media source 145 is internal to IVI system 110, such as a memory storage device, ECU, media stream, etc. In other examples, media source 145 is external to IVI system 110, such as a wireless connection to a service hosting the multimedia stream. Programmable circuit system 320 identifies one or more displays 160, 165, 175 corresponding to the data from media source 145. In some examples, programmable circuit system 320 encodes additional data to the data from media source 145, corresponding to different operations of IVI system 110. For example, programmable circuit system 320 adds identification data to a portion of the data from media source 145 to specify one or more displays 160, 165, 175 corresponding to the media. In such examples, the identification data may specify one or more displays 160, 165, 175. The programmable circuit system 320 supplies data to the serializer circuit system 330 for transmission to the display drivers 155, 170.

[0082] In the example operation, the serializer circuitry 330 receives data from the programmable circuitry 320 on multiple parallel data paths. The serializer circuitry 330 serializes the data from the multiple parallel data paths to generate first and second serial data streams, whose data rates are greater than the data rates of the parallel data paths from the programmable circuitry 320. The serializer circuitry 330 uses the forward channel of communication channel 155A to transmit the first serial data stream to the deserializer circuitry 340. The data of the first serial data stream is referred to as first forward channel data (DATA). FC_0The serializer circuit system 330 uses the forward channel of communication channel 155B to transmit the second serial data stream to the deserializer circuit system 340. The data in the second serial data stream is called the second forward channel data (DATA). FC_1 Advantageously, increasing the number of communication channels between the serializer circuit system 330 and the deserializer circuit system 340 increases the possible number of displays that the IVI system 110 can support at a given time.

[0083] In the example operation, the deserializer circuit system 340 receives the first and second serial data streams after traversing communication channels 155A and 155B. Simultaneously, the deserializer circuit system 340 can use the backward channel of communication channel 155A to transmit the first serial data stream to the serializer circuit system 330. The data in the first serial data stream is referred to as the first backward channel data (DATA). BC_0 Similarly, the deserializer circuit system 340 can use the backward channel of communication channel 155B to transmit a second serial data stream to the serializer circuit system 330. The data in the second serial data stream is called the second backward channel data (DATA). BC_1 In such examples, the data rates of the first and second forward channel data can be higher than those of the first and second backward channel data to reduce interference. This type of multi-directional communication along communication channels 155A and 155B is called full-duplex communication. The deserializer circuit system 340 can use the backward channels of communication channels 155A and 155B to verify the reception of the first and second forward channel data, report errors to the programmable circuit system 320, etc. Similarly, the display driver 170 and the serializer circuit system 370 can use full-duplex communication along communication channels 155C and 155D to exchange third and fourth forward channel data (DATA). FC_2 DATA FC_3 ) and third and fourth backward channel data (DATA) BC_2 DATA BC_3 ).

[0084] In example operation, deserializer circuitry 340 deserializes the first and second forward channel data to generate multiple parallel data paths. Decoder circuitry 350 decodes the data from media source 145 based on additional data from programmable circuitry 320. In response to the decoded data, decoder circuitry 350 determines which of displays 160, 165, and 175 corresponds to the data from media source 145. In some examples, in response to determining that the media does not correspond to displays 160 or 165, decoder circuitry 350 supplies the multiple parallel data paths to serializer circuitry 370. In such examples, serializer circuitry 370 serializes and transmits third and fourth forward channel data to display driver 170. Advantageously, display driver 170 can be coupled in series with another instance of display driver 170 via additional communication channels, such as fifth and sixth communication channels.

[0085] In example operation, in response to determining that media from media source 145 corresponds to at least one of displays 160, 165, the decoder circuitry supplies the plurality of parallel data paths to display interface 360. In some examples, display interface 360 ​​constructs data from decoder circuitry 350 to drive one or more of displays 160, 165. In some examples, display interface 360 ​​is at least one of column pixel drivers or row pixel drivers. In such examples, at least one of displays 160, 165 generates a perceptible representation of media from media source 145 in response to display interface 360.

[0086] Example operation of serializer and deserializer systems in IVI System 110 Figure 4 , 5 Further described in section 6. Advantageously, the serialization and deserialization of data from media source 145 reduces the number of connections to one or more of the displays 160, 165, and 175. Furthermore, the serial data stream can accurately traverse relatively large distances across communication channels 155A, 155B, 155C, and 155D.

[0087] Figure 4 This is a block diagram of an example serializer circuit system 400, which is... Figure 2 and 3 Examples of serializer circuit systems 210, 225, and 340. Figure 4 The example deserializer circuit system 400 includes an example serializer 410, an example backward channel transmitter circuit system 420, an example backward channel echo cancellation circuit system 430, an example receiver circuit system 440, and an example clock and data recovery (CDR) circuit system 450. The example echo cancellation circuit system 430 includes an example impedance matching circuit system 460 and an example combinational circuit system 470.

[0088] The deserializer circuit system 400 is configured to be coupled to at least one of communication channels 120A, 135A, 155A, and 155B. Figure 2 and 3 The serializer circuit systems 245 and 330. The serializer circuit system 400 has an input (DATA_IN). BC ) and output (DATA_OUT) FC The inputs and outputs of the deserializer circuit system 400 are configured to be coupled to... Figure 2 Programmable circuit system 235 or Figure 3 One of the decoder circuit systems 350. The input of the deserializer circuit system 400 receives backward channel data for transmission along at least one of communication channels 120A, 135A, 155A, 155B. The output of the deserializer circuit system 400 provides forward channel data from at least one of the communication channels 120A, 135A, 155A, 155B.

[0089] The serializer 410 has inputs and outputs. The input of the serializer 410 is coupled to the input (DATA_IN) of the deserializer circuit system 400. BC The output of serializer 410 is coupled to transmitter circuitry 420. In some examples, serializer 410 is referred to as a backward channel serializer.

[0090] Transmitter circuit system 420 has an input, a first output, and a second output. The input of transmitter circuit system 420 is coupled to serializer 410. The first output of transmitter circuit system 420 is coupled to echo cancellation circuit system 430 and at least one of communication channels 120A, 135A, 155A, and 155B. The second output of transmitter circuit system 420 is coupled to echo cancellation circuit system 430. In some examples, transmitter circuit system 420 is referred to as a backchannel transmitter. Examples of transmitter circuit system 420 are combined. Figure 7 and 8 Further illustration and description.

[0091] The echo cancellation circuit system 430 has a first input, a second input, and an output. The first input of the echo cancellation circuit system 430 is coupled to a transmitter circuit system 420. The second input of the echo cancellation circuit system 430 is coupled to the transmitter circuit system 420 and at least one of communication channels 120A, 135A, 155A, and 155B. The output of the echo cancellation circuit system 430 is coupled to a receiver circuit system 425. In some examples, the echo cancellation circuit system 430 is referred to as a backchannel echo cancellation circuit system. Examples of the echo cancellation circuit system 430 are combined... Figure 7 Further illustration and description.

[0092] Receiver circuitry 440 has inputs and outputs. The input of receiver circuitry 440 is coupled to echo cancellation circuitry 430. The output of receiver circuitry 440 is coupled to CDR circuitry 450. In some examples, receiver circuitry 440 is referred to as a forward channel receiver.

[0093] The CDR circuit system 450 has inputs and outputs. The input of the CDR circuit system 450 is coupled to the receiver circuit system 440. The output of the CDR circuit system 450 is coupled to the output (DATA_OUT) of the deserializer circuit system 400. FC In some examples, the CDR circuit system 450 is referred to as the forward channel CDR circuit system.

[0094] Impedance matching circuit system 460 (also called load circuit system) has input and output. The input of load circuit system 460 is coupled to transmitter circuit system 420. The output of load circuit system 460 is coupled to combinational circuit system 470. An example combination of load circuit system 460... Figure 7 Further illustration and description.

[0095] The combinational circuit system 470 has a first input, a second input, and an output. The first input of the combinational circuit system 470 is coupled to at least one of the transmitter circuit system 420 and communication channels 120A, 135A, 155A, and 155B. The second input of the combinational circuit system 470 is coupled to the transmitter circuit system 420. The output of the combinational circuit system 470 is coupled to the receiver circuit system 440.

[0096] Figure 5 This is a block diagram of an example serializer circuit system 500, which is... Figure 2 and 3 Examples of serializer circuit systems 245 and 330. Figure 5 The example serializer circuit system 500 includes an example serializer 510, an example delay circuit system 520, a first example transmitter circuit system 525, a second example transmitter circuit system 530, an example combination circuit system 535, an example receiver circuit system 540, an example CDR circuit system 550, and an example decoder circuit system 560.

[0097] The serializer circuit system 500 is configured to... Figure 1 , 2 At least one of the communication channels 120A, 135A, 155A, 155B, 155C, and 155D of the third are coupled to Figure 2 , 3 The serializer circuit systems 210, 225, 340, and 400 are used for deserialization. Serializer circuit system 500 has an input (DATA_IN).FC ) and output (DATA_OUT) BC The inputs and outputs of the serializer circuit system 500 are configured to be coupled to... Figure 2 Sensor 255 or Figure 3 One of the programmable circuit systems 320. The input of the serializer circuit system 500 receives forward channel data for transmission along at least one of the communication channels 120A, 135A, 155A, 155B, 155C, and 155D. The output of the serializer circuit system 500 provides backward channel data from at least one of the communication channels 120A, 135A, 155A, 155B, 155C, and 155D.

[0098] The serializer 510 has inputs and outputs. The input of the serializer 510 is coupled to the input (DATA_IN) of the serializer circuit system 500. FC The output of serializer 510 is coupled to delay circuitry 520. In some examples, serializer circuitry 500 is referred to as a forward channel serializer.

[0099] The delay circuit system 520 has inputs and outputs. The input of the delay circuit system 520 is coupled to a serializer 510. The output of the delay circuit system 520 is coupled to transmitter circuit systems 525 and 530. An example of the delay circuit system 520 is provided. Figure 16 Further illustration and description.

[0100] Transmitter circuit system 525 has inputs and outputs. The inputs of transmitter circuit system 525 are coupled to delay circuit system 520 and transmitter circuit system 530. The outputs of transmitter circuit system 525 are coupled to combinational circuit system 535. In some examples, transmitter circuit system 525 is referred to as a secondary transmitter or replica transmitter.

[0101] Transmitter circuit system 530 has inputs and outputs. The input of transmitter circuit system 530 is coupled to delay circuit system 520. In some examples, as shown by dashed lines, the inputs of transmitter circuit systems 525 and 530 are directly coupled to the output of serializer 510. The output of transmitter circuit system 530 is coupled to combinational circuit system 535 and at least one of communication channels 120A, 135A, 155A, 155B, 155C, and 155D. In some examples, transmitter circuit system 530 is referred to as a forward channel transmitter or a master transmitter. Examples of transmitter circuit system 530 combined... Figure 12 , 13 14 further illustrates and describes this.

[0102] The combinational circuit system 535 has a first input, a second input, and an output. The first input of the combinational circuit system 535 is coupled to the transmitter circuit system 525. The second input of the combinational circuit system 535 is coupled to the transmitter circuit system 530 and at least one of communication channels 120A, 135A, 155A, 155B, 155C, and 155D. The output of the combinational circuit system 535 is coupled to the receiver circuit system 540. In some examples, the transmitter circuit system 525 and the combinational circuit system 535 are shown as, or referred to as, an echo cancellation circuit system. Figure 5 In the example, combinational circuit system 535 is a subtraction circuit system. Alternatively, in other examples, combinational circuit system 535 is an alternative circuit system.

[0103] Receiver circuitry 540 has inputs and outputs. The inputs of receiver circuitry 540 are coupled to combinational circuitry 535. The outputs of receiver circuitry 540 are coupled to CDR circuitry 550. In some examples, receiver circuitry 540 is referred to as a backchannel receiver.

[0104] CDR circuit system 550 has inputs and outputs. The input of CDR circuit system 550 is coupled to receiver circuit system 540. The output of CDR circuit system 550 is coupled to decoder circuit system 560. In some examples, CDR circuit system 550 is referred to as a backward channel CDR circuit system.

[0105] Decoder circuit system 560 has inputs and outputs. The input of decoder circuit system 560 is coupled to CDR circuit system 550. The output of decoder circuit system 560 is coupled to the output (DATA_OUT) of serializer circuit system 500. BC In some examples, as shown by the dashed line, the output of CDR circuit system 550 is directly coupled to the output (DATA_OUT) of serializer circuit system 500. BC ).

[0106] Figure 6 This is a block diagram of an example serial deserializer (SerDes) system 600, which includes... Figure 4 The serializer circuit system 400 and Figure 5 The serializer circuit system is a 500 full-duplex communication system. Figure 6 Example deserializer circuit system 400 includes Figure 4 Serializer 410, Figure 4 Transmitter circuit system 420 Figure 4 echo cancellation circuit system 430 Figure 4 Receiver circuit system 440 and Figure 4 The CDR circuit system 450. Figure 6Example serializer circuit system 500 includes Figure 5 Serializer 510, Figure 5 Delay circuit system 520 Figure 5 Transmitter circuit systems 525, 530 Figure 5 Combinatorial circuit system 535, Figure 5 Receiver circuit system 540 Figure 5 CDR circuit system 550 and Figure 5 The decoder circuit system 560.

[0107] The SerDes system 600 includes an example communication channel 610 coupled between deserializer circuitry 400 and serializer circuitry 500. In some examples, communication channel 610 is a coaxial connector. In other examples, communication channel 610 is a standard wire pair or an alternative connection. Figure 2 In the example of ADAS system 105, deserializer circuit system 400 represents deserializer circuit system 210 in ADAS hub 115, and serializer circuit system 500 represents serializer circuit system 245 in peripheral module 120. Figure 3 In the example of IVI system 110, deserializer circuit system 400 represents deserializer circuit system 340 in display driver 155. Furthermore, in Figure 3 In the example of IVI system 110, serializer circuit system 500 represents serializer circuit system 330 in IVI driver circuit system 150 or serializer circuit system 370 in display driver 155.

[0108] In the example operation, the deserializer circuitry 400 receives backward channel data (DATA) from an external data source, such as the programmable circuitry 235 or the decoder circuitry 350, via multiple data paths. BC Serializer 410 generates a backward channel serial data stream in response to backward channel data. Transmitter circuitry 420 transmits backward channel data to serializer circuitry 500 across communication channel 610. Similarly, serializer circuitry 500 receives forward channel data (DATA) from external data sources, such as sensor 255 or programmable circuitry 320, via multiple data paths. FCSerializer 510 generates a forward channel serial data stream in response to forward channel data. In some examples, serializer circuitry 500 includes delay circuitry 520 supporting feedforward equalization (FFE). In such examples, delay circuitry 520 delays the amplitude of digital pulses to reduce attenuation along communication channel 610. Transmitter circuitry 530 transmits forward channel data across communication channel 610 to deserializer circuitry 400. Furthermore, transmitter circuitry 525 provides a copy of the forward channel data to combination circuitry 535.

[0109] In some examples, as further described below, transmitter circuit systems 420, 530 may include circuitry for impedance matching with communication channel 610 to reduce reflections. Furthermore, transmitter circuit systems 420, 530 may have different bandwidths. In such examples, the data rates for forward and backward channel data transmissions are different to prevent interference. In some examples, the bandwidth of transmitter circuit system 420 for transmitting backward channel data is modified to reduce the nonlinear gain contribution of communication channel 610. Advantageously, serializers 410, 510 and transmitter circuit systems 420, 530 support full-duplex data transmission along communication channel 610.

[0110] In the example operation, the deserializer circuit system 400 receives forward channel data (DATA) after propagating along the communication channel 610. FC Receiver circuitry 440 generates a serial data stream representing forward channel data in response to a signal from communication channel 610. In some examples, receiver circuitry 440 isolates communication channel 610 from CDR circuitry 450. Echo cancellation circuitry 430 reduces the contribution of signals received by transmitter circuitry 420 to backward channel data.

[0111] Similarly, the serializer circuit system 500 receives backward channel data (DATA) after propagating along the communication channel 610. BC The combinational circuit system 535 subtracts a copy of the forward channel data from the signal of the communication channel 610. The combinational circuit system 535 provides a communication signal representing the backward channel data to the receiver circuit system 540. The receiver circuit system 540 generates a serial data stream representing the backward channel data in response to the signal from the communication channel 610. In some examples, the receiver circuit system 540 isolates the communication channel 610 from the CDR circuit system 550. Furthermore, the receiver circuit systems 440 and 540 terminate the current to the communication channel 610.

[0112] In example operation, CDR circuitry 450 receives forward channel data from receiver circuitry 440. CDR circuitry 450 retims the forward channel data to generate multiple parallel data paths representing the forward channel data. The output of deserializer circuitry 400 provides the forward channel data to external circuitry, such as programmable circuitry 235 or decoder circuitry 350. Similarly, CDR circuitry 550 receives backward channel data from receiver circuitry 455. CDR circuitry 550 generates multiple parallel data paths representing the backward channel data. In some such example operations, decoder circuitry 560 decodes a portion of the backward channel data before the output of serializer circuitry 500 supplies the backward channel data to external circuitry, such as sensor 255 or programmable circuitry 320.

[0113] Example operation combination of transmitter circuit system 420 and echo cancellation circuit system 430 Figure 7 , 8 Figure 9 further illustrates and describes the example operation of the delay circuit system 520 and the transmitter circuit system 530 in combination. Figure 12 , 13 Figures 14 and 15 further illustrate and describe this. Advantageously, the serialization and deserialization of the forward and backward channel data reduces the number of connections required to traverse the relatively large distances of communication channel 610. Advantageously, the serial data stream can accurately traverse relatively large distances across communication channel 610.

[0114] Figure 7 yes Figure 4 and 6 Transmitter circuit system 420 Figure 4 and 6 The load circuit system 460 and Figure 4 and 6 A block diagram of an example of a combinational circuit system 470. Figure 7 The example transmitter circuit system 420 includes an example AC coupler circuit system 710, an example filter circuit system 720, an example source follower circuit system 730, a first example resistor 740, and a second example resistor 750. Figure 7 In the example, the transmitter circuit system 420 is configured to be coupled to via the example capacitor 755. Figure 6 The communication channel 610. Similarly, the differential output of the transmitter circuit system 420 is terminated through example capacitor 760 and example resistor 765. Figure 7 The example load circuit system 460 includes a first example resistor 770, a second example resistor 780, and a third example resistor 790.

[0115] Transmitter circuit system 420 has a first input, a second input, a first output, a second output, a third output, and a fourth output. The first and second inputs (INP, INM) of transmitter circuit system 420 are configured to be coupled to a digital signal source. The digital signal source provides differential pairs of digital signals at the first and second inputs of transmitter circuit system 420. For example, Figure 4 The serializer 410 provides a serial data stream for use across Figure 6 The communication channel 610 transmits data. The first and second outputs of the transmitter circuit system 420 are coupled to the load circuit system 460. The third output of the transmitter circuit system 420 is coupled to the combination circuit system 470 and capacitor 755. The fourth output of the transmitter circuit system 420 is coupled to the combination circuit system 470 and capacitor 760. In some examples, the transmitter circuit system 420 is referred to as a backward channel transmitter circuit system.

[0116] The load circuit system 460 has a first input, a second input, a first output, and a second output. The first and second inputs of the load circuit system 460 are coupled to the transmitter circuit system 420. The first and second outputs of the load circuit system 460 are coupled to the combinational circuit system 470.

[0117] The combinational circuit system 470 has a first input, a second input, a third input, a fourth input, and an output. The first and second inputs of the combinational circuit system 470 are coupled to a transmitter circuit system 420 and capacitors 755 and 760. The third and fourth inputs of the combinational circuit system 470 are coupled to a load circuit system 460. The output of the combinational circuit system 470 is configured to couple to a receiver circuit system, for example... Figure 4 The receiver circuit system 440.

[0118] AC coupler circuit system 710 has a first input, a second input, a first output, and a second output. The first and second inputs of AC coupler circuit system 710 are coupled to the first and second inputs (INP, INM) of transmitter circuit system 420. The first and second outputs (CD_OUTP, CD_OUTM) of AC coupler circuit system 710 are coupled to filter circuit system 720. An example of AC coupler circuit system 710 is provided. Figure 8 Further illustration and description.

[0119] Filter circuit system 720 has a first input, a second input, a first output, and a second output. The first and second inputs of filter circuit system 720 are coupled to AC coupler circuit system 710. The first and second outputs (BQ_OUTP, BQ_OUTM) of filter circuit system 720 are coupled to source follower circuit system 730. An example of filter circuit system 720 is provided. Figure 8 Further illustration and description.

[0120] The source follower circuit system 730 has a first input, a second input, a first output, and a second output. The first and second inputs of the source follower circuit system 730 are coupled to a filter circuit system 720. The first output (OUTP_Z) of the source follower circuit system 730 is coupled to resistors 740 and 770. The second output (OUTM_Z) of the source follower circuit system 730 is coupled to resistors 750 and 780. An example of the source follower circuit system 730 is provided. Figure 8 Further illustration and description.

[0121] Resistor 740 has a first terminal and a second terminal. The first terminal of resistor 740 is coupled to source follower circuit system 730 and resistor 770. The second terminal of resistor 740 is coupled to combinational circuit system 470 and capacitor 755. In some examples, resistor 740 has a trimming input. In such examples, the trimming circuit system provides a trimming value to resistor 740. The trimming value is used to set the resistance of resistor 740. Such a resistor is called a trimmable resistor.

[0122] Resistor 750 has a first terminal and a second terminal. The first terminal of resistor 750 is coupled to source follower circuit system 730 and resistor 780. The second terminal of resistor 750 is coupled to combinational circuit system 470 and capacitor 760. In some examples, resistor 750 has a trimming input. In such examples, the trimming circuit system provides a trimming value to resistor 750. The trimming value is used to set the resistance of resistor 750. Such a resistor is called a trimmable resistor.

[0123] Capacitor 755 has a first terminal and a second terminal. The first terminal of capacitor 755 is coupled to combined circuit system 470 and resistor 740. The second terminal of capacitor 755 is configured to be coupled to a communication channel, such as communication channel 610.

[0124] Capacitor 760 has a first terminal and a second terminal. The first terminal of capacitor 760 is coupled to combined circuit system 470 and resistor 750. The second terminal of capacitor 760 is coupled to resistor 765.

[0125] Resistor 765 has a first terminal and a second terminal. The first terminal of resistor 765 is coupled to capacitor 760. The second terminal of resistor 765 is coupled to a common terminal that provides a common potential (e.g., ground, AVSS, etc.).

[0126] Resistor 770 has a first terminal and a second terminal. The first terminal of resistor 770 is coupled to source follower circuit system 730 and resistor 740. The second terminal of resistor 770 is coupled to combination circuit system 470 and resistor 790.

[0127] Resistor 780 has a first terminal and a second terminal. The first terminal of resistor 780 is coupled to source follower circuit system 730 and resistor 750. The second terminal of resistor 780 is coupled to combination circuit system 470 and resistor 790.

[0128] Resistor 790 has a first terminal and a second terminal. The first terminal of resistor 790 is coupled to combined circuit system 470 and resistor 770. The second terminal of resistor 790 is coupled to combined circuit system 470 and resistor 780. In some examples, a fine-tuning circuit system provides a fine-tuning value to resistor 740. In such examples, the resistance of resistor 740 is set in response to the fine-tuning value.

[0129] Figure 7 Transmitter circuit system 420 Figure 7 The load circuit system 460 and Figure 7 Example operation of combinational circuit system 470 Figure 10 , 11A 11B is shown and described.

[0130] Figure 8 yes Figure 4 , 5 A schematic diagram of an example of the transmitter circuit system 420 for 6 and 7. Figure 8 Example transmitter circuit system 420 includes Figure 7 AC coupler circuit system 710 Figure 7 The filter circuit system 720 and Figure 7 The source follower circuit system 730. Figure 8 The example AC coupler circuit system 710 includes a first example capacitor 803, a second example capacitor 806, a first example resistor 809, a third example capacitor 812, a fourth example capacitor 815, a fifth example capacitor 818, a second example resistor 821, and a sixth example capacitor 824. Figure 8 The example filter circuit system 720 includes a first example transistor 827, a second example transistor 830, a first example resistor 833, a third example transistor 836, a fourth example transistor 839, a first example capacitor 842, a fifth example transistor 845, a sixth example transistor 848, a second example capacitor 851, a second example resistor 854, and a third example resistor 857. Figure 8 The example source follower circuit system 730 includes a first example transistor 860, a second example transistor 863, an example capacitor 866, an example resistor 869, a third example transistor 872, a fourth example transistor 875, a fifth example transistor 878, and a sixth example transistor 881.

[0131] The AC coupler circuit system 710 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first, second, third, and fourth inputs of the AC coupler circuit system 710 (INP0, INP...) N INM0, INM N This is configured to be coupled to a digital signal source. The digital signal source provides differential pairs of digital signals at the first and second inputs of the transmitter circuit system 420. For example, Figure 4 The serializer 410 provides a serial data stream for use across Figure 6 The communication channel 610 transmits data. The first and second outputs (CD_OUTP, CD_OUTM) of the AC coupler circuit system 710 are coupled to the filter circuit system 720.

[0132] The filter circuit system 720 has a first input, a second input, a first output, and a second output. The first and second inputs of the filter circuit system 720 are coupled to the AC coupler circuit system 710 (CD_OUTP, CD_OUTM). The first and second outputs (BQ_OUTP, BQ_OUTM) of the filter circuit system 720 are coupled to the source follower circuit system 730.

[0133] The source follower circuit system 730 has a first input, a second input, a first output, and a second output. The first and second inputs of the source follower circuit system 730 are coupled to a filter circuit system 720 (BQ_OUTP, BQ_OUTM). The first output (OUTP_Z) of the source follower circuit system 730 is configured to couple to... Figure 7 Resistors 740 and 770. The second output (OUTM_Z) of the source follower circuit system 730 is configured to couple to Figure 7 Resistors of 750 and 780.

[0134] Capacitor 803 has a first terminal and a second terminal. The first terminal of capacitor 803 is coupled to the first input (INP0) of AC coupler circuit system 710. The second terminal of capacitor 803 is coupled to capacitors 806 and 812, resistor 809 and the first output (CD_OUTP) of AC coupler circuit system 710.

[0135] Capacitor 806 has a first terminal and a second terminal. The first terminal of capacitor 806 is coupled to the second input (INP) of AC coupler circuit system 710. N The second terminal of capacitor 806 is coupled to capacitors 803 and 812, resistor 809, and the first output (CD_OUTP) of AC coupler circuit system 710.

[0136] Resistor 809 has a first terminal and a second terminal. The first terminal of resistor 809 is coupled to provide a common-mode voltage (V). CM The common-mode supply terminal of resistor 809 is coupled to capacitors 803, 806, 812 and the first output (CD_OUTP) of AC coupler circuit system 710.

[0137] Capacitor 812 has a first terminal and a second terminal. The first terminal of capacitor 812 is coupled to a common-mode supply terminal that provides a common-mode voltage. The second terminal of capacitor 812 is coupled to capacitors 803 and 806, resistor 809, and the first output (CD_OUTP) of AC coupler circuit system 710. In some examples, capacitor 812 has a trimming input. In such examples, the trimming circuit system provides a trimming value to capacitor 812. The trimming value is used to set the capacitance of capacitor 812. Such capacitors are called adjustable capacitors.

[0138] Capacitor 815 has a first terminal and a second terminal. The first terminal of capacitor 815 is coupled to the third input (INM0) of AC coupler circuit system 710. The second terminal of capacitor 815 is coupled to capacitors 818 and 824, resistor 821 and the second output (CD_OUTM) of AC coupler circuit system 710.

[0139] Capacitor 818 has a first terminal and a second terminal. The first terminal of capacitor 818 is coupled to the fourth input (INM) of AC coupler circuit system 710. N The second terminal of capacitor 818 is coupled to capacitors 815 and 824, resistor 821, and the second output (CD_OUTM) of AC coupler circuit system 710.

[0140] Resistor 821 has a first terminal and a second terminal. The first terminal of resistor 821 is coupled to a common-mode supply terminal that provides a common-mode voltage. The second terminal of resistor 821 is coupled to capacitors 815, 818, 824 and the second output (CD_OUTM) of AC coupler circuit system 710.

[0141] Capacitor 824 has a first terminal and a second terminal. The first terminal of capacitor 824 is coupled to a common-mode supply terminal that provides a common-mode voltage. The second terminal of capacitor 824 is coupled to capacitors 815 and 818, resistor 821, and the second output (CD_OUTM) of AC coupler circuit system 710. In some examples, capacitor 824 has a trimming input. In such examples, the trimming circuit system provides a trimming value to capacitor 824. The trimming value is used to set the capacitance of capacitor 824. Such capacitors are called adjustable capacitors.

[0142] Transistor 827 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 827 is coupled to resistor 833 and transistor 836. The second terminal of transistor 827 is coupled to a common terminal providing a common potential. The control terminal of transistor 827 is coupled to a terminal providing a bias voltage (V). BIAS The bias supply terminal of ).

[0143] Transistor 830 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 830 is coupled to resistor 833 and transistor 839. The second terminal of transistor 830 is coupled to a common terminal that provides a common potential. The control terminal of transistor 830 is coupled to a bias supply terminal that provides a bias voltage.

[0144] Resistor 833 has a first terminal and a second terminal. The first terminal of resistor 833 is coupled to transistors 827 and 836. The second terminal of resistor 833 is coupled to transistors 830 and 839. In some examples, resistor 833 has a trimming input. In such examples, a trimming circuit system provides a trimming value to resistor 833. The trimming value is used to set the resistance of resistor 833. Such a resistor is called a trimmable resistor.

[0145] Transistor 836 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 836 is coupled to capacitor 842 and transistor 845. The second terminal of transistor 836 is coupled to transistor 827 and resistor 833. The control terminal of transistor 836 is coupled to the first output (CD_OUTP) of AC coupler circuit system 710.

[0146] Transistor 839 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 839 is coupled to capacitor 842 and transistor 848. The second terminal of transistor 839 is coupled to transistor 830 and resistor 833. The control terminal of transistor 839 is coupled to the second output (CD_OUTM) of AC coupler circuit system 710.

[0147] Resistor 842 has a first terminal and a second terminal. The first terminal of capacitor 842 is coupled to transistors 836 and 845. The second terminal of capacitor 842 is coupled to transistors 839 and 848. In some examples, capacitor 842 has a trimming input. In such examples, a trimming circuit system provides a trimming value to capacitor 842. The trimming value is used to set the capacitance of capacitor 842. Such capacitors are called adjustable capacitors.

[0148] Transistor 845 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 845 is coupled to transistor 848, capacitor 851, resistor 854, and the first output (BQ_OUTM) of filter circuit system 720. The second terminal of transistor 845 is coupled to transistor 836 and capacitor 842. The control terminal of transistor 845 is coupled to transistor 848, capacitor 851, resistor 857, and the second output (BQ_OUTP) of filter circuit system 720.

[0149] Transistor 848 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 848 is coupled to transistor 845, capacitor 851, resistor 857, and the second output (BQ_OUTP) of filter circuit system 720. The second terminal of transistor 848 is coupled to transistor 839 and capacitor 842. The control terminal of transistor 848 is coupled to transistor 845, capacitor 851, resistor 854, and the first output (BQ_OUTM) of filter circuit system 720.

[0150] Capacitor 851 has a first terminal and a second terminal. The first terminal of capacitor 851 is coupled to the first output (BQ_OUTM) of transistors 845, 848, resistor 854, and filter circuit system 720. The second terminal of capacitor 851 is coupled to the second output (BQ_OUTP) of transistors 845, 848, resistor 854, and filter circuit system 720. In some examples, capacitor 851 has a trimming input. In such examples, the trimming circuit system provides a trimming value to capacitor 851. The trimming value is used to set the capacitance of capacitor 851. Such capacitors are called adjustable capacitors.

[0151] Resistor 854 has a first terminal and a second terminal. The first terminal of resistor 854 is coupled to a supply voltage (e.g., V). DD The supply terminals of resistor 854 (such as AVDD, etc.) are connected to transistors 845 and 848, capacitor 851, and the first output (BQ_OUTM) of filter circuit system 720.

[0152] Resistor 857 has a first terminal and a second terminal. The first terminal of resistor 857 is coupled to a supply terminal that provides the supply voltage. The second terminal of resistor 857 is coupled to the second output (BQ_OUTP) of transistors 845, 848, capacitor 851, and filter circuit system 720.

[0153] Transistor 860 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 860 is coupled to capacitor 866, resistor 869, and transistor 872. The second terminal of transistor 860 is coupled to a common terminal that provides a common potential. The control terminal of transistor 860 is coupled to a bias supply terminal that provides a bias voltage.

[0154] Transistor 863 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 863 is coupled to capacitor 866, resistor 869, and transistor 875. The second terminal of transistor 863 is coupled to a common terminal that provides a common potential. The control terminal of transistor 863 is coupled to a bias supply terminal that provides a bias voltage.

[0155] Capacitor 866 has a first terminal and a second terminal. The first terminal of capacitor 866 is coupled to transistors 860 and 872 and resistor 869. The second terminal of capacitor 866 is coupled to transistors 863 and 875 and resistor 869.

[0156] Resistor 869 has a first terminal and a second terminal. The first terminal of resistor 869 is coupled to transistors 860 and 872 and capacitor 866. The second terminal of resistor 869 is coupled to transistors 863 and 875 and capacitor 866.

[0157] Transistor 872 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 872 is coupled to transistors 875 and 878 and the first output (OUTP_Z) of source follower circuit system 730. The second terminal of transistor 872 is coupled to transistor 860, capacitor 866, and resistor 869. The control terminal of transistor 872 is coupled to transistors 875 and 881 and the second output (OUTM_Z) of source follower circuit system 730.

[0158] Transistor 875 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 875 is coupled to transistors 872 and 881 and the second output (OUTM_Z) of source follower circuit system 730. The second terminal of transistor 875 is coupled to transistor 863, capacitor 866, and resistor 869. The control terminal of transistor 875 is coupled to transistors 872 and 878 and the first output (OUTP_Z) of source follower circuit system 730.

[0159] Transistor 878 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 878 is coupled to a supply terminal that provides the supply voltage. The second terminal of transistor 878 is coupled to the first output (OUTP_Z) of transistors 872, 875, and source follower circuit system 730. The control terminal of transistor 878 is coupled to the first output (BQ_OUTM) of filter circuit system 720.

[0160] Transistor 881 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 881 is coupled to a supply terminal that provides the supply voltage. The second terminal of transistor 881 is coupled to the second output (OUTM_Z) of transistors 872, 875, and source follower circuit system 730. The control terminal of transistor 881 is coupled to the second output (BQ_OUTP) of filter circuit system 720.

[0161] exist Figure 8 In the examples, transistors 827, 830, 836, 839, 845, 848, 860, 863, 872, 875, 878, and 881 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 827, 830, 836, 839, 845, 848, 860, 863, 872, 875, 878, and 881 can be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar junction transistors (BJTs), or p-type equivalents with slight modifications. Transistors 827, 830, 836, 839, 845, 848, 860, 863, 872, 875, 878, and 881 can be depletion-type devices, extended-drain devices, enhancement-type devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 827, 830, 836, 839, 845, 848, 860, 863, 872, 875, 878, and 881 can be implemented on / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0162] Figure 9 yes Figure 7 and 8 A schematic diagram of an example of an AC coupler circuit system 710. Figure 9In the example, the AC coupler circuit system 710 includes a first transistor 905, a second transistor 910, a first resistor 915, a second resistor 920, a third transistor 925, a third resistor 930, a fourth transistor 935, a fourth resistor 940, a first capacitor 945, a fifth transistor 950, a sixth transistor 955, a fifth resistor 960, a sixth resistor 965, a seventh transistor 970, a seventh resistor 975, an eighth transistor 980, an eighth resistor 985, and a second capacitor 990.

[0163] The AC coupler circuit system 710 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first, second, third, and fourth inputs of the AC coupler circuit system 710 (INP0, INP...) N INM0, INM N This is configured to be coupled to a digital signal source. The digital signal source provides differential pairs of digital signals at the first and second inputs of the transmitter circuit system 420. For example, Figure 4 The serializer 410 provides a serial data stream for use across Figure 6 The communication channel 610 transmits data. The first and second outputs (CD_OUTP, CD_OUTM) of the AC coupler circuit system 710 are coupled to the filter circuit system 720.

[0164] Transistor 905 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 905 is coupled to resistor 915. The second terminal of transistor 905 is coupled to a common terminal that provides a common potential. The control terminal of transistor 905 is coupled to transistor 925 and the first input (INP0) of AC coupler circuit system 710.

[0165] Transistor 910 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 910 is coupled to resistor 940. The second terminal of transistor 910 is coupled to a common terminal providing a common potential. The control terminal of transistor 910 is coupled to the second input (INP) of AC coupler circuit system 710. N ).

[0166] Resistor 915 has a first terminal and a second terminal. The first terminal of resistor 915 is coupled to resistors 920, 930, 940, capacitor 945, and the second output (CD_OUTM) of AC coupler circuit system 710. The second terminal of resistor 915 is coupled to transistor 910.

[0167] Resistor 920 has a first terminal and a second terminal. The first terminal of resistor 920 is coupled to transistor 925. The second terminal of resistor 920 is coupled to resistors 915, 930, 940, capacitor 945, and the second output (CD_OUTM) of AC coupler circuit system 710.

[0168] Transistor 925 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 925 is coupled to provide a common-mode voltage (V). CM The common-mode supply terminal of transistor 925 is coupled to resistor 920. The control terminal of transistor 925 is coupled to the first input (INP0) of transistor 905 and AC coupler circuit system 710.

[0169] Resistor 930 has a first terminal and a second terminal. The first terminal of resistor 930 is coupled to transistor 935. The second terminal of resistor 930 is coupled to resistors 915, 920, 940, capacitor 945, and the second output (CD_OUTM) of AC coupler circuit system 710.

[0170] Transistor 935 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 935 is coupled to provide a common-mode voltage (V). CM The common-mode supply terminal of transistor 935 is coupled to resistor 930. The control terminal of transistor 935 is coupled to a common terminal that provides a common potential.

[0171] Resistor 940 has a first terminal and a second terminal. The first terminal of resistor 940 is coupled to resistors 915, 920, 930, capacitor 945, and the second output (CD_OUTM) of AC coupler circuit system 710. The second terminal of resistor 940 is coupled to transistor 910.

[0172] Capacitor 945 has a first terminal and a second terminal. The first terminal of capacitor 945 is coupled to the second output (CD_OUTM) of resistors 915, 920, 930, 940 and AC coupler circuit system 710. The second terminal of capacitor 945 is coupled to a common terminal that provides a common potential.

[0173] Transistor 950 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 950 is coupled to resistor 960. The second terminal of transistor 950 is coupled to a common terminal that provides a common potential. The control terminal of transistor 950 is coupled to transistor 970 and the third input (INM0) of AC coupler circuit system 710.

[0174] Transistor 955 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 955 is coupled to resistor 985. The second terminal of transistor 955 is coupled to a common terminal providing a common potential. The control terminal of transistor 955 is coupled to the fourth input (INM) of AC coupler circuit system 710. N ).

[0175] Resistor 960 has a first terminal and a second terminal. The first terminal of resistor 960 is coupled to resistors 965, 975, 985, capacitor 990, and the first output (CD_OUTP) of AC coupler circuit system 710. The second terminal of resistor 960 is coupled to transistor 950.

[0176] Resistor 965 has a first terminal and a second terminal. The first terminal of resistor 965 is coupled to transistor 970. The second terminal of resistor 965 is coupled to resistors 960, 975, 985, capacitor 990, and the first output (CD_OUTP) of AC coupler circuit system 710.

[0177] Transistor 970 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 970 is coupled to provide a common-mode voltage (V). CM The common-mode supply terminal of transistor 970 is coupled to resistor 965. The control terminal of transistor 970 is coupled to the third input (INM0) of transistor 950 and AC coupler circuit system 710.

[0178] Resistor 975 has a first terminal and a second terminal. The first terminal of resistor 975 is coupled to transistor 980. The second terminal of resistor 975 is coupled to resistors 960, 965, 985, capacitor 990, and the first output (CD_OUTP) of AC coupler circuit system 710.

[0179] Transistor 980 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 980 is coupled to provide a common-mode voltage (V). CM The common-mode supply terminal of transistor 980 is coupled to resistor 975. The control terminal of transistor 980 is coupled to a common terminal that provides a common potential.

[0180] Resistor 985 has a first terminal and a second terminal. The first terminal of resistor 985 is coupled to resistors 960, 965, 975, capacitor 990, and the first output (CD_OUTP) of AC coupler circuit system 710. The second terminal of resistor 985 is coupled to transistor 955.

[0181] Capacitor 990 has a first terminal and a second terminal. The first terminal of capacitor 990 is coupled to resistors 960, 965, 975, 985 and the first output (CD_OUTP) of AC coupler circuit system 710. The second terminal of capacitor 990 is coupled to a common terminal that provides a common potential.

[0182] exist Figure 9 In the examples, transistors 905, 910, 950, and 955 are n-channel MOSFETs. Alternatively, transistors 905, 910, 950, and 955 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or p-type equivalents with slight modifications. Figure 9 In the examples, transistors 925, 935, 970, and 980 are p-channel MOSFETs. Alternatively, transistors 925, 935, 970, and 980 can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or slightly modified n-type equivalent devices. Transistors 905, 910, 925, 935, 950, 955, 970, and 980 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 905, 910, 925, 935, 950, 955, 970, and 980 can be implemented on / on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0183] Figure 10 It means that it can be used. Figure 4 , 5 The flowcharts for example implementations, instantiations, and / or operations of the transmitter circuit system 420 of 6, 7, and 8 are provided. Figure 10 Example operation 1000 begins at block 1005, where the transmitter circuitry 420 receives a signal for transmission. In this example operation, the transmitter circuitry 420 receives first and second digital input signals (INP, INM) from a digital source, such as... Figure 4 and 6 The serializer 410. The first and second digital input signals are a pair of differential signals, representing the signals used for, for example... Figure 6 The communication channel 610 transmits a serial data stream.

[0184] Figure 7 , 8 The AC coupler circuit system 710 of 9 sets the common-mode voltage of the signal (box 1010). In some example operations, such as in... Figure 8In the diagram, capacitors 803, 806, 812 and resistor 809 are relative to the common-mode voltage (V). CM The first digital input signal is set. Similarly, capacitors 815, 818, 824 and resistor 821 set the second digital input signal relative to the common-mode voltage. Advantageously, the AC coupler circuit system 710 couples the first and second digital signals (INP, INM) to the common-mode voltage.

[0185] In some example operations, such as in Figure 9 middle, Figure 9 Resistors 915, 920, 930, 940, 960, 965, 975, and 985 form a resistive voltage divider circuit system. Resistors 915, 920, 930, 940, 960, 965, 975, and 985 divide the digital signals (INP0, INM0) at the input of the transmitter circuit system 420 relative to the common-mode voltage at the common-mode supply. In some examples, resistors 915, 920, 930, 940, 960, 965, 975, and 985 attenuate the digital signals (INP0, INM0) at the input of the transmitter circuit system 420. In such example operations, Figure 9 Resistors 915, 920, 930, 940, 960, 965, 975, and 985, and capacitors 945 and 990, are used to set the rise and fall times at the outputs of the AC coupler circuit system 710. Advantageously, in some examples, setting the output resistance and output capacitance of both the first and second outputs of the AC coupler circuit system 710 to be equal can make the rise and fall times at the first and second outputs equal to each other.

[0186] In some example operations, as shown by the dashed outline, the AC coupler circuit system 710 divides the signal amplitude for pulse amplitude modulation (PAM) (Box 1015). In example operations, the transmitter circuit system 420 receives additional digital input signals with varying amplitudes. For example, capacitors 803 and 815 receive first and second digital signals (INP0, INM0), and capacitors 806 and 818 receive third and fourth digital signals (INP...). N INM N In this type of example, the voltages representing the logic levels of the first and second digital signals are different from the logic levels representing the third and fourth digital signals. This type of modulation used for transmitting multiple signals is called pulse amplitude modulation (PAM). In this example operation, capacitors 803, 806, and 812 divide the first and third digital signals (INP0, INP). NThe combined amplitude of the signals is transmitted by scaling the amplitude of the first scaled digital signal (CD_OUTP). Similarly, capacitors 815, 818, and 824 divide the second and fourth digital signals (INM0, INM...). N The combined amplitude is transmitted by scaling the amplitude of the second scaled digital signal (CD_OUTM). Advantageously, capacitors 803, 806, 812, 815, 818, and 824 support PAM transmission in response to scaling the combined amplitude for transmission.

[0187] In another example of PAM signaling, transistors 905 and 950 receive the first and second digital signals (INP0, INM0), and transistors 910 and 955 receive the third and fourth digital signals (INP0, INM0). N INM N In this type of example, resistors 915, 920, 930, and 940 divide the first and third digital signals (INP0, INP). N The combined amplitude of the signals is transmitted by scaling the amplitude of the first scaled digital signal (CD_OUTP). Similarly, resistors 940, 960, 965, 975, and 985 divide the second and fourth digital signals (INM0, INM...). N The combined amplitude is transmitted by scaling the amplitude of the second scaled digital signal (CD_OUTM). Advantageously, transistors 905, 910, 950, 955 and resistors 915, 920, 930, 940, 960, 965, 975, 985 support PAM signaling in response to scaling the combined amplitude for transmission.

[0188] Figure 7 and 8 The filter circuit system 720 uses a multi-stage filter to filter the AC-coupled signal (Box 1020). In example operation, resistors 833, 854, 857 and transistors 836, 839 pass through a DC gain (GAIN) circuit. DC Amplify the scaled digital signals (CD_OUTP, CD_OUTM). In some examples, the DC gain of the filter circuit system 720 responds to the transconductance of transistors 836 and 839. ), the first resistor of resistor 833 ( ) and the second resistors of resistors 854 and 857 ( In such examples, the DC gain of the filter circuit system 720 is obtained using equation (1). Furthermore, in some examples, resistors 809, 821, and 833 may have tuning inputs to tune the DC gain of the filter circuit system 720. In such example operation, capacitors 842 and 851, transistors 845 and 848, and resistors 854 and 857 form a second-order filter, also known as a bi-quad filter. In some examples, the natural frequency (F) of the filter circuit system 720 is... N The quality factor (Q) responds to the first capacitance of capacitor 842. ), the transconductance of transistors 845 and 848 ( ), the second capacitor of capacitor 851 ( ) and the resistance of resistors 854 and 857 ( In such examples, the natural frequency of the filter circuit system 720 is obtained using equation (2), and the quality factor of the filter circuit system 720 is obtained using equation (3). Furthermore, in some examples, capacitors 842 and 851 may have tuning inputs to tune the bandwidth of the filter circuit system 720. The filter circuit system 720 generates first and second filtered signals (BQ_OUTP, BQ_OUTM) in response to filtering the scaled digital signal.

[0189] Equation (1)

[0190] Equation (2)

[0191] Equation (3)

[0192] Figure 7 and 8 The source follower circuit system 730 compensates for the load at the output (Box 1025). In example operation, transistors 878, 881 drive the first and second output signals (OUTP_Z, OUTM_Z) of the source follower circuit system 730 in response to the first and second filtered signals (BQ_OUTP, BQ_OUTM). In such example operation, transistors 872, 875 are configured as a cross-coupled transistor pair, located after transistors 878, 881. In some examples, transistors 872, 875 compensate for the impedance at the first and second outputs of the source follower circuit system 730 in response to the operation of transistors 878, 881. In some examples, the resistance (R) of the source follower circuit system 730 is... OUT_DOWN ) is based on the capacitance of capacitor 866 ( ), resistor 869 ( ), the transconductance of transistors 872 and 875 ( ), resistors of transistors 872 and 875 ( The frequencies (s) of the first and second output signals (OUTP_Z, OUTM_Z) are also considered. In this example, the resistance of the source follower circuit system 730 is derived using equation (4). Advantageously, the cross-coupling of transistors 872 and 875 increases the bandwidth of the transmitter circuit system 420 in response to the essentially eliminated frequency contribution of the first and second output signals. Advantageously, capacitor 866 further increases the impedance bandwidth of the transmitter circuit system 420 by reducing the frequency dependence of the resistance of the source follower circuit system 730.

[0193] Equation (4)

[0194] Figure 7 Resistor 740 is used to match the impedance of the transmission line (Box 1030). In example operation, resistor 740 and the resistance (R) at the output of the source follower circuit system 730 are... OUT_DOWN The impedance of the communication channel, such as communication channel 610, is configured to match its resistance. For example, in response to the source follower circuit system 730 having a resistance of ten ohms (Ω), the resistance of communication channel 610 having a resistance of fifty ohms, and resistor 740 having a resistance of forty ohms. Advantageously, matching the impedance of communication channel 610 increases power efficiency and reduces reflections.

[0195] Transmitter circuitry 420 transmits signals (Box 1035). In example operation, resistor 740 transmits a scaled version of the output signal (OUTP_Z) by driving communication channel 610. In some examples, resistor 750 transmits a second scaled version of the output signal (OUTM_Z) to termination circuitry, such as capacitor 760 and resistor 765. In other examples, such as when communication channel 610 is a twisted pair, resistor 750 transmits a second scaled version of the output signal by driving communication channel 610.

[0196] Figure 4 , 6 The load circuit system 460 of 7 replicates the impedance of the transmission line (Box 1040). In example operation, resistors 770 and 780 replicate the reduction in amplitude of the output signals (OUTP_Z, OUTM_Z) by resistors 740 and 750. For example, resistors 770 and 780 have the same resistance as resistors 740 and 750.

[0197] Figure 4 , 6The load circuit system 460 of 7 generates a copy of the signal for transmission (Box 1045). In example operation, the resistance of resistor 790 terminates the current to the output signal at the input of the combined circuit system 470. In this example operation, the load circuit system 460 provides a copy of the signal transmitted across the communication channel 610. Advantageously, the low impedance output of the source follower circuit system 730 allows the load circuit system 460 to provide a copy of the output signal to the combined circuit system 470.

[0198] Figure 4 , 6 The combined circuit system 470 of 7 subtracts a copy of the transmitted signal from the signal transmitted on the transmission line (Box 1050). In example operation, the combined circuit system 470 subtracts a copy of the transmitted signal from the signal of the communication channel 610. In this type of example operation, the combined circuit system 470 provides data from other devices to the receiver circuit system 440. This type of cancellation of the transmitted signal is called echo cancellation.

[0199] Figure 4 and 6 The receiver circuitry 440 decodes the data based on the subtracted signal (box 1055). In example operation, the combinational circuitry 470 provides the received signal from the communication channel 610 to the receiver circuitry 440. In this example operation, the receiver circuitry 440 amplifies the received signal, taking into account signal attenuation across the communication channel 610. Control continues back to box 1005.

[0200] Example methods are referenced Figure 10 The flowchart shown is illustrated. However, many other implementations may also be used in this specification. Figure 4 , 5 Methods for transmitter circuit systems 420 of 6, 7, and 8. For example, the execution order of the blocks can be changed, and some of the blocks described can be changed, eliminated, or combined. Similarly, additional operations can be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0201] Figure 11A yes Figure 4 , 6 Figure 1100 shows an example operation of the transmitter circuit system 420 of types 7 and 8. Figure 11A In the example, graph 1100 illustrates the transmitted signal 1110. The transmitted signal 1110 represents signal transmission across communication channel 610 via transmitter circuitry 420. Advantageously, filter circuitry 720 generates the transmitted signal 1110 in response to smoothing relatively abrupt changes in the digital input signal. Advantageously, the transmitted signal 1110 is a sinusoidal signal, less susceptible to inter-symbol interference (ISI), jitter, and harmonic distortion.

[0202] Figure 11B yes Figure 4 , 6 Figure 1120 shows an example operation of the transmitter circuit system 420 across a spectrum for 7 and 8. Figure 11B In the example, graph 1120 has a fundamental frequency of 1130 and a harmonic frequency of 1140. The fundamental frequency 1130 represents the transmission frequency of the signal transmitted by the transmitter circuit system 420. The harmonic frequency 1140 is a multiple of the fundamental frequency 1130. The difference between the signal power at the fundamental frequency 1130 and the harmonic frequency 1140 is called the spurious-free dynamic range (SFDR) of the transmitter circuit system 420. Advantageously, the difference between the signal power at the fundamental frequency 1130 and the harmonic frequency 1140 allows the receiver circuit system 440 to accurately detect the signal at the fundamental frequency 1130.

[0203] Figure 12 yes Figure 5 and 6 The delay circuit system 520 and Figure 5 and 6 A block diagram of an example of a transmitter circuit system 530. Figure 12 The example delay circuit system 520 includes a first example delay element 1205, a second example delay element 1210, a third example delay element 1215, a fourth example delay element 1220, a fifth example delay element 1225, and a sixth example delay element 1230. Figure 12 The example transmitter circuit system 530 includes a first example FFE segment 1235, a second example FFE segment 1240, a third example FFE segment 1245, an example impedance compensation circuit system 1250, and an example load circuit system 1255.

[0204] The delay circuit system 520 has a first input, a second input, a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. The first and second inputs (INP, INM) of the delay circuit system 520 are configured to be coupled to a digital signal source. The digital signal source provides differential pairs of digital signals at the first and second inputs of the delay circuit system 520. For example, Figure 5 The serializer 510 provides a serial data stream for use across Figure 6 The communication channel 610 transmits data. The first and fourth outputs (INP_SEG0, INM_SEG0) of the delay circuit system 520 are coupled to the FFE segment 1235. The second and fifth outputs (INP_SEG1, INM_SEG1) of the delay circuit system 520 are coupled to the FFE segment 1240. The third and sixth outputs (INP_SEGN, INM_SEGN) of the delay circuit system 520 are coupled to the FFE segment 1245.

[0205] Transmitter circuit system 530 has a first input, a second input, a third input, a fourth input, a fifth input, a sixth input, a first output, and a second output. The first, second, third, fourth, fifth, and sixth inputs of transmitter circuit system 530 are coupled to delay circuit system 520. The first and second outputs (OUTP, OUTM) of transmitter circuit system 530 are configured to be coupled to a communication channel, such as communication channel 610.

[0206] Delay element 1205 has an input and an output. The input of delay element 1205 is coupled to delay elements 1210, 1215 and the first input (INP) of delay circuit system 520. The output of delay element 1205 is coupled to FFE segment 1235.

[0207] Delay element 1210 has an input and an output. The input of delay element 1210 is coupled to the first input (INP) of delay elements 1205, 1215 and delay circuit system 520. The output of delay element 1210 is coupled to FFE segment 1240.

[0208] Delay element 1215 has an input and an output. The input of delay element 1215 is coupled to the first input (INP) of delay elements 1205, 1210 and delay circuit system 520. The output of delay element 1215 is coupled to FFE segment 1245.

[0209] Delay element 1220 has an input and an output. The input of delay element 1220 is coupled to the second input (INM) of delay elements 1225, 1230 and delay circuit system 520. The output of delay element 1220 is coupled to FFE segment 1235.

[0210] Delay element 1225 has an input and an output. The input of delay element 1225 is coupled to the second input (INM) of delay elements 1220, 1230 and delay circuit system 520. The output of delay element 1225 is coupled to FFE segment 1240.

[0211] Delay element 1230 has an input and an output. The input of delay element 1230 is coupled to the second input (INM) of delay elements 1220, 1225 and delay circuit system 520. The output of delay element 1230 is coupled to FFE segment 1245.

[0212] FFE segment 1235 has a first input, a second input, a first output, and a second output. The first input of FFE segment 1235 is coupled to delay element 1205. The second input of FFE segment 1235 is coupled to delay element 1220. The first output of FFE segment 1235 is coupled to FFE segments 1240 and 1245 and impedance compensation circuit system 1250. The second output of FFE segment 1235 is coupled to FFE segments 1240 and 1245 and impedance compensation circuit system 1250. Example of FFE segment 1235 Figure 13 and 14 Further illustration and description.

[0213] FFE segment 1240 has a first input, a second input, a first output, and a second output. The first input of FFE segment 1240 is coupled to delay element 1210. The second input of FFE segment 1240 is coupled to delay element 1225. The first output of FFE segment 1240 is coupled to FFE segments 1235 and 1245 and impedance compensation circuit system 1250. The second output of FFE segment 1240 is also coupled to FFE segments 1235 and 1245 and impedance compensation circuit system 1250. (Example of FFE segment 1240 follows.) Figure 13 and 14 Further illustration and description.

[0214] FFE segment 1245 has a first input, a second input, a first output, and a second output. The first input of FFE segment 1245 is coupled to delay element 1215. The second input of FFE segment 1245 is coupled to delay element 1230. The first output of FFE segment 1245 is coupled to FFE segments 1235 and 1240 and impedance compensation circuit system 1250. The second output of FFE segment 1245 is coupled to FFE segments 1235 and 1240 and impedance compensation circuit system 1250. Example of FFE segment 1245 Figure 13 and 14 Further illustration and description.

[0215] Impedance compensation circuit system 1250 has a first input, a second input, a first output, and a second output. The first and second inputs of impedance compensation circuit system 1250 are coupled to FFE segments 1235, 1240, and 1245. The first output of impedance compensation circuit system 1250 is coupled to the first output (OUTP) of load circuit system 1255 and transmitter circuit system 530. The second output of impedance compensation circuit system 1250 is coupled to the second output (OUTM) of load circuit system 1255 and transmitter circuit system 530. An example of impedance compensation circuit system 1250 is provided. Figure 13 and 14 Further illustration and description.

[0216] The load circuit system 1255 has a first output and a second output. The first output of the load circuit system 1255 is coupled to the first output (OUTP) of the impedance compensation circuit system 1250 and the transmitter circuit system 530. The second output of the load circuit system 1255 is coupled to the second output (OUTM) of the impedance compensation circuit system 1250 and the transmitter circuit system 530.

[0217] Figure 12 Delay circuit system 520 and Figure 12 Example operation of transmitter circuit system 530 Figure 12 Show and describe.

[0218] Figure 13 yes Figure 5 , 6 A schematic diagram of an example of the transmitter circuit system 530 of 12. Figure 13 Example transmitter circuit system 530 includes Figure 12 The FFE segments 1235, 1240, 1245 Figure 12 Impedance compensation circuit system 1250 and Figure 12 The load circuit system 1255. Figure 13 Example FFE segment 1235 includes a first example buffer 1305, a first example capacitor 1310, a second example capacitor 1315, a first example resistor 1320, a first example transistor 1325, a second buffer 1330, a third example capacitor 1335, a fourth example capacitor 1340, an example trimmer circuit system 1345, a second example resistor 1350, and a second example transistor 1355. Figure 13 The example impedance compensation circuit system 1250 includes an example capacitor 1360, a first example transistor 1365, and a second example transistor 1370. Figure 13 The example load circuit system 1255 includes a first example resistor 1375 and a second example resistor 1380.

[0219] Transmitter circuit system 530 has a first input, a second input, a third input, a fourth input, a fifth input, a sixth input, a first output, and a second output. The first, second, third, fourth, fifth, and sixth inputs of transmitter circuit system 530 are coupled to delay circuit system 520. The first and second outputs (OUTP, OUTM) of transmitter circuit system 530 are configured to be coupled to a communication channel, for example... Figure 6 Communication channel 610.

[0220] Buffer 1305 has an input and an output. The input of buffer 1305 is coupled to the first input (INP_SEG0) of transmitter circuit system 530. The output of buffer 1305 is coupled to capacitor 1310.

[0221] Capacitor 1310 has a first terminal and a second terminal. The first terminal of capacitor 1310 is coupled to buffer 1305. The second terminal of capacitor 1310 is coupled to capacitor 1315, resistor 1320 and transistor 1325.

[0222] Capacitor 1315 has a first terminal, a second terminal, and a trimming input. The first terminal of capacitor 1315 is coupled to capacitor 1310, resistor 1320, and transistor 1325. The second terminal of capacitor 1315 is coupled to a common terminal that provides a common potential. The trimming input of capacitor 1315 is coupled to trimming circuitry 1345.

[0223] Resistor 1320 has a first terminal and a second terminal. The first terminal of resistor 1320 is coupled to capacitors 1310 and 1315 and transistor 1325. The second terminal of resistor 1320 is coupled to a bias voltage (V) provided. BIAS The bias supply terminal of ).

[0224] Transistor 1325 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1325 is coupled to FFE segments 1240 and 1245, capacitor 1360, and transistor 1365. The second terminal of transistor 1325 is coupled to a common terminal that provides a common potential. The control terminal of transistor 1325 is coupled to capacitors 1310 and 1315 and resistor 1320.

[0225] Buffer 1330 has inputs and outputs. The input of buffer 1330 is coupled to the second input (INM_SEG0) of FFE segment 1235. The output of buffer 1330 is coupled to capacitor 1335.

[0226] Capacitor 1335 has a first terminal and a second terminal. The first terminal of capacitor 1335 is coupled to buffer 1330. The second terminal of capacitor 1335 is coupled to capacitor 1340, resistor 1350 and transistor 1355.

[0227] Capacitor 1340 has a first terminal, a second terminal, and a trimming input. The first terminal of capacitor 1340 is coupled to capacitor 1335, resistor 1350, and transistor 1355. The second terminal of capacitor 1340 is coupled to a common terminal that provides a common potential. The trimming input of capacitor 1340 is coupled to trimming circuitry 1345.

[0228] The fine-tuning circuit system 1345 has a first output and a second output. The first output of the fine-tuning circuit system is coupled to a capacitor 1315. The second output of the fine-tuning circuit system 1345 is coupled to a capacitor 1340.

[0229] Resistor 1350 has a first terminal and a second terminal. The first terminal of resistor 1350 is coupled to capacitors 1335 and 1340 and transistor 1355. The second terminal of resistor 1350 is coupled to a bias supply terminal that provides the supply voltage.

[0230] Transistor 1355 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1355 is coupled to FFE segments 1240 and 1245, capacitor 1360, and transistor 1370. The second terminal of transistor 1355 is coupled to a common terminal that provides a common potential. The control terminal of transistor 1355 is coupled to capacitors 1335 and 1340 and resistor 1350.

[0231] Capacitor 1360 has a first terminal and a second terminal. The first terminal of capacitor 1360 is coupled to FFE segments 1235, 1240, 1245 and transistors 1325, 1365. The second terminal of capacitor 1360 is coupled to FFE segments 1235, 1240, 1245 and transistors 1355, 1370. In some examples, capacitor 1360 has a trim input. In such examples, a trim circuit system provides a trim value to capacitor 1360. The trim value is used to set the capacitance of capacitor 1360. Such capacitors are called adjustable capacitors.

[0232] Transistor 1365 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1365 is coupled to transistor 1370, resistor 1375, and the second output (OUTM) of transmitter circuit system 530. The second terminal of transistor 1365 is coupled to FFE segments 1235, 1240, 1245, transistor 1325, and capacitor 1360. The control terminal of transistor 1365 is coupled to transistor 1370, resistor 1380, and the first output (OUTP) of transmitter circuit system 530.

[0233] Transistor 1370 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 1370 is coupled to transistor 1365, resistor 1380, and the first output of transmitter circuit system 530. The second terminal of transistor 1370 is coupled to FFE segments 1235, 1240, 1245, transistor 1355, and capacitor 1360. The control terminal of transistor 1370 is coupled to transistor 1365, resistor 1375, and the second output (OUTM) of transmitter circuit system 530.

[0234] Resistor 1375 has a first terminal and a second terminal. The first terminal of resistor 1375 is coupled to a supply terminal that provides the supply voltage. The second terminal of resistor 1375 is coupled to the second output (OUTM) of transistors 1365, 1370 and transmitter circuit system 530.

[0235] Resistor 1380 has a first terminal and a second terminal. The first terminal of resistor 1380 is coupled to a supply terminal that provides the supply voltage. The second terminal of resistor 1380 is coupled to the first output (OUTP) of transistors 1365, 1370 and transmitter circuit system 530.

[0236] exist Figure 13 In the examples, transistors 1325, 1355, 1365, and 1370 are n-channel MOSFETs. Alternatively, transistors 1325, 1355, 1365, and 1370 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or p-type equivalent devices with slight modifications. Transistors 1325, 1355, 1365, and 1370 can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 1325, 1355, 1365, and 1370 can be implemented on / on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0237] Figure 13 The FFE segments 1235, 1240, 1245 Figure 13 Impedance compensation circuit system 1250 and Figure 13 Example operation of the load circuit system 1255 combined Figure 15 Show and describe.

[0238] Figure 14 yes Figure 5 , 6 A schematic diagram of another example of the transmitter circuit system 530 of 12 and 13. Figure 14 Example transmitter circuit system 530 includes Figure 12 The FFE segments 1235, 1240, 1245 Figure 12 Impedance compensation circuit system 1250 and Figure 12 The load circuit system 1255. Figure 14 Example FFE segment 1235 includes a first example multiplexing segment 1410, a second example multiplexing segment 1420, a first example current drive segment 1430, a second example current drive segment 1440, a third example multiplexing segment 1450, a fourth example multiplexing segment 1460, a third example current drive segment 1470, and a fourth example current drive segment 1480.

[0239] Figure 14 Example reuse segment 1410 contains Figure 13 Buffer 1305 Figure 13 Capacitors 1310, 1315 and Figure 13 The resistor is 1320. Figure 14 Example current drive segment 1440 includes Figure 13 The transistor 1325. Figure 14 Example reuse segment 1450 contains Figure 13 Buffer 1330, Figure 13 Capacitors 1335, 1340 and Figure 13 The resistor is 1350. Figure 14 Example current drive segment 1470 includes Figure 13 The 1355 transistor.

[0240] exist Figure 13 In this embodiment, the transmitter circuitry 530 is configured to implement PAM using multiplexing sections 1410, 1420, 1450, 1460 and current-driven sections 1430, 1440, 1470, 1480. In some examples, the transmitter circuitry 530 may be modified to include any number of multiplexing sections or current-driven sections to support additional signals. Figure 14 The FFE segments 1235, 1240, 1245 Figure 14 Impedance compensation circuit system 1250 and Figure 14 Example operation of the load circuit system 1255 combined Figure 15 Show and describe.

[0241] Figure 15 It means that it can be used. Figure 5 , 6 The flowcharts for example implementations of the transmitter circuit system 530 of 1, 12, 13 and 14, including example machine-readable instructions or example operations 1500, are provided. Figure 15 Example operation 1500 begins at block 1505, where capacitors 1315 and 1340 set the FFE tap weights. In this example operation, capacitors 1310 and 1315 form a first voltage divider circuit system, and capacitors 1335 and 1340 form a second voltage divider circuit system. In this type of example operation, the capacitance ratio of capacitors 1310 and 1335 to capacitors 1315 and 1340 is used to set the scaling ratio of the input signal. In some examples, FFE segment 1235 includes a fine-tuning circuit system 1345 for setting the capacitance of capacitors 1315 and 1340. In this type of example, the scaling ratio of capacitors 1310, 1315, 1335, and 1340 to the input signal is referred to as the tap weight.

[0242] Delay circuit system 520 sets the FFE delay (box 1510). In example operation, delay elements 1205, 1220 delay the edges of the input signal by a first delay, delay elements 1210, 1225 delay the edges of the input signal by a second delay, and delay elements 1215, 1230 delay the edges of the input signal by a third delay. In this example operation, the transmitted signal has a first amplitude before the end of the first delay, a second amplitude before the end of the second delay, and a third amplitude before the end of the third delay. This variation in transmitted amplitude is called feedforward equalization (FFE). In this example, the delay of delay circuit system 520 is used for the sequencing of FFE segments 1235, 1240, 1245.

[0243] Transmitter circuitry 530 receives signals for transmission (Box 1515). In example operation, transmitter circuitry 530 receives first and second digital input signals (INP, INM) from a digital source, such as... Figure 5 and 6 The serializer 510. The first and second digital input signals are a pair of differential signals, representing the signals used for, for example... Figure 6 The communication channel 610 transmits a serial data stream.

[0244] The delay circuit system 520 delays the signal to form multiple delayed signals (box 1520). In example operation, the delay circuit system 520 continues to sort the current contributions of each of the FFE segments 1235, 1240, and 1245 according to the length of the delay value. For example, the FFE segments 1235, 1240, and 1245 begin to absorb current in response to the edge of the input signal. At a first time, after a first delay of the delay elements 1205 and 1220, the FFE segment 1235 stops conducting current, thereby reducing the transmission amplitude. At a second time, after a second delay of the delay elements 1210 and 1225, the FFE segment 1240 stops conducting current, thereby further reducing the transmission amplitude. At a third time, after a third delay of the delay elements 1215 and 1230, the FFE segment 1245 stops conducting current, thereby ending the transmission. Advantageously, the delay circuit system 520 sorts the current contributions of the FFE segments 1235, 1240, and 1245. Alternatively, the transmitter circuit system 530 can be modified to use an alternative circuit system to sequence the currents of FFE segments 1235, 1240, and 1245.

[0245] Capacitors 1310, 1315, 1335, and 1340 divide the amplitude of the delayed signal by the FFE tap weight (Box 1525). In example operation, capacitors 1310 and 1315 divide the input signal by the capacitance ratio, and capacitors 1335 and 1340 divide the input signal by the capacitance ratio. In this example operation, adjusting the capacitance of capacitors 1315 and 1340 controls the segmentation of the input signal. Advantageously, the segmentation of the input signal by capacitors 1310, 1315, 1335, and 1340 controls the amplitude of the current contribution of FFE segment 1235. Similarly, adjusting the corresponding capacitance ratio of the respective capacitors of FFE segments 1240 and 1245 controls the reduction of the amplitude during the FFE period.

[0246] Resistors 1320 and 1350 set the bias of the FFE signal (Box 1530). In the example operation, resistors 1320 and 1350 will bias the voltage (V) BIAS The control terminals of transistors 1325 and 1355 are coupled to them. In some examples, the current from resistors 1320 and 1350 shortens the switching time of transistors 1325 and 1355 in response to biasing the control terminals toward a threshold voltage. In other examples, the current from resistors 1320 and 1350 sets the common-mode voltage of the divided input signal.

[0247] Transistors 1325 and 1355 generate drive current based on the FFE signal and a delay (Box 1535). In example operation, transistors 1325 and 1355 are controlled by a divided input signal. In this type of example operation, transistors 1325 and 1355 draw current from impedance compensation circuitry 1250 in response to receiving a divided input signal corresponding to a logic high (e.g., logic one).

[0248] Impedance compensation circuitry system 1250 combines the drive current of the FFE signal (box 1540). In example operation, transistors 1365 and 1370 are cross-coupled to form a positive feedback loop that actively compensates for the output impedance. This feedback loop between capacitor 1360 and transistors 1365 and 1370 provides a summing node for the current from FFE segments 1235, 1240, and 1245. In some examples, the summing node is referred to as virtual ground. In this example operation, transistors 1365 and 1370, in response to the cross-coupling, sequence the supply of combined current from resistors 1375 and 1380.

[0249] Impedance compensation circuitry 1250 filters the drive current (box 1545). In example operation, capacitor 1360 and transistors 1365, 1370 filter the drive current from FFE segments 1235, 1240, 1245 in response to cross-coupling.

[0250] Impedance compensation circuitry system 1250 compensates for the load at the output (box 1550). In example operation, the resistance (R) of impedance compensation circuitry system 1250 is... OUT_DOWN The resistance is independent of the load. The impedance compensation circuit system has a resistance (R) of 1250. OUT_DOWN ) is based on the capacitance of capacitor 1360 ( ), the transconductance of transistors 1365 and 1370 ( ), the first resistor of transistors 1325 and 1355 ( ), the second resistor of transistors 1365 and 1370 ( The frequencies (s) of the first and second output signals (OUTP, OUTM) are also considered. In this example, the resistance of the impedance compensation circuit system 1250 is derived using equation (5). Advantageously, in response to compensating for return losses at relatively high frequencies, transistors 1365, 1370 and capacitor 1360 increase the impedance bandwidth of the transmitter circuit system 530. In this example operation, the impedance at the outputs (OUTP, OUTN) of the transmitter circuit system 530 is determined by a resistor (R) parallel to the impedance compensation circuit system 1250. OUT_DOWN The resistors are set to 1375 and 1380.

[0251] Equation (5)

[0252] The load circuit system 1255 matches the impedance of the transmission line (box 1555). In example operation, resistors 1375 and 1380 are configured to match the impedance of the communication channel during the positive portion of signal transmission. In this type of example operation, the impedance compensation circuit system 1250 matches the impedance of the transmission line for the negative portion of signal transmission.

[0253] Transmitter circuitry 530 transmits signals (box 1560). In example operation, transistors 1365 and 1370 drive communication channel 610 by using current flowing through the FFE segments 1235, 1240, and 1245 of resistors 1375 and 1380. In this example operation, there is no current conduction by transistor 1365 that increases the voltage of the second output signal (OUTM). Similarly, current conduction by transistor 1365 pulls down the second output signal in response to a voltage difference across resistor 1375. Control continues back to box 1505.

[0254] Example methods are referenced Figure 15 The flowchart shown is illustrated. However, many other implementations may also be used in this specification. Figure 5 , 6Methods for the transmitter circuit system 530 of 12, 13, and 14. For example, the execution order of the blocks can be changed, and some of the blocks described can be changed, eliminated, or combined. Similarly, additional operations can be included before, between, or after the blocks shown in the illustrated example during the manufacturing process.

[0255] Figure 16 yes Figure 5 , 6 Graph 1600 shows an example operation of transmitter circuit system 530 of 1, 2, 3, and 4. Figure 16 In the example, graph 1600 shows a non-cross-coupled impedance 1610 and a cross-coupled impedance 1620 over a frequency range. In operation, the non-cross-coupled impedance 1610 decreases as the frequency increases. This decrease is in response to the parasitic capacitance of the FFE segment and the load capacitance. In the example operation of the transmitter circuit system 530, the cross-coupled impedance 1620 compensates for the attenuation of the communication channel 610 as the frequency increases. Advantageously, Figure 13 and 14 The cross-coupled transistors 1365 and 1370 compensate for signal attenuation at high frequencies.

[0256] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., including, comprising, including, having, etc.) in the preamble or in any kind of claim statement, additional elements, items, etc., may be present without falling outside the scope of the corresponding claim or statement. As used herein, for example, when the phrase "at least" is used as a transitional term in the preamble of a claim, it is open-ended, just as the terms "comprising" and "including" are open-ended. When used in the form of, for example, A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" refers to an implementation that includes any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0257] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude plurals. As used herein, the term "a / an" refers to one or more of the stated objects. The terms "a / an", "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or actions may be implemented by, for example, the same entity or object. Additionally, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that the combination of features is unfeasible and / or disadvantageous.

[0258] As used herein, unless otherwise stated, the term "above" describes the relationship of two parts relative to the Earth. The first part is above the second part if the second part has at least one section between the Earth and the first part. Similarly, as used herein, the first part is "below" the second part when the first part is closer to the Earth than the second part. As mentioned above, the first part can be above or below the second part, where one or more of the following exist: there are other parts between them, there are no other parts between them, the first and second parts are in contact, or the first and second parts are in direct contact with each other.

[0259] As used in such a patent, stating that any part (e.g., layer, film, region, area, or plate) is located on another part in any way (e.g., positioned on it, located on it, placed on it, or formed on it, etc.) indicates that the referenced part is in contact with said other part, or that the referenced part is above said other part, with one or more intermediate parts positioned therebetween.

[0260] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate member between at least one of the referenced elements in a relative movement between the connection reference or elements. Therefore, a connection reference does not necessarily imply that two elements are directly connected or fixed to each other. As used herein, the statement that any part is in “contact” with another part is defined to mean that there is no intermediate portion between the two parts.

[0261] Unless otherwise specifically stated, descriptors such as “first,” “second,” and “third” are used herein without any meaning that indicates priority, physical order, arrangement in a list, or sorting, but merely as labels or at least one of any names to distinguish elements in order to facilitate understanding of the described examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in the claims by different descriptors (such as “second” or “third”). In such cases, such descriptors are used only to clearly identify these elements in the context of the discussion (as in the claims), for example, where these elements may otherwise share the same name.

[0262] As used herein, “approximately” and “about” modify their objects / values ​​to identify variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. For example, unless otherwise specified, “approximately” and “about” may indicate that these dimensions are within a tolerance of + / - 10%.

[0263] As used herein, the phrase “communication” includes variations thereof, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and not requiring direct physical (e.g., wired) communication or constant communication, but also including selective communication carried out at at least one of periodic intervals, predetermined intervals, non-periodic intervals or one-off events.

[0264] As used herein, a “programmable circuit system” is defined to include at least one of the following: (i) one or more special-purpose circuits (e.g., application-specific integrated circuits (ASICs)) configured to perform a particular operation and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that are programmable to perform one or more particular functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as a central processing unit (CPU) capable of executing first instructions to perform one or more operations or functions; an FPGA programmable with second instructions that enable a field-programmable gate array (FPGA) to be configured and / or constructed to instantiate one or more operations or functions corresponding to the first instructions; a graphics processing unit (GPU) capable of executing first instructions to perform one or more operations or functions; a digital signal processor (DSP) capable of executing first instructions to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers capable of executing first instructions to perform one or more operations or functions; or integrated circuits, such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented in a heterogeneous computing system that includes multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., or any combination thereof) and orchestration techniques (e.g., application programming interfaces (APIs)) that can assign computational tasks to programmable circuit systems of suitable type that can perform computational tasks.

[0265] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupled with multiple circuit elements, system-on-a-chip (SoC), etc.

[0266] In this specification, the term "coupled" may cover a connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by the control signal generated by device A.

[0267] A device “configured” to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform the function and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Such configuration may be achieved through at least one of the device’s firmware or software programming, through at least one of the device’s hardware components and interconnects’ construction or layout, or through a combination thereof.

[0268] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless explicitly stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0269] In the specification and claims, the described "circuit system" may comprise one or more circuits. A circuit or device described herein as containing certain components can actually be used to couple to those components to form the described circuit system or device. For example, a structure described as comprising one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., voltage and / or current sources) can actually comprise only a semiconductor element within a single physical device (e.g., at least one in a semiconductor die or integrated circuit (IC) package) and can be used, during or after manufacturing, for example by at least one of an end user or a third party, to couple to at least some of the passive elements or sources to form the described structure.

[0270] The circuits described herein can be reconfigured to include the replaced components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some components in the described examples are included in the integrated circuit, and other components are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as outside the integrated circuit may be included in the integrated circuit, and some features shown as inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are at least one of the following: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0271] The use of the phrase “ground” in the above description includes at least one of the following: chassis ground, earth, floating ground, virtual ground, digital ground, public ground, or any other form of ground connection applicable to or suited to the teachings of this specification. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates a difference of + / -10% from said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0272] Within the scope of the claims, the described embodiments may be modified, and other embodiments are possible.

Claims

1. An apparatus comprising: A filter circuit system having a first output and a second output; A source follower circuit system has a first input, a second input, and an output, wherein the first input of the source follower circuit system is coupled to the first output of the filter circuit system, and the second input of the source follower circuit system is coupled to the second output of the filter circuit system. A resistor having a first terminal and a second terminal; A load circuit system having an input and an output, wherein the input of the load circuit system is coupled to the output of the source follower circuit system and the first terminal of the resistor; as well as A combinational circuit system having a first input and a second input, the first input of the combinational circuit system being coupled to a second terminal of the resistor, and the second input of the combinational circuit system being coupled to the output of the load circuit system.

2. The device of claim 1, wherein the filter circuit system further has a first input and a second input, and the device further includes an AC coupler circuit system having a first output and a second output, the first output of the AC coupler circuit system being coupled to the first input of the filter circuit system, and the second output of the AC coupler circuit system being coupled to the second input of the filter circuit system.

3. The device of claim 2, wherein the resistor is a first resistor, and the AC coupler circuit system comprises: A first capacitor, which has terminals; A second capacitor has terminals; The second resistor has a first terminal and a second terminal; as well as A third capacitor has a first terminal and a second terminal, the first terminal of the third capacitor being coupled to the first input of the filter circuit system, the terminal of the first capacitor, the terminal of the second capacitor and the first terminal of the second resistor, and the second terminal of the third capacitor being coupled to the second terminal of the second resistor.

4. The device of claim 1, wherein the filter circuit system comprises: A first capacitor has a first terminal and a second terminal; A first transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the first terminal of the first capacitor; The second transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first capacitor; as well as A second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is coupled to the first input of the source follower circuit system, the second terminal of the first transistor, and the control terminal of the second transistor. The second terminal of the second capacitor is coupled to the second input of the source follower circuit system, the control terminal of the first transistor, and the second terminal of the second transistor.

5. The device of claim 4, wherein the resistor is a first resistor, and the filter circuit system further comprises: A third transistor having a first terminal and a second terminal, wherein the first terminal of the third transistor is coupled to the first terminal of the first capacitor and the first terminal of the first transistor; A fourth transistor having a first terminal and a second terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the first capacitor and the first terminal of the second transistor; The second resistor has a first terminal and a second terminal; A fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor being coupled to the second terminal of the third transistor and the first terminal of the second resistor; as well as A sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor being coupled to the second terminal of the fourth transistor and the second terminal of the second resistor, and the control terminal of the sixth transistor being coupled to the control terminal of the fifth transistor.

6. The device of claim 1, wherein the resistor is a first resistor, and the source follower circuit system comprises: A first transistor having a first terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the first output of the filter circuit system; A second transistor having a first terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the second output of the filter circuit system; The third transistor has a first terminal, a second terminal, and a control terminal; A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the first terminal of the second transistor and the control terminal of the third transistor, and the control terminal of the fourth transistor is coupled to the first terminal of the first resistor, the input of the load circuit system, the first terminal of the first transistor, and the first terminal of the third transistor. as well as A second resistor has a first terminal and a second terminal, the first terminal of the second resistor being coupled to the second terminal of the third transistor, and the second terminal of the second resistor being coupled to the second terminal of the fourth transistor.

7. The device of claim 6, wherein the source follower circuit system further comprises: A capacitor having a first terminal and a second terminal; A fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor being coupled to the second terminal of the third transistor, the first terminal of the second resistor, and the first terminal of the capacitor; and A sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor being coupled to the second terminal of the fourth transistor, the second terminal of the second resistor and the second terminal of the capacitor, and the control terminal of the sixth transistor being coupled to the control terminal of the fifth transistor.

8. The device of claim 1, wherein the resistor is a first resistor, the output of the source follower circuit system is a first output, the source follower circuit system further has a second output, the combined circuit system further has a third input, and the load circuit system comprises: A second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the first output of the source follower circuit system and the first terminal of the first resistor; A third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the second output of the source follower circuit system; as well as A fourth resistor has a first terminal and a second terminal, the first terminal of the fourth resistor being coupled to the second terminal of the second resistor and the second input of the combined circuit system, and the second terminal of the fourth resistor being coupled to the second terminal of the third resistor and the third input of the combined circuit system.

9. The device of claim 1, wherein the filter circuit system further has an input, the combination circuit system further has an output, and the device further comprises: A communication channel having a second terminal coupled to the resistor and a terminal of the first input of the combined circuit system; A serializer circuit system having an output coupled to the input of the filter circuit system; as well as A receiver circuit system having an input coupled to the output of the combined circuit system.

10. The device of claim 9, wherein the terminal of the communication channel is a first terminal, the communication channel further has a second terminal, the receiver circuit system is a first receiver circuit system, and the device further comprises: Transmitter circuit system, which has an output; as well as The second receiver circuit system has a second terminal coupled to the communication channel and an input to the output of the transmitter circuit system.

11. An apparatus comprising: A receiver circuit system having an input; A transmitter circuit system having a first output, a second output, a third output, and a fourth output; as well as Echo cancellation circuit system, comprising: A load circuit system having a first input, a second input, a first output, and a second output, wherein the first input of the load circuit system is coupled to the first output of the transmitter circuit system, and the second input of the load circuit system is coupled to the second output of the transmitter circuit system; as well as A combinational circuit system having a first input, a second input, a third input, a fourth input, and an output, wherein the first input of the combinational circuit system is coupled to the third output of the transmitter circuit system, the second input of the combinational circuit system is coupled to the fourth output of the transmitter circuit system, the third input of the combinational circuit system is coupled to the first output of the load circuit system, the fourth input of the combinational circuit system is coupled to the second output of the load circuit system, and the output of the combinational circuit system is coupled to the input of the receiver circuit system.

12. The device of claim 11, wherein the transmitter circuitry comprises: A filter circuit system having a first output and a second output; A source follower circuit system has a first input, a second input, a first output, and a second output, wherein the first input of the source follower circuit system is coupled to the first output of the filter circuit system, and the second input of the source follower circuit system is coupled to the second output of the filter circuit system. A first resistor has a first terminal and a second terminal, the first terminal of the first resistor being coupled to the first input of the load circuit system and the first output of the source follower circuit system, and the second terminal of the first resistor being coupled to the first input of the combined circuit system. as well as A second resistor has a first terminal and a second terminal, the first terminal of the second resistor being coupled to the second input of the load circuit system and the second output of the source follower circuit system, and the second terminal of the second resistor being coupled to the second input of the combined circuit system.

13. The device of claim 12, wherein the filter circuit system further has a first input and a second input, and the device further includes an AC coupler circuit system having a first output and a second output, the first output of the AC coupler circuit system being coupled to the first input of the filter circuit system, and the second output of the AC coupler circuit system being coupled to the second input of the filter circuit system.

14. The device of claim 12, wherein the filter circuit system comprises: A first capacitor has a first terminal and a second terminal; A first transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the first terminal of the first capacitor; The second transistor has a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the first capacitor; as well as A second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is coupled to the first input of the source follower circuit system, the second terminal of the first transistor, and the control terminal of the second transistor. The second terminal of the second capacitor is coupled to the second input of the source follower circuit system, the control terminal of the first transistor, and the second terminal of the second transistor.

15. The device of claim 12, wherein the source follower circuit system comprises: A first transistor having a first terminal and a control terminal, wherein the control terminal of the first transistor is coupled to the first output of the filter circuit system; A second transistor having a first terminal and a control terminal, wherein the control terminal of the second transistor is coupled to the second output of the filter circuit system; The third transistor has a first terminal, a second terminal, and a control terminal; A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the first terminal of the second transistor and the control terminal of the third transistor, and the control terminal of the fourth transistor is coupled to the first terminal of the first resistor, the input of the load circuit system, the first terminal of the first transistor, and the first terminal of the third transistor. as well as A resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the second terminal of the third transistor, and the second terminal of the resistor being coupled to the second terminal of the fourth transistor.

16. The device of claim 11, wherein the load circuit system comprises: A first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first output of the transmitter circuit system; A second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second output of the transmitter circuit system; as well as A third resistor has a first terminal and a second terminal, the first terminal of the third resistor being coupled to the second terminal of the first resistor and the third input of the combined circuit system, and the second terminal of the third resistor being coupled to the second terminal of the second resistor and the fourth input of the combined circuit system.

17. The device of claim 11, wherein the transmitter circuit system is a first transmitter circuit system, the receiver circuit system is a first receiver circuit system, and the device further comprises: A communication channel having a first terminal and a second terminal, the first terminal of the communication channel being coupled to the third output of the first transmitter circuit system and the first input of the combined circuit system; The second transmitter circuit system has an output; as well as The second receiver circuit system has a second terminal coupled to the communication channel and an input to the output of the second transmitter circuit system.

18. An apparatus comprising: The first transmitter circuit system has an output; A communication channel having a first terminal and a second terminal, the first terminal of the communication channel being coupled to the output of the first transmitter circuit system; The second transmitter circuit system has a first output and a second output; An echo cancellation circuit system having a first input, a second input, and an output, wherein the first input of the echo cancellation circuit system is coupled to the first output of the second transmitter circuit system, and the second input of the echo cancellation circuit system is coupled to the second terminal of the communication channel and the second output of the second transmitter circuit system; as well as A receiver circuit system having an input coupled to the output of the echo cancellation circuit system.

19. The device of claim 18, wherein the echo cancellation circuit system further comprises a third input and a fourth input, and the device further comprises: The second transmitter circuit system includes: A filter circuit system having a first output and a second output; A source follower circuit system has a first input, a second input, a first output, and a second output, wherein the first input of the source follower circuit system is coupled to the first output of the filter circuit system, and the second input of the source follower circuit system is coupled to the second output of the filter circuit system. A first resistor has a first terminal and a second terminal, the first terminal of the first resistor being coupled to the second terminal of the communication channel, the first input of the echo cancellation circuit system and the first output of the source follower circuit system, and the second terminal of the first resistor being coupled to the second input of the echo cancellation circuit system. as well as A second resistor has a first terminal and a second terminal. The first terminal of the second resistor is coupled to the third input of the echo cancellation circuit system and the second output of the source follower circuit system. The second terminal of the second resistor is coupled to the fourth input of the echo cancellation circuit system. The echo cancellation circuit system includes: A load circuit system having an input and an output, the input of the load circuit system being coupled to the first output of the second transmitter circuit system; and A combined circuit system having a first input, a second input, and an output, wherein the first input of the combined circuit system is coupled to a second terminal of the communication channel and a second output of the second transmitter circuit system, the second input of the combined circuit system is coupled to the output of the load circuit system, and the output of the combined circuit system is coupled to the input of the receiver circuit system.

20. The device of claim 18, wherein the first transmitter circuit system comprises: The first feedforward equalization (FFE) segment has an output; The second FFE segment has an output; and An impedance compensation circuit system having an input and an output, wherein the input of the impedance compensation circuit system is coupled to the output of the first FFE segment and the output of the second FFE segment, and the output of the impedance compensation circuit system is coupled to the first terminal of the communication channel.

21. The device of claim 20, wherein the first FFE segment comprises: An amplifier that has an output; A first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the output of the amplifier; A second capacitor has terminals; as well as A transistor having a first terminal and a control terminal, the first terminal of the transistor being coupled to the output of the second FFE segment and the input of the impedance compensation circuit system, and the control terminal of the transistor being coupled to the second terminal of the first capacitor and the terminal of the second capacitor.

22. The device of claim 20, wherein the output of the first FFE segment is a first output, the first FFE segment further has a second output, the output of the second FFE segment is a first output, the second FFE segment further has a second output, and the impedance compensation circuit system comprises: A capacitor having a first terminal and a second terminal; A first transistor has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first transistor is coupled to the first output of the first FFE segment, the first output of the second FFE segment, and the first terminal of the capacitor; and The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the second output of the first FFE segment, the second output of the second FFE segment, and the second terminal of the capacitor. The second terminal of the second transistor is coupled to the control terminal of the first transistor. The control terminal of the second transistor is coupled to the first terminal of the communication channel and the second terminal of the first transistor.

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