High-speed USB isolation chip and working method thereof

Abstract

This invention discloses a high-speed USB isolation chip and its operating method, comprising: encoding the original data with unremoved fill bits to reduce the signal-to-frequency ratio, and transmitting it to the opposite die through a high-voltage isolation coupling device; encoding a custom data packet to reduce the signal-to-frequency ratio, and transmitting it to the opposite die through a high-voltage isolation coupling device for synchronization. This invention solves the problem of difficult isolation transmission of high-speed USB signals, improves the reliability of USB hot-plugging, features a simple and efficient circuit, reduces the high-frequency performance requirements of the manufacturing process, and lowers costs.

Description

[0001] This application is a divisional application of application number 202511843178.7. The original application was filed on December 9, 2025, with application number 202511843178.7, and the invention title is "A High-Speed ​​USB Isolation Chip and Its Working Method". Technical Field

[0002] This invention belongs to the field of USB communication technology, and in particular relates to a high-speed USB isolation chip and its working method. Background Technology

[0003] USB is a universal serial data bus widely used in electronic devices such as PCs, mobile phones, tablets, and instruments. USB supports hot-swapping, and the external USB ports of instruments need to be prepared for hot-swapping by various unknown devices. Some devices using high voltage may pose signal interference and surge risks when hot-swapping USB cables. Features like high-voltage fast charging further increase the risk of damage to the host's USB port from accidental contact with high voltage. Existing technologies have relatively mature isolation solutions for digital signals, but these are mainly suitable for full-duplex single-voltage digital signals or low-speed analog signals. They lack comprehensive isolation for mixed analog signals of various voltage levels, such as approximately 400mV low-voltage 480Mbps high-speed USB signals, approximately 800mV negotiation high-speed handshake signals, and approximately 3.3V full-speed low-speed signals, as well as for event status information such as connection disconnections.

[0004] Existing technologies such as CN102591826B, CN104298641B, and CN103703451B focus on basic signals and operations such as pull-up resistors, pull-down resistors, USB connections, and speed detection, all emphasizing isolation transmission at the physical signal level. However, the original USB signal originally used a wide-bandwidth wired connection, not for transmission through high-voltage isolation devices with limited bandwidth. If transmitted directly without a carrier, the original wideband USB signal would be distorted due to the limited bandwidth of the isolation device. If a carrier scheme is used, the carrier frequency matched to 480Mbps typically needs to be more than 10 times higher, placing high demands on the performance of the high-voltage isolation device.

[0005] On the other hand, due to the large variety of USB signal rates, voltages, and event status information, existing technologies CN104298641B and CN103703451B require the use of many high-voltage isolation devices to transmit various voltages and statuses of physical signals, resulting in large areas, high costs, and poor anti-interference capabilities. Summary of the Invention

[0006] Purpose of the invention: In order to solve the problem of difficulty in isolating and transmitting high-speed USB signals in the prior art and improve the reliability of USB hot-plugging, the present invention provides a high-speed USB isolation chip and its working method.

[0007] Technical solution: A method for operating a high-speed USB isolation chip, comprising the following steps: Generation of the encoded signal for the communication signal: The USB transceiver receives the communication signal and outputs the raw data, which is without removing bit padding bits; the raw data is encoded in a way that reduces the signal frequency ratio, including: encoding using mBnB encoding method, where n>m, to obtain the encoded signal of the communication signal; Generation of the encoding signal of the custom data packet: Obtain at least one of the communication rate and the USB bus status, generate a custom data packet, the custom data packet containing at least one of the communication rate and the USB bus status, and encode the custom data packet in a way that reduces the signal frequency ratio to obtain the encoding signal of the custom data packet; Transmission of encoded signals: The encoded signals include encoded signals of communication signals or encoded signals of custom data packets. The encoded signals are transmitted via a half-duplex high-speed differential transceiver and transmitted to the bare die on the other side through a high-voltage isolation coupling device. Reception and processing of encoded signals: The receiving die receives the encoded signal, decodes it, and transmits the decoded data packet to the USB transceiver and the custom data packet processing module. This includes: first identifying the decoded data packet; if it is identified as a custom data packet, then parsing the custom data packet, synchronizing according to the parsing result, and the USB transceiver does not transmit; if it is not identified as a custom data packet, then the USB transceiver transmits it after a delay of T1 after decoding.

[0008] Furthermore, when the communication signal received by the USB transceiver is a non-high-speed signal, the output of the non-high-speed data stream also includes first converting the non-high-speed data stream into a high-speed data stream with the same frequency as the high-speed USB data stream, and then encoding the high-frequency converted data by reducing the signal frequency ratio to obtain the high-frequency converted encoded signal.

[0009] Furthermore, it also includes a selection process, in which a selection is made from the raw data, the custom data packet, and the high-frequency converted data, and then encoded by reducing the signal frequency ratio to obtain the encoded signal for subsequent transmission.

[0010] Furthermore, the ratio of the highest frequency to the lowest frequency of the encoded signal does not exceed 4, and the number of consecutive 0 bits does not exceed 4, and the number of consecutive 1 bits does not exceed 4.

[0011] Furthermore, upon detecting a device connection, device disconnection, or bus event, a custom data packet is generated. The state machine and control module disable the transmit output of the half-duplex high-speed differential transceiver. After waiting for time T2, the custom data packet is sent to the other side die via the half-duplex high-speed differential transceiver. T2 is not less than the timeout end time agreed upon by the receive module of the half-duplex high-speed differential transceiver. After receiving the custom data packet, the other side die synchronizes the connection status and bus events and replies with an acknowledgment packet.

[0012] Furthermore, after the chip is powered on or reset, both dies default to downlink mode. Each die enables the pull-down detection of its own USB port to check if there is a device connected. When either die detects a device connected to its own USB port, that die sends a custom data packet containing the device connection status or bus event to the other die. Both dies determine the uplink and downlink modes. The die that detects a device connection remains in downlink mode, while the other die enters uplink mode.

[0013] A high-speed USB isolation chip includes at least two dies coupled via a high-voltage isolation coupling device, wherein the dies comprise: A USB transceiver is used to receive communication signals and output raw data, which is not padded with bits; it is also used to transmit data packets received from the other side's die. A state machine and control module are used to acquire at least one of the communication rate and USB bus status; and to synchronize with the counterpart die based on custom data packets. A custom data packet processing module is used to generate custom data packets, which contain at least one of the following: communication rate and USB bus status; it is also used to parse the custom data packets transmitted by the other side's bare die and transmit the parsing results to the state machine and control module. The encoding module is used to encode the original data or custom data packets in a way that reduces the signal-to-frequency ratio, including: encoding using mBnB encoding, where n > m, to obtain the encoded signal; A half-duplex high-speed differential transceiver is used to transmit encoded signals to the opposite die through high-voltage isolation coupling devices, and to receive encoded signals from the opposite die. The decoding module is used to decode the encoded signal transmitted from the bare die on the other side and send the decoded data packet to the delay control unit and the custom data packet processing module. If the custom data packet is identified, it is parsed and synchronized according to the parsing result, and the USB transceiver does not transmit. The delay control unit is used to receive the decoded data packets. When the data packet is a non-custom data packet, it will be sent out by the USB transceiver after a delay of T1 after decoding.

[0014] Furthermore, the die also includes a high-frequency conversion module. When the communication signal received by the USB transceiver is a non-high-speed signal, a non-high-speed data stream is output. The high-frequency conversion module is used to convert the non-high-speed data stream into a high-speed data stream with the same frequency as the high-speed USB data stream.

[0015] Furthermore, the bare die also includes a selection unit, the input of which is connected to at least two of the following: a USB transceiver, a custom data packet processing module, and a high-frequency conversion module; the output of which is connected to an encoding module; and the selection control terminal of which is connected to a state machine and a control module.

[0016] Furthermore, the ratio of the highest frequency to the lowest frequency of the encoded signal does not exceed 4, and the number of consecutive 0 bits does not exceed 4, and the number of consecutive 1 bits does not exceed 4.

[0017] Furthermore, the bare die also includes a RESET protocol handshake module, which connects the USB transceiver and the state machine and control module, and is used to organize bidirectional handshake communication in accordance with USB specification requirements to identify USB high-speed capabilities.

[0018] Furthermore, the die also includes a clock module connected to a USB transceiver, which is also used to output data of the discarded bit padding bits; the clock module includes a clock tracking unit, which is used to calibrate its own clock based on periodic SOF packets in the data of the discarded bit padding bits.

[0019] Furthermore, the two dies include an inner die and an outer die. The outer die further includes a first high-voltage NMOS, a second high-voltage NMOS, a gate drive module, and a boost pump. The drain of the first high-voltage NMOS is connected to the UD+ port of the outer USB, and the source of the first high-voltage NMOS is connected to the D+ terminal of the outer die USB transceiver. The drain of the second high-voltage NMOS is connected to the UD- port of the outer USB, and the source of the second high-voltage NMOS is connected to the D- terminal of the outer die USB transceiver. The rated gate voltage of the first high-voltage NMOS and the second high-voltage NMOS is not less than 3V and not more than 5.5V, and the rated drain voltage is... The operating voltage is not less than 4 times its rated gate voltage; the output terminal of the boost pump is connected to the gate drive module, which is used to provide the first high-voltage NMOS and the second high-voltage NMOS with a gate voltage higher than the external die power supply voltage. The boost pump is controlled by the state machine and the control module according to the communication rate; let the equivalent internal resistance of the inner die USB transceiver be R1, the equivalent internal resistance of the outer die USB transceiver be R2, let the on-resistance of the first high-voltage NMOS be R3, and let the preferred value of the USB specification be R0, then 0.9*R0≤R2+R3≤1.1*R0, 0.9*R0≤R1≤1.1*R0.

[0020] Compared with the prior art, the high-speed USB isolation chip and its working method provided by the present invention have the following beneficial effects:

[0021] (1) Existing technologies focus on isolation transmission at the physical signal level. However, the original USB signal originally uses a wired connection with a wide bandwidth, not for transmission to high-voltage isolation devices with limited bandwidth. If carrierless transmission is used, the original wideband USB signal will be distorted due to the limited bandwidth of the isolation device. If a carrier scheme is used, the carrier frequency matched to 480Mbps usually needs to be more than 10 times the frequency, which places high demands on the performance of the high-voltage isolation device. This invention encodes the high-speed USB signal to reduce the signal frequency ratio. The frequency ratio of the highest frequency of the encoded signal to the lowest frequency of the signal is smaller, which reduces the design difficulty of the isolation device to simultaneously meet the upper and lower frequency limits, and makes it easier to design isolation devices with smaller size and better signal quality. On the other hand, this invention appropriately increases the signal frequency through encoding, and the encoded signal can be directly used for isolation transmission without the need to use a higher frequency carrier that is several times higher than the target signal frequency for modulation in traditional isolation schemes. The circuit is simple and efficient, and the high-frequency performance requirements of the manufacturing process are reduced.

[0022] (2) Existing technologies require the use of numerous high-voltage isolation devices to transmit physical signals with various voltages and states, resulting in high costs. This invention uses coded data packets for isolated transmission, requiring fewer isolation devices and reducing costs. Furthermore, the encoded data transmission facilitates further error correction, while employing USB transceiver-related technologies to improve compatibility and signal quality. Custom data packets of the same type can transmit multiple connection and bus states. By cooperating with the custom data packet processing module and the delay control unit, the isolated transmission channel of normal communication data packets is used to synchronize the bus states and event information on both sides in a timely manner, ensuring the integrity and compatibility of the USB bus function.

[0023] (3) Unlike conventional USB transceivers that automatically remove bit padding, this invention is based on a specially designed USB transceiver that provides a receive output that retains bit padding data bits for encoding, so that internal data is naturally synchronized, no storage is required, the cost is low, and the transmission delay is smaller.

[0024] (4) The full-speed USB data stream and low-speed USB data stream are first converted into 480Mbps data stream, and then the encoding method and path of reducing the signal frequency ratio of high-speed USB data are reused. This unifies the rate of all internal isolated data streams, including custom data packets, reduces the difficulty of isolated transmission bandwidth design, and also reduces the number of isolation devices. Only a pair of differential devices with the fewest devices among various isolation schemes are needed.

[0025] (5) After power-on, it can automatically detect external connections and automatically determine the uplink or downlink mode through custom data packets without manual setting.

[0026] (6) The external USB port connected to the high-speed USB isolation chip can withstand accidental touch and instantaneous high voltage. When an accidental high voltage is detected, it can achieve self-protection, improve the withstand voltage of the USB pin, and avoid accidental damage to the USB pin due to high voltage fast charging. The built-in RESET protocol handshake module automatically identifies the USB data rate and turns on the boost pump as needed to support full-range transmission of USB low-speed or full-speed signals without affecting USB data communication. When transmitting low-voltage USB high-speed signals, the boost pump can be automatically turned off to reduce power consumption. The built-in series high voltage protection device adopts a specially designed low internal resistance USB transceiver, which makes the overall equivalent internal resistance more in line with the preferred value of the USB specification, with smaller overall parasitics and better signal bandwidth and quality. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the internal structure of the high-speed USB isolation chip in Example 1;

[0028] Figure 2 This is a schematic diagram of the internal structure of the high-speed USB isolation chip in Embodiment 2;

[0029] Figure 3 This is a schematic diagram of the internal structure of the high-speed USB isolation chip in Embodiment 3;

[0030] Figure 4 This is a schematic diagram of the internal structure of the high-speed USB isolation chip in Example 4;

[0031] Figure 5 This is a schematic diagram of the internal structure of the high-speed USB isolation chip in Example 5. Detailed Implementation

[0032] The present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments.

[0033] Example 1:

[0034] like Figure 1 As shown, a high-speed USB isolation chip includes at least two dies, which are insulated from each other and are typically mounted on two independent substrates. The inner die provides a set of inner ports, and the outer die provides a set of outer ports. (For simplicity, the diagram is omitted.) Figure 1 Only the internal structure of one side of the bare die is shown; the other side is omitted. The same applies to other embodiments.

[0035] The two dies are coupled via a high-voltage isolation coupling device. This device can exist independently of the two dies or be integrated into either die, and can employ methods such as transformer isolation or capacitor isolation. In this embodiment, the high-voltage isolation coupling device is a 4-port RF-grade high-frequency air-core transformer integrated into the outer die. A stacked two-layer inductor scheme is preferred, with a planar high-frequency transformer as a secondary option. Taking a stacked high-frequency transformer as an example, the two layers are isolated by a high-voltage resistant thick spacer layer (IMD) or polyimide. Each inductor has two ports: the two ports of the lower inductor are internal ports, connected downwards to a half-duplex high-speed differential transceiver via internal metal; the two ports of the upper inductor are two pads, connected to the two pads of the inner die via two metal wires. The high-frequency air-core transformer built into the chip has no magnetic core, and its bandwidth is limited. The lower frequency limit is mainly limited by factors such as inductance and the number of coil turns. If the target signal frequency is too low, the number of coil turns will be large, resulting in large parasitic capacitance, large area, and high cost. The upper frequency limit is mainly limited by its own parasitic capacitance, interlayer parasitic capacitance, and manufacturing process capabilities. If the number of coil turns is large, it will naturally increase parasitic capacitance, leading to insufficient high-frequency performance. Conventional digital isolation schemes are based on a relatively fixed high-frequency carrier. For example, the commonly used OOK modulation uses two states, with and without a carrier, to transmit 1 and 0 digital signals. Because the high-frequency carrier always has only a single frequency, the bandwidth required for isolation transmission is very narrow, and the isolation device is relatively easy to design. However, this scheme can only transmit target digital signals with relatively low frequencies, usually one-tenth or even lower than the high-frequency carrier frequency. Otherwise, the jitter of the digital signal decoded by the receiver will be relatively large, causing signal timing distortion. Existing technology is difficult to apply to the transmission of high-speed USB data with a target signal of 480Mbps. The scheme of this embodiment can easily achieve the effect of isolating and transmitting high-speed USB data using high-voltage isolation coupling devices.

[0036] Each bare die includes: a USB transceiver, an encoding module, a custom data packet processing module, a half-duplex high-speed differential transceiver, a decoding module, a delay control unit, a state machine and control module, a RESET protocol handshake module, and a clock module, and may also include other modules.

[0037] A USB transceiver is used to receive communication signals. It can output regular data with padded bits removed or raw data without padded bits removed. Regular data is used for calibrating its own clock or for common applications such as USB controllers. Raw data is used for signal encoding and isolated transmission, avoiding timing gaps caused by removing padded bits from regular data. No additional data storage and synchronization are required, ensuring natural internal data synchronization and lower transmission latency. The USB transceiver also transmits data packets received from the other side's die (from the isolation chip). The USB transceiver can also provide connection status and control ports, connecting to RESET protocol handshake modules, state machines, and control modules. This allows the state machine and control module to know the USB bus status and communication rate in real time, such as detecting bus events like device connection, disconnection, bus reset, and wake-up.

[0038] The encoding module is used to encode the original data by reducing the signal frequency ratio to obtain the encoded signal;

[0039] A half-duplex high-speed differential transceiver is used to transmit encoded signals to the other side die through high-voltage isolation coupling devices, and to receive encoded signals from the other side die. The half-duplex high-speed differential transceiver may include an amplitude detection circuit to detect the presence of half-duplex communication signals. The detection result is connected to the state machine and control module, and can be used for idle state judgment, transmit / receive switching, timeout detection, etc. of half-duplex circuits.

[0040] The state machine and control module are used to obtain the communication rate and USB bus status, and to synchronize with the other side's bare chip according to custom data packets. The state machine and control module usually need to connect to various modules within the bare chip on this side to know their status and control their execution.

[0041] A custom data packet processing module is used to generate custom data packets, which include communication rate and USB bus status, or may include only one of these as needed; it is used to parse the custom data packets transmitted by the other side's bare die, and transmit the parsing results to the state machine and control module for synchronization;

[0042] The decoding module decodes the coded signals transmitted from the other end's die and sends the decoded data packets to the USB transceiver and the custom data packet processing module. If the data packet received by the USB transceiver is not a custom data packet, it is sent out. If the data packet received by the custom data packet is a custom data packet, it is parsed and synchronized according to the content of the custom data packet. Generally, custom data packets are sent immediately after the two devices establish a connection to synchronize them. After synchronization, the transmission of communication signals, i.e., sending non-custom data packets, begins.

[0043] If the application is needed in scenarios where custom data packets may be sent at any time, a delay control unit can be included. The bare die may also include a delay control unit, which receives the decoded data packets. When the data packet is a non-custom data packet, it is sent out by the USB transceiver after a delay of T1 time after decoding. T1 time is used to identify the data packet. If it is a custom data packet, it is only synchronized with the custom data packet processing module and is not sent through the USB transceiver.

[0044] To further support full-speed and low-speed data, the die may also include a high-frequency conversion module. When the communication signal received by the USB transceiver is a non-high-speed signal, a non-high-speed data stream is output. The high-frequency conversion module is used to convert the non-high-speed data stream into a high-frequency data stream with the same frequency as the high-speed USB data.

[0045] To improve the reusability of the circuit modules, the die may further include a selection unit. The input of the selection unit is connected to at least two of the following: a USB transceiver, a custom data packet processing module, and a high-frequency conversion module. The output of the selection unit is connected to an encoding module. The selection unit is controlled by a state machine and a control module. The selection unit is preferably positioned before the encoding module, but it can also be positioned after the encoding module, i.e., encoding precedes selection. The die also includes a RESET protocol handshake module, connected to the USB transceiver, the state machine, and the control module. This module is used to organize bidirectional handshake communication according to USB specifications to identify USB high-speed capabilities, including controlling the USB termination resistor and controlling the transmission and reception of Chirp J and Chirp K according to specifications.

[0046] The die also includes a clock module connected to a USB transceiver, which is also used to output conventional discarded bit stuffing data. The clock module may also include a clock tracking unit, which is used to calibrate its own clock based on periodic SOF packets in the discarded bit stuffing data.

[0047] A method for operating a high-speed USB isolation chip includes the following steps:

[0048] Generation of the encoded signal of the communication signal: The USB transceiver receives the communication signal and outputs the raw data, which is without removing the bit padding bits; the raw data is encoded in a way that reduces the signal frequency ratio to obtain the encoded signal of the communication signal;

[0049] The generation of the encoded signal for the custom data packet involves acquiring the communication rate and USB bus status, or, as needed, only one of these. The changes in the bus status and communication rate are processed by the custom data packet processing module to generate a high-speed custom data packet containing the aforementioned information. This custom data packet includes the communication rate and USB bus status, or, as needed, only one of these. The custom data packet is transmitted to the other side for synchronization. The other side will reproduce the aforementioned bus behavior or status and reply with an acknowledgment packet. To ensure reliability, if no acknowledgment packet is received after a timeout, the process will be retried after a certain period. The custom data packet is encoded using a reduced signal-to-frequency ratio method to obtain the encoded signal. Alternatively, the generation and encoding processes of the custom data packet can be performed simultaneously. Specifically, the number of consecutive 0s and 1s can be intentionally controlled during the generation of the custom data packet, effectively incorporating a built-in reduced signal-to-frequency ratio encoding. Therefore, the reduced signal-to-frequency ratio encoding module can be skipped, and the data can be directly sent to the half-duplex high-speed differential transceiver.

[0050] Transmission of encoded signals: The encoded signals include encoded signals of communication signals or encoded signals of custom data packets. The encoded signals are transmitted via a half-duplex high-speed differential transceiver and transmitted to the bare die on the other side through a high-voltage isolation coupling device.

[0051] Encoded signal reception and processing: The receiving die receives the encoded signal, decodes it, and transmits the decoded signal to the delay control unit and the custom data packet processing module. The custom data packet processing module identifies whether it is a custom data packet based on the specific header identifier of the custom data packet. If it is identified as a custom data packet, it parses the custom data packet, synchronizes the USB bus status and communication rate based on the parsing result, and controls the delay control unit or the USB transceiver to shut down the output directly or through the state machine and control module within time T1, so that the custom data packet will not be sent through the USB transceiver. Specifically, T1 is mainly determined by the number of bits required to identify the custom data packet, and is at least the time required for the identification of the custom data packet, usually equivalent to the time of several data bits. Preferably, after identifying the custom data packet, the output enable of the USB transceiver is forcibly disabled. In fact, at this time, the USB transceiver has not yet output due to the delay of the delay control unit, thus ensuring that the custom data packet will not be sent next. Another optional solution is to identify the custom data packet in the delay control unit, obtain information from it, and send it to the state machine and control module, so that the delay control unit or the state machine and control module shut down the output of the USB transceiver. Alternatively, the signal frequency reduction decoding module can be skipped, and the raw data received by the half-duplex high-speed differential transceiver can be directly identified as custom data packets. For example, by comparing specific identifiers in the header, the identification of custom data packets can be achieved in multiple stages. If a custom data packet is not identified, it is sent by the USB transceiver after a delay of T1 after decoding. Whether the data packet is sent can be controlled by directly controlling the output enable of the USB transceiver, or by controlling the output enable of the delay control unit.

[0052] Encoding by reducing the signal-to-frequency ratio includes using mBnB encoding to obtain an encoded signal, where n > m. The ratio of the highest frequency to the lowest frequency of the encoded signal does not exceed 4, and the number of consecutive 0 bits does not exceed 4, and the number of consecutive 1 bits does not exceed 4. Multiple consecutive 0s or 1s correspond to a lower frequency signal; for example, six consecutive unchanged bits are equivalent to a low frequency that is one-sixth the frequency of a high frequency, resulting in a wider bandwidth. This makes it difficult for high-voltage isolation devices to balance increasing inductance (increasing the number of coil turns) with reducing parasitic capacitance. A smaller frequency ratio reduces the design difficulty of high-voltage isolation devices, reduces the difficulty of bandwidth compensation in the receiver amplifier, and reduces signal distortion. When using 8B10B encoding, the bit rate increases to 600 Mbps; when using 8B12B encoding, the bit rate increases to 720 Mbps, and the number of consecutive 0s or 1s typically does not exceed 3, with the low frequency being only one-third the frequency of the high frequency. Unlike conventional 8B10B encoding, which focuses on the difference in the number of 0s and 1s and emphasizes solving the DC balance of the signal, the 8B10B encoding described in this embodiment focuses on the number of consecutive 0s or consecutive 1s and emphasizes reducing the frequency ratio. Although it is also called 8B10B, the encoding rules may be different, and the encoding conversion is usually based on table lookup.

[0053] When the USB transceiver receives a non-high-speed signal, such as a 12Mbps full-speed USB signal or a 1.5Mbps low-speed USB signal, the non-high-speed data stream can be first converted into a 480Mbps high-frequency data stream similar to high-speed USB. Specifically, this can be achieved by oversampling the full-speed low-speed data stream using a 480MHz clock, directly converting the low-frequency digital stream into a high-frequency digital stream. Then, the converted high-frequency data is encoded by reducing the signal-to-frequency ratio, resulting in a high-frequency converted coded signal. This overall scheme is equivalent to a two-layer encoding scheme: the first layer is the high-frequency conversion, and the second layer is the encoding to reduce the signal-to-frequency ratio. Alternatively, a similar second-layer encoding to reduce the signal-to-frequency ratio can be performed simultaneously with the high-frequency conversion. Correspondingly, the converted signal can be synchronized at a low frequency after decoding on the receiving end, and theoretically, it can be used directly.

[0054] It also includes a selection step, used to choose one from raw data, custom data packets, and high-frequency converted data for encoding and subsequent transmission. This selection step can be performed before or after encoding. That is, one can first select one from the raw data, custom data packets, and high-frequency converted data and encode the selected data; or each can be encoded first, and then the encoded signal to be transmitted can be selected for transmission. This is more suitable for situations where the encoding step of reducing the signal frequency ratio has been equivalently achieved during the generation or conversion of custom data packets and high-frequency converted data.

[0055] Based on the above-mentioned raw data, custom data packets, and high-frequency converted data encoding isolation transmission, on the one hand, the frequency ratio of the encoded data stream is relatively small, making it more suitable for built-in high-voltage isolation devices without magnetic cores and with limited bandwidth; on the other hand, the data stream rate after encoding is appropriately increased, usually not less than 600Mbps, which can be directly used for isolation transmission without the need for traditional OOK and other modulation isolation schemes, or a higher frequency carrier several times the target signal frequency. The circuit is simple and efficient, reducing the high-frequency performance requirements of the manufacturing process; furthermore, based on the understanding and conversion of USB data streams, USB events, and states, USB signals of various voltages and various event states can be isolated and transmitted at a unified data rate. The overall structure is simple, with fewer isolation devices and lower cost. Compared with physical signal isolation transmission, the isolation transmission based on data packet encoding and decoding has less signal jitter and less distortion.

[0056] Upon detecting a device connection, device disconnection, or bus event, a custom data packet is generated. If the current half-duplex high-speed differential transceiver is found to be transmitting, the transmit output of the half-duplex high-speed differential transceiver is first disabled. After waiting for time T2, the custom data packet is sent to the receiving die via the half-duplex high-speed differential transceiver. T2 is not less than the timeout end time agreed upon by the receiving module of the half-duplex high-speed differential transceiver, typically within a few microseconds, ensuring that the receiving side considers the previous data packet reception complete or terminated due to timeout. Then, the custom data packet representing the aforementioned bus event or connection status is sent via the half-duplex high-speed differential transceiver. After receiving the custom data packet, the receiving die synchronizes the connection status and bus event, and replies with an acknowledgment packet.

[0057] To further enhance ease of use, the chip also supports automatic uplink / downlink mode identification. After power-on or reset, both dies default to downlink mode. Each die uses its own USB port's pull-down switch to detect if a device is connected. When either die detects a device connection on its USB port, it sends a custom data packet containing device connection status or bus events to the other die. The two dies then determine the uplink / downlink mode; the die with the detected device remains in downlink mode, while the other die enters uplink mode. Furthermore, upon detecting a device connection on its own USB port, if it's not a low-speed USB connection, a high-speed USB identification is performed via the RESET protocol handshake module. After identification, the custom data packet is sent.

[0058] Example 2:

[0059] The difference between Example 2 and Example 1 lies in the high-voltage isolation coupling device. Example 2 uses a pair of high-voltage capacitors integrated into the outer die. These capacitors are typically implemented using two metal layers separated by a high-voltage-resistant thick spacer layer (IMD) or polyimide. One end of the capacitor, the lower plate, is connected to a half-duplex high-speed differential transceiver, while the other end, the upper plate, also serves as a PAD to connect to the opposite side. The two PADs of the two capacitors are connected to two PADs on the inner die via metal wires. To improve the isolation withstand voltage, the distance between the two plates should be increased, resulting in a smaller capacitance. To reduce cost, the plate area should be reduced, also leading to a smaller capacitance. These factors result in a very small capacitance in the capacitor isolation scheme, typically less than 1pF, leading to significant attenuation of low-frequency signals and poor transmission. Therefore, higher frequency conversion and encoding with reduced signal-to-frequency ratios are required.

[0060] In Embodiments 1 and 2, the high-voltage isolation coupling device is integrated into the outer die; technically, it can also be integrated into the inner die, or made into a separate device. When using the separate device approach, the separate device has at least two pairs of pads, which need to be connected to the corresponding pads on the inner and outer dies respectively via metal wires. A similar technical solution is the transformer approach, which adds a center tap to improve anti-interference capability.

[0061] like Figure 2 As shown, the data received by the half-duplex high-speed differential transceiver is first decoded by a signal-to-frequency ratio decoding module. The decoding result is sent to the delay control unit and the custom data packet processing module. The delay control unit delays the decoded data stream for a time T1 before transmitting it to the USB transceiver's transmit input. During this time, the custom data packet processing module identifies the specific header identifier of the custom data packet and directly or through a state machine and control module controls the delay control unit to shut down its output, preventing the custom data packet from being transmitted through the USB transceiver.

[0062] This embodiment does not include a clock tracking unit. An accurate clock can be obtained by using an internal crystal oscillator with an external crystal or an external input clock source.

[0063] Example 3:

[0064] Example 3, based on Example 1 or Example 2, further incorporates a high-voltage-resistant module within the outer die to enhance its high-voltage resistance. The high-voltage isolation coupling device utilizes a pair of high-voltage capacitors integrated into the inner die, such as... Figure 3As shown. In this embodiment, the output enable of the USB transceiver is directly controlled by the state machine and the control module. When a specific header identifier of a custom data packet is detected, the output enable of the USB transceiver is disabled. If it is a non-custom data packet, the USB transceiver is controlled to send it after a delay of T1 after decoding. This embodiment does not include a clock tracking unit; an accurate clock can be obtained using an internal crystal oscillator with an external crystal, or an external input clock source.

[0065] Specifically, such as Figure 3 As shown, the outer die also includes a first high-voltage NMOS, a second high-voltage NMOS, a gate drive module, and a boost pump; the drain of the first high-voltage NMOS is connected to the UD+ port of the outer USB, and the source of the first high-voltage NMOS is connected to the D+ terminal of the outer die USB transceiver; the drain of the second high-voltage NMOS is connected to the UD- port of the outer USB, and the source of the second high-voltage NMOS is connected to the D- terminal of the outer die USB transceiver.

[0066] The rated gate operating voltage of the first high-voltage NMOS and the second high-voltage NMOS is not less than 3V and not more than 5.5V. For example, when the rated gate operating voltage is 3.3V, it can be used for USB high-speed signal transmission. When the rated gate operating voltage is 5V, it can be used for USB low-speed, full-speed and high-speed signal transmission. Therefore, it can be selected according to the application scenario, with 5V being the preferred option.

[0067] A boost pump is used to generate a high voltage exceeding the external die power supply voltage, which is then supplied to the gate drive module to drive the gate of the high-voltage NMOS. For example, if the external die is rated to supply 3.3V, and the high-voltage NMOS in this embodiment is a type of NMOS with a rated gate operating voltage of 5V, the boost pump typically boosts the voltage to around 5V to ensure that the high-voltage NMOS can be fully turned on, thereby transmitting a 3.3V USB signal. The boost pump can use a capacitor charge pump or other specific boost techniques. To reduce power consumption, the state machine and control module control the switching of the boost pump or the voltage value output by the gate drive module according to the USB data rate mode. When the USB data rate mode is low speed, full speed, or other non-high-speed signals, the state machine and control module enable the boost pump or directly control the gate drive module to output a higher first gate voltage U1, where 4V < U1 <= 5.5V, and U1 is typically set to 5V, allowing the 3.3V USB signal to pass through the high-voltage NMOS. When the USB data rate mode is high-speed, the state machine and control module either shut down the boost pump or directly control the gate drive module to output the second gate voltage U2, where 2V < U2 < U1. Typically, U2 is the chip's power supply voltage. Since the USB signal voltage amplitude is low in high-speed mode, the boost pump can be shut down to save power, or the gate drive module can select a conventional power supply voltage (e.g., 3.3V) as the gate voltage of the high-voltage NMOS.

[0068] Both the first and second high-voltage NMOS devices are low-gate-voltage, high-drain-voltage devices. Their rated drain voltage Ud is significantly higher than their rated gate voltage Ug. For example, Ud ≥ 4 * Ug, meaning the rated drain voltage of both the first and second high-voltage NMOS devices is no less than four times their rated gate voltage. High-voltage NMOS devices are preferably small-area, low-parasitic, and low-on-resistance switching-type NMOS devices, with NLDMOS being the preferred type. If the rated gate voltage of the high-voltage NMOS is in the 5V or 3.3V range, the drain voltage can be selected from 20V, 28V, or even 48V, where "range" refers to a general range.

[0069] The outer die also includes a first high-voltage ESD protection and a second high-voltage ESD protection. The first high-voltage ESD protection is connected to the outer USB port UD+, and the second high-voltage ESD protection is connected to the outer USB port UD-. The second USB transceiver is specially optimized and does not need to contain ESD protection internally, thereby reducing the transceiver area, reducing circuit parasitics, improving high-frequency characteristics, and increasing signal bandwidth and quality. If the high-voltage NMOS has a sufficiently large area, it will have strong ESD resistance itself, and theoretically, the separate first and second high-voltage ESD protections can be eliminated, with the high-voltage NMOS itself acting as the ESD protection.

[0070] Considering USB specification requirements, impedance matching, and USB signal quality, this embodiment also specifically optimizes the design of the USB transceiver on the outer die. The equivalent internal resistance of the outer die USB transceiver is designed to be lower than the preferred value of the USB specification, and the sum of the internal resistance of the outer die USB transceiver and the on-state resistance of the high-voltage NMOS is equal to or as close as possible to the preferred value of the USB specification. For example, let the equivalent internal resistance of the inner die USB transceiver be R1, the equivalent internal resistance of the outer die USB transceiver be R2, the on-state resistance of the first high-voltage NMOS be R3, and the preferred value of the USB specification be R0. Then, 0.9*R0≤R2+R3≤1.1*R0 and 0.9*R0≤R1≤1.1*R0. For example, the equivalent internal resistance of the outer die USB transceiver should conventionally be designed at 45Ω. In this embodiment, assuming the on-state resistance of the high-voltage NMOS is 5Ω, the equivalent resistance of the outer die USB transceiver should be reduced to 40Ω during design to ensure USB signal impedance matching. The 10% error mentioned above is only a worst-case scenario; the actual error will be even smaller in actual design.

[0071] Example 4:

[0072] The difference between Example 4 and Examples 1 to 3 is that the high-voltage isolation coupling device in Example 4 uses an independent transformer for isolation, such as... Figure 4As shown. The outer die in this embodiment also has high voltage resistance, and the structure of the high voltage resistance module is the same as in Embodiment 3. In this embodiment, the receiving die is enabled by a state machine and a control module controlling the delay control unit output, which is the same as in Embodiment 2.

[0073] The high-speed USB isolation chip in Example 4 supports manual setting of USB uplink and downlink modes via external pins, specifying the uplink or downlink mode for the inner or outer side by using the high and low levels of the pins.

[0074] Example 5:

[0075] The difference between Example 5 and Example 3 is that the die in Example 5 also includes an automatic clock tracking function. For example... Figure 5 As shown, the clock module is connected to a USB transceiver, which is also used to output data of regular discarded bits and fill bits; the clock module may also include a clock tracking unit, which is used to calibrate its own clock according to periodic SOF packets in the data of discarded bits and fill bits.

Claims

1. A method for operating a high-speed USB isolation chip, characterized in that, Includes the following steps: Generation of the encoded signal for the communication signal: The USB transceiver receives the communication signal and outputs the raw data, which is without removing bit padding bits; the raw data is encoded in a way that reduces the signal frequency ratio, including: encoding using mBnB encoding method, where n>m, to obtain the encoded signal of the communication signal; Generation of the encoding signal of the custom data packet: Obtain at least one of the communication rate and the USB bus status, generate a custom data packet, the custom data packet containing at least one of the communication rate and the USB bus status, and encode the custom data packet in a way that reduces the signal frequency ratio to obtain the encoding signal of the custom data packet; Transmission of encoded signals: The encoded signals include encoded signals of communication signals or encoded signals of custom data packets. The encoded signals are transmitted via a half-duplex high-speed differential transceiver and transmitted to the bare die on the other side through a high-voltage isolation coupling device. Reception and processing of encoded signals: The receiving die receives the encoded signal, decodes it, and transmits the decoded data packet to the USB transceiver and the custom data packet processing module. This includes: first identifying the decoded data packet; if it is identified as a custom data packet, then parsing the custom data packet, synchronizing according to the parsing result, and the USB transceiver does not transmit; if it is not identified as a custom data packet, then the USB transceiver transmits it after a delay of T1 after decoding.

2. The method of claim 1, wherein, When the communication signal received by the USB transceiver is a non-high-speed signal, it outputs a non-high-speed data stream. This also includes first converting the non-high-speed data stream into a high-speed data stream with the same frequency as the high-speed USB data stream, and then encoding the high-frequency converted data by reducing the signal frequency ratio to obtain a high-frequency converted encoded signal.

3. The operating method of the high-speed USB isolation chip according to claim 2, characterized in that, It also includes a selection process, where a choice is made from raw data, custom data packets, and high-frequency converted data, and then encoded by reducing the signal frequency ratio to obtain an encoded signal for subsequent transmission.

4. The method of claim 1-3, wherein, The ratio of the highest frequency to the lowest frequency of the encoded signal does not exceed 4, and the number of consecutive 0 bits does not exceed 4, and the number of consecutive 1 bits does not exceed 4.

5. The method of claim 1-3, wherein, Upon detecting a device connection, device disconnection, or bus event, a custom data packet is generated. The state machine and control module disable the transmit output of the half-duplex high-speed differential transceiver. After waiting for time T2, the custom data packet is sent to the other side's bare die via the half-duplex high-speed differential transceiver. T2 is not less than the timeout end time agreed upon by the receiving module of the half-duplex high-speed differential transceiver. After receiving the custom data packet, the other side's bare die synchronizes the connection status and bus events and replies with an acknowledgment packet.

6. The method of claim 1-3, wherein the method further comprises: After the chip is powered on or reset, both dies default to downlink mode. Each die enables pull-down detection of its own USB port to check if a device is connected. When either die detects a device connection on its own USB port, that die sends a custom data packet containing the device connection status or bus event to the other die. Both dies then determine the uplink or downlink mode. The die that detects a device connection remains in downlink mode, while the other die enters uplink mode.

7. A high-speed USB isolation chip, characterized in that, It includes at least two dies, which are coupled through a high-voltage isolation coupling device, wherein the dies comprise: A USB transceiver is used to receive communication signals and output raw data, which is not padded with bits; it is also used to transmit data packets received from the other side's die. A state machine and control module are used to acquire at least one of the communication rate and USB bus status; and to synchronize with the counterpart die based on custom data packets. A custom data packet processing module is used to generate custom data packets, which include at least one of communication rate and USB bus status; Used to parse custom data packets transmitted by the other side's bare die, and transmit the parsing results to the state machine and control module; The encoding module is used to encode the original data or custom data packets in a way that reduces the signal-to-frequency ratio, including: encoding using mBnB encoding, where n > m, to obtain the encoded signal; A half-duplex high-speed differential transceiver is used to transmit encoded signals to the opposite die through high-voltage isolation coupling devices, and to receive encoded signals from the opposite die. The decoding module is used to decode the encoded signal transmitted from the bare die on the other side and send the decoded data packet to the delay control unit and the custom data packet processing module. If the custom data packet is identified, it is parsed and synchronized according to the parsing result, and the USB transceiver does not transmit. The delay control unit is used to receive the decoded data packets. When the data packet is a non-custom data packet, it will be sent out by the USB transceiver after a delay of T1 after decoding.

8. The high speed USB isolation chip of claim 7, wherein, The bare die also includes a high-frequency conversion module. When the communication signal received by the USB transceiver is a non-high-speed signal, a non-high-speed data stream is output. The high-frequency conversion module is used to convert the non-high-speed data stream into a high-speed data stream with the same frequency as the high-speed USB data stream.

9. The high speed USB isolation chip of claim 8, wherein, The bare die also includes a selection unit, the input of which is connected to at least two of the following: a USB transceiver, a custom data packet processing module, and a high-frequency conversion module; the output of which is connected to an encoding module; and the selection control terminal of which is connected to a state machine and a control module.

10. The high speed USB isolation chip of any of claims 7-9, wherein, The ratio of the highest frequency to the lowest frequency of the encoded signal does not exceed 4, and the number of consecutive 0 bits does not exceed 4, and the number of consecutive 1 bits does not exceed 4.

11. The high speed USB isolator chip according to any one of claims 7-9, wherein, The bare die also includes a RESET protocol handshake module, which connects the USB transceiver and the state machine and control module, and is used to organize bidirectional handshake communication in accordance with USB specification requirements to identify USB high-speed capabilities.

12. The high speed USB isolator chip of any of claims 7-9, wherein, The die also includes a clock module connected to a USB transceiver, which is also used to output data of the discarded bit stuffing bits. The clock module includes a clock tracking unit, which is used to calibrate its own clock based on periodic SOF packets in the data of the discarded bit stuffing bits.

13. The high-speed USB isolation chip according to any one of claims 7-9, characterized in that, The two dies include an inner die and an outer die. The outer die further includes a first high-voltage NMOS, a second high-voltage NMOS, a gate drive module, and a boost pump. The drain of the first high-voltage NMOS is connected to the UD+ port of the outer USB, and the source of the first high-voltage NMOS is connected to the D+ terminal of the outer die USB transceiver. The drain of the second high-voltage NMOS is connected to the UD- port of the outer USB, and the source of the second high-voltage NMOS is connected to the D- terminal of the outer die USB transceiver. The rated gate voltage of the first high-voltage NMOS and the second high-voltage NMOS is not less than 3V and not more than 5.5V, and the rated drain voltage is... The voltage is not less than 4 times its rated operating voltage at the gate terminal; the output terminal of the boost pump is connected to the gate drive module, which is used to provide the first high-voltage NMOS and the second high-voltage NMOS with a gate voltage higher than the external die power supply voltage. The boost pump is controlled by the state machine and the control module according to the communication rate; let the equivalent internal resistance of the inner die USB transceiver be R1, the equivalent internal resistance of the outer die USB transceiver be R2, let the on-resistance of the first high-voltage NMOS be R3, and let the preferred value of the USB specification be R0, then 0.9*R0≤R2+R3≤1.1*R0, 0.9*R0≤R1≤1.1*R0.

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