Communication method and electronic device
By combining a multiplexer and a switch controller, the problem of address and bus conflicts between the BIOS and the backplane in complex systems is solved, enabling accurate backplane identification and reliable communication, and improving the system's flexibility and compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2026-06-29
- Publication Date
- 2026-07-31
AI Technical Summary
In systems with complex architectures and numerous backplanes, existing technologies often encounter address and bus conflicts during communication between the BIOS and the backplane, resulting in the backplanes being unable to be accurately identified and communication being unreliable.
By using a multiplexer to achieve address multiplexing and a switch controller to perform bus arbitration, only one channel is active at any given time, thus avoiding address conflicts. Software-configured channel switching replaces fixed hardware connections, improving system flexibility and compatibility.
It enables accurate identification and reliable communication of the backplane in complex systems, avoids address and bus conflicts, and improves the flexibility and compatibility of the system.
Smart Images
Figure CN122489477A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to communication methods and electronic devices. Background Technology
[0002] When a computing device boots up, the Basic Input Output System (BIOS) needs to detect the modular backplane or switch backplane in the device. It reads the backplane's hardware information via the Inter-Integrated Circuit (I2C) bus or System Management Bus (SMBus), and then enumerates and scans downstream devices on the backplane via the Peripheral Component Interconnect Express (PCIe) bus to obtain the vendor and device identifiers, thereby completing resource allocation and system identification for downstream devices. In related technologies, the backplane is directly connected to the I2C or SMBus bus, and each backplane has an independent I2C or SMBus address. The BIOS directly reads the backplane's hardware information via the I2C or SMBus bus. However, this method is suitable for systems with simple architectures and a small number of backplanes. In systems with complex architectures and a large number of backplanes, this method can lead to address and bus conflicts, making it impossible to accurately identify the backplane and preventing the BIOS from reliably communicating with it. Summary of the Invention
[0003] This application provides a communication method and electronic device to at least solve the problem in the related art that, in cases of complex system structure and a large number of backplanes, address conflicts and bus conflicts occur on the backplanes, making it impossible for the backplanes to be accurately identified and for the BIOS to communicate reliably with the backplanes.
[0004] This application provides a communication method applied to a target input / output system, including: When the target input / output system starts up, determine the first multiplexer to be polled; Switch the output channel of the first multiplexer currently being polled to the first channel currently being polled; Acquire control of the switch controller connected to the first channel currently being polled, and switch the output channel of the second multiplexer connected to the switch controller to the second channel currently being polled. Initiate a read hardware information request to the target backplane connected to the currently polled second channel, obtain the hardware information of the target backplane, and return to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed; Return to the step of switching the output channel of the currently polled first multiplexer to the currently polled first channel until the polling of multiple first channels of the currently polled first multiplexer is completed; Return to the step of determining the first multiplexer to be polled until multiple first multiplexers have completed polling.
[0005] This application also provides a communication device applied to a target input / output system, comprising: The determination module is used to determine the first multiplexer to be polled when the target input / output system starts up; The switching module is used to switch the output channel of the currently polling first multiplexer to the currently polling first channel; The acquisition module is used to acquire the control of the switch controller connected to the first channel currently to be polled, and to switch the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled. The first return execution module is used to initiate a hardware information read request to the target backplane connected to the currently polled second channel, obtain the hardware information of the target backplane, and return to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed. The second return execution module is used to return to the execution of the step of switching the output channel of the currently polled first multiplexer to the currently polled first channel until the polling of multiple first channels of the currently polled first multiplexer is completed; The third return execution module is used to return to the execution steps of determining the first multiplexer to be polled until the polling of multiple first multiplexers is completed. This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement any of the above-described communication methods.
[0006] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described communication methods.
[0007] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described communication methods.
[0008] Through this application, when the target input / output system starts, the following steps are taken: First, the current multiplexer to be polled is determined; the output channel of the current multiplexer to be polled is switched to the current first channel to be polled; control of the switch controller connected to the current first channel to be polled is acquired, and the output channel of the second multiplexer connected to the switch controller is switched to the current second channel to be polled; a hardware information read request is initiated to the target backplane connected to the current second channel to be polled to obtain the hardware information of the target backplane; the process of switching the output channel of the second multiplexer connected to the switch controller to the current second channel to be polled is resumed until the polling of multiple second channels of the second multiplexer is completed; the process of switching the output channel of the current multiplexer to be polled is resumed until the polling of multiple first channels of the current multiplexer is completed; the process of determining the current multiplexer to be polled is resumed until the polling of multiple first multiplexers is completed. Address multiplexing is achieved through a first and second multiplexer, allowing devices on different channels to use the same I2C or SMBus address. Because the polling mechanism ensures that only one channel is active at any given time, devices on other channels are invisible to the CPU, thus avoiding backplane address conflicts. Bus arbitration is implemented through a switch controller, ensuring that only one master device can access the downstream bus of the switch controller at any given time, preventing backplane bus conflicts. Therefore, this solution addresses the technical problems in related technologies where reading backplane hardware information leads to address and bus conflicts in complex systems with many backplanes, resulting in inaccurate backplane identification and unreliable BIOS communication. It achieves the technical effect of avoiding backplane address and bus conflicts, accurately identifying the backplane, and enabling reliable BIOS communication with it. Attached Figure Description
[0009] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a schematic diagram illustrating how the BIOS reads hardware information from the backplane in related technologies. Figure 2 This application provides a schematic diagram of the structure of a communication system according to an embodiment of the present application. Figure 3 A flowchart illustrating a communication method provided in an embodiment of this application; Figure 4 A flowchart illustrating yet another communication method provided in an embodiment of this application; Figure 5 A schematic diagram of a structure for controlling the lighting of a downstream target device provided in an embodiment of this application; Figure 6 A flowchart illustrating a specific example of the communication method provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the communication device provided in the embodiments of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0012] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0013] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0014] The BIOS is the core firmware in a computing device, responsible for booting the computer and initializing hardware devices. Its stability and reliability have a significant impact on the operation of the entire system. The computing device can be a server. The BIOS is typically stored on the server's motherboard and can be powered by a battery, retaining data even when the server is powered off. The BIOS contains basic server settings and configuration information, such as boot order, hardware device detection and initialization, system time and date, etc. When the server boots, the BIOS runs first, detecting and initializing hardware devices, and then handing control over to the operating system. Specifically, when the BIOS on the server motherboard boots, it begins detecting the modular backplane or switch backplane in the server, reading the backplane hardware information via the I2C bus or SMBus bus, and then scanning the downstream devices on the backplane via PCIe enumeration to obtain the vendor identifier (ID) and device identifier of the downstream devices, thereby completing resource allocation and system identification of the downstream devices. The hardware information may include backplane identifier, backplane version, and backplane topology information. Modular backplanes include hard drive backplanes, which include Serial Attached Small Computer System Interface (SAS) / Serial Advanced Technology Attachment (SATA) hard drive backplanes, Non-Volatile Memory Express (NVMe) hard drive backplanes, etc. Switch backplanes are the core circuit boards inside servers or switches used to connect various port modules, line cards, and switching engines. They provide the physical channels and electrical connections for high-speed data transmission within the device, acting as the underlying communication backbone for data packets forwarding between different interfaces. Switch backplanes typically employ a multi-layer printed circuit board design, integrating high-speed signal traces, power distribution networks, and clock synchronization circuits. Their bandwidth directly determines the overall throughput and performance ceiling of the switch. In modular core switches or chassis-based servers, high-bandwidth switch backplanes support line-speed forwarding, ensuring unblocked data traffic processing even when all ports are operating at full load simultaneously. They also support hot-swapping, allowing for online replacement of faulty components without affecting overall system operation, making them a key component for ensuring high network availability and scalability.
[0015] SMBus is a two-wire serial bus based on the I2C protocol, widely used in computers and embedded systems for low-speed communication related to system management. It connects multiple devices via a shared clock line (SCL) and data line (SDA), supporting multi-master / slave architectures. It is commonly used to read hardware status information such as temperature, voltage, and fan speed, or to communicate with power management units, batteries, and memory modules (SPDs). While compatible with I2C in terms of physical layer and basic communication mechanisms, SMBus defines stricter electrical specifications, timeout mechanisms, and standardized command sets to improve system reliability and interoperability. It is widely used in PCs, servers, and industrial equipment for system monitoring and management tasks.
[0016] In related technologies, the I2C / SMBus bus serves as the primary physical channel for system management communication, playing a crucial role in information exchange between the BIOS and the backplane. The backplane is directly connected to the I2C or SMBus bus, and each backplane has an independent I2C address or SMBus address. The BIOS directly reads the hardware information of the backplane through the I2C or SMBus bus. Figure 1 This is a schematic diagram illustrating how the BIOS reads hardware information from the backplane in related technologies, such as... Figure 1 As shown, the back panel is described using the Switch back panel as an example. The server motherboard includes a CPU, which runs a BIOS. When the server starts up, the BIOS directly reads the hardware information of the Switch back panel via the I2C or SMBus bus. It's understood that the Switch back panel has multiple PCIe slots.
[0017] However, this method of BIOS-backplane communication is suitable for systems with simple architectures, a small number of backplanes, and where the I2C or SMBus addresses of each backplane do not conflict. In systems with complex architectures and a large number of backplanes, this method will face the following drawbacks: 1. Insufficient address resources: As the number of backplanes increases, the number of backplanes that need to be managed far exceeds the available address range, resulting in frequent address conflicts and backplanes that cannot be correctly identified.
[0018] 2. High risk of bus conflict: In the presence of multiple master controllers, the Central Processing Unit (CPU) and the Baseboard Management Controller (BMC) may access the same backplane simultaneously. Due to the lack of an effective bus arbitration mechanism, bus conflicts can lead to data corruption or communication failure, making it impossible for the BIOS to communicate reliably with the backplane.
[0019] A BMC (Browser Control Center) is a dedicated microcontroller embedded on a server motherboard, responsible for remotely monitoring and managing the server independently of the host system's operating status. It collects hardware information such as temperature, voltage, and fan speed in real time through sensors, supporting remote power on / off, operating system reinstallation, fault diagnosis, and system restart. It can operate even when the server is powered off. The BMC is typically integrated into the server's management network and communicates with external management terminals via the Intelligent Platform Management Interface (IPMI) protocol. Users can perform out-of-band management through a web browser or dedicated tools, greatly improving the maintainability and availability of servers in data center and cloud computing environments.
[0020] 3. Complex and inflexible hardware design: Direct wiring requires laying independent I2C or SMBus signal lines for each expansion slot. As the number of expansion slots increases, the wiring complexity increases dramatically. Moreover, once the hardware is finalized, it is difficult to adapt to different expansion configurations, resulting in poor compatibility.
[0021] In summary, the existing communication methods between the BIOS and the backplane in related technologies are insufficient to meet the requirements of high-density, multi-master controllers for bus communication in terms of avoiding address conflicts, avoiding bus conflicts, and design flexibility. A new communication method is urgently needed to solve these problems.
[0022] To address the aforementioned technical problems, embodiments of this application provide a communication method and an electronic device. The communication method is applied to a target input / output system and includes: when the target input / output system starts up, determining a first multiplexer currently to be polled; switching the output channel of the first multiplexer to be polled to a first channel currently to be polled; acquiring control of a switch controller connected to the first channel currently to be polled, and switching the output channel of a second multiplexer connected to the switch controller to a second channel currently to be polled; initiating a hardware information read request to a target backplane connected to the second channel currently to be polled, obtaining the hardware information of the target backplane, and returning to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled until multiple second channels of the second multiplexer have completed polling; returning to execute the step of switching the output channel of the first multiplexer to be polled to the first channel currently to be polled until multiple first channels of the first multiplexer have completed polling; and returning to execute the step of determining the first multiplexer currently to be polled until multiple first multiplexers have completed polling. The above-described solution achieves address multiplexing through a first and second multiplexer, allowing devices on different channels to use the same I2C or SMBus address. Because the polling mechanism ensures that only one channel is active at any given time, devices on other channels are invisible to the CPU, preventing backplane address conflicts. Furthermore, a switch controller enables bus arbitration, ensuring that only one master device can access the downstream bus of the switch controller at any given time, thus avoiding backplane bus conflicts. Therefore, this solution addresses the technical problems in related technologies where reading backplane hardware information leads to address and bus conflicts in complex systems with numerous backplanes, resulting in inaccurate backplane identification and unreliable BIOS communication. It achieves the technical effects of avoiding backplane address and bus conflicts, accurately identifying the backplane, and enabling reliable BIOS communication. Simultaneously, the software-configurable channel switching method replaces fixed hardware connections, improving system flexibility, compatibility, and scalability.
[0023] The specific application environment architecture or specific hardware architecture on which the execution of the communication method depends is described here.
[0024] The communication method and electronic device provided in this application are suitable for communication between a BIOS and a target backplane, where the target backplane includes a modular backplane and a switch backplane. Figure 2The diagram shown illustrates the structure of the communication system upon which this application is based. This communication system includes: a server motherboard, multiple first multiplexers, multiple switch controllers, multiple second multiplexers, and multiple target backplanes. The server motherboard includes a CPU, which runs a BIOS. When the server motherboard boots up, the BIOS determines the first multiplexer currently to be polled; switches the output channel of the first multiplexer to be polled to the first channel currently to be polled; acquires control of the switch controller connected to the first channel currently to be polled, and switches the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled; initiates a hardware information read request to the target backplane connected to the second channel currently to be polled, obtains the hardware information of the target backplane, and returns to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled until multiple second channels of the second multiplexer have completed polling; returns to execute the step of switching the output channel of the first multiplexer to be polled to the first channel currently to be polled until multiple first channels of the first multiplexer have completed polling; returns to execute the step of determining the first multiplexer currently to be polled until multiple first multiplexers have completed polling.
[0025] Embodiments of this application provide a communication method applied to a target input / output system, namely a BIOS. Figure 3 A flowchart illustrating the communication method provided in the embodiments of this application is shown below. Figure 3 As shown, the communication method includes the following steps: Step S301: When the target input / output system starts, determine the first multiplexer to be polled.
[0026] The system includes multiple first multiplexers. Based on the polling order of the first multiplexers, the current first multiplexer to be polled is determined. The first multiplexer can be an I2C multiplexer PCA9548. The PCA9548 is equivalent to a multiplexer with multiple output channels.
[0027] Step S302: Switch the output channel of the first multiplexer currently to be polled to the first channel currently to be polled.
[0028] After determining the first multiplexer to be polled, each first multiplexer includes multiple first channels. According to the polling order of the first channels, the first channel to be polled is determined. The first multiplexer to be polled is accessed through the SMBus bus, and the output channel of the first multiplexer to be polled is switched to the first channel to be polled.
[0029] For example, the I2C address of the first multiplexer currently being polled is 0xE0, and the first channel currently being polled of the first multiplexer is channel 2. Writing the value 0x04 to the channel register of the first multiplexer currently being polled switches the output channel of the first multiplexer currently being polled to channel 2, thereby routing the SMBus or I2C signal to the switch controller connected to that channel.
[0030] Understandably, each first channel is connected to a switch controller, and each first channel corresponds to one switch controller. The switch controller can be an I2C switch controller, such as the PCA9641. The PCA9641 is a more advanced I2C bus switch that allows multiple master controllers to share access to a set of slave devices. Because there are multiple master controllers, an operation is required to gain control of the switch controller. Specifically, a 0x87 message is sent to the PCA9641's control register to request control. Only when the PCA9641 returns the same value does it indicate that the BIOS has successfully gained control of the downstream bus of the switch controller.
[0031] Step S303: Obtain control of the switch controller connected to the first channel currently to be polled, and switch the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled.
[0032] In this embodiment, acquiring control of the switch controller currently connected to the first channel to be polled means that the processor (CPU) running the BIOS successfully acquires control of the switch controller currently connected to the first channel to be polled. The second multiplexer can be an I2C multiplexer PCA9548. The second multiplexer connected to the switch controller includes multiple second channels. According to the polling order of the second channels, the currently polled second channel is determined. The second multiplexer connected to the switch controller is accessed via the SMBus bus, and the output channel of the second multiplexer connected to the switch controller is switched to the currently polled second channel. In this embodiment, each switch controller is connected to one second multiplexer.
[0033] For example, if the address of the second multiplexer connected to the switch controller connected to the first channel to be polled is 0xE2, and the second channel to be polled by the second multiplexer is channel 1, then 0x02 is written into the channel register of the second multiplexer connected to the switch controller connected to the first channel to be polled, and its output channel is switched to channel 1, which is connected to a target backplane.
[0034] Step S304: Initiate a read hardware information request to the target backplane connected to the currently polled second channel, obtain the hardware information of the target backplane, and return to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed.
[0035] The hardware information read request can be a System Management Bus Read Block (SMBus Read Block) operation. The hardware information storage device on the target backplane receives the hardware information read request and returns the target backplane's hardware information to the BIOS. At this point, the polling of the currently polled second channel is completed. Based on the polling order of the second channel, the currently polled second channel is updated. The process then returns to the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel, and continues with the steps following this step until the polling of multiple second channels of the second multiplexer is completed, i.e., until the hardware information of the target backplane connected to the multiple second channels of the second multiplexer connected to the current switch controller is acquired.
[0036] Step S305: Return to the step of switching the output channel of the currently polled first multiplexer to the currently polled first channel until the polling of multiple first channels of the currently polled first multiplexer is completed.
[0037] After the polling of multiple second channels of the second multiplexer connected to the switch controller connected to the currently polled first channel is completed, the polling order of the first channel is updated, and the process returns to execute the step of switching the output channel of the currently polled first multiplexer to the currently polled first channel, as well as the steps after that, until the polling of multiple first channels of the currently polled first multiplexer is completed.
[0038] Step S306: Return to the step of determining the first multiplexer to be polled until the polling of multiple first multiplexers is completed.
[0039] After the multiple first channels of the currently polling first multiplexer have been polled, the current polling first multiplexer is updated according to the polling order of the first multiplexer. The process then returns to the step of determining the current polling first multiplexer and the steps after that step until the polling of multiple first multiplexers is completed, and the hardware information of all target backplanes is obtained.
[0040] The communication method provided in this application achieves address multiplexing through a first multiplexer and a second multiplexer. Devices on different channels can use the same I2C address or SMBus address. Because the polling mechanism ensures that only one channel is active at any given time, devices on other channels are invisible to the central processing unit, thus avoiding address conflicts on the backplane. Bus arbitration is implemented through a switch controller, ensuring that only one master device can access the downstream bus of the switch controller at any given time, avoiding bus conflicts on the backplane. Therefore, this method solves the technical problem in related technologies where reading backplane hardware information leads to address and bus conflicts in complex systems with many backplanes, resulting in inaccurate backplane identification and unreliable BIOS communication with the backplane. It achieves the technical effect of avoiding backplane address and bus conflicts, accurately identifying the backplane, and enabling reliable BIOS communication with the backplane. Furthermore, the software-configured channel switching method replaces fixed hardware connections, improving the system's flexibility, compatibility, and scalability.
[0041] An embodiment of this application provides a communication method applied to the aforementioned tag input / output system. Figure 4 A flowchart illustrating the communication method provided in the embodiments of this application is shown below. Figure 4 As shown, the communication method includes the following steps: Step S401: When the target input / output system starts, determine the first multiplexer currently to be polled. See details below. Figure 3 Step S301 of the illustrated embodiment will not be described again here.
[0042] Step S402: Switch the output channel of the currently polling first multiplexer to the currently polling first channel.
[0043] Specifically, step S402 includes: Step S4021: Write a first value into the channel register of the current polling first multiplexer to switch the output channel of the current polling first multiplexer to the current polling first channel.
[0044] Step S403: Obtain control of the switch controller connected to the first channel currently to be polled, and switch the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled.
[0045] Specifically, step S403 includes: Step S4031: Write the target command word into the control register of the switch controller to request the processor running the target input / output system to become the master controller of the switch controller.
[0046] The target command word can be 0x87. For example, if the I2C address of the switch controller is 0x84, writing the command word 0x87 into the control register of the switch controller requests the CPU running the BIOS to become the master controller of the downstream bus of the switch controller and establish a connection.
[0047] Step S4032: Read the value in the control register of the switch controller. If the value in the control register of the switch controller is the target command word, then it is determined that the processor running the target input / output system has obtained control of the switch controller.
[0048] Step S404: Initiate a hardware information read request to the target backplane connected to the currently polled second channel, obtain the hardware information of the target backplane, and return to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed. For details, please refer to [link to details]. Figure 3 Step S304 of the illustrated embodiment will not be described again here.
[0049] Step S405: Return to the step of switching the output channel of the currently polling first multiplexer to the currently polling first channel until the polling of multiple first channels of the currently polling first multiplexer is completed. For details, please refer to [link to relevant documentation]. Figure 3 Step S305 of the illustrated embodiment will not be described again here.
[0050] Step S406: Return to the step of determining the first multiplexer to be polled until polling of multiple first multiplexers is completed. See details in [link to relevant documentation]. Figure 3 Step S306 of the illustrated embodiment will not be described again here.
[0051] The communication method provided in this application embodiment enables channel switching through software configuration, allowing flexible selection of the physical area to be accessed without changing the hardware connections, thus laying the foundation for subsequent multi-level addressing and address reuse.
[0052] Bus arbitration is achieved through a "request-verification" mechanism, ensuring mutually exclusive access to downstream buses in a multi-master environment, fundamentally avoiding bus conflicts, and guaranteeing the reliability and security of communication.
[0053] In some optional implementations, the above communication method further includes: Step a1: If the value of the control register of the switch controller is not the target command word, then return to the step of writing the target command word to the control register of the switch controller until the value of the control register of the switch controller is the target command word.
[0054] The communication method provided in this application embodiment, through an automatic retry mechanism, ensures that it will not give up when the bus is occupied by other masters, but will continue to try until it successfully obtains control, thereby improving the reliability and success rate of communication and avoiding communication failures caused by temporary occupation.
[0055] In some optional implementations, the above communication method further includes: Step b1: If the value of the control register of the switch controller is not the target command word, then return to the step of writing the target command word to the control register of the switch controller.
[0056] In step b2, if the number of times the step of writing the target command word to the control register of the switch controller is returned exceeds a preset threshold, and the value of the control register of the switch controller is still not the target command word, an alarm is issued.
[0057] The preset threshold for the number of attempts can be 4 to ensure reliable access control in a multi-master controller environment.
[0058] The communication method provided in this application, by setting an upper limit on the number of retries and an alarm mechanism, ensures communication reliability while avoiding unlimited waiting and system hangs caused by long-term bus occupation or switch controller failure, thus achieving a balance between reliability and availability.
[0059] In some optional implementations, the above communication method further includes: Step c1: Parse the first byte of the obtained target backplane hardware information into the target backplane's identity identifier.
[0060] Specifically, the first byte of the obtained target backplane hardware information is parsed as SWA_INDEX, which is the identity identifier of the target backplane.
[0061] Step c2: Save the target backplane's identity to the target input / output system's platform configuration database for use during the target input / output system's startup.
[0062] Specifically, by calling the PcdSet8S function, the Platform Configuration Database (PCD) item named PcdSWA_INDEX is set to the value of SWA_INDEX, thereby saving this value to the PCD database for later system use. In other words, PcdSet8S(PcdSWA_INDEX, SWA_INDEX) saves the target backplane's identity via the PCD mechanism for later system use.
[0063] In some optional implementations, before switching the output channel of the currently polled first multiplexer to the currently polled first channel, the above communication method further includes: Step d1: Read and save the current value of the channel register of the first multiplexer to be polled.
[0064] In some optional implementations, the above communication method further includes: Step e1: After the current polling of the first multiplexer is completed, the channel register of the current polling of the first multiplexer is restored based on the current value of the channel register of the current polling of the first multiplexer.
[0065] The communication method provided in this application embodiment ensures that the system bus environment returns to its initial state after the polling operation is completed by saving and restoring the original channel state of the first multiplexer, thus avoiding interference with other modules or subsequent operations and achieving lossless switching and friendly coexistence.
[0066] In some optional implementations, the above communication method further includes: Step f1: After the first channel to be polled is completed, write the second value into the control register of the switch controller to release control over the switch controller.
[0067] The second value can be 0x00. After the first channel to be polled is polled, the second value is written into the control register of the switch controller connected to the first channel to be polled, so as to release the control right of the switch controller connected to the first channel to be polled, and ensure that other components of the system (such as BMC) can access the downstream bus of the switch controller normally.
[0068] In some optional implementations, the above communication method further includes: Step g1: After enumerating the downstream devices of the target backplane, obtain the status information of the downstream target devices for the hard disk backplane. The target backplane includes the hard disk backplane.
[0069] After establishing an SMBus or I2C communication channel between the BIOS and the target backplane, this communication mechanism can be further used to implement visual indication of the backplane status. For example, LED status control (i.e., "lighting up") for PCIe slots or NVMe devices. The BIOS-target backplane communication method of this application provides a reliable data path and control basis for the lighting function.
[0070] The downstream target device can be a downstream NVMe hard drive.
[0071] The BIOS or operating system obtains the status information of the downstream NVMe hard drives on the hard drive backplane. The status information includes online, faulty, active, etc.
[0072] Step g2: Based on the status information of the downstream target device, set the light-up field in the slot controller corresponding to the downstream target device.
[0073] The slot controller is the PCIe Slot Control register. Based on the status information of the downstream target device, and following the International Blink Pattern Interpretation (IBPI) specification, the indicator light field in the corresponding slot controller of the downstream target device is set.
[0074] Step g3: Obtain the location information of the downstream target device.
[0075] Step g4: Generate a lighting command based on the lighting field in the slot controller corresponding to the downstream target device and the location information of the downstream target device.
[0076] Step g5: Send the LED lighting command to the controller of the hard disk backplane corresponding to the downstream target device so that the controller executes the LED lighting command.
[0077] The controller is a Complex Programmable Logic Device (CPLD). The BIOS sends an LED activation command to the I2C address 0x20 register of the controller of the hard drive backplane corresponding to the downstream target device through the Virtual PCIe Port (VPP) mechanism.
[0078] The communication method provided in this application extends the backplane hardware information reading capability to light control by reusing the established SMBus / I2C communication channel, realizing closed-loop management from "device identification" to "status visualization", and providing operation and maintenance personnel with intuitive and reliable hard disk status indication.
[0079] In some alternative implementations, step g2 above includes: Step g21: Based on the status information of the downstream target device, determine the indicator light color and flashing mode corresponding to the status information.
[0080] Step g22: Based on the indicator light color and flashing mode corresponding to the status information, set the lighting field in the slot controller corresponding to the downstream target device.
[0081] In some optional implementations, the communication method further includes, before sending the lighting command to the controller of the hard disk backplane corresponding to the downstream target device: Step h1: Write the location information of the downstream target device into the controller of the hard disk backplane corresponding to the downstream target device.
[0082] Specifically, the BIOS or BMC writes CPU / VPP strap information to the I2C address 0x26 register of the controller of the hard drive backplane corresponding to the downstream target device via the SMBus bus. This information is used to identify the location of the downstream target device. The CPU / VPP strap information is the slot selection / binding information provided by the CPU through the VPP mechanism.
[0083] Step h2: The virtualization mode driver status information is passed to the manager so that the manager writes the virtualization mode driver status information to the controller of the hard disk backplane corresponding to the downstream target device.
[0084] The BIOS transmits the Virtualization Mode Driver (VMD) status information to the BIOS Manager (BMC). The BMC then writes the VMD status information to the register at I2C address 0x11 of the controller of the hard drive backplane corresponding to the downstream target device via the I2C bus.
[0085] The light-on command includes virtualization mode driver status information; the controller of the hard disk backplane corresponding to the downstream target device verifies the light-on command based on the location information of the downstream target device and the virtualization mode driver status information written in it, and executes the light-on command if the light-on command verification is successful.
[0086] Specifically, the controller of the hard disk backplane corresponding to the downstream target device compares the location information of the downstream target device written with the location information of the downstream target device in the light-up command. If the comparison passes, it compares the virtualization mode driver status information written with the virtualization mode driver status information in the light-up command. If the comparison passes, it determines that the light-up command has been verified and executes the light-up command.
[0087] The controller of the hard drive backplane corresponding to the downstream target device parses the LED activation command. This command includes the location information of the downstream target device, namely the address and channel information of the I2C multiplexer corresponding to the downstream target device. The command also includes VPP address / port information. In this embodiment, due to hardware design constraints, the VPP address is uniformly configured as 0x40. Based on the parsing result, the CPLD executes the corresponding GPIO operation to control the on / off state of the corresponding LED, thus achieving status indication.
[0088] Figure 5This is a schematic diagram of the structure for controlling the lighting of downstream target devices provided in an embodiment of this application, such as... Figure 5 As shown, the BIOS in the processor sends a power-on instruction (VPP) to the I2C register of the hard drive backplane controller corresponding to the downstream target device via a multiplexer and the connection channel SMB_CONN0_VPP_I2C between the BIOS and the controller. This VPP instruction has bit 0 representing a fault bit and bit 1 representing a location bit. The processor and manager are connected to the switch controller via SMBus. The processor / manager acquires control of the switch controller and writes CPU / VPP strap information to the I2C register of the hard drive backplane controller corresponding to the downstream target device via the multiplexer and the connection channel SMB_BMC_CONN_I2C between the switch controller and the controller. The processor can be processor 0 or processor 1. The BMC writes VMD status information to the I2C register at address 0x11 of the controller of the hard disk backplane corresponding to the downstream target device through the connection channel SMB_BMC_CPLD_I2C between the BMC and the controller of the hard disk backplane corresponding to the downstream target device. The controller of the hard disk backplane corresponding to the downstream target device compares the written location information of the downstream target device with the location information of the downstream target device in the LED lighting command, and compares the written virtualization mode driver status information with the virtualization mode driver status information in the LED lighting command. If the comparison passes, the LED lighting command is verified and executed.
[0089] The communication method provided in this application embodiment ensures the legality and accuracy of the lighting command through a dual verification mechanism, preventing misoperation caused by erroneous or malicious commands, and improving the security and reliability of the system.
[0090] In some optional implementations, the above communication method further includes: Step i1: If the hardware information of the target backplane is not successfully obtained, the step of initiating a read hardware information request to the target backplane currently polled for the second channel connection is executed again.
[0091] Step i2: If the number of times the step of re-executing the step of initiating a read hardware information request to the target backplane connected to the currently polled second channel exceeds the preset number threshold, and the hardware information of the target backplane is still not successfully obtained, then an error log is recorded and the current target backplane is skipped. The process returns to the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed.
[0092] After polling all target backplanes, an exception report is generated based on the error log. The exception report includes the location information of the target backplanes for which hardware information was not successfully obtained and the reason for the failure.
[0093] The communication method provided in this application, through a mechanism of limited retries, skipping faulty backplanes, and generating exception reports, ensures the integrity of polling while avoiding the blocking of the entire polling process due to individual backplane failures, thereby improving the system's fault tolerance and maintainability.
[0094] To describe the communication method in detail, a specific example is provided, which illustrates the process of reading hardware information from a backplane. Figure 6 A flowchart illustrating a specific example of the communication method provided in the embodiments of this application, such as... Figure 6 As shown, this specific example includes the following steps: The current value of the channel register of the first PCA9548 multiplexer with I2C address 0xE0 is read and saved for later recovery. Then, the value 0x04 is written to the channel register of the first PCA9548. This operation switches the output channel of the first PCA9548 to channel 2, thereby routing the SMBus signal to the I2C switch controller PCA9641 connected to that channel.
[0095] Command word 0x87 is written to the control register of PCA9641 (connected to channel 2) with I2C address 0x84, requesting the CPU to become the master controller of the downstream bus and establish a connection. The register value is then read back to verify whether control was successfully acquired. If it fails, it is retried up to four times to ensure reliable access control in a multi-master environment.
[0096] After successfully acquiring control of the PCA9641, the process enters the `obtainSWBoardidFromPCA954X()` sub-process. This sub-process includes writing 0x02 to the channel register of the second PCA9548 (connected to the PCA9641 with I2C address 0xE2), switching its output channel to channel 1. This channel is connected to the Switch expansion board.
[0097] Initiate an SMBus Read Block operation to the Switch expansion board and read the data it returns. Parse the first byte read as SWA_INDEX and save it via PCD mechanism using PcdSet8S(PcdSWA_INDEX, SWA_INDEX) for later use by the system.
[0098] After the information reading is complete, 0x00 is written to the control register of the PCA9641 to release its control over the downstream bus. Then, the channel register of the first PCA9548 that performed the initial operation is restored to its previously saved original value to ensure that other system components (such as the BMC) can access the SMBus bus normally. The entire process is then complete.
[0099] The communication method provided in this application, by combining I2C multiplexing with a bus arbitration mechanism, enables reliable and secure reading of hardware information from pluggable PCIe expansion boards on complex server platforms. It can automatically detect and read the unique identifiers of PCIe switch expansion boards of different models or locations, allowing the system firmware to accurately identify the currently connected hardware topology early in the boot process. This provides crucial information for subsequent PCIe resource allocation, device initialization, and System Management BIOS (SMBIOS) information filling, supporting flexible hardware configuration and hot-swapping management. By introducing the PCA9641 bus switch and strictly enforcing the "request-arbitration-release" control process, it effectively avoids bus conflicts and data corruption that may occur when multiple master controllers such as the CPU and BMC simultaneously access the same group of I2C slave devices, ensuring the safe and reliable parallel operation of out-of-band management and in-band systems. Through the cascading operation of two PCA9548 multiplexers, utilizing a multi-level addressing method of "bus → region → device," it overcomes the limitations of the I2C address space, enabling flexible management of a large number of slave devices. The collected backplane hardware information can be reported to the BMC for asset tracking, fault location, and remote monitoring. Maintenance personnel can clearly understand the actual installation status and card type of each PCIe slot through the BMC, greatly improving server manageability and maintenance efficiency. Furthermore, the communication channel established in this application can also be used for backplane status indication (such as LED lights), enabling visualization of device operating status and further improving on-site maintenance efficiency. Accessing devices located on different physical paths via software configuration rather than fixed wiring allows the same motherboard design to be compatible with various expansion board combinations, reducing hardware design complexity and improving platform versatility and scalability.
[0100] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0101] Embodiments of this application also provide a communication device, such as... Figure 7 As shown, the communication device includes: The determination module 701 is used to determine the first multiplexer to be polled when the target input / output system starts.
[0102] The switching module 702 is used to switch the output channel of the currently polling first multiplexer to the currently polling first channel.
[0103] The acquisition module 703 is used to acquire the control of the switch controller connected to the first channel currently to be polled, and to switch the output channel of the second multiplexer connected to the switch controller to the second channel currently to be polled.
[0104] The first return execution module 704 is used to initiate a read hardware information request to the target backplane connected to the currently polled second channel, obtain the hardware information of the target backplane, and return to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed.
[0105] The second return execution module 705 is used to return to the execution of the step of switching the output channel of the currently polled first multiplexer to the currently polled first channel until the polling of multiple first channels of the currently polled first multiplexer is completed.
[0106] The third return execution module 706 is used to return to the execution steps of determining the first multiplexer to be polled until the polling of multiple first multiplexers is completed.
[0107] In an optional implementation, the switching module 702 includes: The switching unit is used to write a first value into the channel register of the current polling first multiplexer, so as to switch the output channel of the current polling first multiplexer to the current polling first channel.
[0108] In an optional implementation, the acquisition module 703 includes: The first write unit is used to write the target command word into the control register of the switch controller to request the processor running the target input / output system to become the master controller of the switch controller.
[0109] The first reading unit is used to read the value in the control register of the switch controller. If the value in the control register of the switch controller is the target command word, it is determined that the processor running the target input / output system has obtained control of the switch controller.
[0110] In an optional implementation, the communication device further includes: The first return execution unit is used to return to the step of writing the target command word to the control register of the switch controller if the value of the control register of the switch controller is not the target command word, until the value of the control register of the switch controller is the target command word.
[0111] In an optional implementation, the communication device further includes: The second return execution unit is used to return to the step of writing the target command word to the control register of the switch controller if the value of the control register of the switch controller is not the target command word.
[0112] An alarm unit is used to issue an alarm if the number of times the step of writing the target command word to the control register of the switch controller is returned exceeds a preset threshold, and the value of the control register of the switch controller is still not the target command word.
[0113] In an optional implementation, the communication device further includes: The parsing unit is used to parse the first byte of the acquired target backplane hardware information into the target backplane's identity identifier.
[0114] The first storage unit is used to save the identity of the target backplane to the platform configuration database of the target input / output system for use during the startup of the target input / output system.
[0115] In an optional implementation, the communication device further includes: The second reading unit is used to read and save the current value of the channel register of the first multiplexer currently being polled.
[0116] In an optional implementation, the communication device further includes: The recovery unit is used to recover the channel register of the current multiplexer to be polled after the polling of the current multiplexer is completed, based on the current value of the channel register of the current multiplexer to be polled.
[0117] In an optional implementation, the communication device further includes: The second write unit is used to write a second value into the control register of the switch controller after the current polling of the first channel is completed, so as to release control of the switch controller.
[0118] In an optional implementation, the communication device further includes: The first acquisition unit is used to acquire the status information of the downstream target devices for the hard disk backplane after completing the enumeration of the downstream devices of the target backplane. The target backplane includes the hard disk backplane.
[0119] The setting unit is used to set the lamp field in the slot controller corresponding to the downstream target device based on the status information of the downstream target device.
[0120] The second acquisition unit is used to acquire the location information of the downstream target device.
[0121] The generation unit is used to generate a lighting command based on the lighting field in the slot controller corresponding to the downstream target device and the position information of the downstream target device.
[0122] The sending unit is used to send the lighting command to the controller of the hard disk backplane corresponding to the downstream target device, so that the controller executes the lighting command.
[0123] In an optional implementation, the setting unit includes: The determination unit is used to determine the indicator light color and flashing mode corresponding to the status information based on the status information of the downstream target device.
[0124] The configuration subunit is used to set the indicator light field in the slot controller of the downstream target device based on the indicator light color and flashing mode corresponding to the status information.
[0125] In an optional implementation, the communication device further includes: The third writing unit is used to write the location information of the downstream target device into the controller of the hard disk backplane corresponding to the downstream target device.
[0126] The transmission unit is used to transmit virtualization mode driver status information to the manager, so that the manager can write the virtualization mode driver status information to the controller of the hard disk backplane corresponding to the downstream target device.
[0127] For a description of the features in the embodiments corresponding to the communication device, please refer to the relevant descriptions in the embodiments corresponding to the communication method, which will not be repeated here.
[0128] Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, it includes a processor 801 and a memory 802, in which a computer program is stored. The processor 801 is configured to run the computer program to perform the steps in any of the above-described communication method embodiments.
[0129] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described communication method embodiments when it is run.
[0130] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.
[0131] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described communication method embodiments.
[0132] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described communication method embodiments.
[0133] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.
[0134] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0135] The communication method and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A communication method characterized by comprising: Applied to target input / output systems, including: When the target input / output system starts, the first multiplexer to be polled is determined; Switch the output channel of the currently polling first multiplexer to the currently polling first channel; Acquire control of the switch controller connected to the currently polling first channel, and switch the output channel of the second multiplexer connected to the switch controller to the currently polling second channel; Initiate a read hardware information request to the target backplane connected to the currently polled second channel, obtain the hardware information of the target backplane, and return to execute the step of switching the output channel of the second multiplexer connected to the switch controller to the currently polled second channel until the polling of multiple second channels of the second multiplexer is completed; Return to the step of switching the output channel of the currently polled first multiplexer to the currently polled first channel until the polling of multiple first channels of the currently polled first multiplexer is completed; Return to the step of determining the first multiplexer to be polled until multiple first multiplexers have completed polling.
2. The method of claim 1, wherein, The step of switching the output channel of the currently polling first multiplexer to the currently polling first channel includes: Write a first value into the channel register of the currently polled first multiplexer to switch the output channel of the currently polled first multiplexer to the currently polled first channel.
3. The method of claim 1, wherein, The step of obtaining control of the switch controller currently connected to the first channel to be polled includes: Write a target command word into the control register of the switch controller to request the processor running the target input / output system to become the master controller of the switch controller; The value in the control register of the switch controller is read. If the value in the control register of the switch controller is the target command word, it is determined that the processor running the target input / output system has acquired control of the switch controller.
4. The method of claim 3, wherein, The method further includes: If the value of the control register of the switch controller is not the target command word, then return to the step of writing the target command word to the control register of the switch controller until the value of the control register of the switch controller is the target command word.
5. The method of claim 3, wherein, The method further includes: If the value of the control register of the switch controller is not the target command word, then return to the step of writing the target command word to the control register of the switch controller; If the number of times the step of writing the target command word to the control register of the switch controller is returned exceeds a preset threshold, and the value of the control register of the switch controller is still not the target command word, an alarm is issued.
6. The method of claim 1, wherein, The method further includes: The first byte of the obtained hardware information of the target backplane is parsed as the identity identifier of the target backplane; The identity of the target backplane is saved to the platform configuration database of the target input / output system for use during the startup of the target input / output system.
7. The method of claim 1, wherein, Before switching the output channel of the currently polling first multiplexer to the currently polling first channel, the method further includes: Read and save the current value of the channel register of the first multiplexer currently being polled.
8. The method according to claim 7, characterized in that, The method further includes: After the polling of the first multiplexer to be polled is completed, the channel register of the first multiplexer to be polled is restored based on the current value of the channel register of the saved first multiplexer to be polled.
9. The method according to claim 1, characterized in that, The method further includes: After the first channel to be polled is polled, a second value is written into the control register of the switch controller to release control over the switch controller.
10. The method according to claim 1, characterized in that, The method further includes: After enumerating the downstream devices of the target backplane, for the downstream target devices of the hard disk backplane, obtain the status information of the downstream target devices, wherein the target backplane includes the hard disk backplane. Based on the status information of the downstream target device, set the light-up field in the slot controller corresponding to the downstream target device; Obtain the location information of the downstream target device; Based on the lighting field in the slot controller corresponding to the downstream target device and the location information of the downstream target device, a lighting command is generated; The light-up command is sent to the controller of the hard disk backplane corresponding to the downstream target device, so that the controller executes the light-up command.
11. The method according to claim 10, characterized in that, The step of setting the LED field in the slot controller corresponding to the downstream target device based on the status information of the downstream target device includes: Based on the status information of the downstream target device, determine the indicator light color and flashing mode corresponding to the status information; Based on the indicator light color and flashing mode corresponding to the status information, the lighting field in the slot controller corresponding to the downstream target device is set.
12. The method according to claim 10, characterized in that, Before sending the light-up command to the controller of the hard disk backplane corresponding to the downstream target device, the method further includes: Write the location information of the downstream target device into the controller of the hard disk backplane corresponding to the downstream target device; The virtualization mode driver status information is passed to the manager, so that the manager writes the virtualization mode driver status information to the controller of the hard disk backplane corresponding to the downstream target device.
13. The method according to claim 12, characterized in that, The lighting command includes virtualization mode driver status information; the controller of the hard disk backplane corresponding to the downstream target device verifies the lighting command based on the location information of the downstream target device and the virtualization mode driver status information, and executes the lighting command if the lighting command verification is successful.
14. The method according to claim 13, characterized in that, The controller of the hard disk backplane corresponding to the downstream target device compares the written location information of the downstream target device with the location information of the downstream target device in the lighting command. If the comparison is successful, it compares the written virtualization mode driver status information with the virtualization mode driver status information in the lighting command. If the comparison is successful, it determines that the lighting command has been verified and executes the lighting command.
15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the communication method as described in any one of claims 1 to 14.