A 7-bit / 10-bit dual address mode adaptive switching circuit of IIC interface

Abstract

This invention discloses a 7-bit / 10-bit dual address mode adaptive switching circuit for an IIC interface, relating to the field of integrated circuit interface technology. The circuit includes an address frame detection unit and an inverter: the address frame detection unit automatically determines the address mode by recognizing the "11110" signature of the first 5 bits of the SDA bus data; the inverter switches between 7-bit and 10-bit address comparison logic to achieve slave address matching in different modes. This invention requires no additional hardware pins or software instructions, can adaptively switch between 7-bit and 10-bit address modes, adapts to multi-device mixed-mount scenarios, and has the advantages of strong compatibility and stable timing, making it widely applicable to IIC interface circuit design.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits and relates to a 7-bit / 10-bit dual address mode adaptive switching circuit for an IIC interface. Background Technology

[0002] IIC (Inter-Integrated Circuit) was developed in 1982 as a simpler communication method to connect the CPU and peripheral chips in televisions. Televisions were among the first embedded systems to use memory-mapped I / O to interconnect microcontrollers and peripheral devices, requiring a large number of data and address lines, which was both inconvenient and expensive. As embedded system technology continued to develop, the demands on CPU peripheral hardware interfaces increased, necessitating simpler and more efficient interfaces. Integrated circuits with IIC bus functionality emerged in this context. Philips semiconductor engineers developed a bidirectional bus called Inter-Integrated Circuit (IIC) to reduce wiring between various circuit boards and simplify circuitry, enabling efficient control of communication between integrated circuit devices. This allowed system designers and device manufacturers to leverage these similarities to maximize hardware efficiency while simplifying circuitry. Connecting a simple bidirectional synchronous device to the IIC bus requires only a clock and a data line to operate, used for transmitting data, addresses, etc.

[0003] The IIC bus, a standard bus in the global microelectronics communication industry, is a well-known low-speed communication protocol that has undergone four version revisions. The latest version, released in 2012, increases the IIC bus speed from the initial 100 Kbit / s to 5 Mbit / s. To achieve low-speed communication, a standard-mode IIC serial bidirectional bus with a speed of 100 Kbit / s was initially designed. An improved version, version 1.0, was released in 1992, achieving a speed of 400 Kbit / s and named Fast-mode. Due to device requirements for higher bus speeds and lower power supply voltages, version 2.0 was released in 1999, introducing a high-speed mode of up to 3.4 Mbit / s. This mode could be used with high-quality RAM, EEPROM, or serial flash memory, while also adding many energy-saving options. Therefore, the version released in 2007 further increased the Fast-mode speed to 1 Mbit / s, called Fast-mode Plus. The latest version, released in 2012, improved the bus speed, enabling serial data to be transmitted unidirectionally at up to 5 Mbit / s in fast mode, a mode known as Ultra Fast-mode. Notably, high-speed mode devices are fully backward compatible with fast mode, allowing bidirectional transmission in IIC systems across various data rates. Most IIC devices are limited by external factors such as pull-up resistors and cannot reach their maximum speed in transmission mode.

[0004] As a mainstream serial communication interface, the IIC bus is widely used in consumer electronics, industrial control, and other fields. Existing IIC interface circuits typically employ two methods for address mode (7-bit / 10-bit) switching: one is through hardware pin configuration, which requires additional chip pin resources and cannot be dynamically adjusted after switching; the other is through software register configuration, which requires the host to send dedicated instructions, increasing communication overhead and posing timing synchronization risks.

[0005] The above solution has significant drawbacks: the hardware pin configuration method has poor compatibility and cannot adapt to scenarios with multiple devices mounted together; the software configuration method is complex to operate and is prone to timing violations due to command transmission in high-speed communication scenarios, affecting data transmission reliability. In addition, the existing switching circuit has not been optimized for address frame recognition logic, resulting in mismatch between the 10-bit address mode and the 7-bit address slave, which reduces the stability of bus communication.

[0006] This invention aims to solve the technical problems of existing IIC interface address mode switching requiring additional pins or software instructions, poor compatibility, and easy timing violations, and provides a circuit solution that can automatically identify address modes and adaptively switch without additional control signals. Summary of the Invention

[0007] A 7-bit / 10-bit dual address mode adaptive switching circuit for an IIC interface is integrated into the IIC interface control module. It includes an address frame detection unit, a dual-mode matching unit, a timing calibration unit, and a mismatch suppression unit. The specific structure and working mechanism are as follows: (1) Address frame detection unit Core components: A logic array consisting of one 4-input NAND gate and one NOR gate, and a mode decision latch.

[0008] Logic array: One 4-input NAND gate performs logic operations on Q1, Q2, Q3, and Q4. The output result is connected to a NOR gate with Q5. The NOR gate outputs a high-level trigger signal only when Q1-Q5 are "11110" (the 10-bit address mode feature code specified by the IIC protocol).

[0009] Mode determination latch: The clock signal is the 8th rising edge of the SCL bus clock (generated by a 3-bit binary counter). The data input terminal is connected to the output signal of the logic array. The reset signal RESET (active low) is used to pull the output low during power-on initialization to ensure that it works in 7-bit address mode by default.

[0010] Working mechanism: When the IIC host initiates communication, the serial data of the SDA bus is input to the serial-to-parallel converter bit by bit according to the SCL clock cycle. After the first byte of data is sent, the logic array performs feature code matching. If the match is successful ("11110" is detected), the mode determination latch is set and the output level is high (10-bit address mode identifier signal MODE_SEL=1). If the match is unsuccessful, the mode determination latch remains low (MODE_SEL=0, 7-bit address mode identifier).

[0011] (2) Dual-mode matching unit Core components include a 7-bit address comparator, a 10-bit address segmentation comparator, a two-input multiplexer, and a base address configuration module.

[0012] 7-bit address comparator: It consists of 7 two-input XOR gates. The input signals are Q1-Q7 (7-bit address data) output by the serial-to-parallel converter and ADDR_REF [6:0] output by the reference address configuration module. When all XOR gates output high level, it is determined that the address is matched and the output MATCH_7=1 is generated.

[0013] 10-bit address comparator: The high 2-bit register subunit (Q1-Q2) and the 10-bit comparator subunit (Q1-Q10) are composed of 10 XOR NOT gates. The input signals are Q1-Q10 and ADDR_REF[9:0] output by the serial-to-parallel converter, and the output is a 10-bit address matching signal MATCH_10=1.

[0014] Base address configuration: Supports dynamic updating of the base address (ADDR_REF[2:0]) in 7-bit address mode via hardware configuration on A2-A0 pins or bus commands, adapting to custom settings for up to 8 slave addresses.

[0015] Multiplexer: A two-input multiplexer with a CMO transmission gate structure. The control signal is MODE_SEL. When MODE_SEL=0, MATCH_7 is turned on, and when MODE_SEL=1, MATCH_10 is turned on. The final address matching signal MATCH_OUT is output.

[0016] Overall Workflow ① Initialization phase: After power-on, the RESET signal is valid, the mode determination latch outputs a low level (default 7-bit address mode), and the reference address configuration module loads the initial address configured by pins A2-A0; ② Address frame capture: After the IIC host initiates communication, the address frame detection unit captures the serial data on the SDA bus in real time through the serial-to-parallel converter, and completes the shift and parallel conversion according to the SCL clock cycle; ③ Pattern recognition: After the first 5 bits of data are converted, the logic array performs "11110" feature code matching. If the match is successful, the mode determination latch outputs a high level (MODE_SEL=1) on the rising edge of the 8th SCL; otherwise, it remains low (MODE_SEL=0). ④ Address matching: If MODE_SEL=0 (7-bit mode): the selector turns on the 7-bit address comparator, compares Q1-Q7 with ADDR_REF[6:0], and outputs MATCH_7; if MODE_SEL=1 (10-bit mode): the selector turns on the 10-bit address comparator, first registers the two high bits Q1-Q2 through the register, and then compares Q1-Q10 with ADDR_REF[9:0] through the comparison subunit, and outputs MATCH_10; ⑤ Response Trigger: When the MATCH_OUT signal is valid, the IIC interface control module is triggered to generate an ACK response signal, completing the address matching process and entering the data transmission phase. Beneficial effects of this invention: Without requiring additional hardware pins or software instructions, it automatically identifies the address mode through address frame feature codes, adapting to mixed 7-bit / 10-bit address slave scenarios, significantly improving compatibility; the 10-bit address matching process is optimized to avoid mismatches with 7-bit address slaves, improving bus communication stability; the circuit structure is simplified, implemented only through a combination of logic gates and latches, occupying a small chip area, meeting the miniaturization design requirements of IIC interface IP cores. Attached Figure Description

[0017] Figure 1 This is a circuit architecture diagram of the present invention; Figure 2 This is a circuit diagram of the address frame detection unit; Figure 3 Circuit architecture diagram for manual switching between 7-bit and 10-bit dual address modes; Figure 4 Simulation waveform diagram for 7-bit address mode; Figure 5 Simulation waveform diagram for 10-bit address mode; Detailed Implementation

[0018] Address frame detection unit: The serial-to-parallel converter uses an 8-stage shift register (composed of cascaded D flip-flops), taking the output of the first 5 stages as the detection data; the NAND gate logic array consists of 4 two-input NAND gates and 1 NOR gate, outputting a high level when the input data is "11110"; the mode determination flip-flop uses rising edge triggered D flip-flops, with the clock signal being the 5th rising edge of the SCL bus clock; Dual-mode matching unit: The 7-bit address comparator uses a 3-input XOR NOT gate array, and the reference address is configured by pins A2-A0; the high 2 bits of the 10-bit address are registered and compared together through the XOR NOT gate array when the low 8 bits arrive; an inverter gating comparator module is used, and the control signal is the output of the mode determination flip-flop; To make the objectives, technical solutions, and advantages of this invention clearer, the beneficial effects of this invention will be further explained below through four specific embodiments: Example

[0019] Write operations are performed on the IIC interface circuit in 7-bit address mode.

[0020] The specific operation process is as follows: Input 000 through the three interfaces A2-A0 to configure the reference address as 1010000. During the SCL high level, pull SDA low to indicate the start of operation. Write the slave address 1010000 to SDA for matching. In the 8th clock cycle, pull the read / write flag low to indicate that a write operation will follow. The circuit correctly generates the matching signal. Then, through continuous write operations, two frames of data are continuously transmitted to the interface circuit, namely 11010011 and 11011011. The parallel data output at the data output terminal of the overall IIC interface circuit is checked to ensure that it matches the expected written data. The simulation waveform is as follows. Figure 4 As shown Example

[0021] Write operations are performed on the IIC interface circuit in 10-bit address mode.

[0022] The specific operation process is as follows: During the SCL high level, pulling SDA low indicates the start of operation. A 10-bit address mode code 11110 is transmitted via SDA. The detection circuit correctly pulls MODE_SEL high, then inputs the high two bits of the slave address (11), and pulls the read / write flag low in the 8th clock cycle to indicate that a write operation will follow. Then, the low 8 bits of the address (11111111) are transmitted. The circuit correctly generates a matching signal. Then, through continuous write operations, two frames of data (11011011 and 11011100) are continuously transmitted to the interface circuit. The parallel data output at the overall IIC interface circuit is checked to ensure it matches the expected written data. The simulation waveform is as follows. Figure 5 As shown.

[0023] The above-described embodiments are merely illustrative of the implementation methods of the present invention, but should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the protection scope of the present invention.

Claims

1. A 7-bit / 10-bit dual address mode adaptive switching circuit for IIC interface, characterized in that, The 7-bit / 10-bit dual address mode adaptive switching circuit consists of an address frame detection unit and an inverter; the address frame detection unit detects the 10-bit address feature code, and the mode identifier output terminal MODE_SEL controls the operation of the dual address mode comparator. The address frame detection unit includes a logic array and a mode determination latch. The logic array consists of a four-input NAND gate and a two-input NOR gate. The first four bits of data are input to the NAND gate, and the output of the NAND gate and the fifth bit of data are used as inputs to the NOR gate to detect the 10-bit address feature code "11110". The set terminal of the mode determination latch is connected to the output terminal of the NOR gate, and the reset terminal is connected to the reset signal. After reset, it outputs a low level. When the feature code is detected, it outputs a high level signal MODE_SEL. The MODE_SEL signal is input to a 7-bit address comparator via an inverter and directly input to a 10-bit address comparator. Both address comparator control signals are active high. The 7-bit / 10-bit dual address mode adaptive switching circuit adaptively identifies the feature code and switches the address mode through the output of the address frame detection unit. If there is no feature code, the MODE_SEL low level controls the 7-bit address comparator to work. If a feature code is detected, the MODE_SEL high level controls the 10-bit address comparator to work.

Images