B-code time synchronization device

Abstract

This application discloses a B-code time synchronization device. The device includes: a clock signal receiving unit, a field-programmable gate array (FPGA) chip, and a PCIe bus interface chip; the clock signal receiving unit is connected to the FPGA chip, and the FPGA chip is connected to the PCIe bus interface chip; the clock signal receiving unit is used to receive a reference time signal output from an external clock source and convert the reference time signal into a TTL level signal; the FPGA chip is used to parse the TTL level signal to obtain standard time data and output the standard time data to the PCIe bus interface chip via a parallel bus; the PCIe bus interface chip is used to convert the standard time data into PCIe protocol data and transmit it to a central processing unit via the PCIe bus.

Description

Technical Field

[0001] This application relates to the field of power automation equipment technology, and more specifically, to a B-code time synchronization device. Background Technology

[0002] In fields such as power automation and industrial control, stringent requirements are placed on the accuracy and real-time performance of time synchronization between devices. Microsecond-level time synchronization is typically required to ensure the accuracy of event recordings and the reliability of system collaboration. To achieve high-precision time synchronization, standard clock signals such as the Inter-Range Instrumentation Group B Code (IRIG-B) are usually received and parsed via a board, and the time data is transmitted at high speed and with low latency to the central processing unit (CPU) of the power equipment.

[0003] In existing technologies, the solutions for realizing clock signal parsing and data transmission are mainly divided into two categories: one is that the Field Programmable Gate Array (FPGA) transmits the parsed time data to the main CPU through a low-speed serial interface such as a Universal Asynchronous Receiver / Transmitter (UART) or a Quad Serial Peripheral Interface (QSPI); the other is that a high-end FPGA with a built-in Universal Serial Bus (USB) or Peripheral Component Interconnect Express (PCIe) hard core directly sends the data to the main CPU through a high-speed interface.

[0004] However, both of the above solutions have obvious drawbacks: the first type of low-speed serial interface solution has a low transmission rate and a large data delay, and the synchronization accuracy is difficult to meet the requirements of microsecond-level testing and application; although the second type of solution uses a high-speed interface to improve the transmission rate, the high cost of high-end FPGAs with built-in USB or PCIe hard cores is high, the development is difficult, and they often use non-standard structural components, which is not conducive to the motherboard's functional expansion and is difficult to adapt to low-cost, domestically produced mass application scenarios. Summary of the Invention

[0005] The main purpose of this application is to provide a B-code time synchronization device to solve the problems of insufficient accuracy of low-speed interfaces and high cost and development difficulty of high-speed solutions in existing time synchronization schemes. It can achieve microsecond-level high-precision time synchronization and high-speed data transmission under the premise of low cost and easy implementation.

[0006] To achieve the above objectives, this application proposes a B-code time synchronization device, comprising: a clock signal receiving unit, a field-programmable gate array (FPGA) chip, and a PCIe bus interface chip; the clock signal receiving unit is connected to the FPGA chip, and the FPGA chip is connected to the PCIe bus interface chip; the clock signal receiving unit is used to receive a reference time signal output from an external clock source and convert the reference time signal into a TTL level signal; the FPGA chip is used to parse the TTL level signal to obtain standard time data and output the standard time data to the PCIe bus interface chip via a parallel bus; the PCIe bus interface chip is used to convert the standard time data into PCIe protocol data and transmit it to the central processing unit via the PCIe bus.

[0007] According to the B-code time synchronization device provided in this application, a microcontroller unit is further included. The microcontroller unit is connected to the FPGA chip and the central processing unit respectively. The microcontroller unit is used to receive upgrade instructions and upgrade data issued by the central processing unit, and write the upgrade data into the FPGA chip according to the upgrade instructions, so as to realize remote online upgrade of the FPGA chip.

[0008] According to the B-code time synchronization device provided in this application, the microcontroller unit is connected to the FPGA chip via a UART interface and to the central processing unit via an I2C interface.

[0009] According to the B-code time synchronization device provided in this application, a first configuration memory is further included. The first configuration memory is connected to the FPGA chip and is used to store the running configuration program of the FPGA chip.

[0010] According to the B-code time synchronization device provided in this application, the external clock source is an IRIG-B clock source, and the reference time signal is an RS485 level differential signal.

[0011] According to a B-code time synchronization device provided in this application, the clock signal receiving unit includes an RS485 isolated transceiver, which is used to convert the RS485 level differential signal into a 3.3V TTL level signal.

[0012] According to the B-code time synchronization device provided in this application, the PCIe bus interface chip is a CH368 interface chip.

[0013] According to the B-code time synchronization device provided in this application, a second configuration memory is further included, which is connected to the PCIe bus interface chip; the second configuration memory is used to store the running configuration program of the PCIe bus interface chip.

[0014] According to the B-code time synchronization device provided in this application, the FPGA chip is an EG4A20BG256 field-programmable gate array.

[0015] According to the B-code time synchronization device provided in this application, the parallel bus is a 32-bit parallel data bus.

[0016] The technical solutions provided by the embodiments of this application can include the following beneficial effects: Since the clock signal receiving unit converts the external reference time signal into a TTL level signal that the FPGA chip can directly recognize, the FPGA chip can quickly receive and parse the time signal, avoiding parsing delays caused by signal format incompatibility, thus laying the foundation for high-precision time synchronization; Since the FPGA chip outputs the parsed standard time data to the PCIe bus interface chip through a parallel bus, the parallel bus can transmit multiple bits of data simultaneously, thus significantly improving the time data transmission rate, reducing data transmission delay, and meeting the microsecond-level time synchronization accuracy requirements; Since the PCIe bus interface chip... This method converts standard time data in parallel format into PCIe protocol data and transmits it to the central processing unit via the PCIe bus. It eliminates the need for high-end FPGAs with built-in PCIe cores, achieving high-speed data transmission using only a general-purpose FPGA and a dedicated PCIe bus interface chip. This avoids the drawbacks of high-end FPGAs, such as high cost and development complexity, thus reducing the overall cost and development threshold of the B-code time synchronization device. Furthermore, the standardized PCIe bus interface adapts to the expansion needs of mainstream motherboards, facilitating functional expansion. The combination of a general-purpose FPGA and a PCIe bus interface chip also makes domestic selection easier, adapting to low-cost, domestically produced mass-market applications. In this way, it solves the problem of insufficient synchronization accuracy in existing low-speed serial interface solutions while overcoming the drawbacks of high cost and poor scalability of high-end FPGA solutions. While ensuring microsecond-level time synchronization accuracy, it achieves low cost, high compatibility, and domestic adaptation, significantly enhancing its practicality and promotional value in fields such as power automation and industrial control. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings: Figure 1 This is a schematic diagram of the B-code time synchronization device provided in this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0021] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0022] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linked," and "socketing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] This application describes some exemplary embodiments for illustrative purposes. It should be understood that this application may be implemented in other ways not specifically shown in the accompanying drawings.

[0024] like Figure 1 As shown in the figure, this application embodiment provides a B-code time synchronization device 100, which may include: a clock signal receiving unit 101, a field-programmable gate array (FPGA) chip 102, and a PCIe bus interface chip 103. The clock signal receiving unit 101 is connected to the FPGA chip 102, and the FPGA chip 102 is connected to the PCIe bus interface chip 103.

[0025] The clock signal receiving unit 101 is used to receive the reference time signal output by an external clock source and convert the reference time signal into a TTL level signal.

[0026] The FPGA chip 102 is used to parse the TTL level signal to obtain standard time data, and output the standard time data to the PCIe bus interface chip through a parallel bus.

[0027] The PCIe bus interface chip 103 is used to convert the standard time data into PCIe protocol data and transmit it to the central processing unit via the PCIe bus.

[0028] Specifically, an external clock source can output a reference time signal, which is a differential level signal suitable for long-distance transmission. After being transmitted to the B-code time synchronization device 100, it is first received by the clock signal receiving unit 101. The clock signal receiving unit 101 performs level conversion processing on the reference time signal, converting the differential form reference time signal into a TTL level signal that can be directly recognized by the digital chip, and outputs the converted TTL level signal to the FPGA chip 102. After receiving the TTL level signal, the FPGA chip 102 can perform timing identification, data extraction, and decoding processing on the TTL level signal, parsing the standard time data containing standard time information from the TTL level signal. After completing the data parsing and formatting, the FPGA chip 102 can transmit the standard time data in parallel to the PCIe bus interface chip 103 via the parallel bus. After receiving parallel standard time data from FPGA chip 102, PCIe bus interface chip 103 can first perform protocol conversion processing on the parallel standard time data, converting the parallel format standard time data into protocol data conforming to the PCIe bus specification, and then transmit the converted PCIe protocol data to the central processing unit through the PCIe bus, thereby completing the time synchronization of the power equipment.

[0029] Optionally, such as Figure 1 As shown, the B-code time synchronization device 100 provided in this application embodiment may further include a microcontroller unit 104, which is connected to the FPGA chip 102 and the central processing unit respectively. The microcontroller unit 104 is used to receive upgrade instructions and upgrade data issued by the central processing unit, and write the upgrade data into the FPGA chip 102 according to the upgrade instructions, so as to realize remote online upgrade of the FPGA chip 102.

[0030] Specifically, the microcontroller unit 104 acts as the remote upgrade control center for the FPGA chip 102, establishing connections with both the FPGA chip 102 and the central processing unit (CPU) via bidirectional communication links. When firmware updates for the FPGA chip 102 are required, the CPU first generates a transmission packet containing upgrade instructions and corresponding upgrade data, and sends it to the microcontroller unit 104. Upon receiving the packet, the microcontroller unit 104 parses it, separating the upgrade instructions and upgrade data. Then, based on the write address, verification rules, and other information contained in the upgrade instructions, it gradually writes the upgrade data into the configuration storage area of ​​the FPGA chip 102 according to the programming protocol supported by the FPGA chip 102, thus completing the firmware replacement and update. The entire process requires no disassembly of the device or interruption of its operation, enabling remote online upgrade functionality.

[0031] Optionally, such as Figure 1As shown, the microcontroller unit 104 is connected to the FPGA chip 102 via a UART interface and to the central processing unit via an I2C interface.

[0032] Specifically, the microcontroller unit 104 and the FPGA chip 102 establish a serial communication connection via a UART interface. The UART interface achieves bidirectional data transmission through two signal lines (transmitter and receiver), adapts to the serial communication protocol of the FPGA chip, and can stably transmit upgrade data and communication commands. It also features low transmission latency and strong anti-interference capabilities, meeting the reliability requirements of firmware upgrades. The microcontroller unit and the central processing unit are connected via an I2C interface. The I2C interface can achieve communication between multiple master and slave devices through only two signal lines (data line and clock line). The microcontroller unit, as a slave device, receives upgrade commands and data issued by the central processing unit. This interface has a simple transmission protocol and simple hardware structure, and can efficiently complete the transmission of short-distance, small-batch data.

[0033] Optionally, such as Figure 1 As shown, the B-code time synchronization device 100 provided in this application embodiment may further include a first configuration memory 105, which is connected to the FPGA chip 102 and is used to store the running configuration program of the FPGA chip 102.

[0034] Specifically, the first configuration memory 105 is a non-volatile memory, directly connected to the configuration interface pin of the FPGA chip 102. When the B-code time synchronization device 100 is powered on, the FPGA chip 102 automatically starts the configuration loading process, reading the pre-stored running configuration program from the first configuration memory 105 through the configuration interface. This running configuration program contains the logic code of the FPGA chip 102 to implement functions such as IRIG-B code decoding, data parsing, and bus communication. After the FPGA chip 102 is loaded, it executes the corresponding operations according to the logic of the configuration program to ensure that the device can normally realize the time synchronization function. When the firmware upgrade is completed through the microcontroller unit 104, the new configuration program will overwrite the original program in the first configuration memory 105. The FPGA chip 102 will load and run the upgraded program the next time it is powered on.

[0035] Optionally, the external clock source is an IRIG-B clock source, and the reference time signal is an RS485 level differential signal.

[0036] Specifically, the IRIG-B clock source is a universal time synchronization clock source in the industrial field. It can output a time code signal that conforms to the IRIG-B standard. This signal contains complete time information such as year, month, day, hour, minute, and second. It has the characteristics of strong versatility and high synchronization accuracy, and is suitable for scenarios with strict time synchronization requirements, such as power systems and industrial automation. Its output reference time signal adopts the form of RS485 level differential signal. This signal is transmitted through two differential signal lines, and the logic level is represented by the voltage difference between the two signal lines. Compared with single-ended signals, it has stronger anti-electromagnetic interference capability and longer transmission distance. It can adapt to the complex electromagnetic environment of industrial sites and ensure the integrity and accuracy of the reference time signal during long-distance transmission.

[0037] Optionally, the clock signal receiving unit 101 includes an RS485 isolated transceiver, which is used to convert the RS485 level differential signal into a 3.3V TTL level signal.

[0038] Specifically, the RS485 isolation transceiver integrates signal isolation, differential signal reception, and level conversion functions. Its differential input port is connected to the RS485 signal output of an external IRIG-B clock source. First, the internal isolation module achieves electrical isolation between the external signal and the internal circuitry of the device, preventing external interference signals from entering the internal chip and ensuring the stability of the device's operation. Subsequently, the RS485 isolation transceiver converts the received RS485 differential signal into a single-ended 3.3V TTL level signal. The logic high level of this signal is 3.3V and the logic low level is 0V, which perfectly matches the input level requirements of the FPGA chip and can be directly recognized and processed by the FPGA chip, thereby realizing the conversion of the reference time signal from the external transmission format to the internal processing format.

[0039] Optionally, the PCIe bus interface chip is a CH368 interface chip.

[0040] Specifically, the CH368 interface chip is a dedicated PCIe bus protocol conversion chip with bidirectional conversion function between parallel interface and PCIe interface. Its parallel interface end is connected to the parallel bus pin of FPGA chip 102, and can receive parallel format standard time data output by FPGA chip 102. The CH368 interface chip integrates a PCIe protocol stack, which can encapsulate and convert the received parallel data according to the PCIe bus specification to form serial data that conforms to the PCIe protocol. At the same time, the CH368 interface chip integrates a PCIe×1 interface, which can establish a high-speed communication link with the central processing unit through the PCIe bus to realize high-speed transmission of standard time data.

[0041] It should be noted that the PCIe bus interface chip in this application embodiment only needs to have the basic functions of parallel data reception, PCIe protocol conversion and PCIe bus transmission. There is no need to integrate complex expansion modules, nor is there any limitation on specific models, brands or transmission rate levels. Any PCIe bus interface chip that can realize the above basic protocol conversion and data transmission functions is applicable to this solution.

[0042] Optionally, such as Figure 1 As shown, the B-code time synchronization device 100 provided in this application embodiment may further include a second configuration memory 106, which is connected to the PCIe bus interface chip 103; the second configuration memory 106 is used to store the running configuration program of the PCIe bus interface chip 103.

[0043] Specifically, the second configuration memory 106 is a non-volatile memory connected to the configuration storage interface of the PCIe bus interface chip 103. It is used to store the configuration program required for chip operation, including PCIe bus protocol parameters, interface communication timing, device identification information, etc. When the B-code time synchronization device 100 is powered on, the PCIe bus interface chip 103 can automatically read the configuration program from the second configuration memory 106 to complete the chip's initialization configuration, ensuring that the chip can correctly identify the parallel bus data format, adapt to the PCIe bus communication protocol, and realize normal communication with the FPGA chip 102 and the central processing unit. The configuration program is stored in the second configuration memory 106, and the data is not lost after power failure, which can ensure that the device can start stably every time it is powered on.

[0044] Optionally, the FPGA chip is an EG4A20BG256 field-programmable gate array.

[0045] Specifically, the EG4A20BG256 is a domestically produced field-programmable gate array (FPGA) chip with abundant logic resources and peripheral interfaces. Its logic resources include a large number of lookup tables (LUTs) and flip-flops (DFFs), which can meet the logic implementation requirements of functions such as IRIG-B code decoding, data parsing, and parallel bus control. The chip integrates multiple user I / O interfaces, which can be flexibly configured as parallel bus interfaces, UART interfaces, etc., to achieve stable connections with PCIe bus interface chips and microcontroller units, respectively. At the same time, the chip supports 3.3VTTL level input and output, which is completely matched with the output level of the clock signal receiving unit, eliminating the need for additional level conversion circuits, simplifying the hardware structure of the device. In addition, the chip has the characteristics of low power consumption and high reliability, making it suitable for industrial-grade time synchronization devices.

[0046] It should be noted that the FPGA chip in this application embodiment only needs to have the basic functions of frame synchronization, data extraction and basic decoding of TTL level signals. It does not need to integrate high-end hard cores such as PCIe, nor is it limited to specific models, brands or logic resource scale. Any FPGA chip that can realize the above basic parsing functions and support parallel bus data output is applicable to this solution.

[0047] Optionally, the parallel bus is a 32-bit parallel data bus.

[0048] Specifically, the 32-bit parallel data bus consists of 32 data signal lines, each corresponding to one bit of binary data, enabling the simultaneous transmission of 32 bits of binary data. Compared to 8-bit and 16-bit parallel buses, it has a higher data transmission rate. One end of the parallel bus is connected to the GPIO pin of the FPGA chip 102, and the other end is connected to the parallel data input pin of the PCIe bus interface chip 103. The standard time data parsed by the FPGA chip 102 is packaged according to the 32-bit data format and simultaneously transmitted to the PCIe bus interface chip 103 through this bus. This reduces the number of clock cycles for data transmission, improves the transmission efficiency of standard time data from the FPGA chip 102 to the PCIe bus interface chip 103, and ensures the real-time performance of time synchronization.

[0049] In this embodiment, since the clock signal receiving unit converts the external reference time signal into a TTL level signal that the FPGA chip can directly recognize, the FPGA chip can quickly receive and parse the time signal, avoiding parsing delays caused by signal format incompatibility, thus laying the foundation for high-precision time synchronization. Because the FPGA chip outputs the parsed standard time data to the PCIe bus interface chip via a parallel bus, and the parallel bus can transmit multiple bits of data simultaneously, the transmission rate of time data can be significantly improved, and data transmission delays can be reduced, meeting the accuracy requirements of microsecond-level time synchronization. Furthermore, because the standard time data in parallel format is transmitted via the PCIe bus interface chip... Time data is converted into PCIe protocol data and transmitted to the central processing unit via the PCIe bus. This eliminates the need for high-end FPGAs with built-in PCIe cores; high-speed data transmission can be achieved using only a general-purpose FPGA and a dedicated PCIe bus interface chip. This avoids the drawbacks of high-end FPGAs, such as high cost and development complexity, and lowers the overall cost and development threshold of the B-code time synchronization device. Furthermore, the standardized PCIe bus interface adapts to the expansion needs of mainstream motherboards, facilitating functional expansion. The combination of a general-purpose FPGA and a PCIe bus interface chip also makes domestic selection easier, adapting to low-cost, domestically produced mass-market applications. Thus, this solution addresses the insufficient synchronization accuracy of existing low-speed serial interface solutions while overcoming the high cost and poor scalability of high-end FPGA solutions. It achieves low cost, high compatibility, and domestic adaptation while ensuring microsecond-level time synchronization accuracy, significantly enhancing its practicality and promotional value in fields such as power automation and industrial control.

[0050] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0051] Obviously, those skilled in the art should understand that the various units or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps into a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0052] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A B-code time transfer apparatus, characterized by comprising: include: The system includes a clock signal receiving unit, a field-programmable gate array (FPGA) chip, and a PCIe bus interface chip; the clock signal receiving unit is connected to the FPGA chip, and the FPGA chip is connected to the PCIe bus interface chip. The clock signal receiving unit is used to receive the reference time signal output by an external clock source and convert the reference time signal into a TTL level signal; The FPGA chip is used to parse the TTL level signal to obtain standard time data, and output the standard time data to the PCIe bus interface chip through a parallel bus. The PCIe bus interface chip is used to convert the standard time data into PCIe protocol data and transmit it to the central processing unit via the PCIe bus.

2. The B-code timekeeping device of claim 1, wherein, It also includes a microcontroller unit, which is connected to the FPGA chip and the central processing unit respectively; The microcontroller unit is used to receive upgrade instructions and upgrade data issued by the central processing unit, and write the upgrade data into the FPGA chip according to the upgrade instructions, so as to realize remote online upgrade of the FPGA chip.

3. The B-code timekeeping device of claim 2, wherein, The microcontroller unit communicates with the FPGA chip via a UART interface and with the central processing unit via an I2C interface.

4. The B-code time synchronization device according to claim 2, characterized in that, It also includes a first configuration memory, which is connected to the FPGA chip and is used to store the FPGA chip's runtime configuration program.

5. The B-code time synchronization device according to claim 1, characterized in that, The external clock source is an IRIG-B clock source, and the reference time signal is an RS485 level differential signal.

6. The B-code time synchronization device according to claim 5, characterized in that, The clock signal receiving unit includes an RS485 isolated transceiver, which is used to convert the RS485 level differential signal into a 3.3V TTL level signal.

7. The B-code time synchronization device according to claim 1, characterized in that, The PCIe bus interface chip is a CH368 interface chip.

8. The B-code time synchronization device according to claim 7, characterized in that, It also includes a second configuration memory, which is connected to the PCIe bus interface chip; the second configuration memory is used to store the running configuration program of the PCIe bus interface chip.

9. The B-code time synchronization device according to claim 1, characterized in that, The FPGA chip is an EG4A20BG256 field-programmable gate array.

10. The B-code time synchronization device according to claim 1, characterized in that, The parallel bus is a 32-bit parallel data bus.

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