Multi-chip secure communication system and method

Abstract

This application discloses a multi-chip secure communication system and method. The system includes: a first master control chip, at least one target slave chip, and a second intermediate bridge chip. The second intermediate bridge chip is electrically connected to the first master control chip and each target slave chip. The at least one target slave chip includes a third slave chip and a fourth slave chip. The second intermediate bridge chip integrates an input interface group, an SPI component, an I²C component, and an internal selection switch matrix. The internal selection switch matrix includes multiple multiplexers, which are used to control the signal paths to the third and fourth slave chips. Therefore, using this application simplifies PCB design, effectively improves the overall integration and compactness of the multi-chip secure communication system, and enhances communication reliability. It also significantly enhances signal anti-interference capabilities, reduces signal attenuation risks, and ensures high reliability and high bandwidth performance for high-speed communication between multiple chips.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a multi-chip secure communication system and method. Background Technology

[0002] With the development of integrated circuit technology, in multi-chip systems (such as industrial control systems), there is a need for a master control chip to securely communicate with multiple peripheral slave chips. Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I²C) are two widely used, low-cost, short-distance, synchronous / asynchronous serial communication bus standards. To achieve communication sharing between multiple master controllers and multiple slave chips, and to support flexible signal path switching, a reliable and efficient signal routing mechanism is required.

[0003] Currently, for example Figure 1 As shown, a signal routing scheme based on an external discrete multiplexer (MUX) is adopted. The SPI master signal and I²C master signal generated by the main control chip (CHIP1) are transmitted to the SPI / I²C interface. 2 The C-channel communication monitoring chip (CHIP2) is an intermediate chip that processes or transmits signals and generates multiple potential output signals. To selectively route these signals to different target slave chips (such as CHIP3 and CHIP4), multiple independent physical multiplexer devices need to be placed externally to the intermediate chip at the printed circuit board (PCB) level. These external multiplexers receive multiple signals from the intermediate chip and select one output based on control signals, connecting it to the corresponding target slave chip, thus establishing a communication link between the master control chip and different slave chips.

[0004] However, external multiplexers, as independent physical components, occupy valuable PCB space and increase material costs. Their connections with intermediate and slave chips require numerous board-level traces, leading to complex PCB layout and routing, and hindering improvements in overall system integration. Furthermore, signals traveling through long traces and multiple connection points outside the chip are more susceptible to electromagnetic interference (EMI), crosstalk, and impedance mismatch, potentially causing signal attenuation and reducing communication reliability and maximum speed. Summary of the Invention

[0005] This application provides a multi-chip secure communication system. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0006] In a first aspect, embodiments of this application provide a multi-chip secure communication system, the system comprising:

[0007] A first master control chip, at least one target slave chip, and a second intermediate bridge chip, wherein the second intermediate bridge chip is electrically connected to the first master control chip and each target slave chip; wherein, at least one target slave chip includes a third slave chip and a fourth slave chip; The second intermediate bridge chip integrates an input interface group, an SPI component, an I²C component, and an internal selection switch matrix; the input interface group includes an SPI input interface and an I²C input interface. One end of the SPI input interface is connected to the SPI component, and one end of the I²C input interface is connected to the I²C component. The other ends of the SPI input interface and the I²C input interface are connected to the first master control chip. One end of the internal selection switch matrix is ​​connected to the output terminals of the SPI component, the I²C component, the SPI input interface, and the first master control chip, respectively, and the other end is connected to the target slave chip. The internal selection switch matrix includes multiple multiplexers, which are used to control the signal paths to the third slave chip and the fourth slave chip, respectively.

[0008] Secondly, a multi-chip secure communication method, the method comprising: The first master control chip accesses the data of the third slave chip and the data of the fourth slave chip to generate SPI master device signal and I²C master device signal; The input interface group receives SPI master device signals and I²C master device signals from the first master control chip; The SPI component reads and verifies the data of the third slave chip; in response to the SPI master signal, it detects the SPI commands and addresses, and if an illegal command or illegal address is detected, it prevents the command from being sent to the third slave chip. The I²C component reads and verifies the data of the fourth slave chip; in response to the I²C master device signal, it detects the commands and addresses of the I²C, and if an illegal command or illegal address is detected, it will prevent the command from being sent to the fourth slave chip. The internal selection switch matrix routes at least one of the first SPI output signal, the second SPI output signal, the first I²C output signal, the second I²C output signal, the SPI master signal, and the I²C master signal to the third or fourth slave chip.

[0009] In this embodiment, on the one hand, by directly integrating the internal selection switch matrix (containing multiple multiplexers) into the second intermediate bridge chip, the independent components that originally required external connections are internalized as chip logic modules. This not only significantly reduces the physical space occupied by the PCB and lowers hardware material costs, but also eliminates the cumbersome external interconnection traces between chips, simplifying PCB design and effectively improving the overall integration and compactness of the multi-chip secure communication system, while also enhancing communication reliability. On the other hand, by using the internal selection switch matrix integrated into the second intermediate bridge chip to directly control the signal paths to the third and fourth slave chips, the originally lengthy board-level transmission paths are shortened to micron-level interconnections within the chip. This greatly reduces the chance of signals being exposed to external noise and eliminates the impedance caused by multiple connection points, thereby significantly enhancing the signal's anti-interference capability, reducing the risk of signal attenuation, and ensuring high reliability and high bandwidth performance for high-speed communication between multiple chips.

[0010] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0012] Figure 1 This is a schematic diagram of the system architecture of a multi-chip secure communication system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the system architecture of another multi-chip secure communication system provided in the embodiments of this application; Figure 3 This is a schematic diagram of a multi-chip routing process provided in an embodiment of this application; Figure 4 This is a flowchart illustrating a multi-chip secure communication method provided in an embodiment of this application. Detailed Implementation

[0013] The following description and accompanying drawings fully illustrate specific embodiments of this application to enable those skilled in the art to practice them.

[0014] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0015] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of systems and methods consistent with some aspects of this application as detailed in the appended claims.

[0016] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0017] Currently, for example Figure 1 As shown, a signal routing scheme based on an external discrete multiplexer (MUX) is employed. The SPI master device signal and I²C master device signal generated by the master control chip (CHIP1) are transmitted to an intermediate chip (CHIP2) that acts as a bridge or relay. The intermediate chip can process or pass through the signals and generate multiple potential output signals. To selectively route these signals to different target slave chips (such as CHIP3 and CHIP4), multiple independent physical multiplexer devices need to be set up outside the intermediate chip at the printed circuit board (PCB) level. These external multiplexers receive multiple signals from the intermediate chip and select one output according to the control signal, connecting it to the corresponding target slave chip, thereby establishing a communication link between the master control chip and different slave chips.

[0018] The inventors recognized that external multiplexers, as independent physical components, occupy valuable PCB space and increase material costs. Their connections with intermediate and slave chips require numerous board-level traces, leading to complex PCB layout and routing, and hindering improvements in overall system integration. Furthermore, signals traveling through long traces and multiple connection points outside the chip are more susceptible to electromagnetic interference (EMI), crosstalk, and impedance mismatch, potentially causing signal attenuation and reducing communication reliability and maximum speed.

[0019] In this embodiment, on the one hand, by directly integrating the internal selection switch matrix (containing multiple multiplexers) into the second intermediate bridge chip, the independent components that originally required external connections are internalized as chip logic modules. This not only significantly reduces the physical space occupied by the PCB and lowers hardware material costs, but also eliminates the cumbersome external interconnection traces between chips, simplifying PCB design and effectively improving the overall integration and compactness of the multi-chip secure communication system, while also enhancing communication reliability. On the other hand, by using the internal selection switch matrix integrated into the second intermediate bridge chip to directly control the signal paths to the third and fourth slave chips, the originally lengthy board-level transmission paths are shortened to micron-level interconnections within the chip. This greatly reduces the chance of signals being exposed to external noise and eliminates the impedance caused by multiple connection points, thereby significantly enhancing the signal's anti-interference capability, reducing the risk of signal attenuation, and ensuring high reliability and high bandwidth performance for high-speed communication between multiple chips. Exemplary embodiments will be used for detailed description below.

[0020] Please see Figure 2 , Figure 2 This is a schematic diagram of the system architecture of a multi-chip secure communication system provided in an embodiment of this application. The system includes: a first master control chip, at least one target slave chip, and a second intermediate bridge chip. The second intermediate bridge chip is electrically connected to the first master control chip and each target slave chip. The at least one target slave chip includes a third slave chip and a fourth slave chip. The second intermediate bridge chip integrates an input interface group, an SPI component, an I²C component, and an internal selection switch matrix. The input interface group includes an SPI input interface and an I²C input interface. One end of the SPI input interface is connected to the SPI component, and one end of the I²C input interface is connected to the I²C component. The other ends of the SPI input interface and the I²C input interface are connected to the first master control chip. One end of the internal selection switch matrix is ​​connected to the output terminals of the SPI component, the I²C component, the SPI input interface, and the first master control chip, respectively, and the other end is connected to the target slave chip. The internal selection switch matrix includes multiple multiplexers, which are used to control the signal paths to the third slave chip and the fourth slave chip.

[0021] In this communication topology, the first master control chip is the signal initiator or master controller. This chip is configured to generate raw communication protocol signals (such as Serial Peripheral Interface (SPI) signals and Integrated Circuit Bus (I²C) signals) and, as the system's data source, send these raw signals to the second intermediate bridge chip. The target slave chip is the signal receiver or controlled device in the communication topology; it can be understood as the set of all downstream chips in the system that receive signals from the first master control chip and the second bridge chip. The second intermediate bridge chip is the signal relay and processing hub located between the signal source (such as the first master control chip) and the signal destination (such as the target slave chip). Physically, the second intermediate bridge chip is at the central node, establishing electrical connections with both the upstream master control chip and all downstream slave chips.

[0022] The input interface group includes an SPI input interface and an I²C input interface. This input interface group is a collection of ports within the second intermediate bridge chip used to receive raw external signals. This port collection is configured to adapt to the output standard of the first master control chip (such as SPI level and I²C timing). The input interface group contains multiple independent pins or channels to support parallel input of multiple protocols.

[0023] The SPI processing unit is a logic circuit module within the second intermediate bridge chip dedicated to processing the serial peripheral interface protocol. The SPI processing unit is configured to perform specific operations on the input raw SPI signals. These operations include, but are not limited to: protocol conversion, timing adjustment, data buffering, level shifting, master / slave mode switching, or signal enhancement. Its output is connected to an internal selection switch matrix, providing a path for the processed SPI signal.

[0024] The I²C processing unit is a logic circuit module within the second intermediate bridge chip dedicated to processing integrated circuit bus protocols. This unit is configured to perform specific operations on the input raw I²C signals. These operations include, but are not limited to: address mapping, clock stretching processing, debouncing filtering, voltage level translation, or bus isolation. Its output is connected to an internal selection switch matrix, providing a path for the processed I²C signals.

[0025] The multiplexer is the basic switching logic unit that constitutes the internal selection switch matrix. Specifically, it is a combinational logic circuit with multiple inputs and one (or multiple) outputs. Each multiplexer is configured to select a unique signal from multiple candidate signal sources and conduct it to its output under the action of a control signal. The combination of multiple multiplexers forms an independent and controllable path to the third and fourth slave chips. For example, the third slave chip may specifically be a third SPI memory chip, and the fourth slave chip may specifically be a fourth I... 2 C memory chip.

[0026] In some embodiments of this application, a first master control chip is used to access data from the third slave chip and the fourth slave chip to generate an SPI master device signal and an I²C master device signal; an input interface group is used to receive the SPI master device signal and the I²C master device signal from the first master control chip; an SPI component is used to read and verify the data from the third slave chip; in response to the SPI master device signal, it detects SPI commands and addresses, and if an illegal command or illegal address is detected, it sends a prohibition command to the third slave chip; an I²C component is used to read and verify the data from the fourth slave chip; in response to the I²C master device signal, it detects I²C commands and addresses, and if an illegal command or illegal address is detected, it sends a prohibition command to the fourth slave chip; an internal selection switch matrix is ​​used to route at least one of the first SPI output signal, the second SPI output signal generated by the SPI component, the first I²C output signal, the second I²C output signal generated by the I²C component, the SPI master device signal, and the I²C master device signal to the third slave chip or the fourth slave chip.

[0027] In one possible implementation, the first master control chip is configured as the signal initiator of the communication system. It integrates an SPI master controller module and an I²C master controller module to generate standard SPI master device signals (e.g., including clock SCLK, chip select CS, master-output-slave-in MOSI, and master-in-slave-output MISO signals) and I²C master device signals (e.g., including serial clock SCL and serial data SDA signals). The second intermediate bridge chip has an input interface group, which physically manifests as a set of pins or pads electrically connected to the output of the first master control chip via PCB traces. The input interface group is configured to receive and sample the SPI master device signals and I²C master device signals from the first master control chip in real time, and then offload the raw signals to subsequent processing links within the chip.

[0028] Specifically, the input of the SPI component is coupled to the SPI signal channel of the input interface group. This unit is configured to perform preset signal conditioning operations (such as, but not limited to, level conversion, timing retiming, drive capability enhancement, or protocol format conversion) on the received raw SPI master device signals, as well as the first SPI output signal and the second SPI output signal generated during SPI component communication.

[0029] Specifically, the input of the I²C component is coupled to the I²C signal channel of the input interface group. Similarly, this unit is configured to perform preset signal conditioning operations (such as, but not limited to, address mapping, clock extension processing, noise filtering, or voltage domain translation) on the received raw I²C master device signals, generating a first I²C output signal and a second I²C output signal.

[0030] Specifically, the core control logic of the second intermediate bridge chip is embodied in an internal selection switch matrix. This matrix has multiple inputs and at least two outputs (corresponding to physical output pins leading to the third and fourth slave chips, respectively). The input pool of the internal selection switch matrix includes the following six candidate signal sources: a first SPI output signal from the SPI component; a second SPI output signal from the SPI component; a first I²C output signal from the I²C component; a second I²C output signal from the I²C component; the original SPI master signal from the input interface group (i.e., a bypass signal, not passing through the SPI component); and the original I²C master signal from the input interface group (i.e., a bypass signal, not passing through the I²C component). The internal selection switch matrix is ​​configured to dynamically select at least one of the above six candidate signal sources as a valid signal in response to a pre-integrated control logic unit and conduct it to the specified output path.

[0031] In some embodiments of this application, for example Figure 2 As shown, the SPI component includes an SPI master mode module, an SPI communication monitoring unit, and an SPI pass-through mode module. The SPI master mode module is used to read and verify the data of the third slave chip. The SPI communication monitoring unit is used to respond to the SPI master device signal and detect the SPI commands and addresses when the first master control chip accesses data from the third slave chip through the SPI input interface. If an illegal command or illegal address is detected, the command will be prohibited from being sent to the third slave chip. The SPI pass-through mode module is used to realize pass-through communication between the first master control chip and the third slave chip. The internal selection switch matrix includes a first SPI multiplexer and a second SPI multiplexer. The first input terminal of the first SPI multiplexer is connected to the output of the SPI master mode module, and the second input terminal of the first SPI multiplexer is connected to the output of the SPI communication monitoring unit. The output terminal of the first SPI multiplexer is set as a first SPI output port, and the first SPI output port is connected to the first input terminal of the second SPI multiplexer.

[0032] Furthermore, the first input terminal of the second SPI multiplexer is connected to the input interface group through the SPI pass-through mode module, so that the SPI master device signal from the first master control chip is input to the second SPI multiplexer as a candidate signal without being processed by the SPI component; the second input terminal of the second SPI multiplexer is connected to the output terminal of the first SPI multiplexer; the output terminal of the second SPI multiplexer constitutes the second SPI output port, and the second SPI output port is connected to the input terminal of the third slave chip.

[0033] It should be noted that the first SPI multiplexer enables flexible switching between deep protocol processing (master mode) and lightweight signal forwarding (transparent transmission mode) within the chip, adapting to the differentiated timing or protocol logic requirements of different slave chips. On the other hand, the second SPI multiplexer further introduces the original SPI master device signal from the input interface group as a bypass input, constructing a three-level signal selectable path of original direct connection, transparent transmission relay, and master mode simulation. This multi-level multiplexing structure not only greatly improves the flexibility of signal routing and the fault tolerance of the system without adding additional external components, but also effectively reduces signal transmission delay and optimizes PCB layout complexity, thereby significantly enhancing the reliability, compatibility, and integration of the multi-chip secure communication system.

[0034] In some embodiments of this application, for example Figure 2 As shown, the I²C component includes an I²C master mode module, an I²C communication monitoring unit, and an I²C transparent transmission mode module. The I²C master mode module is used to read and verify the data of the fourth slave chip. The I²C communication monitoring unit is used to detect I²C commands and addresses when the first master chip accesses data from the fourth slave chip through the I²C input interface, and to prohibit the sending of commands to the fourth slave chip if illegal commands and addresses are detected. The I²C transparent transmission mode module is used to realize transparent communication between the first master chip and the fourth slave chip. The internal selection switch matrix includes a first I²C multiplexer and a second I²C multiplexer. The first input terminal of the first I²C multiplexer is connected to the output of the I²C master mode module, and the second input terminal of the first I²C multiplexer is connected to the output of the I²C communication monitoring unit. The output terminal of the first I²C multiplexer is set as a first I²C output port, and the first I²C output port is connected to the first input terminal of the second I²C multiplexer.

[0035] Furthermore, the first input terminal of the second I²C multiplexer is connected to the input interface group through the I²C transparent transmission mode module, so that the I²C master device signal from the first master control chip is input to the second I²C multiplexer as a candidate signal without passing through the I²C component; the second input terminal of the second I²C multiplexer is connected to the output terminal of the first I²C multiplexer; the output terminal of the second I²C multiplexer constitutes the second I²C output port, and the second I²C output port is connected to the input terminal of the fourth slave chip.

[0036] It should be noted that the first I²C multiplexer enables flexible switching between active protocol access (master mode) and passive signal relay (transparent transmission mode) within the chip, accurately adapting to the differentiated requirements of the fourth slave chip for I²C timing control, address mapping, or electrical characteristics. On the other hand, the second I²C multiplexer introduces the original I²C master device signal from the first master control chip as a direct bypass input, constructing a three-level selectable signal path: direct drive of the original signal, forwarding in transparent transmission mode, and deep processing in master mode. This multi-level multiplexing structure not only greatly improves the configuration flexibility and communication robustness of the I²C bus system without adding external components, but also effectively avoids unnecessary signal processing delays and simplifies PCB routing complexity, thereby significantly enhancing the system compatibility, reliability, and integration efficiency under the multi-slave chip architecture.

[0037] The internal selection switch matrix integrates a control logic unit.

[0038] In some embodiments of this application, the specific process of routing to the third slave chip includes: a control logic unit generating a control signal; when the control signal indicates that a first-level selection operation is performed using a first SPI multiplexer, the control logic unit selects an intermediate SPI signal between a first SPI output signal output by the SPI master mode module and a second SPI output signal output by the SPI communication monitoring unit; or, when the control signal indicates that a second-level selection operation is performed using a second SPI multiplexer, the control logic unit selects an SPI master device signal from the input interface group through the SPI pass-through mode module; when the SPI master device signal is selected, the control logic unit constructs an SPI pass-through path and sends the SPI master device signal to the second SPI multiplexer; or, when an intermediate SPI signal is selected, an SPI processing path is constructed and the intermediate SPI signal is sent to the second SPI multiplexer; the control logic unit sends the intermediate SPI signal or the SPI master device signal to the third slave chip through the second SPI multiplexer.

[0039] In some embodiments of this application, the specific process of routing to the fourth slave chip includes: a control logic unit generating a control signal; when the control signal indicates that a first-level selection operation is performed using a first I²C multiplexer, the control logic unit selects an intermediate I²C signal between the first I²C output signal output by the I²C master mode module and the second I²C output signal output by the I²C communication monitoring unit; or, when the control signal indicates that a second-level selection operation is performed using a second I²C multiplexer, the control logic unit selects an I²C master device signal from the first master control chip through the I²C pass-through mode module; when the I²C master device signal is selected, the control logic unit constructs an I²C direct path and sends the I²C master device signal to the second I²C multiplexer; or, when an intermediate I²C signal is selected, an I²C processing path is constructed and the intermediate I²C signal is sent to the second I²C multiplexer; the control logic unit sends the intermediate I²C signal or the I²C master device signal to the fourth slave chip through the second I²C multiplexer.

[0040] For example Figure 3 As shown, Figure 3 This is a schematic diagram of a multi-chip routing process provided in this application. First, the control logic unit generates one or more sets of control signals based on the current system state or external configuration instructions. These signals will serve as the basis for all subsequent routing decisions. The control logic unit determines which type of chip the target that needs to communicate belongs to: if it is the third slave chip, it enters the SPI routing process; if it is the fourth slave chip, it enters the I²C routing process.

[0041] In the SPI routing process, the control logic unit again uses a multiplexer for selection based on control signal indications. First-level selection (enabling the first SPI multiplexer): The system selects between two pre-processed signals: the first SPI output signal (from the master mode module, including protocol emulation / timing adjustment) and the second SPI output signal (from the SPI communication monitoring unit, only performing level conversion or buffering). The selected signal is called the intermediate SPI signal. An SPI processing path is then constructed, sending this intermediate signal to the second SPI multiplexer. Second-level selection (enabling the second SPI multiplexer): The system skips the master mode module and the SPI communication monitoring unit, directly selecting the original input SPI master device signal (i.e., the raw signal from the first master control chip without any processing) through the SPI pass-through mode module, and constructs an SPI pass-through path, sending it directly to the second SPI multiplexer. Finally, all signals are output to the third slave chip through the second SPI multiplexer, completing the directional transmission under the SPI protocol.

[0042] In the I²C routing process, the structure is completely symmetrical to SPI, reflecting design consistency and scalability. First-level selection (enabling the first I²C multiplexer): The system selects between the first I²C output signal from the I²C master mode module and the second I²C output signal from the I²C communication monitoring unit to obtain an intermediate I²C signal, constructing an I²C processing path, and sending it to the second I²C multiplexer. Second-level selection (enabling the second I²C multiplexer): The system directly selects the original I²C master device signal through the I²C pass-through mode module, constructing an I²C direct path, with all internal processing units directly connected to the second I²C multiplexer. Finally, the signal is output to the fourth slave chip via the second I²C multiplexer, completing efficient routing under the I²C protocol.

[0043] In some embodiments of this application, the specific process of generating control signals includes: receiving routing configuration information from a first master control chip, the routing configuration information including a desired communication mode identifier and a timing parameter identifier, the desired communication mode identifier including at least pass-through mode, master mode conversion, and communication monitoring mode conversion; generating an independent hierarchical control word for each communication channel, the hierarchical control word including a first-level selection bit and a second-level selection bit; when the desired communication mode identifier is pass-through mode, setting the second-level selection bit to an active level to instruct the second SPI multiplexer or the second I²C multiplexer to select the SPI master device signal from the input interface group or the I²C master device signal from the first master control chip through the SPI pass-through mode module or the I²C pass-through mode module, and shielding the output influence of the first-level selection bit; or, when the desired communication mode identifier is master mode conversion or communication monitoring mode conversion, setting the second-level selection bit to an inactive level. The system instructs the second SPI multiplexer or the second I²C multiplexer to select the output signal from the first multiplexer via the SPI pass-through mode module or the I²C pass-through mode module. When switching to master mode, the first-level selection bit is set to an active level to select the output of the SPI master mode module or the I²C master mode module. When switching to communication monitoring mode, the first-level selection bit is set to an active level to select the output of the SPI communication monitoring unit or the I²C communication monitoring unit. The set first-level selection bit is converted into a first control signal and sent to the corresponding selection control terminal of the first multiplexer. The set second-level selection bit is converted into a second control signal and sent to the corresponding selection control terminal of the second multiplexer. The first and second control signals are independently controllable, allowing the SPI path to the third slave chip and the communication path to the fourth slave chip to operate in parallel under different communication modes.

[0044] In this embodiment, on the one hand, by directly integrating the internal selection switch matrix (containing multiple multiplexers) into the second intermediate bridge chip, the independent components that originally required external connections are internalized as chip logic modules. This not only significantly reduces the physical space occupied by the PCB and lowers hardware material costs, but also eliminates the cumbersome external interconnection traces between chips, simplifying PCB design and effectively improving the overall integration and compactness of the multi-chip secure communication system, while also enhancing communication reliability. On the other hand, by using the internal selection switch matrix integrated into the second intermediate bridge chip to directly control the signal paths to the third and fourth slave chips, the originally lengthy board-level transmission paths are shortened to micron-level interconnections within the chip. This greatly reduces the chance of signals being exposed to external noise and eliminates the impedance caused by multiple connection points, thereby significantly enhancing the signal's anti-interference capability, reducing the risk of signal attenuation, and ensuring high reliability and high bandwidth performance for high-speed communication between multiple chips.

[0045] Please see Figure 4 This is a flowchart illustrating a multi-chip secure communication method provided in an embodiment of this application. Figure 4 As shown, the detection method in this application embodiment may include the following steps: S101, the first master control chip accesses the data of the third slave chip and the data of the fourth slave chip to generate SPI master device signal and I²C master device signal; S102, the input interface group receives the SPI master device signal and the I²C master device signal from the first master control chip; S103, the SPI component reads and verifies the data of the third slave chip; in response to the SPI master signal, it detects the SPI commands and addresses, and if an illegal command or illegal address is detected, it prevents the command from being sent to the third slave chip; S104, the I²C component reads and verifies the data of the fourth slave chip; in response to the I²C master device signal, it detects the commands and addresses of the I²C, and if an illegal command or illegal address is detected, it prevents the command from being sent to the fourth slave chip; S105, the internal selection switch matrix routes at least one of the first SPI output signal, the second SPI output signal, the first I²C output signal, the second I²C output signal, the SPI master signal, and the I²C master signal to the third slave chip or the fourth slave chip.

[0046] The internal selection switch matrix integrates a control logic unit.

[0047] In some embodiments of this application, the specific process of routing to the third slave chip includes: a control logic unit generating a control signal; when the control signal indicates that a first-level selection operation is performed using a first SPI multiplexer, the control logic unit selects an intermediate SPI signal between a first SPI output signal output by the SPI master mode module and a second SPI output signal output by the SPI communication monitoring unit; or, when the control signal indicates that a second-level selection operation is performed using a second SPI multiplexer, the control logic unit selects an SPI master device signal from the input interface group through the SPI pass-through mode module; when the SPI master device signal is selected, the control logic unit constructs an SPI pass-through path and sends the SPI master device signal to the second SPI multiplexer; or, when an intermediate SPI signal is selected, an SPI processing path is constructed and the intermediate SPI signal is sent to the second SPI multiplexer; the control logic unit sends the intermediate SPI signal or the SPI master device signal to the third slave chip through the second SPI multiplexer.

[0048] In some embodiments of this application, the specific process of routing to the fourth slave chip includes: a control logic unit generating a control signal; when the control signal indicates that a first-level selection operation is performed using a first I²C multiplexer, the control logic unit selects an intermediate I²C signal between the first I²C output signal output by the I²C master mode module and the second I²C output signal output by the I²C communication monitoring unit; or, when the control signal indicates that a second-level selection operation is performed using a second I²C multiplexer, the control logic unit selects an I²C master device signal from the first master control chip through the I²C pass-through mode module; when the I²C master device signal is selected, the control logic unit constructs an I²C direct path and sends the I²C master device signal to the second I²C multiplexer; or, when an intermediate I²C signal is selected, an I²C processing path is constructed and the intermediate I²C signal is sent to the second I²C multiplexer; the control logic unit sends the intermediate I²C signal or the I²C master device signal to the fourth slave chip through the second I²C multiplexer.

[0049] Specifically, the process of generating control signals includes: receiving routing configuration information from the first master control chip, the routing configuration information including a desired communication mode identifier and a timing parameter identifier, the desired communication mode identifier including at least pass-through mode, master mode conversion, and communication monitoring mode conversion; generating an independent hierarchical control word for each communication channel, the hierarchical control word including a first-level selection bit and a second-level selection bit; when the desired communication mode identifier is pass-through mode, setting the second-level selection bit to an active level to instruct the second SPI multiplexer or the second I²C multiplexer to select the SPI master device signal from the input interface group or the I²C master device signal from the first master control chip through the SPI pass-through mode module or the I²C pass-through mode module, and shielding the output influence of the first-level selection bit; or, when the desired communication mode identifier is master mode conversion or communication monitoring mode conversion, setting the second-level... The selection bit is set to an invalid level to instruct the second SPI multiplexer or the second I²C multiplexer to select the output signal from the first multiplexer; when switching to master mode, the first-level selection bit is set to an active level to select the output of the SPI master mode module or the I²C master mode module; when switching to communication monitoring mode, the first-level selection bit is set to an active level to select the output of the SPI communication monitoring unit or the I²C communication monitoring unit; the set first-level selection bit is converted into a first control signal and sent to the selection control terminal of the corresponding first multiplexer; the set second-level selection bit is converted into a second control signal and sent to the selection control terminal of the corresponding second multiplexer; wherein, the first control signal and the second control signal are independently controllable, so that the SPI path to the third slave chip and the communication path to the fourth slave chip can be in different communication modes in parallel.

[0050] In this embodiment, on the one hand, by directly integrating the internal selection switch matrix (containing multiple multiplexers) into the second intermediate bridge chip, the independent components that originally required external connections are internalized as chip logic modules. This not only significantly reduces the physical space occupied by the PCB and lowers hardware material costs, but also eliminates the cumbersome external interconnection traces between chips, simplifying PCB design and effectively improving the overall integration and compactness of the multi-chip secure communication system, while also enhancing communication reliability. On the other hand, by using the internal selection switch matrix integrated into the second intermediate bridge chip to directly control the signal paths to the third and fourth slave chips, the originally lengthy board-level transmission paths are shortened to micron-level interconnections within the chip. This greatly reduces the chance of signals being exposed to external noise and eliminates the impedance caused by multiple connection points, thereby significantly enhancing the signal's anti-interference capability, reducing the risk of signal attenuation, and ensuring high reliability and high bandwidth performance for high-speed communication between multiple chips.

[0051] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program for multi-chip secure communication can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium for multi-chip secure communication can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0052] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A multi-chip secure communication system, characterized in that, The system includes: A first master control chip, at least one target slave chip, and a second intermediate bridge chip, wherein the second intermediate bridge chip is electrically connected to the first master control chip and each target slave chip; wherein the at least one target slave chip includes a third slave chip and a fourth slave chip; The second intermediate bridge chip integrates an input interface group, an SPI component, an I²C component, and an internal selection switch matrix; wherein, the input interface group includes an SPI input interface and an I²C input interface; One end of the SPI input interface is connected to the SPI component, and one end of the I²C input interface is connected to the I²C component. The other ends of the SPI input interface and the I²C input interface are connected to the first master control chip. One end of the internal selection switch matrix is ​​connected to the output terminals of the SPI component, the I²C component, the SPI input interface, and the first master control chip, respectively, and the other end is connected to the target slave chip. The internal selection switch matrix includes multiple multiplexers, which are used to control the signal paths to the third slave chip and the fourth slave chip, respectively.

2. The multi-chip secure communication system according to claim 1, characterized in that, The first master control chip is used to access the data of the third slave chip and the data of the fourth slave chip to generate SPI master device signal and I²C master device signal; The input interface group is used to receive SPI master device signals and I²C master device signals from the first master control chip; The SPI component is used to read and verify the data of the third slave chip; In response to the SPI master device signal, the SPI commands and addresses are detected. If an illegal command or illegal address is detected, the command will be prevented from being sent to the third slave chip. The I²C component is used to read and verify the data of the fourth slave chip; In response to the I²C master device signal, the I²C commands and addresses are detected. If an illegal command or illegal address is detected, the command will be prevented from being sent to the fourth slave chip. The internal selection switch matrix is ​​used to route at least one of the first SPI output signal, the second SPI output signal generated by the SPI component, the first I²C output signal, the second I²C output signal generated by the I²C component, the SPI master signal, and the I²C master signal to the third slave chip or the fourth slave chip.

3. The multi-chip secure communication system according to claim 2, characterized in that, The SPI component includes an SPI master mode module, an SPI communication monitoring unit, and an SPI transparent transmission mode module; The SPI master mode module is used to read and verify the data of the third slave chip; The SPI communication monitoring unit is used to respond to the SPI master device signal and detect the SPI commands and addresses when the first master control chip accesses data to the third slave chip through the SPI input interface. If an illegal command or illegal address is detected, the command to be prohibited from being sent to the third slave chip will be blocked. The SPI transparent transmission mode module is used to realize transparent communication between the first master control chip and the third slave chip. The internal selection switch matrix includes a first SPI multiplexer and a second SPI multiplexer; The first input terminal of the first SPI multiplexer is connected to the output of the SPI master mode module, and the second input terminal of the first SPI multiplexer is connected to the output of the SPI communication monitoring unit; The output of the first SPI multiplexer is set as the first SPI output port, and the first SPI output port is connected to the first input of the second SPI multiplexer.

4. The multi-chip secure communication system according to claim 3, characterized in that, The first input terminal of the second SPI multiplexer is connected to the input interface group through the SPI pass-through mode module, so that the SPI master device signal from the first master control chip is input to the second SPI multiplexer as a candidate signal without being processed by the SPI component. The second input terminal of the second SPI multiplexer is connected to the output terminal of the first SPI multiplexer; The output of the second SPI multiplexer forms the second SPI output port, which is connected to the input of the third slave chip.

5. A multi-chip secure communication system according to claim 2, characterized in that, The I²C component includes an I²C main mode module, an I²C communication monitoring unit, and an I²C transparent transmission mode module; The I²C master mode module is used to read and verify the data of the fourth slave chip; The I²C communication monitoring unit is used to detect I²C commands and addresses when the first master control chip accesses data to the fourth slave chip through the I²C input interface, and to prohibit the sending of commands to the fourth slave chip if illegal commands and illegal addresses are detected. The I²C transparent transmission mode module is used to realize transparent transmission communication between the first master control chip and the fourth slave chip; The internal selection switch matrix includes a first I²C multiplexer and a second I²C multiplexer; The first input terminal of the first I²C multiplexer is connected to the output of the I²C master mode module, and the second input terminal of the first I²C multiplexer is connected to the output of the I²C communication monitoring unit; The output of the first I²C multiplexer is set as the first I²C output port, and the first I²C output port is connected to the first input of the second I²C multiplexer.

6. A multi-chip secure communication system according to claim 5, characterized in that, The first input terminal of the second I²C multiplexer is connected to the input interface group through the I²C transparent mode module, so that the I²C master device signal from the first master control chip can be input to the second I²C multiplexer as a candidate signal without passing through the I²C component. The second input terminal of the second I²C multiplexer is connected to the output terminal of the first I²C multiplexer; The output of the second I²C multiplexer constitutes the second I²C output port, which is connected to the input of the fourth slave chip.

7. A multi-chip secure communication system according to claim 4, characterized in that, The internal selection switch matrix integrates a control logic unit; Routing to the third slave chip includes: The control logic unit generates control signals; When the control signal indicates that a first-level selection operation is performed using the first SPI multiplexer, the control logic unit selects an intermediate SPI signal between the first SPI output signal output by the SPI master mode module and the second SPI output signal output by the SPI communication monitoring unit; or, when the control signal indicates that a second-level selection operation is performed using the second SPI multiplexer, the control logic unit selects the SPI master device signal from the input interface group through the SPI pass-through mode module. When the SPI master signal is selected, the control logic unit constructs an SPI pass-through path and sends the SPI master signal to the second SPI multiplexer; or, when the intermediate SPI signal is selected, it constructs an SPI processing path and sends the intermediate SPI signal to the second SPI multiplexer. The control logic unit sends the intermediate SPI signal or the SPI master signal to the third slave chip through the second SPI multiplexer.

8. A multi-chip secure communication system according to claim 6, characterized in that, The internal selection switch matrix integrates a control logic unit; The routing to the fourth slave chip includes: The control logic unit generates control signals; When the control signal indicates that a first-level selection operation is performed using the first I²C multiplexer, the control logic unit selects an intermediate I²C signal between the first I²C output signal output by the I²C master mode module and the second I²C output signal output by the I²C communication monitoring unit; or, when the control signal indicates that a second-level selection operation is performed using the second I²C multiplexer, the control logic unit selects the I²C master device signal from the first master control chip through the I²C transparent transmission mode module. When the I²C master device signal is selected, the control logic unit constructs an I²C direct path and sends the I²C master device signal to the second I²C multiplexer; or, when the intermediate I²C signal is selected, it constructs an I²C processing path and sends the intermediate I²C signal to the second I²C multiplexer. The control logic unit sends the intermediate I²C signal or the I²C master device signal to the fourth slave chip through the second I²C multiplexer.

9. A multi-chip secure communication system according to claim 7 or 8, characterized in that, The generation control signal includes: The system receives routing configuration information from the first main control chip. The routing configuration information includes a desired communication mode identifier and a timing parameter identifier. The desired communication mode identifier includes at least a pass-through mode, a main mode switch, and a communication monitoring mode switch. An independent hierarchical control word is generated for each communication channel. The hierarchical control word includes a first-level selection bit and a second-level selection bit. When the desired communication mode is identified as the pass-through mode, the second-level selection bit is set to an active level to instruct the second SPI multiplexer or the second I²C multiplexer to select the SPI master device signal from the input interface group or the I²C master device signal from the first master control chip through the SPI pass-through mode module or the I²C pass-through mode module, and to shield the output influence of the first-level selection bit; or, when the desired communication mode is identified as the master mode conversion or communication monitoring mode conversion, the second-level selection bit is set to an inactive level to instruct the second SPI multiplexer or the second I²C multiplexer to select the output signal from the first multiplexer; When switching to the master mode, the first-level selection bit is set to an active level to select the output of the SPI master mode module or the I²C master mode module; when switching to the communication monitoring mode, the first-level selection bit is set to an active level to select the output of the SPI communication monitoring unit or the I²C communication monitoring unit. The configured first-level selection bit is converted into a first control signal and sent to the selection control terminal of the corresponding first multiplexer. The configured second-level selection bit is converted into a second control signal and sent to the selection control terminal of the corresponding second multiplexer. The first control signal and the second control signal are independently controllable, enabling the SPI path to the third slave chip and the communication path to the fourth slave chip to operate in different communication modes in parallel.

10. A multi-chip secure communication method implemented using the system according to any one of claims 1-9, characterized in that, The method includes: The first master control chip accesses the data of the third slave chip and the data of the fourth slave chip to generate SPI master device signal and I²C master device signal; The input interface group receives SPI master device signals and I²C master device signals from the first master control chip; The SPI component reads and verifies the data of the third slave chip; in response to the SPI master signal, it detects the SPI commands and addresses, and if an illegal command or illegal address is detected, it prevents the command from being sent to the third slave chip. The I²C component reads and verifies the data of the fourth slave chip; in response to the I²C master device signal, it detects the commands and addresses of the I²C, and if an illegal command or illegal address is detected, it will prevent the command from being sent to the fourth slave chip. The internal selection switch matrix routes at least one of the first SPI output signal, the second SPI output signal generated by the SPI component, the first I²C output signal, the second I²C output signal generated by the I²C component, the SPI master signal, and the I²C master signal to the third slave chip or the fourth slave chip.

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