Sealing chip, control method thereof, application and electronic device

Abstract

This application relates to the field of integrated circuits and advanced packaging technology, and provides a co-packaged chip and its control method, application, and electronic device. The co-packaged chip includes: a first chip, which includes a first interconnect module; and a second chip, which includes a second interconnect module. The first and second interconnect modules have at least one set of identical interconnect interfaces, and the first and second chips are co-packaged and connected through these interconnect interfaces. The first chip is used to collect data from a sensing module and / or a perception module, encrypt the data, and transmit the encrypted data to the second chip through the first interconnect module. The second chip is used to decrypt the encrypted data, perform artificial intelligence inference operations on the decrypted data, and encrypt the inference result before transmitting it back to the first chip through the second interconnect module. This enables decoupling of the first and second chips, meeting the requirements for rapid combination and matching in diverse end-side application scenarios.

Description

Technical Field

[0001] This application relates to the fields of integrated circuits and advanced packaging technology, specifically to a co-packaged chip and its control method, application, and electronic equipment. Background Technology

[0002] With the deep integration of IoT and AI technologies, smart applications have permeated a wide range of fields, including smart homes, smart meters, health measurement, battery management systems, and predictive maintenance in industry. These edge scenarios place extreme demands on devices' real-time response, data privacy and security, and energy efficiency, driving AI computing tasks to move from the cloud to terminal devices. However, the core control unit serving these scenarios—the traditional microcontroller (MCU)—has inherent architectural bottlenecks. Most deployed MCUs were not designed with a dedicated AI acceleration unit, and their core computing power is insufficient to efficiently support the inference tasks of complex AI models such as modern neural networks. Redesigning and tape-out a new system-on-a-chip (SoC) integrating an AI acceleration unit for such scenarios would face severe challenges such as long development cycles and high one-time engineering costs, especially failing to meet the urgent market demands for rapid iteration and cost control. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide a packaged chip and its control method, application and electronic device to solve the above technical problems.

[0004] In a first aspect, embodiments of this application provide a packaged chip, comprising: A first chip, the first chip including a first interconnect module; The second core chip includes a second interconnect module; The first interconnect module and the second interconnect module have at least one set of identical interconnect interfaces, and the first core and the second core are connected in a sealed manner through the interconnect interfaces; The first chip is used to collect data from the sensing module and / or perception module, encrypt the data, and transmit the encrypted data to the second chip through the first interconnect module. The second chip is used to decrypt the encrypted data, perform artificial intelligence inference operations on the decrypted data, encrypt the inference results, and send them back to the first chip through the second interconnect module. This enables the decoupling of the first and second chips, allowing for rapid combination and matching of various edge application scenarios. The first and second interconnect modules enable "plug-and-play" AI function upgrades, avoiding the need for complete system-level chip fabrication for each AI application, reducing costs, and shortening the development cycle.

[0005] Secondly, embodiments of this application also provide a control method for a packaged chip, comprising: When the first chip collects data from the sensing module and / or perception module, the first chip calls the first information security module to encrypt the data, and transmits the encrypted data to the second chip through the first interconnection module. When the second core receives the encrypted data, it calls the second information security module to decrypt the encrypted data, calls the neural network processing module to perform artificial intelligence inference operations on the decrypted data, and calls the second information security module to encrypt the inference result. The encrypted inference result is then sent back to the first core through the second interconnection module. This enables collaborative interaction and real-time control between the first and second cores. At the same time, with the help of the high parallel AI computing power of the second core, heterogeneous decoupling and efficient collaboration of "control and intelligence" are achieved.

[0006] Thirdly, embodiments of this application also provide an electronic device, including a device body and the aforementioned encapsulated chip disposed on the device body.

[0007] Fourthly, embodiments of this application also provide a packaged chip as described above, which is used for battery power monitoring in electronic devices.

[0008] Fifthly, embodiments of this application also provide a packaged chip as described above, which is used for fault prediction / detection in an industrial environment.

[0009] Sixthly, embodiments of this application also provide a packaged chip as described above, the packaged chip being used for health measurement.

[0010] The co-packaged chip provided in this application embodiment includes: a first chip, the first chip including a first interconnect module; and a second chip, the second chip including a second interconnect module; the first interconnect module and the second interconnect module have at least one set of identical interconnect interfaces, and the first chip and the second chip are co-packaged and connected through the interconnect interfaces; the first chip is used to collect data from a sensing module and / or a perception module, encrypt the data, and transmit the encrypted data to the second chip through the first interconnect module; the second chip is used to decrypt the encrypted data, perform artificial intelligence inference operations on the decrypted data, encrypt the inference results, and transmit them back to the first chip through the second interconnect module. This enables the decoupling of the first chip and the second chip, meets the requirements for rapid combination and matching of diverse edge application scenarios, and achieves "plug-and-play" AI function upgrades through the first interconnect module and the second interconnect module. This solves the problem of poor flexibility of traditional single-chip integration solutions, which cannot quickly adapt to the differentiated requirements of computing power and power consumption in different edge scenarios. At the same time, it avoids the need for complete system-level chip tape-out for each AI application, thereby reducing costs and shortening the development cycle.

[0011] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic diagram of the architecture of the encapsulated chip provided in an embodiment of this application is shown.

[0014] Figure 2 A schematic diagram of the architecture of the first chip provided in an embodiment of this application is shown.

[0015] Figure 3 A schematic diagram of the architecture of a first chip provided in another embodiment of this application is shown.

[0016] Figure 4 A schematic diagram of the architecture of the second core provided in an embodiment of this application is shown.

[0017] Figure 5 A flowchart illustrating the control method for a co-packaged chip provided in an embodiment of this application is shown.

[0018] Figure 6 A flowchart illustrating a control method for a co-packaged chip according to another embodiment of this application is shown. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0022] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0023] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0024] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0025] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0026] Most traditional microcontrollers are not designed with a dedicated AI acceleration unit, and their core computing power is insufficient to efficiently support the inference tasks of complex AI models such as modern neural networks. If a completely new system-on-a-chip with an integrated AI acceleration unit is redesigned and fabricated for such scenarios, the design and fabrication verification cycle will be as long as 12-18 months, which is extremely costly and unsuitable for the fragmented IoT market, especially failing to meet the urgent needs of rapid market iteration and cost control.

[0027] Existing solutions involve running pure software AI models on general-purpose microcontrollers, but this approach suffers from low computational efficiency and cannot meet the real-time requirements of many scenarios. While there are explorations into heterogeneous integration of different functional modules using Chiplet technology, traditional single-chip integration solutions lack flexibility and cannot quickly adapt to the varying computing power and power consumption demands of different edge scenarios. Therefore, designing a dedicated AI accelerator Chiplet solution that can flexibly adapt to these diverse edge scenarios, achieve efficient and standardized integration with the vast and diverse traditional microcontrollers on the market, and significantly reduce R&D costs and time remains a critical technical challenge that the industry urgently needs to address.

[0028] like Figure 1 As shown, Figure 1 The schematic illustration shows a packaged chip 100 provided in an embodiment of this application. The packaged chip 100 includes a first chip 10 and a second chip 20. The first chip 10 includes a first interconnect module 101, and the second chip 20 includes a second interconnect module 201. The first interconnect module 101 and the second interconnect module 201 have at least one set of identical interconnect interfaces. The first chip 10 and the second chip 20 are packaged and connected through the interconnect interfaces.

[0029] The encapsulation connection can be understood as the interconnection of data and control paths between the first chip 10 and the second chip 20 through an interconnection interface. At the same time, the first chip 10 and the second chip 20 are physically encapsulated using advanced packaging technology. Advanced packaging technology, such as silicon interposer and microbumps, physically encapsulates the first chip 10 and the second chip 20 at high density to form a complete heterogeneous architecture.

[0030] In this embodiment, the first chip 10 integrates a first interconnect module 101, which is responsible for connecting with external sensing modules and / or perception modules, and performing data encryption and task scheduling on-chip. The second chip 20 integrates a second interconnect module 201, which is used for artificial intelligence inference operations and result feedback. Specifically, the first chip 10 is used to collect data from the sensing modules and / or perception modules, encrypt the data, and transmit the encrypted data to the second chip 20 through the first interconnect module 101. The second chip 20 is used to decrypt the encrypted data, perform artificial intelligence inference operations on the decrypted data, and encrypt the inference result before transmitting it back to the first chip 10 through the second interconnect module 201.

[0031] Through the above methods, the embodiments of this application enable the first chip 10 (such as a traditional microcontroller) to quickly acquire edge AI capabilities by integrating the second chip 20 without undergoing complex redesign and tape-out, greatly shortening the product development cycle and reducing development costs. Furthermore, the decoupling of the first chip 10 and the second chip 20 allows for rapid combination and matching across diverse edge application scenarios. The first interconnect module 101 and the second interconnect module 201 achieve "plug-and-play" AI function upgrades, solving the problem of poor flexibility in traditional single-chip integration solutions, which cannot quickly adapt to the differentiated computing power and power consumption requirements of different edge scenarios.

[0032] As one embodiment, the first interconnect module 101 includes at least one of a USB interface, an SPI interface, and a QSPI interface; the second interconnect module 201 includes at least one of a USB interface, an SPI interface, and a QSPI interface. The SPI interface includes three signal lines: SCLK, MOSI, and MISO; the QSPI interface includes five signal lines: SCLK and DAT0~DAT3; and the USB interface includes two differential signal lines: DP and DN. Because the USB, SPI, and QSPI interfaces have fewer interface signals, fewer connections are required in the package, thereby reducing packaging and testing costs and increasing yield. The first interconnect module 101 and the second interconnect module 201 are compatible with USB, SPI, and QSPI interfaces, adapting to various application scenarios.

[0033] When the first core 10 and the second core 20 are sealed together, they are directly connected through the same type of interface. For example, the second interconnect module 201 includes three interfaces: USB interface, SPI interface, and QSPI interface. The first interconnect module 101 only has a USB interface, SPI interface, or QSPI interface. Then, the first core 10 and the second core 20 select the interface supported by both for direct connection. If both the first interconnect module 101 and the second interconnect module 201 have SPI interfaces, the SPI interface is preferred for direct connection. If both the first interconnect module 101 and the second interconnect module 201 have QSPI interfaces, the QSPI interface is preferred for direct connection. If both the first interconnect module 101 and the second interconnect module 201 have USB interfaces, the USB interface is preferred for direct connection.

[0034] As one example, please refer to Figure 2The first chip 10 includes a first bus 102, a first processing module 103, an access control module 104, a first information security module 105, and a first storage module 106, all connected to the first bus 102. A first interconnect module 101 is connected to the first bus 102. The first bus 102 serves as the on-chip module interconnect backbone, such as an AMBAAHB / AXI bus or a custom high-speed bus. The first processing module 103 can be a low-power control CPU, such as an ARM Cortex-M series or RISC-V, responsible for firmware operation, task scheduling, and data preprocessing. The access control module 104 manages the access permissions and task priorities of each peripheral device and the first storage module 106. The first information security module 105 can integrate an AES / SM4 encryption engine, SHA hash, TRNG, or a key management unit (KMU) for data encryption, integrity verification, and tamper protection. The first storage module 106 includes non-volatile memory (NVM) and static random access memory (SRAM). The non-volatile memory, such as Flash / eFlash, is used to store boot code and configuration parameters. Static random access memory is used for runtime data caching. The first interconnect module 101 is connected to the first bus 102 and controlled by the first processing module 103 to realize high-speed data and control interaction with the second core 20.

[0035] As one example, please refer to Figure 3 The first core 10 also includes a first interface module 107 and a second interface module 108, respectively connected to the first bus 102. The first interface module 107 is used to connect to the sensing module, and the second interface module 108 is used to connect to the perception module. Both the first interface module 107 and the second interface module 108 are connected to the first bus 102 and are uniformly scheduled by the first processing module 103 to realize a closed loop from physical world perception to AI inference result feedback. The first interface module 107 is used to acquire raw data (such as temperature, image, sound, etc.) from the sensing module, including an ADC interface, a DCMI interface, and... / PCM interface. The second interface module 108 is used to implement user input to the system and system output to the user (such as displaying inference results, voice prompts, light indicators, etc.), including interface, Interfaces, DCMI interface. Sensing modules include, but are not limited to, temperature, pressure, current, optical, image, and sound sensors. Perception modules include, but are not limited to, cameras, microphones, displays, touchscreens, and LEDs.

[0036] As one example, please refer to Figure 4The second chip 20 includes a second bus 202, a second processing module 203, a neural network processing module 204, a second information security module 205, and a second storage module 206, all connected to the second bus 202. A second interconnect module 201 is connected to the second bus 202. The second bus 202 serves as the on-chip module interconnect backbone, such as an AMBA, AHB / AXI, or a custom high-speed bus. The second processing module 203 can be a low-power control CPU, responsible for system initialization, task management, and security monitoring. The neural network processing module 204 (such as an NPU core) has artificial intelligence inference computing capabilities, specifically for accelerating inference of models such as CNN, RNN, and Transformer. The second information security module 205 has functions such as decryption, tamper-proofing of the inference process, and encryption of inference results, working in conjunction with the first information security module 105 of the first chip 10 to achieve end-to-end data protection. The second storage module 206 includes non-volatile memory (NVM) and static random access memory (SRAM). The non-volatile memory, such as Flash / eFlash, is used to store models and weights. Static random access memory (SRAM) serves as an input / output buffer, used to store intermediate activation values. The second interconnect module 201 is connected to the second bus 202 and is responsible for interacting with the encrypted data and control commands of the first chip 10.

[0037] The co-packaged chip 100 of this application embodiment is a heterogeneous integrated chip. By co-packing a first chip 10 and a second chip 20 within a single package, it achieves the integration of traditional control functions and AI inference functions. It can be applied to scenarios such as intelligent battery management systems, smart meters, smart homes, health measurement, and industrial predictive maintenance. For example, in a battery power monitoring scenario, the first chip 10 and the second chip 20 are interconnected via an SPI interface, and the first chip 10 is connected to a battery pack sensor via an ADC interface. In a fault prediction / detection scenario in an industrial environment, the first chip 10 and the second chip 20 are interconnected via an SPI interface, and the first chip 10 is connected to an environmental detection sensor via an ADC interface. In a health measurement scenario, the first chip 10 and the second chip 20 are interconnected via an SPI interface, and the first chip 10 is connected to an analog front-end via an SPI interface.

[0038] like Figure 5 As shown, Figure 5 The control method for the encapsulated chip 100 provided in an embodiment of this application is illustrated schematically. The control method includes: Step S10: When the first chip acquires data from the sensing module and / or perception module, the first chip calls the first information security module to encrypt the data and transmits the encrypted data to the second chip through the first interconnection module.

[0039] In this step, the first chip collects data from the sensing module through the first interface module and data from the perception module through the second interface module. The sensing module includes, but is not limited to, sensors for temperature, pressure, current, optics, image, and sound. The perception module includes, but is not limited to, cameras, microphones, displays, touchscreens, and LEDs.

[0040] In one embodiment, when the first chip acquires data from the sensing module, the first chip invokes the first information security module to encrypt the data and transmits the encrypted data to the second chip via the first interconnect module. In another embodiment, when the first chip acquires data from the sensing module, the first chip invokes the first information security module to encrypt the data and transmits the encrypted data to the second chip via the first interconnect module. In yet another embodiment, when the first chip acquires data from both the sensing module and the sensing module, the first chip invokes the first information security module to encrypt the data and transmits the encrypted data to the second chip via the first interconnect module.

[0041] The specific implementation methods of the first information security module and the first interconnection module have been described in detail in the architecture section above, and will not be repeated here. For example, when the first processing module enters a low-power standby state, it monitors the status registers of the first interface module and / or the second interface module through polling or interruption. When data input is detected, the first processing module is immediately woken up and executes the data preprocessing process. The first processing module continues to call the first information security module to encrypt the input data in real time, generate ciphertext data packets, and then transmit the ciphertext data packets to the second chip through the first interconnection module.

[0042] Step S20: When the second core receives encrypted data, the second core calls the second information security module to decrypt the encrypted data, calls the neural network processing module to perform artificial intelligence inference operations on the decrypted data, and calls the second information security module to encrypt the inference result. The encrypted inference result is then sent back to the first core through the second interconnection module.

[0043] In this step, the second core receives encrypted data through the second interconnect module, the second information security module decrypts the encrypted data, and the second processing module sends the decrypted data to the neural network processing module to perform artificial intelligence inference. After the inference is completed, the second information security module encrypts the inference result and sends it back to the first core through the second interconnect module. The neural network processing module (such as an NPU core) has artificial intelligence inference computing capabilities and is specifically designed to accelerate the inference of models such as CNN, RNN, and Transformer.

[0044] The control method of the above-mentioned co-packaged chip enables collaborative interaction and real-time control between the first chip and the second chip. At the same time, with the help of the high parallel AI computing power of the second chip, heterogeneous decoupling and efficient collaboration of "control and intelligence" are achieved.

[0045] As one embodiment, in step S10, after the first core calls the first information security module to encrypt the data and transmits the encrypted data to the second core through the first interconnect module, the method further includes: the first core generates an instruction to start the second core through the first processing module and sends it to the second core through the first interconnect module; in step S20, after the second core calls the second information security module to decrypt the encrypted data and before calling the neural network processing module to perform artificial intelligence inference operations on the decrypted data, the method further includes: the second core receives the instruction from the second interconnect module, parses the instruction through the second processing module, configures the operating parameters of the neural network processing module according to the parsing result, and prompts the neural network processing module to enter the inference execution state.

[0046] The instructions include information such as model ID and input / output addresses. Operating parameters include accuracy, weight compression, and layer fusion. This embodiment enables on-demand triggering of AI inference through task collaboration between the first and second core particles.

[0047] As one embodiment, in step S20, after the second chip calls the second information security module to decrypt the encrypted data, the method further includes: the second processing module writes the decrypted data into the first storage area in the second storage module, and the first storage area is pre-configured as the input buffer of the neural network processing module; after the neural network processing module performs artificial intelligence inference operations on the decrypted data, the method further includes: the neural network processing module writes the inference result into the second storage area in the second storage module, and the second storage area is pre-configured as the output buffer of the neural network processing module.

[0048] In this embodiment, the first storage area and the second storage area are physically or logically isolated to avoid read / write conflicts and improve parallel access efficiency.

[0049] As one embodiment, in step S20, before the second chip calls the second information security module to decrypt the encrypted data, the method further includes: after the second chip is powered on, the second processing module loads the startup code from the second storage module and performs an initialization operation, which includes: initializing the second interconnect module, the second information security module, configuring the neural network processing module, and the second storage module.

[0050] In this step, initializing the second interconnect module includes matching the interface protocol of the first chip; initializing the second information security module includes loading the key and verifying the firmware signature; configuring the neural network processing module includes configuring the calculation accuracy, weight compression mode, layer fusion strategy, etc.; configuring the second storage module includes preloading commonly used activation values ​​from NVM to a fixed area of ​​SRAM to reduce dynamic loading latency during inference, and dividing the second storage module into a first storage area and a second storage area.

[0051] As one embodiment, in step S10, before the first chip acquires data from the sensing module and / or perception module, the process further includes, after the first chip is powered on, executing a program from the first storage module through the first processing module to initialize the first interconnect module, the first interface module, and the second interface module.

[0052] In this step, after the first chip powers on, the first processing module reads the boot code from non-volatile memory (NVM, such as eFlash) and executes the interconnect interface (such as SPI / QSPI / USB) controller initialization program, including: configuring the interface operating mode, setting DMA channel mapping and interrupt priority, and enabling hardware CRC check and timeout detection mechanisms; the first processing module continues to execute the initialization program, configuring the ADC, DCMI, and... Interfaces include: setting ADC sampling rate, resolution, channel scan order, and trigger source (such as timer trigger); configuring DCMI timing parameters to match the camera output format; and initialization. Master clock and data alignment mode, adapted to digital microphone sampling rate.

[0053] For example, such as Figure 6As shown, the specific workflow of the first chip is as follows: Step S11: The first chip is powered on and started; Step S12: The first processing module initializes the first interconnect module from the NVM execution program; Step S13: The first processing module initializes the first interface module and the second interface module from the NVM execution program; Step S14: The first processing module detects data input; Step S15: The first processing module calls the first information security module to encrypt the data and then transmits it to the second chip through the first interconnect module; Step S16: The first processing module generates an instruction to start the second chip and sends it to the second chip through the first interconnect module; Step S17: The first processing module enters a low-power mode or continues to execute other tasks; Step S18: The first processing module reads the inference result sent by the second chip and completes the corresponding operation. The specific workflow of the second chip is as follows: Step S21: The second chip is powered on and started; Step S22: The second processing module initializes the second interconnect module from the NVM execution program; Step S23: The second processing module initializes the second information security module from the NVM execution program; Step S24: The second processing module configures the neural network processing module from the NVM execution program; Step S25: The second processing module preloads commonly used activation values ​​from the NVM to a fixed area of ​​SRAM from the NVM execution program, and divides the SRAM into a first storage area and a second storage area; Step S26: The second chip enters a sleep waiting state; Step S27: When the second processing module receives encrypted data, it calls the second information security module to decrypt it and writes the decrypted data into the first storage area; Step S28: When the second processing module receives an instruction from the second interconnect module, it starts the neural network processing module; Step S29: The neural network processing module performs AI inference from the NVM and processes the decrypted data; Step S30: The neural network processing module writes the inference result into the second storage area; Step S31: The neural network processing module notifies the second processing module that the inference is complete and the inference result is stored in the second storage area; Step S32: The second processing module transmits the inference result to the first chip through the second interconnect module.

[0054] This application also provides an electronic device, which includes a device body and a packaged chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. This electronic device, through the decoupling of the first and second chips, meets the requirements for rapid combination and matching of diverse edge application scenarios. It achieves "plug-and-play" AI function upgrades through the first and second interconnect modules, solving the problem of poor flexibility of traditional single-chip integration solutions and their inability to quickly adapt to the different computing power and power consumption requirements of different edge scenarios. This allows the first chip (such as a traditional microcontroller) to quickly obtain edge AI capabilities by integrating the second chip without undergoing complex redesign and tape-out, greatly shortening the product development cycle and reducing development costs.

[0055] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A co-packaged chip, characterized in that, include: A first chip, the first chip including a first interconnect module; The second core chip includes a second interconnect module; The first interconnect module and the second interconnect module have at least one set of identical interconnect interfaces, and the first core and the second core are connected in a sealed manner through the interconnect interfaces; The first chip is used to collect data from the sensing module and / or perception module, encrypt the data, and transmit the encrypted data to the second chip through the first interconnect module; the second chip is used to decrypt the encrypted data, perform artificial intelligence inference operations on the decrypted data, encrypt the inference results, and send them back to the first chip through the second interconnect module.

2. The encapsulated chip as described in claim 1, characterized in that, The first interconnect module includes at least one of a USB interface, an SPI interface, and a QSPI interface; the second interconnect module includes at least one of a USB interface, an SPI interface, and a QSPI interface.

3. The encapsulated chip as described in claim 1, characterized in that, The first chip includes a first bus, a first processing module, an access control module, a first information security module, and a first storage module, all connected to the first bus. The first interconnect module is connected to the first bus.

4. The packaged chip as described in claim 3, characterized in that, The first chip also includes a first interface module and a second interface module that are respectively connected to the first bus. The first interface module is used to connect to the sensing module, and the second interface module is used to connect to the perception module.

5. The encapsulated chip as described in claim 1, characterized in that, The second chip includes a second bus, a second processing module, a neural network processing module, a second information security module, and a second storage module, all connected to the second bus. The second interconnect module is connected to the second bus.

6. A control method for a packaged chip as described in any one of claims 1-5, characterized in that, include: When the first chip collects data from the sensing module and / or perception module, the first chip calls the first information security module to encrypt the data, and transmits the encrypted data to the second chip through the first interconnection module. When the second core receives the encrypted data, the second core calls the second information security module to decrypt the encrypted data, calls the neural network processing module to perform artificial intelligence inference operations on the decrypted data, calls the second information security module to encrypt the inference result, and sends the encrypted inference result back to the first core through the second interconnection module.

7. The control method for a packaged chip as described in claim 6, characterized in that, After the first core calls the first information security module to encrypt the data and transmits the encrypted data to the second core through the first interconnect module, the process further includes: the first core generating an instruction to start the second core through the first processing module and sending it to the second core through the first interconnect module; After the second core calls the second information security module to decrypt the encrypted data and before calling the neural network processing module to perform artificial intelligence inference operations on the decrypted data, the process further includes: the second core receiving the instruction from the second interconnect module, parsing the instruction through the second processing module, configuring the operating parameters of the neural network processing module according to the parsing result, and prompting the neural network processing module to enter the inference execution state.

8. The control method for a co-packaged chip as described in claim 7, characterized in that, After the second chip calls the second information security module to decrypt the encrypted data, the process further includes: the second processing module writes the decrypted data into a first storage area in the second storage module, wherein the first storage area is pre-configured as the input buffer of the neural network processing module; After the neural network processing module performs artificial intelligence inference operations on the decrypted data, the method further includes: the neural network processing module writes the inference result into the second storage area in the second storage module, and the second storage area is pre-configured as the output buffer of the neural network processing module.

9. The control method for a co-packaged chip as described in claim 8, characterized in that, Before the second chip calls the second information security module to decrypt the encrypted data, the process further includes: after the second chip is powered on, the second processing module loads the startup code from the second storage module and performs an initialization operation, which includes: initializing the second interconnect module, the second information security module, configuring the neural network processing module, and the second storage module.

10. An electronic device, characterized in that, It includes a device body and a packaged chip as described in any one of claims 1-5 disposed on the device body.

11. A packaged chip as described in any one of claims 1-5, the packaged chip being used for battery power monitoring in an electronic device.

12. A packaged chip as described in any one of claims 1-5, the packaged chip being used for fault prediction / detection in an industrial environment.

13. A packaged chip as described in any one of claims 1-5, the packaged chip being used for health measurement.

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