Method, device and computer equipment for building communication paths of network-on-chip

Abstract

This disclosure provides a method, apparatus, and computer device for constructing communication paths in an on-chip network, relating to the field of digital integrated circuits. The method includes: generating connection relationships between network interface units and multiple nodes according to predefined network interface unit description rules; generating communication paths for the on-chip network, including: extracting information of existing paths from system data path configuration; parsing the nodes included in the existing paths; processing adjacent node pairs segment by segment to generate multiple path segments; and concatenating the multiple path segments to generate the communication path of the on-chip network; and constructing virtual channel links based on the connection relationships of multiple nodes. The virtual channel links can connect non-adjacent nodes in the existing paths. By introducing the virtual channel link mechanism, deadlock can be resolved, communication bandwidth utilization can be effectively improved, and low-latency communication can be supported.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to the design of system-on-chip (SoC) and network-on-chip (NoC), and especially to methods, apparatus, computer devices, computer-readable storage media and computer program products for constructing communication paths for networks-on-chip. Background Technology

[0002] In the fields of SoC and NoC design, with the continuous expansion of multi-core processors and heterogeneous computing units, the complexity of internal system communication has increased significantly. In terms of communication path construction, traditional methods often use fixed routes or simple rule derivation; in terms of link modeling, conventional point-to-point links (such as basic data transmission links) lack the ability to abstract high-performance communication scenarios. Summary of the Invention

[0003] This disclosure provides a method, apparatus, computer device, computer-readable storage medium, and computer program product for constructing communication paths for on-chip networks.

[0004] According to one aspect of this disclosure, a method for constructing communication paths in an on-chip network is provided. The method includes: generating multiple network interface units corresponding to multiple nodes and connection relationships between multiple nodes according to predefined network interface unit description rules; generating communication paths in the on-chip network, including: extracting information of existing paths from system data path configuration; parsing the nodes included in the existing paths; processing adjacent node pairs among the nodes included in the existing paths segment by segment to generate multiple path segments; and concatenating the multiple path segments to generate the communication path of the on-chip network; and constructing one or more virtual channel links according to the connection relationships of the multiple nodes, wherein the virtual channel links can connect non-adjacent nodes in the existing paths, including: generating link identifiers, link types, and link structures for one or more virtual channel links; and adding attributes to one or more virtual channel links, wherein the attributes include clock domain, serialization parameters, and virtual channel configuration.

[0005] In some embodiments, the network interface unit description rules include: node enable set, interface type, protocol type and parameter configuration, data flow identifier and hierarchical structure, address mapping relationship and performance attribute parameters.

[0006] In some embodiments, the address mapping relationship or performance attribute parameters in the network interface unit description rule are in the form of functions. Generating multiple network interface units according to the predefined network interface unit description rule includes: evaluating the values ​​based on the coordinates or context information of the current multiple nodes to dynamically configure the attributes of the multiple network interface units.

[0007] In some embodiments, generating the connection relationships between multiple network interface units and multiple nodes corresponding to multiple nodes according to predefined network interface unit description rules includes: locating multiple nodes; generating an identifier for a corresponding network interface unit for each of the multiple nodes; constructing a hierarchical structure for each network interface unit, wherein the hierarchical structure of each network interface unit includes an interface, a data flow, and a mapping sub-node; generating a mapping entry for the data flow of the hierarchical structure of each network interface unit according to the network interface unit description rules, wherein the mapping entry is used to record address-related attributes; and generating the connection relationships between multiple nodes in the system specification description.

[0008] In some embodiments, splicing multiple path segments to generate a communication path for a network-on-a-chip includes performing the following steps for each path segment: when the node pairs of the path segment meet predefined connection rules, connecting the node pairs of the path segment using predefined special connection rules; when the node pairs of the path segment meet virtual channel connection conditions, connecting the node pairs of the path segment using a virtual channel link; and when the node pairs of the path segment do not meet the predefined connection rules and virtual channel connection conditions, connecting the node pairs of the path segment using a normal link.

[0009] In some embodiments, concatenating multiple path segments to generate a communication path for an on-chip network includes: for a request path, concatenating the path segments in the request path by sequentially generating path elements in the direction from the start point to the end point; and for a response path, concatenating the path segments in the response path by sequentially generating path elements in the direction from the end point to the start point.

[0010] In some embodiments, the method further includes: automatically pipelined configuration of the data path after generating the communication path and one or more virtual channel links.

[0011] In some embodiments, the method further includes: dividing multiple nodes into modules according to predefined hierarchical partitioning rules.

[0012] In some embodiments, the method further includes: generating a visual network structure of multiple nodes based on the coordinates of multiple nodes.

[0013] According to another aspect of this disclosure, a communication path construction apparatus for an on-chip network is provided. The apparatus includes: a network interface unit generation module configured to generate multiple network interface units corresponding to multiple nodes and connection relationships between multiple nodes according to predefined network interface unit description rules; and a communication path generation module configured to generate communication paths for the on-chip network, including: an extraction submodule configured to extract information of existing paths from system data path configuration; a parsing submodule configured to parse nodes included in the existing paths; and a path segment generation submodule configured to process adjacent node pairs among the nodes included in the existing paths segment by segment to generate multiple communication paths. The network includes: a path segment generation module; a splicing communication submodule configured to splice multiple path segments to generate a communication path for the on-chip network; and a virtual channel link generation module configured to construct one or more virtual channel links based on the connection relationships of multiple nodes, wherein the virtual channel links can connect non-adjacent nodes in an existing path, including: a first virtual channel link generation submodule configured to generate the link identifier, link type, and link structure of one or more virtual channel links; and a second virtual channel link generation submodule configured to add attributes to one or more virtual channel links, wherein the attributes include a clock domain, serialization parameters, and virtual channel configuration.

[0014] According to another aspect of this disclosure, a computer device is provided, comprising: at least one processor; and a memory having a computer program stored thereon, wherein the computer program, when executed by the at least one processor, causes the at least one processor to perform the methods provided above in this disclosure.

[0015] According to another aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0016] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, causes the processor to perform the methods as provided above in this disclosure.

[0017] According to one or more embodiments of this disclosure, the automated construction of the NoC architecture significantly reduces the workload of manual configuration, improves design efficiency, avoids errors caused by manual path maintenance, and improves system consistency. At the same time, by introducing a virtual channel link mechanism, deadlock can be resolved, communication bandwidth utilization can be effectively improved, and low-latency communication can be supported.

[0018] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0019] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0020] Figure 1 This is a flowchart illustrating a method for constructing communication paths in an on-chip network according to an exemplary embodiment.

[0021] Figure 2 This is a flowchart illustrating a portion of the process of a communication path construction method for an on-chip network according to an exemplary embodiment.

[0022] Figure 3 This is a block diagram illustrating a communication path construction apparatus for an on-chip network according to an exemplary embodiment.

[0023] Figure 4 An example computer device is shown in which any of the embodiments described herein may be implemented. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0025] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0026] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0027] In existing technologies, the configuration of Network Interface Units (NIUs), the definition of communication paths, and the allocation of link resources are typically done manually. This involves designers writing configuration files or scripts one by one based on the system topology to statically describe the connection relationships between various nodes, data paths, and protocol parameters. Furthermore, in terms of communication path construction, traditional methods often employ fixed routes or simple rule derivations, making it difficult to flexibly adapt to complex connection requirements. Regarding link modeling, conventional point-to-point links (such as basic data transmission links) lack the ability to abstract high-performance communication scenarios and struggle to support optimization mechanisms such as virtual channels and multi-path parallelism.

[0028] Traditional methods suffer from the following significant drawbacks: First, the manual configuration process is cumbersome and error-prone, requiring extensive and repetitive modifications as the system scales up or the topology changes, resulting in low design efficiency and high maintenance costs. Second, the lack of a unified modeling mechanism between path definition and link resources leads to inconsistencies between communication paths and underlying implementations, affecting the accuracy of system performance evaluation. Third, traditional link models have limited expressive power and struggle to describe complex communication behaviors, such as virtual channel mechanisms with priority, reuse, or time-division characteristics, thus limiting the system's optimization space in high-bandwidth, low-latency scenarios. Finally, existing methods are insufficient in terms of automation and scalability, making it difficult to support parametric design and rapid architecture exploration.

[0029] The embodiments of this disclosure provide a communication path construction method for on-chip networks, which can realize automatic generation of network interface units, automatic derivation of communication paths, and unified modeling of virtual channel links, thereby improving the degree of design automation, reducing manual intervention, enhancing the consistency of system modeling, and supporting the efficient expression of complex communication mechanisms, thus solving the problems of low efficiency, error susceptibility, and insufficient scalability in the prior art.

[0030] Figure 1 This is a flowchart illustrating a communication path construction method 100 for an on-chip network according to an exemplary embodiment.

[0031] like Figure 1As shown, this disclosure proposes a communication path construction method 100 for an on-chip network, including: step S110, generating multiple network interface units corresponding to multiple nodes and connection relationships between multiple nodes according to predefined network interface unit description rules; step S120, generating a communication path for the on-chip network, including: step S121, extracting information of existing paths from system data path configuration; step S122, parsing the nodes included in the existing paths; step S123, processing adjacent node pairs among the nodes included in the existing paths segment by segment to generate multiple path segments; and step S124, splicing multiple path segments to generate a communication path for the on-chip network; and step S130, constructing one or more virtual channel links according to the connection relationships of multiple nodes, wherein the virtual channel links can connect non-adjacent nodes in the existing paths, including: step S131, generating link identifiers, link types, and link structures for one or more virtual channel links; and step S132, adding attributes to one or more virtual channel links, wherein the attributes include clock domain, serialization parameters, and virtual channel configuration.

[0032] In step S110, multiple network interface units corresponding to multiple nodes and the connection relationships between multiple nodes can be generated according to predefined network interface unit description rules.

[0033] In the example, network interface unit (NIC) description rules can be predefined by the user. Based on these predefined rules, NICs corresponding to multiple nodes and their connection relationships can be automatically generated. For example, in a system-on-a-chip (SoC) containing four processing units and a storage controller, the rules specify the enabled node set, interface type, and address mapping. The system then automatically generates an initiating interface for each processing unit, a target interface for the storage controller, and establishes corresponding request and response connections.

[0034] In the example, each node can correspond to one or more network interface units.

[0035] In the example, the network interface unit description rules can be configured by user input or by obtaining the configuration file through the software model address to achieve automated configuration. Here, the source of the network interface unit description rules is not restricted.

[0036] In step S120, a communication path for the on-chip network can be generated, which may include steps S121, S122, S123 and S124.

[0037] In step S121, information about existing paths can be extracted from the system data path configuration.

[0038] In the example, information about existing paths is extracted from the system data path configuration, that is, the predefined sequence of path nodes in the configuration file is parsed. For example, the system data path configuration defines a path from the processing unit to the storage controller: Processing Unit → Switch Node A → Switch Node B → Storage Controller.

[0039] In the example, the system data path configuration can be entered by the user, obtained from predefined rules, or obtained from existing or generated path structures; there are no restrictions here.

[0040] In step S122, the nodes included in the existing path can be parsed.

[0041] Continuing with the example above, after the system reads the configuration, it sequentially parses out the identifiers of the four node processing units, switch node A, switch node B, and storage controller, such as PU0, Switch_A, Switch_B, and MCU.

[0042] In some examples, the node set can also be deduplicated, removing duplicate nodes and extracting valid path nodes.

[0043] In step S123, adjacent node pairs in the existing path are processed segment by segment to generate multiple path segments.

[0044] In the example, adjacent node pairs (PU0, Switch_A), (Switch_A, Switch_B), and (Switch_B, MCU) are processed segment by segment to generate multiple path segments.

[0045] In step S124, multiple path segments are spliced ​​together to generate a communication path for the on-chip network.

[0046] In the example, multiple path segments are concatenated to generate the communication path of the on-chip network. For instance, after processing the path "PU0→Switch_A→Switch_B→MCU" segment by segment, the system generates a virtual channel link segment "PU0→Switch_A", a normal link segment "Switch_A→Switch_B", and a predefined rule segment "Switch_B→MCU". Subsequently, the system concatenates these segments end to end according to the original node order to form the complete "PU0→Switch_A→Switch_B→MCU" communication path, and writes it into the system configuration for use in actual data transmission.

[0047] In step S130, one or more virtual channel links are constructed based on the connection relationship of multiple nodes, wherein the virtual channel links can connect non-adjacent nodes in the existing path.

[0048] In the example, one or more virtual channel links are constructed based on the connection relationships of multiple nodes. These virtual channel links can connect non-adjacent nodes in an existing path. For example, the original path is "Processing Unit → Switching Node A → Switching Node B → Storage Controller," which contains three communication hops. A virtual channel link "Processing Unit → Switching Node B" can be constructed, directly traversing intermediate node A, thereby reconstructing the path to "Processing Unit → Switching Node B → Storage Controller," effectively reducing the number of path hops and communication latency.

[0049] In step S131, the link identifier, link type and link structure of one or more virtual channel links can be generated.

[0050] In the example, a link identifier can be generated based on the starting node and the target node; the link type can be a request link or a response link; the link structure can include links originating from the interface unit, links originating from the switching node, and links pointing to the target interface or switching node.

[0051] In the example, a unique identifier "VC_XY" can be generated for the direct virtual channel between processing unit X and storage controller Y, and its link type can be marked as "request link" according to the data transmission direction. Subsequently, the complete structure of the link is constructed, including the initiating link segment from the interface unit of X, the straight-through tunnel segment across intermediate switching nodes, and the receiving link segment pointing to Y, forming an end-to-end virtual channel description.

[0052] In step S132, attributes can be added to one or more virtual channel links, where attributes may include clock domain, serialization parameters, and virtual channel configuration.

[0053] In the example, the system adds the following attributes to the virtual channel link "VC_XY" between the processing unit X and the storage controller Y: the clock domain is set to "CLK_500MHz", the serialization parameter is configured to "8-bit parallel to 32-bit serial", and the virtual channel is configured to allocate two independent VC buffers (VC0 for high-priority requests and VC1 for ordinary data).

[0054] In some examples, a physical link can be divided into multiple independent virtual channels (VCs), each with its own buffer and flow control logic. For instance, a physical link might be divided into three virtual channels: VC0, VC1, and VC2. Each channel manages its own buffer and operates independently. When a potential deadlock risk is detected, different types of data flows can be assigned to different virtual channels. For example, request packets use the VC0 channel, response packets use the VC1 channel, and write packets use the VC2 channel. Even if the request data flow in the VC0 channel becomes blocked, the response data flow in the VC1 channel can still proceed independently, preventing cross-category circular dependencies. Alternatively, one or more virtual channels can be reserved as dedicated channels specifically for transmitting control packets or special packets that might break a deadlock. For example, if a deadlock occurs between VC0 and VC1, the system can send a deadlock recovery control packet through the reserved VC2 channel, instructing relevant nodes to release their buffers and thus resolve the deadlock. Priorities can be assigned to different virtual channels, allowing higher-priority channels to preempt bandwidth resources from lower-priority channels. You can also set priorities for different virtual channels. When a deadlock is detected in a low-priority channel, traffic in a high-priority channel can still pass through normally, carrying a deadlock release command to break the deadlock state.

[0055] Therefore, the automated construction of the NoC architecture significantly reduces the workload of manual configuration, improves design efficiency, avoids errors caused by manual path maintenance, and improves system consistency. At the same time, by introducing a virtual channel link mechanism, deadlock can be resolved, communication bandwidth utilization can be effectively improved, and low-latency communication can be supported.

[0056] In some embodiments, the network interface unit description rules may include: node enable set (en region), interface type (initiator or target), protocol type and parameter configuration, data flow identifier and hierarchical structure, address mapping relationship (mapping relationship between global address, local address and mask), and performance attribute parameters.

[0057] In the example, the enabled node can be four computing cores (Core0~3); the interface type is set to initiator; the protocol is AXI, the burst length is configured to be 256; the data stream identifier is "Compute_Stream"; the address mapping maps the global address 0x0000_0000~0x0FFF_FFFF to the local address 0x0000_0000, and the mask is 0xF000_0000; the performance parameters are set to bandwidth of 16GB / s and high priority.

[0058] In some embodiments, the address mapping relationship or performance attribute parameters in the network interface unit description rule can be in the form of a function. Generating multiple network interface units according to the predefined network interface unit description rule may include: evaluating the values ​​based on the coordinates or context information of the current multiple nodes to dynamically configure the attributes of the multiple network interface units.

[0059] In some examples, the coordinates (x, y) of a node in the network topology can be generated according to the network interface unit description rules. For instance, the coordinates (3, 2) of a processing unit in the network topology can be generated according to the network topology coordinate generation rules defined in the network interface unit description rules. It is understood that the network interface unit description rules can be any rules related to the interface units of a node, and there are no restrictions here.

[0060] In the example, the network interface unit description rule defines the address mapping as "base address = 0x1000 × node x-coordinate", and the performance parameter function is expressed as "arbitration weight = the square of the node y-coordinate". If the processing unit is located at coordinates (3,2), the system automatically calculates the base address as 0x3000 and the arbitration weight as 4. Furthermore, if the node temperature is too high in the context information, the function automatically reduces the bandwidth limit, thereby achieving dynamic attribute configuration.

[0061] Figure 2 This is a flowchart illustrating part of process S110 of a communication path construction method for an on-chip network according to an exemplary embodiment.

[0062] refer to Figure 2 In some embodiments, step S110 may include step S111, locating multiple nodes; step S112, generating an identifier for each of the multiple nodes corresponding to a network interface unit; step S113, constructing a hierarchical structure for each network interface unit, wherein the hierarchical structure of each network interface unit includes an interface, a data stream, and a mapping sub-node; step S114, generating a mapping entry for the data stream of the hierarchical structure of each network interface unit according to the network interface unit description rules, wherein the mapping entry is used to record address-related attributes; and step S115, generating the connection relationship of multiple nodes in the system specification description.

[0063] The following examples illustrate each step of the above process. In the example, there is a 2×2 on-chip network containing four processing nodes: node C(0,0), node D(0,1), node E(1,0), and node F(1,1).

[0064] In step S111, based on the node enable set in the network interface unit description rule, all nodes that need to generate interfaces can be scanned and located in the network architecture description. For example, if the network interface unit description rule specifies the enabled nodes as {C,D,E,F}, the system can traverse the network topology, confirm that all four nodes exist and are in an enabled state, and record their coordinate information.

[0065] In step S112, a unique interface unit identifier can be generated for each located node. For example, node C generates "NIU_C", node D generates "NIU_D", node E generates interface identifier "NIU_E", and node F generates "NIU_F". This identifier is used for subsequent connection relationship references and configuration management.

[0066] In step S113, a three-layer internal structure can be constructed for each interface unit: an interface layer, a data flow layer, and a mapping layer. For example, for NIU_C, the interface node "NIU_C" contains a data flow node "Stream_C", which in turn contains a mapping node "Map_C". The interface layer can describe the overall attributes, the data flow layer can define the data transmission channel, and the mapping layer can record address translation information.

[0067] In step S114, a specific mapping entry can be generated for each data stream based on the address mapping relationship in the network interface unit description rules. For example, the rule specifies that the global address range of node A is 0x0000_0000~0x0FFF_FFFF, mapped to the local address 0x0000_0000, and the mask is 0xF000_0000. Based on this, the system generates a mapping entry for the NIU_A data stream, recording attributes such as global address, local address, and mask.

[0068] In step S115, the identifiers, hierarchical structures, and mapping entries of all interface units are integrated to generate a description of the connection relationships between nodes. For example, according to the network topology, NIU_C is connected to switch node SW_00, NIU_D is connected to SW_01, NIU_E is connected to SW_10, and NIU_F is connected to SW_11. The system writes these connection relationships into the system specification description file, specifying the port mapping and data flow between each interface unit and the switch node.

[0069] In some embodiments, step S124 may include performing the following steps for each of the multiple path segments: when the node pairs of the path segment meet the predefined connection rules, connecting the node pairs of the path segment using predefined special connection rules; when the node pairs of the path segment meet the virtual channel connection conditions, connecting the node pairs of the path segment using a virtual channel link; and when the node pairs of the path segment do not meet the predefined connection rules and virtual channel connection conditions, connecting the node pairs of the path segment using a normal link.

[0070] In the example, the predefined connection rule could be that the first network interface unit of the first node connects to the second network interface unit of the next horizontal node; the specific connection rule is not limited here.

[0071] In the example, the node pair (A, B) is marked as a "high-speed direct connection rule" in the system's predefined connection rule base. This rule requires the use of a dedicated direct connection channel with low latency and high bandwidth. The link between A and B can be established directly using the predefined connection method without further checks. This type of rule is typically used for connections in systems with specific fixed requirements, such as tightly coupled interfaces between processors and cache controllers.

[0072] In the example, although there is no predefined connection rule for node pair (B,C), B and C meet the conditions for a virtual channel connection: for example, they are in the same clock domain, physically close, and have high communication traffic. Based on this, it can be determined that a virtual channel link should be used to connect B and C. Multiple virtual channel buffers should be allocated to this link to support the parallel transmission of different types of data streams (such as requests and responses), thereby improving link utilization.

[0073] In the example, the node pair (C,D) has neither predefined connection rules nor meets the conditions for a virtual channel connection (e.g., D is an outdated interface module that does not support the virtual channel protocol). A standard point-to-point data transmission link can be used to connect C and D, without any additional virtual channels or special optimization mechanisms. This type of standard link is suitable for general communication scenarios where bandwidth and latency requirements are not high.

[0074] In some embodiments, step S124 may include: for a request path, generating path elements sequentially from the start point to the end point to concatenate path segments in the request path; and for a response path, generating path elements sequentially from the end point to the start point to concatenate path segments in the response path.

[0075] In the example, in the on-chip system, processing unit A needs to write data to memory controller D, and D then returns a write response. The system has generated three path segments for the path "A→B→C→D": (A,B), (B,C), and (C,D). Here, A is the request initiator and D is the destination.

[0076] The request path is used to transmit write request commands and data, with the direction from A to D. The system sequentially concatenates path segments into a complete request path according to the direction from the starting point A to the ending point D: First, it takes segment (A, B) to generate a path element from the initiating interface of A to the input port of the B exchange node; then it takes segment (B, C) to generate a path element from the output port of B to the input port of C; finally, it takes segment (C, D) to generate a path element from the output port of C to the target interface of D. These three path elements are concatenated end-to-end in the order A→B→C→D to form a complete request path configuration.

[0077] The response path is used to transmit the write response signal returned by D, and its direction is opposite to the request path, i.e., from D to A. The system concatenates path segments in reverse order, following the direction from the endpoint D to the starting point A: First, it reverses the segment (C,D) to generate a path element from the target interface of D to the output port of C; then, it reverses the segment (B,C) to generate a path element from the input port of C to the output port of B; finally, it reverses the segment (A,B) to generate a path element from the input port of B to the receiving interface of A. These three path elements are concatenated in the order D→C→B→A to form a complete response path configuration, ensuring that the response signal can return along the original path.

[0078] In some examples, such as the path "A→B→C→D→A" forming a square path, the response signal can return directly from D to A without having to return along the original path D→C→B→A. Furthermore, whether the return path of the response signal is a return along the original path or a direct return can be configured through the network interface unit description rules.

[0079] In some embodiments, method 100 may further include: automatically pipelined configuration of the data path after generating the communication path and one or more virtual channel links.

[0080] In the example, a communication path "A→X→Y→D" is generated from processing unit A to storage controller D, and a virtual channel link "A" is constructed for the direct connection across intermediate nodes X and Y. "D". This path involves multiple switching nodes and long physical traces, resulting in significant timing convergence pressure. Pipeline registers need to be inserted to increase the maximum operating frequency. After the path and links are generated, the pipeline configuration process is automatically triggered: First, all network interface units associated with the path (the initiating interface of A, the target interface of D) and the performance configuration nodes of the switching nodes (X and Y) traversed by the path are obtained. Since A is the request initiator and D is the target, the pipeline direction of the request path can be determined as A→D (forward), and the pipeline direction of the response path is D→A (reverse). Then, the physical length and timing constraints of each link segment in the path can be analyzed. For example, if a link between X and Y spans a long physical distance, and the virtual channel link "A" is detected to be... "D" contains the routing logic. Then, pipelines can be automatically inserted: in the request channel, a pipeline register is inserted at the output of A's initiating interface, on the link between X and Y, and at the input of Y to D; in the response channel, pipeline registers are correspondingly inserted at the output of D, on the link between Y and X, and at the input of X to A; in the virtual channel link, additional pipelines are inserted before and after the arbitration logic of the virtual channel link to improve the timing of complex control logic. Finally, the enable status flags of all the above pipeline nodes are written into the system configuration to enable these registers.

[0081] Thus, paths that might otherwise lead to timing violations due to long paths can achieve higher clock frequencies and stable data transmission through automated multi-stage pipeline insertion, thereby improving system timing performance.

[0082] In some embodiments, method 100 may further include: dividing multiple nodes into modules according to predefined hierarchical division rules.

[0083] In some examples, modules can be partitioned based on clock domains. A clock domain refers to a collection of digital circuit logic regions driven by the same clock signal. In the virtual channel link attribute configuration, the clock domain parameter is used to specify the clock signal followed by each module in the link (such as network interface units, switching nodes, and virtual channel buffers). For example, the system can set different clock domain attributes for a virtual channel link connecting a high-speed processing unit and a low-speed peripheral: the initiating end uses a 500MHz clock, the destination end uses a 100MHz clock, and asynchronous bridging logic is inserted in the middle of the link for cross-clock domain synchronization. By configuring the clock domain independently for each virtual channel link, the system can support multi-clock domain design, meet the timing requirements of modules with different performance levels, and reduce overall power consumption.

[0084] In some examples, modules can be partitioned based on reset domains. A reset domain is a collection of digital circuit logic regions controlled by the same reset signal. In on-chip network design, reset domains define which logic units are synchronously initialized to a known state when the reset signal is valid. Virtual channel link attributes can include reset domain configurations to specify the reset group to which each component in the link belongs. For example, a system can classify virtual channel links directly connected to the processor core as reset domain A (follow core reset) and links connected to peripheral interfaces as reset domain B (independent reset). When a module malfunctions and requires a partial reset, the system only issues a reset signal to the virtual channel links within its own reset domain, while links in other reset domains remain in normal working order, thus avoiding performance loss and recovery delays caused by a global reset.

[0085] For example, a 2×2 on-chip network contains four processing nodes: node A(0,0), node B(0,1), node C(1,0), and node D(1,1), and four switching nodes: SW_00(0,0), SW_01(0,1), SW_10(1,0), and SW_11(1,1). The hierarchical partitioning rules in this example could include: using the X-value of the coordinate as the basis for module partitioning, with nodes X=0 belonging to the "left half module" and nodes X=1 belonging to the "right half module"; and each module containing processing nodes belonging to that region and corresponding switching nodes.

[0086] The system can divide these nodes into different modules according to predefined hierarchical partitioning rules. This can include: the system traversing the eight nodes in the network (four processing nodes and four exchange nodes) and reading the coordinate information of each node; determining the module according to the rules, for example, nodes A(0,0) and SW_00(0,0) with X=0 are assigned to the "left half module", nodes B(0,1) and SW_01(0,1) with X=0 are also assigned to the "left half module", nodes C(1,0) and SW_10(1,0) with X=1 are assigned to the "right half module", and nodes D(1,1) and SW_11(1,1) with X=1 are also assigned to the "right half module"; and writing module identification information into the attributes of each node. For example, add "module = left_partition" to the attributes of node A, and add "module = right_partition" to the attributes of node C; in the system structure description, the system generates two module-level nodes: "left half module" and "right half module", and attaches the corresponding child nodes to them; for cross-module structures, such as links connecting the left and right halves (e.g., cross-module links connecting SW_00 to SW_10), determine the module to which the source node SW_00 belongs as "left half module", and mark "cross_module = left_to_right" in the link attributes, so as to facilitate subsequent cross-module timing analysis and pipeline insertion.

[0087] By dividing the system into modules as described above, the originally scattered nodes are organized into a clear hierarchical structure, which facilitates subsequent layout and routing, power consumption analysis and independent simulation verification, and improves the maintainability and scalability of the system.

[0088] In some embodiments, method 100 may further include: generating a visual network structure of multiple nodes based on the coordinates of multiple nodes.

[0089] For example, the example 2×2 on-chip network contains four processing unit nodes: PE00(0,0), PE01(0,1), PE10(1,0), and PE11(1,1), and four switching nodes: SW00(0,0), SW01(0,1), SW10(1,0), and SW11(1,1). Each node is assigned logical coordinates, which can automatically generate a visual description for graphical interface display.

[0090] The system performs the following steps to generate the visual structure: Traverse all nodes, obtain the minimum coordinate (0,0) and maximum coordinate (1,1), and determine the network boundary range as 0~1 in the horizontal direction and 0~1 in the vertical direction; calculate network supplementation, for example, based on the display canvas size (e.g., 800×600 pixels) and the number of grids (2×2), calculate that the horizontal and vertical step sizes are both 200 pixels, and the display position of each node is (starting horizontal coordinate + node horizontal coordinate × step size, starting vertical coordinate + node vertical coordinate × step size); locate each node, for example, PE00 and SW00 are located at the same coordinate (0,0), the system draws a combined node or places them adjacently at position (100, 100), PE01 and SW01 are located at (0,1), drawn at (100, 300), PE10 and SW10 are located at (1,0), drawn at (300, 100), PE11 and SW11 are located at (1,1), drawn at (300, 100). At position 300); calculate the link display position. For example, for a horizontal link, SW00 and SW01 can be connected, with their ordinates being the same (both 0). The system uses a horizontal offset to draw a straight line from the right side of SW00 to the left side of SW01. For a vertical link, SW00 and SW10 can be connected, with their abscissas being the same (both 0). The system uses a vertical offset to draw a straight line from the bottom of SW00 to the top of SW10. For diagonal or complex links, a suitable Bézier curve path can be calculated based on the coordinates of the source and target nodes to avoid overlapping with other links. For tunnel structures (such as virtual channel links spanning multiple nodes), double-dot representation or dashed line style can be used. For example, a link from PE00 directly to PE11 can be drawn with a red dashed line and labeled "virtual channel" in the middle. Generate coordinate attributes. For example, generate the final display coordinate attributes for each node, such as PE00 obtaining "visual_x=100, visual_y=100" and SW11 obtaining "visual_x=300, visual_y=300". Generate a set of control point coordinates for each link, such as "start=(200,100), end=(250,100)" for a horizontal link.

[0091] In some examples, a visual network structure of multiple nodes can be generated based on their actual physical locations. This visual network structure can present the actual physical locations and distances of the nodes, and annotate the corresponding physical parameters. For example, four processing units are located at (0μm, 0μm), (0μm, 500μm), (500μm, 0μm), and (500μm, 500μm), respectively. After reading the physical coordinates of each node, the system generates a visual layout proportionally, intuitively showing that the distance between PE00 and PE01 is 500μm, and the distance between PE00 and PE11 is approximately 707μm. Simultaneously, the system annotates the physical parameters on the links: long-distance links are labeled "line length 707μm, estimated delay 0.35ns," and short-distance links are labeled "line length 500μm, estimated delay 0.25ns."

[0092] In the example, the visualization structure description can be updated. For instance, all coordinate attributes can be written to a visualization description file (such as JSON or XML format). After the front-end tool reads the file, it can render a complete on-chip network topology diagram on the canvas, including node locations, link directions, and special tunnel structures, thereby helping designers intuitively understand the network layout and perform debugging and optimization.

[0093] Figure 3 This is a block diagram illustrating a communication path construction apparatus 300 for a network-on-chip according to an exemplary embodiment.

[0094] refer to Figure 3 In some embodiments, the on-chip network communication path construction apparatus 300 includes: a network interface unit generation module 310, configured to generate multiple network interface units corresponding to multiple nodes and connection relationships between multiple nodes according to predefined network interface unit description rules; and a communication path generation module 320, configured to generate communication paths for the on-chip network, including: an extraction submodule 321, configured to extract information of existing paths from system data path configuration; a parsing submodule 322, configured to parse the nodes included in the existing paths; and a path segment generation submodule 323, configured to process adjacent node pairs among the nodes included in the existing paths segment by segment to generate multiple... The system includes: a path segment; and a splicing communication submodule 324, configured to splice multiple path segments to generate a communication path for the on-chip network; and a virtual channel link generation module 330, configured to construct one or more virtual channel links based on the connection relationships of multiple nodes, wherein the virtual channel links can connect non-adjacent nodes in an existing path, including: a first virtual channel link generation submodule 331, configured to generate the link identifier, link type, and link structure of one or more virtual channel links; and a second virtual channel link generation submodule 332, configured to add attributes to one or more virtual channel links, wherein the attributes include a clock domain, serialization parameters, and virtual channel configuration.

[0095] Therefore, the automated construction of the NoC architecture significantly reduces the workload of manual configuration, improves design efficiency, avoids errors caused by manual path maintenance, and improves system consistency. At the same time, by introducing a virtual channel link mechanism, deadlock can be resolved, communication bandwidth utilization can be effectively improved, and low-latency communication can be supported.

[0096] In some embodiments, the address mapping relationship or performance attribute parameter in the network interface unit description rule can be in the form of a function. The network interface unit generation module 310 further includes a dynamic configuration attribute submodule, which is configured to evaluate the attributes of multiple network interface units based on the coordinates or context information of the current multiple nodes.

[0097] In some embodiments, the network interface unit generation module 310 may further include: a node positioning submodule configured to locate multiple nodes; a network interface unit identification submodule configured to generate an identifier for each of the multiple nodes corresponding to a network interface unit; a network interface unit construction submodule configured to construct a hierarchical structure for each network interface unit, wherein the hierarchical structure of each network interface unit includes an interface, a data stream, and mapping child nodes; a mapping entry generation submodule configured to generate mapping entries for the data stream of the hierarchical structure of each network interface unit according to the network interface unit description rules, wherein the mapping entries are used to record address-related attributes; and a connection relationship generation submodule configured to generate connection relationships between multiple nodes in the system specification description.

[0098] In some embodiments, the communication path generation module 320 may further include: a request path generation submodule, configured to generate path elements sequentially from the start point to the end point to splice path segments in the request path; and a response path generation submodule, configured to generate path elements sequentially from the end point to the start point to splice path segments in the response path.

[0099] In some embodiments, the communication path construction apparatus 300 for a network-on-chip may further include a pipeline configuration module configured to automatically pipeline the data path after generating the communication path and one or more virtual channel links.

[0100] In some embodiments, the communication path construction apparatus 300 for the on-chip network may further include: a node partitioning module, configured to partition multiple nodes into modules according to predefined hierarchical partitioning rules.

[0101] In some embodiments, the on-chip network communication path construction apparatus 300 may further include: a visualization module configured to generate a visualized network structure of multiple nodes based on the coordinates of multiple nodes.

[0102] The operations of the aforementioned network interface unit generation module 310, communication path generation module 320, extraction submodule 321, parsing submodule 322, path fragment generation submodule 323, communication splicing submodule 324, virtual channel link generation module 330, first virtual channel link generation submodule 331, and second virtual channel link generation submodule 332 can be combined. Figure 1 The operations of steps S110, S120, S130, S121, S122, S123, S124, S131 and S132 are the same, so the details of each aspect will not be repeated here.

[0103] According to one aspect of this disclosure, a computer device is also provided, comprising: at least one processor; and a memory storing a computer program thereon, wherein the computer program, when executed by the at least one processor, causes the at least one processor to perform the steps of any of the method embodiments described above.

[0104] According to one aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, causes the processor to perform the steps of any of the method embodiments described above.

[0105] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0106] Figure 4 An example computer device 400 is shown in which any of the embodiments described herein may be implemented. Computer device 400 may be used to implement one or more components of the systems and methods described above. Computer device 400 may include a bus 402 or other communication mechanism for communicating information, and one or more processors 404 coupled to the bus 402 for processing information. Processor 404 may be, for example, one or more general-purpose microprocessors.

[0107] Computer device 400 may also include main memory 406, such as random access memory (RAM), cache, and / or other dynamic storage devices, coupled to bus 402, for storing information and instructions to be executed by processor 404. Main memory 406 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 404. Such instructions, when stored in a storage medium accessible to processor 404, can make computer device 400 a special-purpose machine customized to perform the operations specified in the instructions. Main memory 406 may include non-volatile media and / or volatile media. Non-volatile media may include, for example, optical discs or magnetic disks. Volatile media may include dynamic memory. Common media formats may include, for example, floppy disks, collapsible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs (read-only optical disc drives), any other optical data storage media, any physical media with a perforated arrangement, RAM (random access memory), DRAM (dynamic random access memory), PROM (programmable read-only memory) and EPROM (erasable programmable read-only memory), FLASH-EPROM (fast erase programmable read-only memory), NVRAM (non-volatile random access memory), any other memory chips or tape cartridges, or network versions of the above.

[0108] Computer device 400 may implement the techniques described herein using custom hardwired logic, one or more ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), firmware, and / or program logic, which, when combined with computer device 400, enable computer device 400 to become a special-purpose machine or to be programmed therein. According to one embodiment, the techniques described herein are executed by computer device 400 in response to processor 404 executing one or more sequences of one or more instructions contained in main memory 406. Such instructions may be read into main memory 406 from another storage medium, such as storage device 408. Executing the sequence of instructions contained in main memory 406 causes processor 404 to perform the processing steps described herein. For example, the processes / methods disclosed herein may be implemented by computer program instructions stored in main memory 406. When these instructions are executed by processor 404, they may perform the steps shown in the corresponding figures and as described above. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0109] Computer device 400 also includes a network interface 410 coupled to bus 402. Network interface 410 can provide bidirectional data communication coupled to one or more network links connected to one or more networks. As another example, network interface 410 can be a local area network (LAN) card to provide data communication connectivity with a compatible LAN (or a WAN component communicating with a WAN (wide area network)). Wireless links can also be implemented.

[0110] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0111] Each process, method, and algorithm described in the preceding sections can be embodied in a code module executed by one or more computer systems or computer processors including computer hardware, and can be fully or partially automated by them. These processes and algorithms can be implemented, in part or in whole, in a specific application circuit.

[0112] When the functions disclosed herein are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, can be embodied in the form of a software product. This software product can be stored in a storage medium and includes instructions to cause a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the methods described in the embodiments of this application. The storage medium may include a flash drive, a portable hard drive, ROM, RAM, a magnetic disk, an optical disk, another medium suitable for storing program code, or any combination thereof.

[0113] The embodiments disclosed herein can be implemented via a cloud platform, server, or group of servers that interact with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can install platform applications.

[0114] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0115] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.

[0116] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.

[0117] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0118] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.

[0119] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.

[0120] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.

[0121] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.

Claims

1. A method for constructing communication paths in an on-chip network, characterized in that, The method includes: Based on predefined network interface unit description rules, generate multiple network interface units corresponding to multiple nodes and the connection relationships between the multiple nodes; Generating the communication path of the on-chip network includes: Extract information about existing paths from the system data path configuration; Parse the nodes included in the existing path; The existing path includes adjacent node pairs, which are processed segment by segment to generate multiple path segments; and The multiple path segments are concatenated to generate the communication path of the on-chip network; and One or more virtual channel links are constructed based on the connection relationships of the multiple nodes, wherein the virtual channel links can connect non-adjacent nodes in the existing path, including: Generate the link identifier, link type, and link structure of the one or more virtual channel links; and Add attributes to one or more virtual channel links, wherein the attributes include clock domain, serialization parameters, and virtual channel configuration.

2. The method according to claim 1, characterized in that, The network interface unit description rules include: node enable set, interface type, protocol type and parameter configuration, data flow identifier and hierarchical structure, address mapping relationship and performance attribute parameters.

3. The method according to claim 2, characterized in that, The address mapping relationship or performance attribute parameter in the network interface unit description rule is in functional form. The generation of the plurality of network interface units according to the predefined network interface unit description rule includes: The values ​​are evaluated based on the current coordinates or context information of the multiple nodes to dynamically configure the attributes of the multiple network interface units.

4. The method according to claim 1, characterized in that, Based on predefined network interface unit description rules, generating multiple network interface units corresponding to multiple nodes and the connection relationships between the multiple nodes includes: Locate the multiple nodes; For each of the plurality of nodes, generate an identifier for a corresponding network interface unit; Construct a hierarchical structure for each network interface unit, wherein the hierarchical structure of each network interface unit includes an interface, a data stream, and a mapping sub-node; According to the network interface unit description rules, a mapping entry is generated for the data stream of the hierarchical structure of each network interface unit, wherein the mapping entry is used to record address-related attributes; and Generate the connection relationships between multiple nodes in the system specification description.

5. The method according to claim 1, characterized in that, The process of concatenating the multiple path segments to generate the communication path of the on-chip network includes: For each of the plurality of path segments, perform the following steps: When the node pairs of a path segment satisfy the predefined connection rules, the node pairs of the path segment are connected using the predefined special connection rules; When the node pairs of a path segment meet the virtual channel connection conditions, the node pairs of the path segment are connected using the virtual channel link; and When the node pairs of a path segment do not meet the predefined connection rules and the virtual channel connection conditions, a normal link is used to connect the node pairs of the path segment.

6. The method according to claim 1, characterized in that, The process of concatenating the multiple path segments to generate the communication path of the on-chip network includes: For the request path, path elements are generated sequentially from the start point to the end point to concatenate the path segments in the request path; and For the response path, path elements are generated sequentially from the endpoint to the starting point to splice the path segments in the response path.

7. The method according to claim 1, characterized in that, The method further includes: After generating the communication path and the one or more virtual channel links, the data path is automatically pipelined.

8. The method according to claim 1, characterized in that, The method further includes: The multiple nodes are divided into modules according to predefined hierarchical division rules.

9. The method according to claim 1, characterized in that, The method further includes: A visual network structure of the multiple nodes is generated based on their coordinates.

10. A communication path construction device for an on-chip network, characterized in that, The device includes: The network interface unit generation module is configured to generate multiple network interface units corresponding to multiple nodes and the connection relationship between the multiple nodes according to predefined network interface unit description rules. A communication path generation module, configured to generate communication paths for the on-chip network, includes: The extraction submodule is configured to extract information about existing paths from the system data path configuration. The parsing submodule is configured to parse the nodes included in the existing path; A path segment generation submodule is configured to process adjacent node pairs in the existing path segment by segment to generate multiple path segments; and A splicing communication submodule is configured to splice the plurality of path segments to generate the communication path of the on-chip network; and A virtual channel link generation module is configured to construct one or more virtual channel links based on the connection relationships of the plurality of nodes, wherein the virtual channel links can connect non-adjacent nodes in the existing path, including: The first virtual channel link generation submodule is configured to generate the link identifier, link type and link structure of the one or more virtual channel links; The second virtual channel link generation submodule is configured to add attributes to one or more virtual channel links, wherein the attributes include clock domain, serialization parameters and virtual channel configuration.

11. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-9.

13. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-9.

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