A chip security architecture for embodied intelligent robots and a resource scheduling method thereof

Abstract

This invention discloses a chip security architecture and resource scheduling method for embodied intelligent robots. It includes: a heterogeneous collaborative computing cluster composed of multiple computing nodes integrating CPU, GPU, FPGA, and in-memory computing chips, employing a two-level parallel mechanism; a compilation security framework for in-memory computing, which constructs a compilation toolchain through machine description normalization and semantic extension, compiling operators into hardware code through two stages of mechanism analysis and strategy implementation, and continuously optimizing by combining security verification and feedback-based performance evaluation; and a heterogeneous resource integrated scheduling module, which allocates tasks to the most suitable hardware chip on the optimal node for execution based on load prediction and task type, with real-time feedback of runtime data to iteratively optimize scheduling and security strategies. This invention achieves a paradigm shift in security from external monitoring to intrinsic immunity, improving the energy efficiency, real-time performance, and security of embodied intelligent robots.

Description

Technical Field

[0001] This invention relates to the field of chip architecture for embodied intelligent robots, and more specifically to a chip security architecture and resource scheduling method for embodied intelligent robots. Background Technology

[0002] Currently, embodied intelligent robots have entered a period of rapid development driven by large models, multimodal perception, and deep human-machine interaction. Relying on the cognitive and decision-making capabilities of general artificial intelligence models, combined with bionic bodies, dexterous manipulation, and environmental adaptation technologies, robots are shifting from executing single instructions to autonomous understanding, planning, and closed-loop operations. They are gradually being applied in scenarios such as industrial manufacturing, inspection and maintenance, home services, and scientific research. Overall, the technology is iterating rapidly and the industrialization process is accelerating, but it still faces key bottlenecks such as versatility, stability, cost, and battery life. It is at a critical stage of transitioning from laboratory demonstrations to large-scale practical application.

[0003] The computational architecture of embodied intelligent robots typically adopts a layered heterogeneous collaborative architecture. A large cloud-based or edge-based model serves as the "brain," responsible for cognition, reasoning, language interaction, and task planning. Real-time motion controllers and lightweight perception models act as the "cerebellum," responsible for posture calculation, force control, obstacle avoidance, and fine manipulation. The underlying layer relies on multiple sensors (vision, laser, force sensing, inertial measurement, etc.) to complete environmental modeling and ontological perception. Through edge-cloud collaboration, a closed-loop fusion of high-dimensional cognitive decision-making and low-latency motion control is achieved, balancing intelligent generalization capabilities with the real-time performance, security, and robustness of physical interaction. The brain, cerebellum, and brainstem of an embodied intelligent robot correspond to different computing power and real-time requirements, employing a layered heterogeneous chip collaborative approach: the brain is primarily based on high-performance GPUs (Graphics Processing Units), NPUs (Neural Processing Units), or computing cards; the cerebellum uses FPGAs (Field Programmable Gate Arrays) or dedicated motion control chips; and the brainstem mainly uses embedded chips such as MCUs (Microprogrammed Control Units) and DSPs (Digital Signal Processors). Under the von Neumann computing architecture, due to differences in process technology and packaging, the performance gap between processors and memory has been widening year by year. The time and power loss of data exchange between the two have become obstacles to the continuation of Moore's Law, resulting in embodied intelligent chips, systems and security facing embodied intelligent robots in dynamic physical interactions with problems of response lag and energy efficiency and safety imbalance. Summary of the Invention

[0004] This invention takes the collaborative architecture of "brain (cognitive decision-making) - cerebellum (real-time control) - ontology (physical execution)" as a breakthrough point, and proposes a chip security architecture and resource scheduling method for embodied intelligent robots. It integrates data storage and computing into the same chip, and designs a memory-computing chip with high energy efficiency, low power consumption, and high-precision training and inference. It aims to overcome the energy efficiency loss caused by the separation of computing and storage in traditional architectures. At the same time, by embedding interpretable decision-making and scheduling algorithms, it overcomes the bottleneck of lagging security protection, and realizes a paradigm shift in system security protection from "external monitoring" to "endogenous immunity".

[0005] To achieve the above-mentioned technical objectives, the present invention provides the following technical solution: A chip security architecture for embodied intelligent robots, specifically comprising: The heterogeneous collaborative computing cluster consists of multiple computing nodes, each integrating a CPU, GPU, FPGA, and in-memory computing chip. The cluster adopts a two-level parallel mechanism that combines inter-node parallelism and intra-node parallelism. The GPU and FPGA establish a bidirectional direct communication link with each other as master and slave through the PCIe bus, bypassing the CPU and memory for direct data transmission. A compiler security framework for in-memory computing is proposed, which constructs a compiler toolchain through machine description normalization and programming semantic extension. The compiler toolchain is used for compilation, and the compilation process is divided into two stages: mechanism analysis and policy implementation, which compiles operators into hardware code. Security verification is carried out by comprehensively considering multi-dimensional information, and a feedback performance evaluation mechanism is established to continuously optimize the compilation process. The heterogeneous resource integrated scheduling module is coupled with the compilation security framework and the heterogeneous collaborative computing cluster, and is used to allocate tasks to the most suitable hardware chip of the optimal computing node in the heterogeneous collaborative computing cluster based on load prediction and task type. After the task data enters the heterogeneous collaborative computing cluster, it undergoes compute-storage fusion processing by the in-memory computing chip, while an in-memory computing-oriented compiler security framework performs affine transformation and security verification. Once the security verification is passed, the data is sent to the heterogeneous resource integrated scheduling module for allocation decision-making, assigning the task to the most suitable hardware chip on the optimal computing node in the heterogeneous collaborative computing cluster for execution. During the execution process, the running data is fed back to the heterogeneous resource integrated scheduling module and the in-memory computing-oriented compiler security framework in real time, iteratively optimizing the scheduling and security strategies until the task is completed.

[0006] Furthermore, the two-level parallel mechanism is specifically as follows: Inter-node parallelism: Distributed storage is used among computing nodes, with each computing node storing data independently. Process-level tasks between computing nodes communicate data through the message passing mechanism of the MPI programming model. Intra-node parallelism: Within a single computing node, the CPU runs logical processing tasks, while the GPU runs fine-grained, intensive computing tasks; a storage method combining distributed and shared storage is adopted, with the GPU having independently accessible video memory and sharing the system main memory with the CPU; data sharing between the CPU and GPU is achieved through a main memory / video memory mapping mechanism.

[0007] Furthermore, the GPU and FPGA establish a bidirectional direct communication link via the PCIe bus, bypassing the CPU and memory for direct data transmission. Direct GPU and FPGA communication is established via the PCIe bus, with each communication data passing through the PCIe switch only once and without copying the communication information into the CPU memory. When the GPU acts as the master and the FPGA acts as the slave, the FPGA's memory is mapped to the PCIe bus for the GPU to read and write directly. When the FPGA acts as the master and the GPU acts as the slave, the GPU's read and write operations on the FPGA's memory are first implemented in the manner of the GPU acting as the master, and then the GPU Direct RDMA interface is extended to implement read and write operations on the GPU's memory.

[0008] Furthermore, the construction of the compilation toolchain through machine description normalization and programming semantic extension specifically involves: Machine description standardization: A method combining hierarchical hardware abstraction layer (HAL) modeling and instruction set architecture (ISA) formal description is adopted to provide a unified abstract representation of CPUs, GPUs, FPGAs, and in-memory computing chips. Each hardware chip in the heterogeneous collaborative computing cluster is abstracted into three categories of standard hardware objects. A hardware-independent intermediate representation (IR) and a unified operation semantic interface are constructed, encapsulating memory access, computation, and synchronization control into standard primitives. A hardware capability attribute table is established to standardize the declaration of computing power type, data bit width, parallelism, access latency, and communication bandwidth. Instruction set commonalities are discovered through opcode clustering, operand pattern matching, and data flow feature extraction. These commonalities include general computation, general memory access, general control, and in-memory computing-specific instructions. Finally, machine description text for the in-memory computing architecture is generated, including in-memory computing-specific fields, heterogeneous communication descriptions, real-time latency constraints, and security attribute tags. Programming Semantic Extension: Semantic definition is performed on in-memory computing compilation, clarifying the semantic boundaries of scalar computation, vector computation, tensor computation, in-memory coupling, near-memory access, and hardware synchronization. Semantics are extracted within the scope of computation graph representation and operator acceleration, and in-memory coupling semantics are extracted for in-memory architecture. Based on semantic definition and extraction, semantic representations of in-memory coupling, computation graph representations of tensor programs, and data transmission related semantic representations are formed. On the basis of traditional parallel computing semantics, in-memory coupling semantics, near-memory access semantics, data flow driven semantics, real-time control semantics, and intrinsic safety constraint semantics are added. Tensor operators are designed and implemented to form a compilation toolchain that supports in-memory computing.

[0009] Furthermore, the compilation process using a compiler toolchain is divided into two stages: mechanism analysis and policy implementation. Specifically, compiling the operator into hardware code involves: Mechanism analysis stage: Based on the polyhedral model, affine transformations are performed on nested loops to construct an affine transformation matrix for in-memory computing architecture. The affine transformation matrix is ​​abstracted into algebraic operations of affine functions, iterative vectors, and data dependency matrices, resulting in the integer set of scheduling algorithms; The scheduling algorithm is solved by solving the integer set through integer linear programming or scheduling tree search, and the output is a legal loop schedule that satisfies the hardware execution constraints. Strategy implementation phase: Operator parallelism and locality analysis are performed based on a polyhedral model. The inputs include computation graph, operator type, tensor shape, data dependency matrix, legal loop scheduling, affine transformation matrix, and machine description. Operator parallelism is quantified by the maximum parallel iteration space dimension and vectorizable length, while operator locality is quantified by reuse distance and cache miss rate prediction. Based on the analysis results of operator parallelism and locality, an architecture-adaptive scheduling generation is performed: for the CPU, multi-threaded parallelism, loop-based block scheduling, and instruction reordering scheduling are generated; for the GPU, three-level parallelism (grid, block, and thread) and shared memory block scheduling are generated; for the FPGA, pipelined parallelism, bit-width matching, and systolic array scheduling are generated; for the in-memory computing unit, near-memory scheduling, in-situ computation scheduling, and no-shift execution sequences are generated; the scheduler automatically selects a matching scheduling template based on the hardware capability attribute table in the machine description and generates a legal execution order; the in-memory computing unit is the smallest hardware execution unit in the in-memory computing chip; Employing a multi-level cache collaborative allocation and minimum-cost data flow deployment algorithm, we achieve automated cache allocation and data deployment, deploying hot data, computationally intensive data, and streaming data to the corresponding storage levels as needed. Based on the legal execution order and data deployment results, hardware executable code is output through the target architecture code generation stage.

[0010] Furthermore, the establishment of a feedback-based performance evaluation mechanism for continuous optimization of the compilation process includes: By combining automatic feedback mechanisms with manual parameter adjustment, the instruction scheduling, memory management, and security verification processes are optimized. An optimization parameter search space is established, wherein the optimization parameters include cyclic allocation parameters, parallel configuration parameters, cache allocation parameters, data flow scheduling parameters, in-memory computing architecture parameters, and security constraint parameters; The computational features, memory access features, structural features, locality features, hardware adaptation features, and security features of operators are extracted using the operator feature disjunction method. Feature vectors are used to represent these features, and pruning and clustering are then performed. Using deep learning, code is generated with initial parameters such as loop block size, parallel dimension, vectorization length, and security check level. The code is then run on the target hardware and feedback data including latency, utilization, cache hit rate, power consumption, data migration amount, and security check time are collected. The cost estimation function is constructed and iterated based on feedback data; the cost estimation function under different combinations of optimization parameters is predicted using a machine learning model; and the combination of optimization parameters that minimizes the cost estimation function is selected as the optimal combination of parameters. Security checks are performed simultaneously during the optimization process: based on task security level, data sensitivity level, hardware permission domain, access behavior, communication security, real-time constraints, and system status, a security state machine and trusted checkpoints are used to identify security challenges, including unauthorized access, illegal execution, and timing anomalies, ensuring the secure operation of the system. Specifically, in this embodiment: a security state machine is established to monitor data flow, control flow, and memory access behavior in real time; unauthorized access, data leakage, illegal execution, and timing anomalies are determined based on multi-dimensional information; trusted checkpoints are forcibly inserted into security-critical tasks; memory isolation, permission locking, and in-situ computation anti-tampering are implemented for in-memory computing units; if security fails, execution is refused, downgrading is triggered, and a security mode is switched, thereby ensuring the secure operation of the system. After optimization and security verification, the optimal compilation strategy was determined for in-memory computing architecture and robot target task scenarios.

[0011] This application also discloses a resource scheduling method for a chip security architecture for embodied intelligent robots, which specifically includes: Collect real-time load data of each computing node in the heterogeneous collaborative computing cluster when the embodied robot is solving different complex tasks; preprocess the real-time load data to remove dirty data; Based on the preprocessed real-time load data, the predicted load of each computing node is obtained using a data-driven model, which includes an integrated moving average autoregressive model and a random forest model. Based on the predicted load, and considering the architectural characteristics of different computing tasks and computing nodes, an evolutionary computing-based scheduling optimization method is adopted to determine the allocation scheme between computing tasks and computing nodes. The computing tasks are allocated to each computing node according to the allocation plan, and the CPU, GPU or FPGA in the computing node are arranged to execute them.

[0012] Furthermore, the step of determining the allocation scheme between computing tasks and computing nodes based on the predicted load, considering different computing tasks and the architectural characteristics of computing nodes, and employing an evolutionary computation-based scheduling optimization method specifically involves: By utilizing machine learning techniques, a computing node performance model is constructed by comprehensively considering the inherent attributes of computing nodes and the performance preferences of different computing architectures for different computing tasks. The inherent attributes of computing nodes include the hardware model, number of cores, storage capacity, communication bandwidth, computing power precision, real-time capability, and security capability of CPU / GPU / FPGA. The performance preferences include: CPU is suitable for logic / control intensive tasks, GPU is suitable for computation / data parallel tasks, FPGA is suitable for communication / real-time tasks, and in-memory computing chips are suitable for memory access / near-memory computing tasks. The computing node performance model uses execution time, utilization, bandwidth, power consumption, real-time performance, and security adaptability as quantitative indicators to output a score on the adaptability between tasks and computing nodes. Based on the predicted load, computing nodes whose load exceeds a preset threshold are filtered out to form a candidate computing node set; Using a divide-and-conquer approach, the correlation between tasks is measured from four dimensions: data correlation, execution dependency correlation, resource requirement correlation, and real-time correlation. Tasks with a correlation higher than a preset threshold are divided into the same task cluster. Each task cluster is treated as an independent sub-scheduling problem. All tasks within the same task cluster are assigned to the same computing node and executed using the same type of hardware chip within that computing node. Within each task cluster, the processing order of each task is optimized based on execution dependencies, correlations, real-time cycles, and hardware compatibility. An evolutionary algorithm is used to optimize the scheduling of each sub-scheduling problem. Task clusters are assigned to a specific hardware chip on a specific computing node in a candidate computing node set for execution. In the scheduling optimization phase, task clusters are used as the basic allocation unit, and task clusters are bound to computing nodes for optimization. An individual of the evolutionary algorithm is represented as a candidate scheme for assigning a task cluster to a certain type of hardware chip on a computing node. The fitness value of each individual is the fitness score between the task cluster and the computing node. The fitness score between the task cluster and the computing node is the weighted sum or arithmetic mean of the fitness scores between all tasks and computing nodes in the cluster. A hybrid search operator is designed to adjust the search direction based on task type, performance preference, and relevance between tasks, and to iteratively generate candidate allocation schemes. The candidate scheme with the highest fitness is selected as the allocation scheme between the task cluster and the computing nodes. Finally, the allocation scheme and processing order of each task and computing node are obtained.

[0013] Furthermore, within each task cluster, optimizing the processing order of each task based on execution dependencies, correlations, real-time cycles, and hardware adaptability specifically involves: Within the same task cluster, tasks are executed in the following order according to priority: First, tasks with data dependencies and execution order constraints are executed in priority; second, tasks with high real-time requirements are scheduled first; third, highly related tasks are arranged adjacently; and finally, tasks with the same hardware preferences are executed consecutively.

[0014] Furthermore, the hybrid search operator includes a task allocation operator, a resource mapping operator, an execution sorting operator, and a local optimization operator, specifically: Task allocation operator and resource mapping operator are basic mandatory operators and are always enabled; execution sorting operator and local optimization operator are enhanced operators and are adaptively enabled based on task cluster type and task correlation within the cluster. Task allocation operator: responsible for the allocation and adjustment of task clusters to computing nodes, ensuring that all tasks within the same task cluster are allocated to the same computing node for execution; Resource mapping operator: responsible for mapping and adjusting the task cluster to the hardware chip within the computing node, ensuring that all tasks within the same task cluster are executed using the same hardware chip; Execution ordering operator: responsible for adjusting the execution order, parallel timing, and synchronization strategy of tasks within the same task cluster; Local optimization operator: Based on hardware adaptability and system constraints, it performs local optimization on the basis of a determined computing node and hardware chip allocation scheme.

[0015] Based on the above technical solution, the present invention has at least the following beneficial effects: This invention, through the aforementioned innovative design, achieves a complete technical solution encompassing in-memory computing as the underlying support, efficient collaboration among heterogeneous hardware, joint optimization at the compiler layer, intrinsic security throughout the entire process, and two-stage adaptive scheduling. Compared to existing embodied intelligent robot chip architectures, this invention overcomes the low energy efficiency and high latency issues caused by the traditional von Neumann architecture's separation of computation and storage, reduces communication overhead between heterogeneous hardware, improves task parallelism and data locality, and achieves a shift in security mechanisms from external monitoring to intrinsic immunity. Furthermore, through forward-looking load prediction and adaptive evolutionary scheduling, it significantly improves resource utilization and system real-time performance, better meeting the practical needs of embodied intelligent robots in industrial, service, and inspection scenarios for high computing power, low latency, low power consumption, high security, and high reliability. It effectively compensates for the shortcomings of existing technologies in terms of versatility, real-time performance, energy efficiency, and security. Attached Figure Description

[0016] Figure 1 This is a framework diagram of a heterogeneous collaborative computing cluster based on CPU, GPU, and FPGA. Figure 2 This is a schematic diagram of inter-task communication within a heterogeneous collaborative computing cluster framework. Figure 3 This is a schematic diagram of a direct communication mechanism between a GPU and an FPGA based on PCIe. Figure 4 A design scheme diagram for an efficient instruction set and compiler security framework for in-memory computing; Figure 5 A schematic diagram illustrating the optimization of the compilation process using a feedback-based performance evaluation mechanism interpreted using runtime graphs; Figure 6 This is a schematic diagram of a scheduling optimization method based on evolutionary computation. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] Although the steps in this invention are arranged by reference numerals, this is not intended to limit the order of the steps. Unless the order of the steps is explicitly stated or the execution of a step requires other steps as a basis, the relative order of the steps can be adjusted. It is understood that the term "and / or" as used herein refers to and covers any and all possible combinations of one or more of the associated listed items.

[0019] This invention proposes a chip security architecture for embodied intelligent robots, which specifically includes: The heterogeneous collaborative computing cluster consists of multiple computing nodes, each integrating a CPU, GPU, FPGA, and in-memory computing chip. Based on the traditional parallel processing mechanism, and taking full account of the storage structure characteristics of the GPU, the cluster adopts a two-level parallel mechanism at the hardware level, combining inter-node parallelism and intra-node parallelism. The GPU and FPGA establish a bidirectional direct communication link with each other as master and slave through the PCIe bus, bypassing the CPU memory for direct data transmission. In this embodiment, a high-performance, large-scale heterogeneous collaborative computing architecture cluster is constructed using multi-core CPUs and many-core GPUs as components. To meet the processing requirements of various complex tasks, this embodiment incorporates FPGAs into the CPU / GPU collaborative computing architecture and achieves direct message passing between the GPU and FPGA via the PCIe bus. Ultimately, a large-scale heterogeneous collaborative computing cluster based on CPU / GPU / FPGA is established, providing comprehensive computing power support for the efficient solution of various complex tasks. Figure 1 The diagram shows the framework of the heterogeneous collaborative computing cluster of the present invention.

[0020] In a preferred embodiment, the two-level parallel mechanism is specifically as follows: Inter-node parallelism: Distributed storage is used among computing nodes, with each computing node storing data independently. Process-level tasks between computing nodes communicate data through the message passing mechanism of the MPI programming model. Intra-node parallelism: Within a single computing node, the CPU runs logical processing tasks, while the GPU runs fine-grained, intensive computing tasks; a storage method combining distributed and shared storage is adopted, with the GPU having independently accessible video memory and sharing the system main memory with the CPU; data sharing between the CPU and GPU is achieved through a main memory / video memory mapping mechanism.

[0021] like Figure 1 As shown, in this embodiment, the entire heterogeneous collaborative computing cluster will consist of multiple task flows; data communication between task flows will be controlled by a message passing mechanism based on the MPI (Massage Passing Interface) programming model. Figure 2 As shown, cluster nodes A and B communicate via the "send" and "receive" functions of the MPI interface. By constructing a corresponding message buffer within each node, a producer-consumer relationship is established between the two nodes. In the heterogeneous cluster, the node acting as the producer writes data to the message buffer and controls it. When the buffer is full, it triggers a signal to call the corresponding interface to send data. Nodes acting as consumers read data from the buffer and update their status simultaneously.

[0022] Each task flow includes a logic processing main control program module running on the CPU and a large-scale kernel computing module running on the GPU. The logic processing main control program running on the CPU still uses the traditional programming model, while the large-scale kernel computing module running on the GPU uses the OpenCL programming model to complete data-level parallel computing between fine-grained, high-density core units within the GPU. Within a heterogeneous cluster node, since the CPU and GPU have independently accessible system main memory and video memory, in order to reduce the data communication overhead between CPU logical tasks and GPU computing kernel tasks, and to fully utilize the advantages of OpenCL for heterogeneous platform programming, a main memory / video memory mapping mechanism is adopted to achieve data sharing between the two.

[0023] To quickly process various complex tasks, this invention incorporates FPGA into a CPU / GPU collaborative computing cluster architecture. Given that FPGA-based in-memory computing, AI processing, and communication task processing platforms that are closer to the task have high requirements for computing power and real-time performance, a direct communication mechanism between the GPU and FPGA must be established.

[0024] Therefore, as a preferred implementation, this embodiment establishes direct GPU and FPGA communication via the PCIe bus to reduce data read / write latency, such as... Figure 3 As shown, communication between the three computing units is achieved by setting up a PCIe bus between the CPU, GPU, and FPGA. Under this communication architecture, the GPU and FPGA can communicate directly, overcoming the shortcomings of read operations in PCIe communication where the GPU is the host controller. At the same time, each communication data only passes through the PCIe switch once, and the communication information is not copied to the CPU memory. In PCIe bus connection mode, the GPU and FPGA form a bidirectional communication link with each other as master and slave: When the GPU acts as the master and the FPGA acts as the slave, the FPGA's memory is mapped to the PCIe bus for the GPU to read and write directly. When the FPGA acts as the master and the GPU acts as the slave, the GPU's read and write operations on the FPGA's memory are first implemented in the manner of the GPU acting as the master, and then the GPU Direct RDMA interface is extended to implement read and write operations on the GPU's memory.

[0025] In this heterogeneous collaborative computing cluster, the GPU corresponds to the brain (cognitive decision-making), the FPGA corresponds to the cerebellum (real-time control), and the CPU corresponds to the brainstem / system central nervous system (scheduling and security management). The three correspond one-to-one with the brain-cerebellum-body architecture and work together, corresponding to the hierarchical heterogeneous collaborative architecture of the embodied intelligent robot.

[0026] Compiler security frameworks for in-memory computing, such as Figure 4 As shown, a compilation toolchain is constructed through machine description normalization and programming semantic extension; the compilation toolchain is used for compilation, and the compilation process is divided into two stages: mechanism analysis and strategy implementation, compiling operators into hardware code; security verification is carried out by comprehensively considering multi-dimensional information to ensure the safe and reliable operation of the embodied intelligent system; finally, a feedback performance evaluation mechanism is established to continuously optimize the compilation process.

[0027] As a preferred embodiment, such as Figure 4 As shown in this embodiment, the construction of the compilation toolchain through machine description normalization and programming semantic extension specifically involves: Machine description standardization: A method combining hierarchical hardware abstraction layer (HAL) modeling and instruction set architecture (ISA) formal description is adopted to provide a unified abstract representation of CPUs, GPUs, FPGAs, and in-memory computing chips. Each hardware chip in the heterogeneous collaborative computing cluster is abstracted into three categories of standard hardware objects. A hardware-independent intermediate representation (IR) and a unified operation semantic interface are constructed, encapsulating memory access, computation, and synchronization control into standard primitives. A hardware capability attribute table is established to standardize the declaration of computing power type, data bit width, parallelism, access latency, and communication bandwidth. Instruction set commonalities are discovered through opcode clustering, operand pattern matching, and data flow feature extraction. These commonalities include general computation, general memory access, general control, and in-memory computing-specific instructions. Finally, machine description text for the in-memory computing architecture is generated, including in-memory computing-specific fields, heterogeneous communication descriptions, real-time latency constraints, and security attribute tags. A compiler is a program that maps high-level programming languages ​​to low-level hardware languages; for in-memory computing applications, the advantages of in-memory computing architecture must be highlighted. Therefore, the instruction set designed takes into account the specific needs of specific scenarios. Through the above-mentioned machine description standardization operations, this application can achieve the synchronization and vectorization of computation and storage when facing massive computation and storage, breaking through the limitations of bandwidth and clock frequency of traditional architectures, and also laying the foundation for hardware-level compilation process optimization.

[0028] The machine description text in this application differs from traditional machine descriptions in the following ways: New in-memory computing-specific fields: including attributes not found in traditional machine descriptions, such as near-memory computing units, in-situ operations, and storage array parallelism; Supports heterogeneous collaborative communication description: explicitly describes hardware direct connection paths such as PCIe / RDMA / NoC, while traditional descriptions are only for single-core / homogeneous systems; Parallelism and Real-Time Declarations: Added latency levels, throughput, and parallelizable dimensions to adapt to real-time robot control; Embedded security attributes: Built-in permission domains, trusted execution, and access control tags support intrinsic security.

[0029] Programming semantic extension: Semantic definition of in-memory computing compilation, clarifying the semantic boundaries of scalar computing, vector computing, tensor computing, in-memory coupling, near-memory access, and hardware synchronization; at the same time, semantics are extracted in the scope of computation graph representation, semantics are extracted in the scope of operator acceleration, and in-memory coupling semantics are extracted for in-memory architecture. In this embodiment, semantic extraction within the scope of computation graph representation includes: unifying computational logic such as neural network operators, robot kinematics solution, and multimodal perception fusion into data flow directed graph semantics, explicitly representing data producer-consumer relationships, execution dependencies, and parallel executable regions, and extracting core semantic information such as tensor dimensions, data layout, memory access locality, and loop iteration domains. Semantic extraction within the scope of operator program acceleration includes: extracting hardware-accelerated semantic features such as parallel granularity, pipeline stages, data rearrangement methods, and computation reuse modes from operator implementations for three types of typical robot tasks: computationally intensive, communication-intensive, and control-intensive, and mapping them to the hardware capabilities of CPU / GPU / FPGA / in-memory computing units. Semantic extraction of in-memory computing coupling: For in-memory computing architecture, we have extracted exclusive semantics such as in-situ computing, near-memory computing, parallel storage array, and non-moving computing. This clarifies the execution mode in which computing operations are performed directly in the storage unit without data movement, which is different from the traditional "read first, then compute, then write" semantics.

[0030] Based on semantic definition and semantic refinement, we form semantic representations of in-memory computation coupling, computation graph representations of tensor programs, and semantic representations related to data transmission. On the basis of traditional parallel computing semantics, we add in-memory computation coupling semantics, near-memory access semantics, data flow driven semantics, real-time control semantics, and intrinsic safety constraint semantics. We design and implement tensor operators to form a compilation toolchain that supports in-memory computation.

[0031] In this embodiment, the semantic representation of in-memory computation coupling, the computation graph representation of tensor programs, and the semantic representation related to data transmission are all standardized semantic expressions further formed on the basis of the semantic definition and semantic refinement of in-memory computation integration. The three, together with the semantic definition and semantic refinement mentioned above, constitute a complete semantic extension process: First, the semantic boundary of in-memory computation integration is clarified through semantic definition; second, semantic refinement is completed through the categories of computation graph representation, operator program acceleration, and in-memory computation coupling characteristics; finally, the refined semantic information is standardized and described by the semantic representation of in-memory computation coupling, the computation graph representation of tensor programs, and the semantic representation related to data transmission, forming a unified semantic representation that can be directly recognized by the compilation toolchain, providing a semantic foundation for subsequent tensor operator implementation, code generation, and optimization.

[0032] By constructing a programming semantic model, this invention evolves the programming interface of the in-memory computing model based on the traditional model, enabling efficient sharing or transmission of data and control flow coordination among various computing and storage resources. Finally, combining the characteristics of the in-memory computing architecture, a complete compilation toolchain is designed and implemented, thereby maximizing the performance of the reconfigurable in-memory computing prototype chip for intelligent applications in scenarios such as collaborative heterogeneous computing and large-scale I / O operations.

[0033] As a preferred embodiment, such as Figure 4 As shown, in this embodiment, the compilation process using a compilation toolchain is divided into two stages: mechanism analysis and strategy implementation. Specifically, compiling the operator into hardware code involves: Mechanism analysis stage: Affine transformations are performed on nested loops based on a polyhedral model, and the nested loops are constructed into an affine transformation matrix for an in-memory computing architecture. This affine transformation matrix is ​​the mathematical foundation and starting point for subsequent mechanism analysis, and provides a unified geometric and algebraic expression framework for subsequent algebraic abstraction. The affine transformation matrix is ​​abstracted into algebraic operations of affine functions, iterative vectors, and data dependency matrices to obtain the integer set of the scheduling algorithm. This transforms the nested execution order, data dependency, and parallel constraints into a computable mathematical form, completing the key transformation from geometric polyhedra to algebraic equations. It inherits the modeling results and provides computable objects for scheduling solutions. The scheduling algorithm solves the integer set by using integer linear programming or scheduling tree search, and outputs a legal loop schedule that satisfies the hardware execution constraints, directly providing an executable scheduling basis for the strategy implementation stage; Strategy implementation phase: Operator parallelism and locality analysis are performed based on a polyhedral model: Operator parallelism is defined as the number of iteration dimensions / thread-level parallelism that an operator can execute simultaneously without breaking data dependencies; Operator locality is defined as the degree of data reuse in time / space, cache hit trend, and memory access continuity of the operator; In this embodiment, the computation graph, operator type, tensor shape, data dependency matrix, legal loop scheduling, affine transformation matrix, and machine description are used as inputs. The maximum parallel iteration space dimension and vectorizable length are used to quantify operator parallelism, and the reuse distance and cache miss rate are used to predict and quantify operator locality. Based on the analysis results of operator parallelism and locality, an architecture-adaptive scheduling generation is performed: for CPUs, multi-threaded parallelism, loop-based block scheduling, and instruction reordering scheduling are generated; for GPUs, three-level parallelism (grid, block, and thread) and shared memory block scheduling are generated; for FPGAs, pipelining parallelism, bit-width matching, and systolic array scheduling are generated; for in-memory computing units, near-memory scheduling, in-situ computation scheduling, and no-shift execution sequences are generated. The scheduler automatically selects a matching scheduling template based on the hardware capability attribute table in the machine description and generates a legal execution order. The in-memory computing unit is the smallest hardware execution unit in the in-memory computing chip. The in-memory computing chip is actually a complete chip device that includes multiple in-memory computing units, peripheral circuits, control logic, and interfaces.

[0034] A multi-level cache collaborative allocation and minimum cost data flow deployment algorithm is adopted to achieve automated cache allocation and data deployment (automated cache allocation and data deployment are implemented based on data characteristics, storage level and scheduling constraints, and are not directly performed according to the legal execution order), deploying hot data, computationally intensive data and streaming data to the corresponding storage level as needed; In the strategy implementation phase, operator parallelism and locality analysis provide the core basis, architecture adaptive scheduling generation provides a legal execution order, automated cache allocation and data deployment ensure execution efficiency, and finally, based on the legal execution order and data deployment results, hardware-executable code is output through the target architecture code generation stage. Thus, through the implementation of compiler optimization functions and corresponding runtime support, the compiler compiles programs with a high degree of abstraction into intelligent code that is efficiently executed for a specific computing platform.

[0035] In a preferred embodiment, the establishment of a feedback performance evaluation mechanism for continuous optimization of the compilation process includes: By combining automatic feedback mechanisms with manual parameter tuning, the entire compilation process, including instruction scheduling and memory management, is continuously optimized. Figure 5 As shown; An optimization parameter search space is established, which includes loop allocation parameters (block size, block dimension, loop order), parallel configuration parameters (number of threads, parallel dimension, vectorization length), cache allocation parameters (data layout, reuse strategy, prefetch length), data flow scheduling parameters (execution order, synchronization point, communication timing), in-memory computing architecture parameters (in-situ computing enablement, near-memory execution mode, array parallelism), and security constraint parameters (permission verification level, data isolation granularity, trusted execution region). The operator features are extracted using the operator feature disjunction method. These features include computational features (operator type, computational intensity, number of MACs, data bit width), memory access features (memory access mode, data reuse, consecutive access length), structural features (tensor dimension, iteration depth, dependency relationship, parallel dimension), locality features (temporal reuse, spatial reuse, cache hit trend), hardware adaptation features (suitability for CPU / GPU / FPGA / in-memory computing units), and security features (whether sensitive data is involved, whether trusted execution is required). Feature vectors are used to represent these features and then pruning and clustering them. The operator features after vector representation, pruning, and clustering are used to construct the optimization parameter search space, provide input for the deep learning automatic optimization model, guide hardware adaptive scheduling and security verification decisions, and reduce the complexity of the optimization search, ultimately achieving efficient automatic optimization in the compilation process. Using deep learning, code is generated with initial parameters such as loop block size, parallel dimension, vectorization length, and security check level. The code is then run on the target hardware and feedback data including latency, utilization, cache hit rate, power consumption, data migration amount, and security check time are collected. The cost estimation function is constructed and iterated based on feedback data; the cost estimation function under different combinations of optimization parameters is predicted using a machine learning model; and the combination of optimization parameters that minimizes the cost estimation function is selected as the optimal combination of parameters. Security checks are performed simultaneously during the optimization process: based on task security level, data sensitivity level, hardware permission domain, access behavior, communication security, real-time constraints, and system status, security dilemmas, including unauthorized access, illegal execution, and timing anomalies, are identified through a security state machine and trusted verification points to ensure the safe operation of the system. After optimization and security verification, the optimal compilation strategy was determined for in-memory computing architecture and robot target task scenarios.

[0036] Furthermore, this application also discloses a resource scheduling method for a chip security architecture for embodied intelligent robots, specifically including: Collect real-time load data (such as the usage of computing resources such as processors, memory, and communication bandwidth in each computing node) of the heterogeneous collaborative computing cluster when the embodied robot is solving different complex tasks; use big data preprocessing techniques such as data cleaning, data integration, data reduction, and data transformation to remove dirty data from the real-time load data; Based on the preprocessed real-time load data, the predicted load of each computing node is obtained using a data-driven model to establish a computing node resource scheduling method, realize dynamic allocation of computing resources, and reduce system energy consumption; the data-driven model includes an integrated moving average autoregressive model (ARIMA) and a random forest model. In this embodiment, the ARIMA model is used as an example to introduce the main idea of ​​computing node load prediction.

[0037] First, the preprocessed node loads are sorted chronologically, and the resulting load sequence data is stabilized using d-order differencing. Then, the autocorrelation coefficient of the stabilized load sequence is calculated. and partial autocorrelation coefficient The load at time t is predicted using the following formula. ; ; Where n is the number of autoregressive terms and m is the number of moving average terms. For constant terms, The error can be calculated from the load data at the current time and the historical observation time p. Considering the sudden nature of load changes in computing nodes, the prediction results obtained using only the ARIMA model may contain significant errors. Therefore, based on the idea of ​​ensemble learning, we propose to combine multiple prediction models such as ARIMA and random forest to improve the performance of the prediction method. The ARIMA model is used to fit the linear trend and periodic changes of the computing node load, while the random forest model is used to fit the nonlinear fluctuations and sudden changes in the load. By calculating the prediction errors of each model in the historical window, higher weights are assigned to models with smaller errors. The prediction results of the two models are then adaptively weighted and fused to obtain the final node load prediction value. This combination method fully leverages the prediction advantages of different models, improving the prediction accuracy and robustness of the node load of embodied intelligent robots, and is particularly suitable for scenarios where the load fluctuates suddenly.

[0038] Based on the predicted load, and considering the architectural characteristics of different computing tasks and computing nodes, an evolutionary computing-based scheduling optimization method is adopted to determine the allocation scheme between computing tasks and computing nodes. As a preferred embodiment, in this embodiment, such as Figure 6 As shown, the specific steps for determining the allocation scheme between computing tasks and computing nodes using an evolutionary computation-based scheduling optimization method, based on predicted load and considering the architectural characteristics of different computing tasks and computing nodes, are as follows: By utilizing machine learning techniques, a computing node performance model is constructed by comprehensively considering the inherent attributes of computing nodes and the performance preferences of different computing architectures for different computing tasks. The inherent attributes of computing nodes include the hardware model, number of cores, storage capacity, communication bandwidth, computing power precision, real-time capability, and security capability of CPU / GPU / FPGA. The performance preferences include: CPU is suitable for logic / control intensive tasks, GPU is suitable for computation / data parallel tasks, FPGA is suitable for communication / real-time tasks, and in-memory computing chips are suitable for memory access / near-memory computing tasks. The computing node performance model uses execution time, utilization, bandwidth, power consumption, real-time performance, and security adaptability as quantitative indicators to output a score on the adaptability between tasks and computing nodes. Based on the predicted load, computing nodes whose load exceeds a preset threshold are filtered out to form a candidate computing node set; Using a divide-and-conquer approach, the correlation between tasks is measured from four dimensions: data correlation, execution dependency correlation, resource requirement correlation, and real-time correlation. Tasks with a correlation higher than a preset threshold are grouped into the same task cluster. Each task cluster is treated as an independent sub-scheduling problem. All tasks within the same task cluster are assigned to the same computing node and executed using the same type of hardware chip within that computing node.

[0039] Within each task cluster, the processing order of each task is optimized based on execution dependencies, correlations, real-time cycles, and hardware compatibility. As a preferred implementation, the specific processing order of tasks within a cluster is as follows: Within the same task cluster, tasks are executed in the following order based on priority: First, tasks with data dependencies and execution order constraints are executed in priority; second, tasks with high real-time requirements are scheduled first based on real-time cycle priority; third, highly related tasks are arranged adjacently to improve data locality and resource reuse efficiency; and finally, tasks with the same hardware preferences are executed consecutively to reduce hardware switching and resource reconfiguration overhead.

[0040] An evolutionary algorithm is used to optimize the scheduling of each sub-scheduling problem. Task clusters are assigned to a specific hardware chip on a specific computing node in a candidate computing node set for execution. During the scheduling optimization phase, task clusters are used as the basic allocation unit, and task clusters are bound to computing nodes for optimization. An individual in the evolutionary algorithm is represented as a candidate scheme for assigning a task cluster to a certain type of hardware chip on a computing node. The fitness value of each individual is the fitness score between the task cluster and the computing node. The fitness score between the task cluster and the computing node is the weighted sum or arithmetic mean of the fitness scores between all tasks and computing nodes within the cluster.

[0041] In this embodiment, when calculating the suitability score between task clusters and computing nodes, if there are differences in task characteristics within the cluster and uneven load on computing nodes, a weighted summation value is used. The weighted summation weight is set according to the task's computational load, resource usage ratio, importance, or real-time priority. If dealing with scenarios where task characteristics are similar and the load is balanced, the arithmetic mean can be used directly.

[0042] Design a hybrid search operator to adjust the search direction based on task type, performance preference, and relevance between tasks, and iteratively generate candidate assignment schemes; In a preferred embodiment, the hybrid search operator includes a task allocation operator, a resource mapping operator, an execution sorting operator, and a local optimization operator, specifically: Task allocation operator and resource mapping operator are basic mandatory operators and are always enabled; execution sorting operator and local optimization operator are enhanced operators and are adaptively enabled based on task cluster type and task correlation within the cluster. Task allocation operator: responsible for the allocation and adjustment of task clusters to computing nodes, ensuring that all tasks within the same task cluster are allocated to the same computing node for execution; Resource mapping operator: responsible for mapping and adjusting the task cluster to the hardware chip within the computing node, ensuring that all tasks within the same task cluster are executed using the same hardware chip; Execution ordering operator: responsible for adjusting the execution order, parallel timing, and synchronization strategy of tasks within the same task cluster; Local optimization operator: Based on hardware adaptability and system constraints, it performs local optimization on the basis of a determined computing node and hardware chip allocation scheme.

[0043] In this embodiment, to address the different optimization requirements of different types of task clusters, a combination of execution sorting operators and local optimization operators is used to achieve differentiated adaptive scheduling: For computationally intensive task clusters (performance-oriented GPUs), the execution sorting operator and local optimization operator are enabled. Based on the completion of node allocation and hardware mapping, the parallel execution timing is optimized, the computational parallelism is improved, and the scheduling switching overhead is reduced. For communication / real-time intensive task clusters (performance-oriented FPGAs), the execution ordering operator and local optimization operator are enabled to ensure the deterministic timing of task execution, reduce end-to-end latency, and meet real-time constraints; For memory-intensive task clusters (performance-biased in-memory computing chips), the execution sorting operator and local optimization operator are enabled to optimize the data near-memory deployment and in-situ computing strategy, reducing data migration; For logic / control intensive task clusters (CPU-intensive), enable execution ordering operators and local optimization operators to optimize the execution order of control flow and reduce control overhead and scheduling complexity.

[0044] Furthermore, while the overall correlation within the same task cluster is high, there are still strong and weak correlations among subtasks: for combinations of subtasks with high task correlation and tight data dependencies, the execution sorting operator is used to adjust to serial execution to ensure consistency of execution logic; for combinations of subtasks with low task correlation and no strong data dependencies, the execution sorting operator enables parallel execution within the same node and the same hardware chip to improve system throughput; the local optimization operator performs fine-grained parameter adjustments and resource balancing within the legal solution space determined by task allocation and resource mapping, including fine-tuning of execution latency, optimization of cache ratio, optimization of bandwidth allocation, and optimization of parallel sharding. Unlike traditional global search algorithms, the local optimization operator used in this application has local hardware awareness and real-time constraint awareness capabilities, which can quickly converge to obtain the optimal and most stable scheduling scheme, making it more suitable for the high real-time and high-reliability computing requirements of embodied intelligent robots.

[0045] The candidate scheme with the highest fitness is selected as the allocation scheme between the task cluster and the computing nodes; finally, the allocation scheme and processing order of each task and computing node are obtained.

[0046] In summary, this invention proposes a chip security architecture and resource scheduling method for embodied intelligent robots, which can overcome the energy efficiency loss caused by the separation of computing and storage in traditional architectures. At the same time, by embedding interpretable decision and scheduling algorithms, it overcomes bottlenecks such as lagging security protection, and realizes a paradigm shift in system security protection from "external monitoring" to "endogenous immunity".

[0047] In this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to at least one embodiment or example described in connection with a specific feature, structure, material, or characteristic. These specific features, structures, materials, or characteristics may be combined in a suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples and their features described in this specification.

[0048] The logic and / or steps shown in the flowchart or otherwise described can be viewed as a sequence of executable instructions for implementing logical functions. These instructions may be implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device. Such systems, apparatus, or devices include processor systems or other systems capable of receiving and executing instructions.

[0049] The above embodiments detail the principles and implementation methods of the present invention, and illustrate its working principle using specific examples. These examples are only used to help understand the method and core ideas of the present invention. Furthermore, based on the ideas of the present invention, actual implementation methods and application scope may vary. Therefore, the content of this specification should not be construed as limiting the present invention.

Claims

1. A chip security architecture for embodied intelligent robots, characterized by, Specifically, it includes: The heterogeneous collaborative computing cluster consists of multiple computing nodes, each of which integrates a CPU, GPU, FPGA, and in-memory computing chip. The cluster adopts a two-level parallel mechanism that combines inter-node parallelism and intra-node parallelism; the GPU and FPGA establish a bidirectional direct communication link between each other via the PCIe bus, bypassing the CPU memory for direct data transmission; A compiler security framework for in-memory computing is proposed, which constructs a compiler toolchain through machine description normalization and programming semantic extension. The compiler toolchain is used for compilation, and the compilation process is divided into two stages: mechanism analysis and policy implementation, which compiles operators into hardware code. Security verification is carried out by comprehensively considering multi-dimensional information, and a feedback performance evaluation mechanism is established to continuously optimize the compilation process. The heterogeneous resource integrated scheduling module is coupled with the compilation security framework and the heterogeneous collaborative computing cluster, and is used to allocate tasks to the most suitable hardware chip of the optimal computing node in the heterogeneous collaborative computing cluster based on load prediction and task type. After the task data enters the heterogeneous collaborative computing cluster, it is processed by the in-memory computing chip for computing-storage fusion processing, while the compilation security framework for in-memory computing performs affine transformation and security verification. After the security check is passed, the task is sent to the heterogeneous resource integrated scheduling module for allocation decision, which assigns the task to the most suitable hardware chip of the best computing node in the heterogeneous collaborative computing cluster for execution. During the execution process, the running data is fed back to the heterogeneous resource integrated scheduling module and the compilation security framework for in-memory computing in real time, and the scheduling strategy and security strategy are iteratively optimized until the task is completed.

2. The chip security architecture for embodied intelligence oriented robot according to claim 1, wherein, The two-level parallel mechanism is specifically as follows: Inter-node parallelism: Distributed storage is used among computing nodes, with each computing node storing data independently. Process-level tasks between computing nodes communicate data through the message passing mechanism of the MPI programming model. Intra-node parallelism: Within a single computing node, the CPU runs logical processing tasks, while the GPU runs fine-grained, intensive computing tasks; a storage method combining distributed and shared storage is adopted, with the GPU having independently accessible video memory and sharing the system main memory with the CPU; data sharing between the CPU and GPU is achieved through a main memory / video memory mapping mechanism.

3. The chip security architecture for embodied intelligence oriented robot according to claim 1, wherein, The GPU and FPGA establish a bidirectional direct communication link via the PCIe bus, bypassing the CPU and memory for direct data transmission. Direct GPU and FPGA communication is established via the PCIe bus, with each communication data passing through the PCIe switch only once and without copying the communication information into the CPU memory. When the GPU acts as the master and the FPGA acts as the slave, the FPGA's memory is mapped to the PCIe bus for the GPU to read and write directly. When the FPGA acts as the master and the GPU acts as the slave, the GPU's read and write operations on the FPGA's memory are first implemented in the manner of the GPU acting as the master, and then the GPU Direct RDMA interface is extended to implement read and write operations on the GPU's memory.

4. A chip security architecture for embodied intelligent robots according to claim 1, characterized in that, The construction of the compilation toolchain through machine description normalization and programming semantic extension specifically involves: Machine description standardization: A method combining hierarchical hardware abstraction layer (HAL) modeling and instruction set architecture (ISA) formal description is adopted to provide a unified abstract representation of CPUs, GPUs, FPGAs, and in-memory computing chips. Each hardware chip in the heterogeneous collaborative computing cluster is abstracted into three categories of standard hardware objects. A hardware-independent intermediate representation (IR) and a unified operation semantic interface are constructed, encapsulating memory access, computation, and synchronization control into standard primitives. A hardware capability attribute table is established to standardize the declaration of computing power type, data bit width, parallelism, access latency, and communication bandwidth. Instruction set commonalities are discovered through opcode clustering, operand pattern matching, and data flow feature extraction. These commonalities include general computation, general memory access, general control, and in-memory computing-specific instructions. Finally, machine description text for the in-memory computing architecture is generated, including in-memory computing-specific fields, heterogeneous communication descriptions, real-time latency constraints, and security attribute tags. Programming Semantic Extension: Semantic definition is performed on in-memory computing compilation, clarifying the semantic boundaries of scalar computation, vector computation, tensor computation, in-memory coupling, near-memory access, and hardware synchronization. Semantics are extracted within the scope of computation graph representation and operator acceleration, and in-memory coupling semantics are extracted for in-memory architecture. Based on semantic definition and extraction, semantic representations of in-memory coupling, computation graph representations of tensor programs, and data transmission related semantic representations are formed. On the basis of traditional parallel computing semantics, in-memory coupling semantics, near-memory access semantics, data flow driven semantics, real-time control semantics, and intrinsic safety constraint semantics are added. Tensor operators are designed and implemented to form a compilation toolchain that supports in-memory computing.

5. A chip security architecture for embodied intelligent robots according to claim 1, characterized in that, The compilation process using a compiler toolchain is divided into two stages: mechanism analysis and policy implementation. Specifically, the compilation of the operator into hardware code involves: Mechanism analysis stage: Based on the polyhedral model, affine transformations are performed on nested loops to construct an affine transformation matrix for in-memory computing architecture. The affine transformation matrix is ​​abstracted into algebraic operations of affine functions, iterative vectors, and data dependency matrices, resulting in the integer set of scheduling algorithms; The scheduling algorithm is solved by solving the integer set through integer linear programming or scheduling tree search, and the output is a legal loop schedule that satisfies the hardware execution constraints. Strategy implementation phase: Operator parallelism and locality analysis are performed based on a polyhedral model. The inputs include computation graph, operator type, tensor shape, data dependency matrix, legal loop scheduling, affine transformation matrix, and machine description. Operator parallelism is quantified by the maximum parallel iteration space dimension and vectorizable length, while operator locality is quantified by reuse distance and cache miss rate prediction. Based on the analysis results of operator parallelism and locality, adaptive scheduling is generated for the architecture: multi-threaded parallelism, loop block scheduling, and instruction rearrangement scheduling are generated for CPU; three-level parallelism (grid, block, and thread) and shared memory block scheduling are generated for GPU; and pipelined parallelism, bit width matching, and systolic array scheduling are generated for FPGA. The in-memory computing unit generates near-memory scheduling, in-situ computing scheduling, and non-moving execution sequences; the scheduler automatically selects a matching scheduling template based on the hardware capability attribute table in the machine description and generates a legal execution order; the in-memory computing unit is the smallest hardware execution unit in the in-memory computing chip; Employing a multi-level cache collaborative allocation and minimum-cost data flow deployment algorithm, we achieve automated cache allocation and data deployment, deploying hot data, computationally intensive data, and streaming data to the corresponding storage levels as needed. Based on the legal execution order and data deployment results, hardware executable code is output through the target architecture code generation stage.

6. A chip security architecture for embodied intelligent robots according to claim 1, characterized in that, The establishment of a feedback-based performance evaluation mechanism for continuous optimization of the compilation process includes: By combining automatic feedback mechanisms with manual parameter adjustment, the instruction scheduling, memory management, and security verification processes are optimized. An optimization parameter search space is established, wherein the optimization parameters include cyclic allocation parameters, parallel configuration parameters, cache allocation parameters, data flow scheduling parameters, in-memory computing architecture parameters, and security constraint parameters; The computational features, memory access features, structural features, locality features, hardware adaptation features, and security features of operators are extracted using the operator feature disjunction method. Feature vectors are used to represent these features, and pruning and clustering are then performed. Using deep learning, code is generated with initial parameters such as loop block size, parallel dimension, vectorization length, and security check level. The code is then run on the target hardware and feedback data including latency, utilization, cache hit rate, power consumption, data migration amount, and security check time are collected. The cost estimation function is constructed and iterated based on feedback data; the cost estimation function under different combinations of optimization parameters is predicted using a machine learning model; and the combination of optimization parameters that minimizes the cost estimation function is selected as the optimal combination of parameters. Security checks are performed simultaneously during the optimization process: based on task security level, data sensitivity level, hardware permission domain, access behavior, communication security, real-time constraints, and system status, security dilemmas, including unauthorized access, illegal execution, and timing anomalies, are identified through a security state machine and trusted verification points to ensure the safe operation of the system. After optimization and security verification, the optimal compilation strategy was determined for in-memory computing architecture and robot target task scenarios.

7. A resource scheduling method for a chip security architecture for embodied intelligent robots according to any one of claims 1-6, characterized in that, Specifically, it includes: Collect real-time load data of each computing node in the heterogeneous collaborative computing cluster when the embodied robot is solving different complex tasks; preprocess the real-time load data to remove dirty data; Based on the preprocessed real-time load data, the predicted load of each computing node is obtained using a data-driven model, which includes an integrated moving average autoregressive model and a random forest model. Based on the predicted load, and considering the architectural characteristics of different computing tasks and computing nodes, an evolutionary computing-based scheduling optimization method is adopted to determine the allocation scheme between computing tasks and computing nodes. The computing tasks are allocated to each computing node according to the allocation plan, and the CPU, GPU or FPGA in the computing node are arranged to execute them.

8. A resource scheduling method for a chip security architecture for embodied intelligent robots according to claim 7, characterized in that, The specific steps for determining the allocation scheme between computing tasks and computing nodes based on the predicted load, considering different computing tasks and the architectural characteristics of computing nodes, and employing an evolutionary computation-based scheduling optimization method are as follows: By utilizing machine learning techniques, a computing node performance model is constructed by comprehensively considering the inherent attributes of computing nodes and the performance preferences of different computing architectures for different computing tasks. The inherent attributes of computing nodes include the hardware model, number of cores, storage capacity, communication bandwidth, computing power precision, real-time capability, and security capability of CPU / GPU / FPGA. The performance preferences include: CPU is suitable for logic / control intensive tasks, GPU is suitable for computation / data parallel tasks, FPGA is suitable for communication / real-time tasks, and in-memory computing chips are suitable for memory access / near-memory computing tasks. The computing node performance model uses execution time, utilization, bandwidth, power consumption, real-time performance, and security adaptability as quantitative indicators to output a score on the adaptability between tasks and computing nodes. Based on the predicted load, computing nodes whose load exceeds a preset threshold are filtered out to form a candidate computing node set; Using a divide-and-conquer approach, the correlation between tasks is measured from four dimensions: data correlation, execution dependency correlation, resource requirement correlation, and real-time correlation. Tasks with a correlation higher than a preset threshold are divided into the same task cluster. Each task cluster is treated as an independent sub-scheduling problem. All tasks within the same task cluster are assigned to the same computing node and executed using the same type of hardware chip within that computing node. Within each task cluster, the processing order of each task is optimized based on execution dependencies, correlations, real-time cycles, and hardware compatibility. An evolutionary algorithm is used to optimize the scheduling of each sub-scheduling problem. Task clusters are assigned to a specific hardware chip on a specific computing node in a candidate computing node set for execution. In the scheduling optimization phase, task clusters are used as the basic allocation unit, and task clusters are bound to computing nodes for optimization. An individual of the evolutionary algorithm is represented as a candidate scheme for assigning a task cluster to a certain type of hardware chip on a computing node. The fitness value of each individual is the fitness score between the task cluster and the computing node. The fitness score between the task cluster and the computing node is the weighted sum or arithmetic mean of the fitness scores between all tasks and computing nodes in the cluster. A hybrid search operator is designed to adjust the search direction based on task type, performance preference, and relevance between tasks, and to iteratively generate candidate allocation schemes. The candidate scheme with the highest fitness is selected as the allocation scheme between the task cluster and the computing nodes. Finally, the allocation scheme and processing order of each task and computing node are obtained.

9. A resource scheduling method for a chip security architecture for embodied intelligent robots according to claim 8, characterized in that, Within each task cluster, the specific steps for optimizing the processing order of each task based on execution dependencies, correlations, real-time cycles, and hardware compatibility are as follows: Within the same task cluster, tasks are executed in the following order according to priority: First, tasks with data dependencies and execution order constraints are executed in priority; second, tasks with high real-time requirements are scheduled first; third, highly related tasks are arranged adjacently; and finally, tasks with the same hardware preferences are executed consecutively.

10. A resource scheduling method for a chip security architecture for embodied intelligent robots according to claim 8, characterized in that, The hybrid search operator includes a task allocation operator, a resource mapping operator, an execution sorting operator, and a local optimization operator, specifically: Task allocation operator and resource mapping operator are basic mandatory operators and are always enabled; execution sorting operator and local optimization operator are enhanced operators and are adaptively enabled based on task cluster type and task correlation within the cluster. Task allocation operator: responsible for the allocation and adjustment of task clusters to computing nodes, ensuring that all tasks within the same task cluster are allocated to the same computing node for execution; Resource mapping operator: responsible for mapping and adjusting the task cluster to the hardware chip within the computing node, ensuring that all tasks within the same task cluster are executed using the same hardware chip; Execution ordering operator: responsible for adjusting the execution order, parallel timing, and synchronization strategy of tasks within the same task cluster; Local optimization operator: Based on hardware adaptability and system constraints, it performs local optimization on the basis of a determined computing node and hardware chip allocation scheme.

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