A strong puf method and system against machine learning attacks
By introducing S-BOX nonlinear confusion and cascaded LFSR post-processing circuits into a strong PUF, the linear relationship between excitation and response is disrupted, solving the problems of insufficient security and excessive power consumption of strong PUF in machine learning attacks, and achieving a balance between high security and low power consumption.
Patent Information
- Application Number
- CN202610618867.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-07
- Publication Date
- 2026-07-31
AI Technical Summary
Existing strong PUFs lack sufficient security against machine learning attacks, and their post-processing circuits consume excessive power, affecting device stability and battery life.
The original excitation is obfuscated by S-BOX nonlinear obfuscation processing, and the response is processed by cascaded LFSR post-processing circuit modules to build a dual protection system, which disrupts the linear relationship between excitation and response and reduces power consumption.
It effectively reduced the prediction accuracy of machine learning models for CRP, reduced the power consumption of post-processing circuits, improved the security and stability of strong PUF, and achieved a balance between high security and low power consumption.
Smart Images
Figure CN122490602A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit security and hardware circuit design technology, and relates to a strong PUF anti-machine learning attack method and system based on stimulus obfuscation and LFSR post-processing. Background Technology
[0002] Physically unclonable functions (PUFs), as an emerging hardware security primitive, have gained widespread attention and application in fields such as the Internet of Things (IoT) and information security in recent years. Their working mechanism utilizes the unpredictable, minute process variations generated during integrated circuit manufacturing. These variations cannot be precisely replicated even under identical manufacturing processes and design conditions, giving each chip a unique "fingerprint." PUFs operate through challenge-response pairs (CRPs). When a specific challenge signal (stimulus) is input, the chip generates a corresponding output (response) based on its unique physical characteristics. This characteristic gives PUFs significant advantages in scenarios such as chip anti-counterfeiting, identity authentication, and key generation and storage. For example, they are used in military chips and IoT devices to ensure hardware authenticity, and in smart card chips to prevent financial fraud.
[0003] Based on the number of Request for Proof (CRPs), PUFs can be divided into two categories: weak PUFs and strong PUFs. Weak PUFs have a smaller number of CRPs, and their CRP space grows linearly with the number of entropy sources, exhibiting good randomness and a low bit error rate. Strong PUFs, on the other hand, have a number of CRPs that are exponentially related to the stimulus length, and are typically used for device security authentication. Theoretically, if the stimulus-response process of a strong PUF is considered as a function with a finite number of unknown parameters, an attacker, after collecting some leaked CRPs, can use machine learning or deep learning algorithms to build a mathematical model to accurately predict unknown CRPs, thereby creating a serious security vulnerability.
[0004] To address this challenge, various anti-attack techniques have been proposed, such as stimulus-response obfuscation and structural nonlinearity techniques. However, existing solutions generally have shortcomings. While some improved solutions can enhance anti-attack capabilities to a certain extent, they often come with a significant increase in hardware resource consumption. For example, patent application CN120223084A discloses a PUF structure and authentication method based on delay difference quantization. This method uses an LFSR obfuscation structure to divide the final quantized data OUT into two parts. By associating the initial seed and shift count, which affect the LFSR output, with the quantized data, and considering that the quantized data originates from the symmetrical path delay difference of the PUF, the nonlinear entropy source in the PUF exhibits a highly nonlinear relationship between challenge and response under the unpredictable state transitions of the LFSR. However, regarding power consumption control in PUF post-processing circuits, many current PUF LFSR post-processing circuits suffer from high power consumption during operation. Traditional single LFSR circuits cannot guarantee good pseudo-randomness in data processing while controlling power consumption. In power-sensitive applications such as IoT devices and portable electronic products, high power consumption will not only shorten the device's battery life, but may also cause problems such as overheating, affecting the device's stability and lifespan. Summary of the Invention
[0005] The technical problem to be solved by this invention is how to improve the safety performance of strong PUF and reduce the power consumption of strong PUF post-processing circuit.
[0006] The present invention solves the above-mentioned technical problems through the following technical solutions: A strong PUF (Programmable Array Component) method for resisting machine learning attacks includes the following steps: Receive the original stimulus C, and perform S-BOX nonlinear obfuscation processing on the original stimulus C to obtain the obfuscated stimulus C'; The confusion stimulus C' is input to the strong PUF module, and the original response R is generated according to the physical characteristics of the strong PUF module; The original response R is input to the LFSR post-processing circuit module for post-processing to generate the final response R'.
[0007] Furthermore, the original excitation C has a bit width of m, and the m-bit original excitation signal C is divided into k sub-blocks with a bit width of 8. ,in .
[0008] Furthermore, the S-BOX nonlinear obfuscation processing of the original excitation C specifically involves: First, use the pre-set S-BOX data replacement lookup table to process each sub-block. Perform a replacement mapping and output the obfuscated excitation sub-block. Then use the data merging module to merge all Obtaining the confusing excitation signal .
[0009] Furthermore, the lookup table for the preset S-BOX data replacement is generated based on the AES algorithm.
[0010] Furthermore, the post-processing specifically involves: inputting the original response signal R into the first LFSR, triggering the second LFSR through gated clock logic with the output of the first LFSR, and outputting the final response signal R' from the second LFSR.
[0011] Furthermore, the first LFSR and the second LFSR are in a cascaded structure, and the first LFSR is configured as follows: p The second LFSR is configured as follows: (Fibonacci LFSR, second LFSR configuration is...) q The Fibonacci LFSR is a non-zero initial seed.
[0012] Furthermore, when the strong PUF module is of the multi-bit input single-bit output type, the original response signal R is extended, specifically as follows: Multiple strong PUF modules are configured, and the m independent strong PUF modules are parallelized. The same confused excitation signal C' is input to each strong PUF module to generate an m-bit raw response. , This represents the original response signal output by the m-th strong PUF module.
[0013] This invention also provides a system based on the above-mentioned strong PUF anti-machine learning attack method, including a controller module, and a serial port receiving module, an S-BOX nonlinear excitation obfuscation module, a strong PUF module, an LFSR post-processing circuit module, and a serial port transmitting module connected in sequence; the serial port receiving module receives the original excitation signal C sent by the host computer, generates an effective signal and sends it to the S-BOX nonlinear excitation obfuscation module, the S-BOX nonlinear excitation obfuscation module generates an obfuscated excitation C' and sends it to the strong PUF module, the strong PUF module generates the original response R and sends it to the LFSR post-processing circuit module, the LFSR post-processing circuit module generates the final response R' and sends it to the host computer through the serial port transmitting module for CRPs analysis.
[0014] Furthermore, the S-BOX nonlinear excitation confusion module includes a lookup table for pre-set S-BOX data replacement and a data merging module; The LFSR post-processing circuit module includes a gated clock AND gate, a first LFSR, and a second LFSR. The first LFSR and the second LFSR have the same structure. The input and output terminals of the first LFSR are respectively connected to the first input and the second input terminals of the gated clock AND gate, and the output terminal of the gated clock AND gate is connected to the second LFSR.
[0015] Furthermore, the first LFSR includes a D flip-flop, a MUX, and an XOR gate; multiple D flip-flops are cascaded, the output of each D flip-flop is connected to the first input of the corresponding MUX, the second input of the MUX is set to 0, the data selection terminal of the MUX is connected to the input of the LFSR, the output of the MUX is connected to the first input of the corresponding XOR gate, the second input of the XOR gate is connected to the output of the next stage XOR gate, the output of the first stage XOR gate is connected to the input of the corresponding D flip-flop, the second input of the last stage XOR gate is set to 0, the CLK terminals of all D flip-flops are connected together, and the reset terminals of all D flip-flops are connected together.
[0016] The advantages of this invention are: This invention constructs a dual protection system combining "nonlinear excitation obfuscation" and "response post-processing": at the front end, the excitation signal is nonlinearly obfuscated using an S-BOX and the original excitation signal is nonlinearly obfuscated using a lookup table, disrupting its direct linear correlation with the input of the strong PUF module, thereby blocking the attacker's modeling path; at the back end, a dual LFSR cascaded structure triggered by a gated clock is adopted, especially the design logic of LFSR_A triggering LFSR_B, which ensures that the data after post-processing the response has high pseudo-randomness while reducing the power consumption of the post-processing circuit.
[0017] The method provided by this invention prevents the obfuscation stimulus C' and the original response R from being disclosed externally. Attackers can only obtain the obfuscated mapping of (CR'), thus hiding the CRP and preventing attackers from building an effective model. Furthermore, the stimulus obfuscation module and the LFSR post-processing circuit module form a two-level mapping relationship, forcing attackers to crack both mapping relationships simultaneously, which greatly reduces the prediction accuracy.
[0018] This invention hides the real stimulus-response pairs through a two-level mapping relationship, making it impossible for attackers to build an effective prediction model. It effectively reduces the prediction accuracy of machine learning models for the CRP of strong PUFs to about 50%, and effectively controls the power consumption of the LFSR post-processing circuit while ensuring the randomness of the output response. This fundamentally improves the security of strong PUFs and achieves a balance between the performance and low power consumption of the post-processing circuit. It helps to solve the problems of traditional strong PUFs being vulnerable to machine learning modeling attacks and the excessive power consumption of the post-processing circuit, and provides a practical hardware security primitive that combines high security and low power consumption. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the structure of the strong PUF anti-machine learning attack system according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of the strong PUF module in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure of the S-BOX nonlinear excitation confusion module according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the LFSR post-processing circuit module according to Embodiment 1 of the present invention; Figure 5 This is a flowchart of the strong PUF anti-machine learning attack method of Embodiment 1 of the present invention; Figure 6 This is a comparison chart of the results of the strong PUF anti-machine learning attack method of Embodiment 1 of the present invention and the existing APUF anti-attack method. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 As shown, specifically, this invention proposes a strong PUF anti-machine learning attack system, including a controller module, and a serial port receiving module, an S-BOX nonlinear excitation obfuscation module, a strong PUF module, an LFSR post-processing circuit module, and a serial port transmitting module connected in sequence; the serial port receiving module receives the original excitation signal C (original challenge data) sent by the host computer, generates an effective signal and sends it to the S-BOX nonlinear excitation obfuscation module, the S-BOX nonlinear excitation obfuscation module generates an obfuscated excitation C' and sends it to the strong PUF module, the obfuscated excitation C' generated by the S-BOX nonlinear excitation obfuscation module (… Figure 1 The signal (s_box_challenge) is also sent to the controller module. The controller module outputs a small pulse signal (signal) and inputs it to the strong PUF module. The strong PUF module generates the original response R( Figure 1 The response is sent to the LFSR post-processing circuit module, which then generates the final response R'. Figure 1The response (LSFR_response) is sent to the host computer via a serial port transmission module for CRP analysis.
[0022] like Figure 3 As shown, the S-BOX nonlinear excitation confusion module includes a lookup table for preset S-BOX data replacement and a data merging module.
[0023] like Figure 4 As shown, the LFSR post-processing circuit module includes a gated clock AND gate, an LFSR_A connected to the front end of the gated clock AND gate, and an LFSR_B connected to the back end. The two LFSRs have the same structure, consisting of several cascaded D flip-flops. The output of the D flip-flops is connected to a MUX, the data selection terminal of the MUX is connected to the input stimulus, and the output is connected to an XOR gate for feedback.
[0024] Specifically, the LFSR post-processing circuit module includes a gated clock AND gate, a first LFSR ( Figure 4 The middle is LFSR_A) and the second LFSR ( Figure 4 (The first LFSR is LFSR_B). The input and output terminals of the first LFSR are connected to the first and second input terminals of the gated clock AND gate, respectively, and the output terminal of the gated clock AND gate is connected to the second LFSR.
[0025] In this embodiment, the first LFSR and the second LFSR have the same structure. Taking the first LFSR as an example, the first LFSR includes a D flip-flop, a MUX, and an XOR gate. Multiple D flip-flops are cascaded. The output of each D flip-flop is connected to the first input of the corresponding MUX. The second input of the MUX is set to 0. The data selection terminal of the MUX is connected to the input of the LFSR. The output of the MUX is connected to the first input of the corresponding XOR gate. The second input of the XOR gate is connected to the output of the next stage XOR gate. The output of the first stage XOR gate is connected to the input of the corresponding D flip-flop. The second input of the last stage XOR gate is set to 0. The CLK terminals of all D flip-flops are connected together, and the reset terminals of all D flip-flops are connected together. Specifically, the CLK terminal is the clock input terminal.
[0026] In this embodiment, the MUX is specifically a 2-to-1 multiplexer, with the data selection terminal of the MUX used to connect to the input excitation and the output terminal used to connect to the XOR gate for feedback.
[0027] In this embodiment, the strong PUF module can be any strong PUF circuit that requires performance optimization against machine learning attacks, including but not limited to typical APUF, ROPUF, and improved XOR-APUF, CROPUF, etc. This embodiment uses APUF as an example for illustration. Figure 2 As shown.
[0028] like Figure 5 As shown, this invention proposes a strong PUF (Power-Only Functional Array) method to resist machine learning attacks, comprising the following steps: Step 1: Determine the strong PUF type, input excitation signal bit width, and communication method.
[0029] In this embodiment, the bit width of the input raw stimulus signal is first determined based on any type of strong PUF module. Then, the external input raw stimulus signal C is generated by the host computer using Python. The raw stimulus signal C has a bit width of m. The m-bit raw stimulus signal C is then divided into k sub-blocks with a bit width of 8. ,in Sub-blocks of external input excitation C It receives and stores data, while generating data validity control signals to ensure timing synchronization.
[0030] Next, the communication method is determined. The communication method for the system to receive the original excitation signal C and output the final response R' can be any one of UART serial communication, SPI communication or Ethernet communication.
[0031] In this embodiment, a 16-bit stimulus input arbiter PUF (APUF) is used as the strong PUF module. The 16-bit APUF determines the data width of the input stimulus C to be 16 bits, and UART serial communication is used as the communication method with the host computer. The host computer uses a Python script to divide the 16-bit external input stimulus signal C as the original challenge data into 8-bit blocks to obtain sub-blocks. Through the input terminal of the serial port receiving module ( Figure 1 The system receives the data (using UART_RX) and stores the received stimulus in a register as input stimulus C. When the external stimulus signal arrives, the serial port receiving module receives the input data byte by byte (8 bits) and generates a valid signal (...). Figure 1 The signal is set to rx_valid to ensure timing synchronization, and then sent to the S-BOX nonlinear excitation obfuscation module for excitation replacement and obfuscation. The serial port receiving module receives data from the host computer via the Uart_rx input. After receiving the data, the serial port receiving module stores it in a register and generates a data valid signal (rx_valid). A high rx_valid signal indicates that the value in the register is currently valid and usable. Figure 1 The word "challenge" is used in this context.
[0032] like Figure 2 As shown, specifically, the strong PUF module includes a 16-level delay path and an arbitrator structure. Each delay path includes two completely symmetrical MUXs. The data selection terminal of the MUX inputs the sub-block corresponding to the current level delay path. The first input and second input of each of the two MUXs in the first-stage delay path are connected to a signal. The output of each MUX is connected to the first input of one MUX and the second input of another MUX in the next-stage delay path, and so on. The outputs of the two MUXs in the last stage are connected to the input and reset of the arbiter structure, respectively. The arbiter structure is specifically a D flip-flop, which generates a one-bit original response with the arbiter through the internal path delay difference.
[0033] In this embodiment, the function of the signal is to input into the strong PUF module. After the signal is split into two and propagated through two paths, the two signal signals will show a trend of one before the other. Such a pulse signal input into the D flip-flop can output 0 or 1, which respectively represent that the upper path delay is lower or the lower path delay is lower.
[0034] Step 2: Receive the original excitation signal C, and perform S-BOX nonlinear obfuscation processing on the original excitation signal C to obtain the obfuscated excitation signal C'.
[0035] In this embodiment, the original excitation signal C received by the serial port receiving module is input to a preset S-BOX nonlinear excitation obfuscation module for processing. The S-BOX nonlinear excitation obfuscation module in this embodiment uses a pure digital logic lookup table (LUT) structure, which is a fixed S-BOX lookup table generated based on the AES algorithm. The input original excitation is split into 8-bit sub-blocks, directly replaced by nonlinear mapping in the lookup table, and then merged and output. The S-BOX nonlinear obfuscation processing in this embodiment is essentially a static nonlinear mapping based on an encryption algorithm (AES algorithm). It does not require additional "sub-PUF" hardware overhead, nor does it involve complex timing iterative feedback. Instead, it utilizes the strong nonlinear mathematical characteristics of the S-BOX to directly disrupt the linear relationship between excitation and response, resulting in a simpler circuit implementation and stronger determinism.
[0036] Specifically, S2 involves: first, using a lookup table for pre-set S-BOX data replacement to process each sub-block... Perform a replacement mapping and output the obfuscated excitation sub-block. Then use the data merging module to merge all Obtaining the confusing excitation signal This is used to disrupt the linear mapping relationship between the original excitation signal C and the output of the strong PUF module, making it impossible for attackers to restore the valid input through inverse transformation; wherein, the lookup table for the preset S-BOX data replacement is generated based on the AES algorithm.
[0037] like Figure 3 As shown, specifically, the 16-bit original excitation signal C input from the host computer is divided into 8-bit blocks in step 1 and then divided into sub-blocks. The input is in the form of S-BOX nonlinear excitation obfuscation module, which performs 8-bit replacement mapping through a lookup table and outputs the corresponding 8-bit obfuscated excitation sub-block. Then, the 8-to-16 bit data merging module is used to merge all the data. 16-bit confusing excitation signal obtained Specifically, the data merging module is an 8-to-16-bit FIFO module.
[0038] Step 3: Input the confusion excitation signal C' into the strong PUF module, and generate the original response signal R according to the physical characteristics of the strong PUF module.
[0039] In this embodiment, the 16-bit obfuscated excitation output by the S-BOX nonlinear excitation obfuscation module is used. The input is fed into the 16-bit APUF circuit, and the challenge signal (specifically the ambiguity excitation signal in this embodiment) is processed according to the physical parameters of the PUF module (APUF circuit in this embodiment). It responds and outputs the original response signal R.
[0040] Furthermore, for the strong PUF module with multi-bit input and single-bit output, the original response signal R is extended. Specifically, multiple strong PUF modules are set up in the system, and the m independent strong PUF modules are parallelized. The same confusion excitation signal C' is input to each strong PUF module to generate an m-bit original response. , This represents the original response signal output by the m-th strong PUF module.
[0041] Taking this embodiment with 16-bit input and 1-bit output as an example, 16 APUF circuits are set up in the system and parallelized. Each circuit receives the same confusion excitation signal C' and generates a 16-bit original response. .
[0042] In this embodiment, since a strong PUF module with multi-bit input and single-bit output can only produce a unique response, parallelizing the strong PUF module can output multi-bit response signals, enhancing the randomness of the entropy source and greatly improving output entropy and parallelism. To ensure that the delays of the two transmission paths are as equal as possible, this embodiment imposes placement constraints (symmetrical layout) and necessary delay adjustments on the MUX and other components of the APUF to optimize randomness and balance the output. Specifically, the APUF layout constraints in this embodiment include the following two parts: Device-level placement constraints: To overcome the asymmetry caused by automatic placement and routing in FPGA development tools, the physical coordinates (Site) of each switching unit MUX are manually locked in the FPGA development tool, which forces the switching unit MUX of the two delay paths to be strictly symmetrical in physical space; wherein, the FPGA development tool can be the Vivado design suite.
[0043] Module-level region constraints (Pblock): The APUF core logic, LFSR post-processing circuit and serial port FIFO module are respectively confined to specific regions of the FPGA chip to ensure timing convergence and facilitate resource isolation during uniqueness testing.
[0044] Furthermore, the multi-bit raw response output by the strong PUF module, or the multi-bit raw response generated after parallelization, is acquired and stored. Simultaneously, a data validity control signal is generated to ensure timing synchronization and subsequent data post-processing. The multi-bit raw response is kept internally and not leaked externally, effectively preventing attackers from directly obtaining it.
[0045] Step 4: Input the original response signal R into the LFSR post-processing circuit module for post-processing to generate the final response signal R'.
[0046] In this embodiment, the post-processing specifically involves: inputting the original response signal R to the first LFSR, triggering the second LFSR through the gated clock logic with the output of the first LFSR, and outputting the final response signal R' from the second LFSR.
[0047] In this embodiment, the first LFSR and the second LFSR in the LFSR post-processing circuit module are cascaded, and the first LFSR is configured as follows: p The 1 / 2 Fibonacci LFSR is initialized with a non-zero seed to generate sequences with high linear complexity. The second LFSR is configured as follows: q A Fibonacci LFSR is used to generate a final response signal with high pseudo-randomness by triggering a second LFSR from a first LFSR through a gated clock AND gate. This results in low-power generation of the final response signal. The response is pseudo-randomized, which significantly reduces power consumption compared to the LFSR post-processing circuit of a single LFSR.
[0048] like Figure 4 As shown, specifically, the 16-bit raw response signal R is input to the LFSR for post-processing to generate the final response. Both the first and second LFSRs are configured as 8-bit Fibonacci LFSRs, with an initial seed of 0x55, used to generate sequences with high linear complexity. The first and second LFSRs have identical structures; each LFSR consists of eight cascaded D flip-flops. The output of each D flip-flop is connected to the first input of the corresponding MUX, the second input of the MUX is set to 0, the data selection terminal of the MUX is connected to the input of the LFSR (i.e., the original response signal R), and the output of the MUX is connected to an XOR gate to receive feedback information.
[0049] The LFSR post-processing circuit module proposed in this embodiment differs from the traditional LFSR in the following ways: First, compared to the fixed structure of traditional LFSRs, each LFSR in this embodiment contains multiple MUXs. The 16-bit raw response signal R generated by the strong PUF module is directly connected to the data selection terminal of the MUX. Each bit in the raw response signal R directly determines whether the feedback tap of the corresponding stage register is connected to an XOR gate. If a bit responds as "1", it indicates that the feedback path of that stage is on; if it is "0", it is off. This embodiment dynamically changes the characteristic polynomial (feedback topology) of the LFSR using the response, rather than simply changing the seed. This means that for different PUF responses, the circuit structure of the LFSR itself undergoes a physical-level reconstruction, and the complexity of the pseudo-random sequence it generates is far higher than that of a fixed-polynomial LFSR.
[0050] Secondly, compared to the power consumption control of traditional LFSRs, this embodiment uses a serially cascaded structure of the first and second LFSRs in the LFSR post-processing circuit module. The first LFSR is driven by the system clock, but the clock input of the second LFSR is controlled by the feedback output of the first LFSR through an AND gate. Only when the shift output of the first LFSR is 1 (high level) can the clock signal be transmitted to the second LFSR through the AND gate, triggering the second LFSR to operate once. Since the probability of the first LFSR outputting 0 and 1 is close to 50%, the second LFSR remains stationary (does not flip) for about half the time. In contrast, traditional LFSRs operate continuously. In this embodiment, the dynamic flip rate of the second LFSR is reduced by about 50%, thus significantly reducing the overall power consumption of the post-processing circuit. Furthermore, the non-uniform stepping method of controlling the stepping of LFSR_B by the pseudo-random sequence of LFSR_A results in a non-linear exponential increase in the period and complexity of the final output sequence, making its resistance to machine learning far superior to simple parallel or single-stage LFSRs.
[0051] Finally, the most fatal weakness of the strong PUF module lies in the extremely strong linear relationship between the input stimulus (Challenge) and the internal delay path, making it very easy for attackers to fit the delay parameters through machine learning. Before the stimulus enters the physical circuit, the highly nonlinear mathematical properties of the S-BOX scramble the original stimulus space, isolating the "original stimulus" collected by the attacker from the "physical stimulus" that actually acts on the PUF through a mathematical barrier. After the response output, the topology reconstruction LFSR processing is performed again. If only post-processing is used, attackers can still deduce the linear model of the PUF kernel through a large amount of data. Therefore, this embodiment constructs a double nonlinear mapping by destroying the input linearity through the front-end S-BOX and the output linearity through the back-end LFSR. This structure forces attackers to simultaneously crack two nonlinear functions (AES S-BOX and reconfigurable LFSR) and the intermediate physical unidirectional function, resulting in an exponential increase in computational complexity.
[0052] Furthermore, the final response output of the LFSR post-processing circuit module. It performs data acquisition and storage, and generates data validity control signals to ensure timing synchronization and subsequent data post-processing.
[0053] Furthermore, the final response is transmitted via a serial port module. The signal is sent to the host computer for CRP analysis. Specifically, in this embodiment, the 16-bit final response signal is... Using the communication method determined in step 1, the 16-bit data is split into two 8-bit data blocks using a 16-to-8-bit FIFO module, and then the data is serially sent to the host computer using an 8-bit UART.
[0054] In this embodiment, CRPs are analyzed by performing various performance tests on the strong PUF module. Specifically, after receiving the data, the host computer analyzes the data and calculates the test indicators to detect the improvement or change in the machine learning resistance performance of the strong PUF module after adding the S-BOX nonlinear excitation confusion module and the LFSR post-processing circuit module. The test indicators include machine learning resistance performance and randomness.
[0055] In a preferred embodiment, the improved machine learning resistance of the enhanced strong PUF is determined using the following logic: The prediction accuracy of the final response R' was tested using a variety of machine learning algorithms to evaluate its resistance to machine learning attacks. These algorithms included logistic regression (LR), support vector machine (SVM), and multilayer perceptron (MLP).
[0056] In a preferred embodiment, the randomness of judging the improved strong PUF is determined using the following logic: The randomness of the final response R' was tested using the NIST SP800-22 statistical test suite, which contains 15 independent statistical tests designed to evaluate the randomness of binary sequences from multiple perspectives.
[0057] This invention aims to address the security issues of strong physically unclonable functions (PUFs), especially for strong PUF type circuits, when facing machine learning modeling attacks, and simultaneously optimize the balance between power consumption and random performance in their post-processing circuits.
[0058] This invention constructs a dual protection system combining "nonlinear excitation obfuscation" and "response post-processing": at the front end, the excitation signal is nonlinearly obfuscated using an S-BOX and the original excitation signal is nonlinearly obfuscated using a lookup table, disrupting its direct linear correlation with the input of the strong PUF module, thereby blocking the attacker's modeling path; at the back end, a dual LFSR cascaded structure triggered by a gated clock is adopted, especially the design logic of LFSR_A triggering LFSR_B, which ensures that the data after post-processing the response has high pseudo-randomness while reducing the power consumption of the post-processing circuit.
[0059] The method provided by this invention enables confusion stimulation. and the original response It is not disclosed to outsiders; attackers can only obtain... The obfuscation mapping effectively hides the CRP (Confirmation of Probability), preventing attackers from building an effective model. Furthermore, the excitation obfuscation module and the LFSR post-processing circuit module form a two-level mapping relationship, forcing attackers to simultaneously crack both layers of mapping, significantly reducing prediction accuracy.
[0060] like Figure 6 Figure (a) shows the results of a machine learning attack resistant scheme based on the classic APUF. The prediction accuracy using various machine learning algorithms, including logistic regression (LR), support vector machine (SVM), and multilayer perceptron (MLP), remains in the range of 60%–70% (SVM and LR) and 80%–90% (MLP). However, as... Figure 6(b) illustrates the strong PUF anti-machine learning attack method proposed in this embodiment, which reduces the prediction accuracy of the aforementioned machine learning algorithm to the range of 50%~60%. This invention hides the true stimulus-response pairs through a two-level mapping relationship, preventing attackers from establishing an effective prediction model. This effectively reduces the prediction accuracy of the machine learning model for the CRP of the strong PUF to approximately 50%, and effectively controls the power consumption of the LFSR post-processing circuit while ensuring the randomness of the output response. This fundamentally improves the security of the strong PUF and achieves a balance between the performance and low power consumption of the post-processing circuit. It helps solve the problems of traditional strong PUFs being vulnerable to machine learning modeling attacks and the excessive power consumption of the post-processing circuit, providing a practical hardware security primitive that combines high security and low power consumption.
[0061] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for resisting machine learning attacks using a strong PUF (Programmable Array of Elements) is characterized by, Includes the following steps: Receive the original stimulus C, and perform S-BOX nonlinear obfuscation processing on the original stimulus C to obtain the obfuscated stimulus C'; The confusion stimulus C' is input to the strong PUF module, and the original response R is generated according to the physical characteristics of the strong PUF module; The original response R is input to the LFSR post-processing circuit module for post-processing to generate the final response R'.
2. The method for resisting machine learning attacks with strong PUF according to claim 1, characterized in that, The original excitation signal C has a bit width of m. The m-bit original excitation signal C is divided into k sub-blocks with a bit width of 8. ,in .
3. The method for resisting machine learning attacks with strong PUF according to claim 2, characterized in that, The S-BOX nonlinear obfuscation process for the original excitation C is specifically as follows: First, use the pre-set S-BOX data replacement lookup table to process each sub-block. Perform a replacement mapping and output the obfuscated excitation sub-block. Then use the data merging module to merge all Obtaining the confusing excitation signal .
4. A strong PUF anti-machine learning attack method according to claim 3, characterized in that, The lookup table for the preset S-BOX data replacement is generated based on the AES algorithm.
5. A method for resisting machine learning attacks with strong PUF according to claim 3, characterized in that, The post-processing specifically involves: inputting the original response signal R into the first LFSR, triggering the second LFSR through the gated clock logic with the output of the first LFSR, and outputting the final response signal R' from the second LFSR.
6. A method for resisting machine learning attacks with strong PUF according to claim 5, characterized in that, The first LFSR and the second LFSR are in a cascaded structure, and the first LFSR is configured as follows: p The second LFSR is configured as follows: (Fibonacci LFSR, second LFSR configuration is...) q The Fibonacci LFSR is a non-zero initial seed.
7. A method for resisting machine learning attacks with strong PUF according to claim 1, characterized in that, When the strong PUF module is of the multi-bit input single-bit output type, the original response signal R is extended as follows: Multiple strong PUF modules are configured, and the m independent strong PUF modules are parallelized. The same confused excitation signal C' is input to each strong PUF module to generate an m-bit raw response. , This represents the original response signal output by the m-th strong PUF module.
8. A system based on the strong PUF anti-machine learning attack method according to any one of claims 1-7, characterized in that, The system includes a controller module, and a serial port receiving module, an S-BOX nonlinear excitation confusion module, a strong PUF module, an LFSR post-processing circuit module, and a serial port transmitting module connected in sequence. The serial port receiving module receives the original excitation signal C sent by the host computer, generates a valid signal, and sends it to the S-BOX nonlinear excitation confusion module. The S-BOX nonlinear excitation confusion module generates a confused excitation C' and sends it to the strong PUF module. The strong PUF module generates the original response R and sends it to the LFSR post-processing circuit module. The LFSR post-processing circuit module generates the final response R' and sends it to the host computer through the serial port transmitting module for CRPs analysis.
9. A robust PUF anti-machine learning attack system according to claim 8, characterized in that, The S-BOX nonlinear excitation confusion module includes a lookup table for pre-set S-BOX data replacement and a data merging module; The LFSR post-processing circuit module includes a gated clock AND gate, a first LFSR, and a second LFSR. The first LFSR and the second LFSR have the same structure. The input and output terminals of the first LFSR are respectively connected to the first input and the second input terminals of the gated clock AND gate, and the output terminal of the gated clock AND gate is connected to the second LFSR.
10. A robust PUF anti-machine learning attack system according to claim 8, characterized in that, The first LFSR includes a D flip-flop, a MUX, and an XOR gate; multiple D flip-flops are cascaded, the output of each D flip-flop is connected to the first input of the corresponding MUX, the second input of the MUX is set to 0, the data selection terminal of the MUX is connected to the input of the LFSR, the output of the MUX is connected to the first input of the corresponding XOR gate, the second input of the XOR gate is connected to the output of the next stage XOR gate, the output of the first stage XOR gate is connected to the input of the corresponding D flip-flop, the second input of the last stage XOR gate is set to 0, the CLK terminals of all D flip-flops are connected together, and the reset terminals of all D flip-flops are connected together.