Hardware Trojan detection method and system based on multi-modal feature fusion and LLM fine-tuning

Abstract

This invention relates to a hardware Trojan detection method and system based on multimodal feature fusion and LLM fine-tuning, belonging to the field of integrated circuit hardware security detection technology. It addresses the problem of improving the detection accuracy of LLM in detecting RTL-level hardware Trojans. The method includes: structurally merging structural, behavioral, and dynamic features to construct a multimodal joint feature set; generating an instruction fine-tuning dataset based on the multimodal joint feature set and the hardware Trojan detection instruction set; and using a parameter-efficient lightweight fine-tuning method to fine-tune a pre-trained language model using the instruction fine-tuning dataset to obtain a target model optimized for hardware Trojan detection. This invention extracts and fuses multimodal features such as structure, behavior, and dynamics of RTL code to construct an information-dense circuit representation, and uses instruction fine-tuning and LoRA lightweight fine-tuning methods to adaptively train the LLM, achieving high-precision and high-efficiency detection of RTL-level hardware Trojans.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit hardware security detection technology, and relates to a hardware Trojan detection method and system based on multimodal feature fusion and LLM fine-tuning. Background Technology

[0002] With the globalization and increasing complexity of the integrated circuit (IC) industry chain, the risk of hardware malware implantation is rising, posing a serious threat to system functionality, sensitive information, and even national security. Hardware malware detection at the register-transfer level (RTL) in the early stages of IC design is a crucial step in ensuring chip security.

[0003] Currently, methods for detecting hardware trojans at the RTL level can be mainly divided into two categories: static analysis and dynamic analysis. Static analysis methods identify abnormal patterns by parsing the syntactic structure of RTL code, but due to the complexity and abstraction level of the code, it is difficult to understand deep logical semantics. Dynamic analysis methods monitor circuit behavior through simulation, but their effectiveness heavily depends on the coverage of test stimuli, making it difficult to detect hidden trojans with extremely stringent trigger conditions.

[0004] In recent years, machine learning-based detection methods have been developed. For example, the invention patent with publication number CN116522334A discloses an RTL-level hardware Trojan detection method based on graph neural networks. This method flattens the RTL code and extracts the data flow graph, and then uses a graph neural network model for training and detection. However, this approach has the following drawbacks: (1) loss of hierarchical information: the code flattening process may destroy the modular structure information of the design, weakening the detection capability of Trojans disguised by hierarchical design. (2) strong dependence on model training: the performance of graph neural network models is highly dependent on large-scale, high-quality labeled datasets, and model training and graph structure processing consume huge amounts of computing resources.

[0005] With the development of Large Language Model (LLM) technology, a small number of studies have begun to explore its application in the field of hardware security. For example, some researchers have proposed using LLM to generate hardware Trojans or to use it for code vulnerability analysis. For example, the invention patent with publication number CN120068071A discloses a method for generating a gate-level netlist hardware Trojan test set based on a large language model. The method uses prompt words to allow the large language model to provide hardware Trojan design services. Then, the large language model continuously iterates and reflects based on the provided knowledge base and constraints to generate the final design code. However, this method has the following defects: (1) Insufficient feature fusion: The method directly provides the RTL source code of the parent circuit mounted on the LLM and directly uses the RTL source code as the input of the LLM. It fails to effectively integrate the multi-dimensional features such as structure, behavior, and timing contained in the hardware design, which limits the analysis depth of the LLM. (2) Lack of targeted optimization: The method directly uses a general large model for zero-sample or few-sample inference and does not fine-tune the model for the specific task of hardware Trojan detection, resulting in insufficient detection accuracy and reliability. (3) Input length limit: Since RTL code is usually very long, directly inputting LLM will exceed the context window limit of most LLMs, resulting in information loss or analysis failure. Summary of the Invention

[0006] The technical problem to be solved by this invention is how to improve the detection accuracy of LLM in detecting RTL-level hardware Trojans.

[0007] The present invention solves the above-mentioned technical problems through the following technical solutions:

[0008] A hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning includes the following steps: S1, Obtain the source code of the RTL design circuit to be tested, and preprocess the source code of the RTL design circuit to be tested, including code merging and simplification; S2, extract structural features, behavioral features and dynamic features from the preprocessed RTL design circuit source code, and structurally merge the structural features, behavioral features and dynamic features to construct a multimodal joint feature set; S3 establishes a hardware Trojan detection instruction set, including various natural language instructions; S4. Generate an instruction fine-tuning dataset based on the multimodal joint feature set and the hardware Trojan detection instruction set. Each structured data in the instruction fine-tuning dataset is in the form of a triple, including instruction, input, and output. S5 employs a parameter-efficient, lightweight fine-tuning method, using an instruction fine-tuning dataset to fine-tune the pre-trained language model, resulting in a target model optimized for hardware Trojan detection. S6, execute S1~S2 to construct a new multimodal joint feature set for the new circuit under test, and input the hardware Trojan detection instruction set into the target model for reasoning analysis; S7 determines whether the new circuit under test contains a hardware Trojan based on the output of the target model, and evaluates the model performance.

[0009] Furthermore, S2 includes the following: S21, by parsing the AST of the RTL code and extracting structural features, the structural features include module hierarchy, module instantiation relationship, port definition, signal declaration and assignment logic; S22, DFG is generated by logical synthesis of RTL code, and structural features are extracted, including operation nodes and signal dependencies in the data path; S23, by simulating and running the RTL code, dynamic features are extracted, including key signal trajectories; S24. The structural features, behavioral features and dynamic features extracted from S21 to S23 are structurally merged to form a unified multimodal description of the designed circuit and to construct a multimodal joint feature set.

[0010] Further, S21 specifically involves: First, parsing the preprocessed RTL code in S1 using the open-source Verilog parsing tool PyVerilog to generate an AST; then, traversing the AST using a depth-first search algorithm to extract module hierarchy, module instantiation relationships, port definitions, signal declarations, and assignment logic information to form structural features; finally, storing the structural features in JSON format.

[0011] Furthermore, S22 specifically involves: using the open-source logic synthesis tool Yosys to synthesize the RTL code, converting the behavioral-level RTL description into an intermediate representation of gate-level logic and exporting it through Yosys commands, parsing out the DFG from it, and utilizing the characteristic that the DFG can explicitly depict the data path to extract the operation nodes and signal dependencies in the data path as key behavioral features.

[0012] Further, S23 specifically involves: First, using the high-performance Verilog simulator Verilator to simulate the RTL code, converting the Verilog code into a high-performance C++ model and compiling it into an executable file; then, using an automated script to generate a C++ test platform to drive the simulation, applying preset input stimuli to the circuit; next, during the simulation process, using the trace simulator option to generate a VCD waveform file recording the changes in signal values ​​over time; finally, parsing and extracting dynamic features from the VCD file.

[0013] Furthermore, the structured merging described in S24 specifically involves creating a JSON-formatted data object for each circuit sample under test. The data object includes a label field and three keys: structure, behavior, and dynamic, which respectively store structured data representing structural features, behavioral features, and dynamic features.

[0014] Furthermore, the instruction mentioned in S4 is specifically a single instruction randomly or sequentially selected from the hardware Trojan detection instruction set; the input is specifically a complete JSON object containing multimodal features constructed for any circuit in the multimodal joint feature set; the output is specifically the real label of the circuit corresponding to the input, including Trojan-Free and Trojan-Inserted, where Trojan-Free indicates no Trojan and Trojan-Inserted indicates the presence of a Trojan.

[0015] Furthermore, the pre-trained language model mentioned in S5 is specifically Qwen2.5-7B or ChatGLM3-6B; the pre-trained language model is trained in an environment equipped with NVIDIA A100 GPU or higher computing resources using standard low-rank adaptive techniques.

[0016] Furthermore, the model performance evaluation described in S7 specifically involves calculating key performance indicators as model evaluation indicators, including accuracy, precision, true positive rate, true negative rate, false negative rate, false negative rate, and F1 score.

[0017] This invention also provides a hardware Trojan detection system based on multimodal feature fusion and LLM fine-tuning, comprising: The preprocessing module is used to obtain the source code of the RTL design circuit under test and to preprocess the source code of the RTL design circuit under test, including code merging and simplification. The multimodal feature extraction module is used to extract structural features, behavioral features and dynamic features from the preprocessed RTL design circuit source code, and to structurally merge the structural features, behavioral features and dynamic features to construct a multimodal joint feature set; The detection instruction module is used to establish a hardware Trojan detection instruction set, including various natural language instructions; The dataset generation module generates an instruction fine-tuning dataset based on a multimodal joint feature set and a hardware Trojan detection instruction set. Each structured data item in the instruction fine-tuning dataset is in the form of a triple, including instruction, input, and output. The model fine-tuning module is used to fine-tune the pre-trained language model using a parameter-efficient and lightweight fine-tuning method with an instruction fine-tuning dataset to obtain a target model optimized for hardware Trojan detection. The reasoning and analysis module is used to perform preprocessing on the new circuit under test to construct a new multimodal joint feature set from the preprocessing module to the multimodal feature extraction module, and to input the hardware Trojan detection instruction set into the target model for reasoning and analysis. The model evaluation module is used to determine whether a new circuit under test contains a hardware Trojan based on the output of the target model, and to evaluate the model performance.

[0018] The advantages of this invention are: This invention proposes a hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning. By systematically fusing multimodal hardware features and performing efficient and targeted fine-tuning of LLM, it successfully solves many limitations of existing technologies in RTL hardware Trojan detection, providing a high-precision and high-efficiency innovative solution. It overcomes the problems of insufficient semantic understanding in static analysis, limited coverage in dynamic analysis, and the failure of existing LLM application methods to effectively fuse multi-dimensional hardware features and lack of targeted optimization in existing technologies.

[0019] First, by extracting and fusing the multimodal features of RTL code, such as structure, behavior, and dynamics, this invention constructs a circuit representation that is more information-intensive than pure source code. It can comprehensively capture the multidimensional characteristics of the circuit and effectively identify complex hardware Trojans that employ cross-dimensional camouflage strategies.

[0020] Secondly, by constructing an instruction fine-tuning dataset and using the LoRA lightweight method to adaptively train the LLM, this invention enables the model to learn the hidden patterns of hardware Trojans under multi-dimensional features. This significantly improves detection accuracy and recall while greatly reducing the computational and storage resource requirements, allowing the invention to run efficiently even in ordinary hardware environments.

[0021] Finally, the fully automated detection process of this invention covers the entire process from feature extraction to model inference, which not only improves detection efficiency but also lowers the technical threshold, laying a solid foundation for the promotion and application of this method in practical engineering. Attached Figure Description

[0022] Figure 1 This is a flowchart of the hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to Embodiment 1 of the present invention; Figure 2 This is a system block diagram of the hardware Trojan detection system based on multimodal feature fusion and LLM fine-tuning according to Embodiment 1 of the present invention. Figure 3 This is a schematic diagram illustrating the operation of constructing a multimodal joint feature set according to Embodiment 1 of the present invention; Figure 4 This is a comparative diagram of the LORA fine-tuning method of Embodiment 1 of the present invention and the conventional fine-tuning method; Figure 5 This is a schematic diagram comparing the evaluation indicators of Qwen2.5-7B before and after fine-tuning based on the detection method in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram comparing the evaluation indicators of ChatGLM3-6B before and after fine-tuning based on the detection method in Embodiment 1 of the present invention. Figure 7 This is a schematic diagram comparing the evaluation indicators of Gemma-2B before and after fine-tuning based on the detection method in Embodiment 1 of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 Specifically, a hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning is disclosed, including: S1. Obtain the source code of the RTL design circuit to be tested, and preprocess the source code of the RTL design circuit to be tested, including code merging and simplification.

[0025] In S1, the RTL design circuit specifically involves obtaining a reference circuit from a public dataset. This embodiment uses reference circuits such as AES and RS232 selected from the TrustHub dataset as examples for illustration.

[0026] First, obtain the source code of the RTL design circuit to be tested; then, use a script to sort multiple Verilog source code files with the .v extension of the same circuit topologically according to module dependencies and merge them into one file; next, use regularization methods such as regularization expressions to remove comments and blank lines in the code and optimize the code format to reduce the complexity of subsequent processing.

[0027] S2, extract structural features, behavioral features, and dynamic features from the preprocessed RTL design circuit source code, and structurally merge these features to construct a multimodal joint feature set. For example... Figure 3 As shown, S2 includes the following specific contents: S21, by parsing the AST of the RTL code and extracting structural features, the structural features include module hierarchy, module instantiation relationship, port definition, signal declaration and assignment logic.

[0028] In step S21, structural features are extracted from static code to capture the organizational structure and syntactic elements of the RTL design circuit. Specifically, firstly, the preprocessed RTL design circuit source code (hereinafter referred to as RTL code) in S1 is parsed using the open-source Verilog parsing tool PyVerilog to generate an Abstract Syntax Tree (AST); then, the AST is traversed using a depth-first search algorithm to extract module hierarchy, module instantiation relationships, port definitions, signal declarations, and assignment logic information to form structural features; finally, the structural features are stored in JSON (JavaScript Object Notation) format.

[0029] In a preferred embodiment, a recursive function can be written to traverse the AST based on the tree structure parsed by PyVerilog. For example, starting from the root node of the AST (usually the Source node), its child nodes (such as ModuleDef, Decl, Assign, etc.) can be recursively visited until the leaf nodes are reached. During the traversal, target information containing the above-mentioned structural features is extracted, and finally these structural features are organized and stored in JSON format.

[0030] In this embodiment, the method for obtaining each component of the structural feature is further explained: By identifying all module definitions in the designed circuit and their instantiation call relationships, a module hierarchy tree is constructed, and the module hierarchy and instantiation relationships are extracted.

[0031] The port definition is achieved by extracting the name, direction, and bit width information of the input, output, and bidirectional ports of each module.

[0032] The names and bit widths of signals such as reg and wire declared within the module are used as signal declarations.

[0033] The assignment logic is achieved by identifying and recording the target and expression of continuous assignment statements (assign) and blocking / non-blocking assignment statements within always blocks.

[0034] S22, DFG is generated by logical synthesis of RTL code, and structural features are extracted, including operation nodes and signal dependencies in the data path.

[0035] In step S22, behavioral features of the RTL code are extracted to capture the functionality and logic flow of the designed circuit at the data layer. Specifically, the RTL code is synthesized using the open-source logic synthesis tool Yosys, converting the behavioral-level RTL description into an intermediate representation of gate-level logic and exporting it via Yosys commands. From this, a data flow graph (DFG) is parsed. Utilizing the DFG's ability to explicitly depict data paths, the computational nodes and signal dependencies within the data paths are extracted as key behavioral features.

[0036] In a preferred embodiment, to extract behavioral features from a data flow graph (DFG), the following typical command can be executed: `yosys -p "synth;write_json -"design.v`. This command first synthesizes `design.v`, then exports the synthesized netlist in JSON format (`write_json`). From the exported JSON data structure, the computational nodes (such as `add_op`) representing data paths and the signal dependencies (directed edges) can be parsed, thereby constructing the data flow graph (DFG) as key behavioral features. The computational nodes include all arithmetic logic units that identify the data path, such as adders, XOR gates, multiplexers, etc. The signal dependencies are specifically represented by directed edges in the data flow graph, indicating the dependency of data flowing from one node (such as an input port, register output) to another node (such as an operation unit input, module output).

[0037] S23, by simulating and running the RTL code, dynamic features are extracted, including key signal trajectories.

[0038] In step S23, the trajectory information of key signal values ​​changing over time is obtained by simulating the RTL code, and the timing-related dynamic behavior is captured by simulating the actual operation of the circuit. Specifically, firstly, the RTL code is simulated using the high-performance Verilog simulator Verilator, converting the Verilog code into a high-performance C++ model and compiling it into an executable file; then, an automated script is used to generate a C++ testbench to drive the simulation, applying preset input stimuli to the circuit; next, during the simulation, the trace simulator option is used to generate a VCD (Value Change Dump) waveform file recording the changes of signal values ​​over time; finally, the dynamic features are parsed and extracted from the VCD file.

[0039] The key signal trajectory includes the numerical sequence of the key signal within the simulation cycle. The extraction of dynamic features specifically involves selecting key signals in the design circuit, including signals such as status registers, counters, and main data buses, and recording the numerical sequence of the key signal at each clock cycle or specific time point during the simulation process.

[0040] S24. The structural features, behavioral features and dynamic features extracted from S21 to S23 are structurally merged to form a unified multimodal description of the designed circuit and to construct a multimodal joint feature set.

[0041] In this embodiment, the structured merging specifically involves: taking JSON format as an example, creating a unified data object for each circuit sample under test, with each data object having a clear semantic meaning; the data object is indexed by the circuit file name and includes a label field to indicate its true category as "Trojan-Free" or "Trojan-Inserted"; the main body of the data object contains three keys: structure, behavior, and dynamic, whose values ​​are the structural features, behavioral features, and dynamic features extracted and structured (JSON format) from steps S21, S22, and S23, respectively. Through this key-value pair organization, features from different sources and modalities are aligned to the same circuit entity, forming an information-dense, structurally clear multimodal joint feature set, which can be directly used as the "input" part of the instruction fine-tuning dataset.

[0042] In this embodiment, the multimodal joint feature set constructed in step S24 forms a multimodal joint feature set with high information density that can comprehensively characterize circuit characteristics.

[0043] S3 establishes a hardware Trojan detection instruction set, including various natural language instructions.

[0044] In this embodiment, to guide the large language model to accurately understand the task intent in subsequent steps, a diverse set of hardware Trojan detection instructions is pre-designed and established. This instruction set contains various natural language instructions designed to guide the model in analysis and judgment. The instructions differ in their questioning style, analytical perspective, and language; for example, "Please analyze the provided multimodal features to determine if the circuit contains a hardware Trojan," or "Evaluate the security of this design based on its structure, behavior, and dynamic data." The diversity of the hardware Trojan detection instruction set in this embodiment aims to improve the generalization ability and robustness of the fine-tuned model.

[0045] S4. Generate an instruction fine-tuning dataset based on the multimodal joint feature set and the hardware Trojan detection instruction set. Each structured data in the instruction fine-tuning dataset is in the form of a triple, including instruction, input, and output.

[0046] In this embodiment, the multimodal joint feature set and hardware Trojan detection instruction set constructed in S2~S3 are combined with the real labels of the designed circuit to transform them into structured data containing instruction, input and output triples. By combining all circuit samples and all instructions, an instruction fine-tuning dataset that can be directly used for LLM instruction fine-tuning is generated.

[0047] Specifically, the instruction is a single instruction randomly or sequentially selected from the hardware Trojan detection instruction set. The input is a complete JSON object containing multimodal features constructed for any circuit from the multimodal joint feature set. The output is the actual label of the circuit corresponding to the input, including Trojan-Free and Trojan-Inserted, where Trojan-Free indicates no Trojan and Trojan-Inserted indicates the presence of a Trojan.

[0048] S5 employs a parameter-efficient, lightweight fine-tuning method, using an instruction fine-tuning dataset to fine-tune the pre-trained language model, resulting in a target model optimized for hardware Trojan detection.

[0049] In this embodiment, the pre-trained language model can be a small open-source language model as the base model, including but not limited to Qwen2.5-7B, ChatGLM3-6B, etc.

[0050] In this embodiment, the efficient and lightweight fine-tuning method specifically employs standard low-rank adaptive (LoRA). Preferably, this embodiment provides a fine-tuning parameter configuration for hardware Trojan detection tasks, wherein key fine-tuning parameter settings include a LoRA rank of 8, 4-bit quantization (use_4bit_quantization:true), a learning rate of 2e-4, and 3 training epochs. The pre-trained language model is trained in an environment equipped with NVIDIA A100 GPUs or higher computing resources. During training, only a small number of trainable parameters introduced by LoRA are updated, while most parameters of the main model remain frozen, thereby achieving efficient utilization of computing and storage resources.

[0051] S6: Perform S1~S2 on the new circuit under test to construct a new multimodal joint feature set, and input the hardware Trojan detection instruction set into the target model for inference analysis.

[0052] In this embodiment, after fine-tuning in step S5, a target model optimized for RTL hardware Trojan detection is obtained. When it is necessary to detect a new and unknown RTL circuit, the new circuit under test is first processed through the complete process of steps S1 to S2 to extract features and construct its multimodal joint feature set. Then, an instruction is selected from the instruction set in step S3, and the instruction and the feature set of the new RTL circuit under test are used as input and fed into the fine-tuned target model for inference analysis.

[0053] S7 determines whether the new circuit under test contains a hardware Trojan based on the output of the target model, and evaluates the model performance.

[0054] In this embodiment, the output of the target model is specifically "Trojan-Free" or "Trojan-Inserted".

[0055] Furthermore, to verify the effectiveness of the hardware Trojan detection method proposed in this invention, a set of independent test sets were used for batch testing, and a series of key performance indicators were calculated as model evaluation indicators, including accuracy, precision, true positive rate (TPR, i.e., recall), true negative rate (TNR), false negative rate (FNR), false positive rate (FPR), and F1 score (balancing precision and recall).

[0056] In this embodiment, the evaluation indicators are further explained: The accuracy rate represents the overall prediction accuracy of the model and reflects its comprehensive detection capability. In hardware security scenarios, it needs to be analyzed in conjunction with recall to avoid the "accuracy trap," such as high accuracy but severe false negatives due to imbalanced samples. This can be represented by the following logic:

[0057] Where TP represents the number of correctly detected Trojan circuits, FN represents the number of undetected Trojan circuits, TN represents the number of correctly identified normal circuits, and FP represents the number of normal circuits that were mistakenly identified as Trojans.

[0058] Precision represents the proportion of true positives among samples identified as Trojans. High precision means low false positives, reducing unnecessary design verification costs. For example, false positives can lead to misclassification of normal circuits. This can be represented by the following logic:

[0059] True Positive Rate (TPR) represents the percentage of genuine Trojans that are correctly detected, and is the most critical indicator of hardware security. False Negative Detections (FN) could lead to backdoor risks in chips, as represented by the following logic:

[0060] The True Negative (TNR) represents the ability of a normal circuit to be correctly identified, complementing the FPR. A high TNR ensures efficient design verification and avoids over-examination of harmless circuits, as represented by the following logic:

[0061] The false negative rate (FNR) represents the proportion of genuine Trojans that are not detected, and is directly related to security risks. It is represented by the following logic:

[0062] The false positive rate (FPR) represents the proportion of a normal circuit that is mistakenly identified as a Trojan. A high FPR increases verification overhead, but is less harmful than a high false negative rate (FNR), and can be represented by the following logic:

[0063] The F1 score (balancing precision and recall) represents the harmonic mean of precision and recall, used to balance the risks of false positives and false negatives, and is expressed using the following logic:

[0064] To verify the effectiveness of the hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning proposed in this embodiment, a systematic experiment was conducted on the TrustHub public dataset. Specifically, using AES circuits (54 samples) as the dataset, this embodiment constructed a multimodal joint feature set (a total of 2484 instruction data) containing structural, behavioral, and dynamic features, and used LoRA technology to fine-tune Qwen2.5-7B, ChatGLM3-6B, and Gemma-2B respectively. Figures 5-7 As shown, after fine-tuning, the overall performance of the three models on the independent test set improved by an average of more than 20%, specifically: Qwen2.5-7B improved by an average of 19.41% across all metrics, ChatGLM3-6B improved by an average of 22.45% across all metrics, and Gemma-2B improved by an average of 24.24% across all metrics.

[0065] Experimental results show that after fine-tuning and training using the method of this invention, all performance indicators of the target model are significantly improved.

[0066] like Figure 2As shown, the present invention also provides a detection system that applies the above-mentioned hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning, comprising: The preprocessing module is used to obtain the source code of the RTL design circuit under test and preprocess the source code of the RTL design circuit under test. The preprocessing includes code merging and simplification.

[0067] The multimodal feature extraction module is used to extract structural features, behavioral features, and dynamic features from the preprocessed RTL design circuit source code, and to structurally merge the structural features, behavioral features, and dynamic features to construct a multimodal joint feature set.

[0068] The detection instruction module is used to establish a hardware Trojan detection instruction set, including various natural language instructions.

[0069] The dataset generation module generates an instruction fine-tuning dataset based on a multimodal joint feature set and a hardware Trojan detection instruction set. Each structured data item in the instruction fine-tuning dataset is in the form of a triple, including an instruction, an input, and an output.

[0070] The model fine-tuning module is used to fine-tune the pre-trained language model using a parameter-efficient and lightweight fine-tuning method with an instruction fine-tuning dataset, resulting in a target model optimized for hardware Trojan detection.

[0071] The reasoning and analysis module is used to perform preprocessing on new circuits under test, construct new multimodal joint feature sets from the preprocessing module to the multimodal feature extraction module, and input the hardware Trojan detection instruction set into the target model for reasoning and analysis.

[0072] The model evaluation module is used to determine whether a new circuit under test contains a hardware Trojan based on the output of the target model, and to evaluate the model performance.

[0073] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hardware Trojan detection method based on multi-modal feature fusion and LLM fine-tuning, characterized in that, Includes the following steps: S1, Obtain the source code of the RTL design circuit to be tested, and preprocess the source code of the RTL design circuit to be tested, including code merging and simplification; S2, extract structural features, behavioral features and dynamic features from the preprocessed RTL design circuit source code, and structurally merge the structural features, behavioral features and dynamic features to construct a multimodal joint feature set; S3 establishes a hardware Trojan detection instruction set, including various natural language instructions; S4. Generate an instruction fine-tuning dataset based on the multimodal joint feature set and the hardware Trojan detection instruction set. Each structured data in the instruction fine-tuning dataset is in the form of a triple, including instruction, input, and output. S5 employs a parameter-efficient, lightweight fine-tuning method, using an instruction fine-tuning dataset to fine-tune the pre-trained language model, resulting in a target model optimized for hardware Trojan detection. S6, execute S1~S2 to construct a new multimodal joint feature set for the new circuit under test, and input the hardware Trojan detection instruction set into the target model for reasoning analysis; S7 determines whether the new circuit under test contains a hardware Trojan based on the output of the target model, and evaluates the model performance.

2. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 1, characterized in that, S2 includes the following: S21, by parsing the AST of the RTL code and extracting structural features, the structural features include module hierarchy, module instantiation relationship, port definition, signal declaration and assignment logic; S22, DFG is generated by logical synthesis of RTL code, and structural features are extracted, including operation nodes and signal dependencies in the data path; S23, by simulating and running the RTL code, dynamic features are extracted, including key signal trajectories; S24. The structural features, behavioral features and dynamic features extracted from S21 to S23 are structurally merged to form a unified multimodal description of the designed circuit and to construct a multimodal joint feature set.

3. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 2, characterized in that, Specifically, S21 involves: First, parsing the preprocessed RTL code in S1 using the open-source Verilog parsing tool PyVerilog to generate an AST; then, traversing the AST using a depth-first search algorithm to extract module hierarchy, module instantiation relationships, port definitions, signal declarations, and assignment logic information to form structural features; finally, storing the structural features in JSON format.

4. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 2, characterized in that, S22 specifically involves: using the open-source logic synthesis tool Yosys to synthesize the RTL code, converting the behavioral-level RTL description into an intermediate representation of gate-level logic, and exporting it through Yosys commands. From this representation, a DFG is parsed out, and the characteristics of the DFG in explicitly depicting the data path are utilized to extract the computation nodes and signal dependencies in the data path as key behavioral features.

5. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 2, characterized in that, S23 specifically involves: First, using the high-performance Verilog simulator Verilator to simulate the RTL code, converting the Verilog code into a high-performance C++ model and compiling it into an executable file; then, using an automated script to generate a C++ test platform to drive the simulation, applying preset input stimuli to the circuit; next, during the simulation, using the trace simulator option to generate a VCD waveform file that records the changes in signal values ​​over time; finally, parsing and extracting dynamic features from the VCD file.

6. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 2, characterized in that, The structured merging described in S24 specifically involves creating a JSON-formatted data object for each circuit sample under test. The data object includes a label field and three keys: structure, behavior, and dynamic, which respectively store structured data representing structural features, behavioral features, and dynamic features.

7. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 1, characterized in that, The instruction mentioned in S4 is specifically a single instruction randomly or sequentially selected from the hardware Trojan detection instruction set; the input is specifically a complete JSON object containing multimodal features constructed for any circuit in the multimodal joint feature set; the output is specifically the real label of the circuit corresponding to the input, including Trojan-Free and Trojan-Inserted, where Trojan-Free indicates no Trojan and Trojan-Inserted indicates the presence of a Trojan.

8. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 1, characterized in that, The pre-trained language model mentioned in S5 is specifically Qwen2.5-7B or ChatGLM3-6B; it employs standard low-rank adaptive techniques and is trained in an environment equipped with NVIDIA A100 GPU or higher computing resources.

9. The hardware Trojan detection method based on multimodal feature fusion and LLM fine-tuning according to claim 1, characterized in that, The model performance evaluation described in S7 specifically involves calculating key performance indicators as model evaluation metrics, including accuracy, precision, true positive rate, true negative rate, false negative rate, false negative rate, and F1 score.

10. A hardware Trojan detection system based on multimodal feature fusion and LLM fine-tuning, characterized in that, include: The preprocessing module is used to obtain the source code of the RTL design circuit under test and to preprocess the source code of the RTL design circuit under test, including code merging and simplification. The multimodal feature extraction module is used to extract structural features, behavioral features and dynamic features from the preprocessed RTL design circuit source code, and to structurally merge the structural features, behavioral features and dynamic features to construct a multimodal joint feature set; The detection instruction module is used to establish a hardware Trojan detection instruction set, including various natural language instructions; The dataset generation module generates an instruction fine-tuning dataset based on a multimodal joint feature set and a hardware Trojan detection instruction set. Each structured data item in the instruction fine-tuning dataset is in the form of a triple, including instruction, input, and output. The model fine-tuning module is used to fine-tune the pre-trained language model using a parameter-efficient and lightweight fine-tuning method with an instruction fine-tuning dataset to obtain a target model optimized for hardware Trojan detection. The reasoning and analysis module is used to perform preprocessing on the new circuit under test to construct a new multimodal joint feature set from the preprocessing module to the multimodal feature extraction module, and to input the hardware Trojan detection instruction set into the target model for reasoning and analysis. The model evaluation module is used to determine whether a new circuit under test contains a hardware Trojan based on the output of the target model, and to evaluate the model performance.

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