A method and system for constructing a three-dimensional thermal network model for power modules

Abstract

This invention discloses a method and system for constructing a three-dimensional thermal network model for power modules. The invention first obtains the parameters of each material layer and the convective heat transfer coefficient of the fluid. Through single-chip simulation, the distribution of heat flux density along the thickness direction is obtained. After fitting the heat flux density attenuation coefficient, the equivalent heat transfer area is derived based on heat flux conservation and abstracted as an equal-area ellipse. After physical boundary trimming and overlapping region division, the effective heat transfer area is obtained. Based on this, a longitudinal thermal resistance is constructed, and a lateral coupling thermal resistance is established based on the chip center distance and overlapping area. Simultaneously, the effective area of ​​the heat sink bottom surface is mapped to the fin side, and the convective heat transfer thermal resistance is calculated. Using the effective heat transfer area of ​​each layer as temperature nodes, the equivalent heat capacity is obtained by discrete integration over the material layer volume. Finally, each thermal resistance and heat capacity is used as a basic element to form a three-dimensional thermal network model. This method can uniformly handle boundary effects and multi-chip thermal coupling, is applicable to different power modules and heat dissipation structures, and enables rapid thermal design.

Description

Technical Field

[0001] This invention belongs to the field of thermal management of power semiconductor devices, and particularly relates to a method and system for constructing a three-dimensional thermal network model for power modules. Background Technology

[0002] With the rapid development of applications such as new energy vehicles, power electronics, and variable frequency drives, the integration of power modules is constantly increasing and operating conditions are becoming more stringent. This leads to a continuous rise in the operating temperature of IGBT modules, significantly increasing their failure risk. Studies have shown that high temperature factors account for approximately 55% of failure causes. Therefore, developing efficient thermal management solutions to enhance the heat dissipation capacity of IGBT modules, reduce chip junction temperature, and improve reliability is crucial.

[0003] Currently, high-power-density, multi-chip integrated power modules widely adopt ceramic copper-clad substrates, thick copper layers, and high-performance heat sink structures. In such structures, there are obvious lateral thermal diffusion and thermal coupling phenomena between chips. At the same time, the thickness and thermal conductivity of the multilayer materials inside the module vary significantly, resulting in insufficient accuracy of junction temperature or device temperature prediction models based solely on one-dimensional thermal conductivity assumptions.

[0004] On the other hand, junction temperature calculation of power modules based on thermal network models has become a research hotspot in power module reliability operation technology. Numerous academic papers have conducted theoretical analyses, while practical methods for engineering applications have also emerged. For example, the Chinese invention patent "Online Junction Temperature Calculation Method for Three-Phase IGBT Power Modules" (CN111783287B) proposes an online junction temperature calculation algorithm suitable for three-phase IGBT modules; the Chinese invention patent "A Junction Temperature Prediction Method and System for Power Semiconductor Devices" (CN118965842B) incorporates contact thermal resistance into the junction temperature prediction model based on fractal contact theory.

[0005] Chinese invention patent CN111783287B establishes a transient loss model and a Foster-type thermal network model for a three-phase IGBT power module. It represents the thermal network as a state-space equation and discretizes it, thereby enabling online calculation of the junction temperature of each chip within the three-phase IGBT power module on a digital signal processor. While this method details the power loss modeling approach and the online calculation process, it still has the following shortcomings:

[0006] 1. Its thermal network model adopts the traditional n-order Foster type RC network. The thermal resistance and thermal capacity parameters are mostly obtained by overall fitting. It lacks a physical layer description of the internal thermal diffusion process of multiple layers such as chip, solder, metal layer, ceramic layer and heat sink. It is difficult to accurately reflect the thermal diffusion and thermal coupling path between multiple chips under finite size in the model.

[0007] 2. This method focuses on how to efficiently calculate the junction temperature online under known thermal network parameters. It does not provide a general systematic method for constructing a three-dimensional thermal network model and its parameters from geometric and material parameters. In particular, it lacks a mechanism for extracting and updating thermal resistance and thermal capacity parameters for complex encapsulation structures.

[0008] Chinese invention patent CN118965842 B starts with the contact thermal resistance of thyristors and power semiconductor devices, and uses fractal contact theory to obtain the contact thermal resistance of each contact surface under different normal loads. It then uses both bulk thermal resistance and contact thermal resistance in the junction temperature prediction model, thereby improving the accuracy of junction temperature prediction and reflecting the influence of normal loads on junction temperature. This method is highly targeted in contact interface modeling, but it also has the following shortcomings:

[0009] 1. Its thermal resistance modeling mainly focuses on the interlayer contact interface. The thermal diffusion inside each solid layer is mostly modeled using a one-dimensional volume thermal resistance model. It assumes that the cross-sectional area does not change with the thickness and does not consider the significant lateral thermal diffusion effect and the evolution of heat transfer area with depth in high power density and multi-chip modules.

[0010] 2. This method establishes a junction temperature prediction model for a single device or a one-dimensional heat transfer path. It does not construct a three-dimensional thermal network structure that can simultaneously characterize longitudinal heat diffusion, finite-size boundary obstacles, and multi-chip lateral thermal coupling for multi-chip power modules. Furthermore, the modeling of node thermal capacity is still relatively coarse.

[0011] In summary, existing technologies either focus on efficient online junction temperature calculation based on given thermal network parameters or on obtaining the thermal resistance of the contact interface. There is still a lack of a method to construct a three-dimensional thermal network model that can start from the single-chip calibration conditions, systematically characterize the internal thermal diffusion, boundary effects and multi-chip thermal coupling of multi-layer structures, and simultaneously and accurately construct the node thermal capacity and convective heat transfer thermal resistance. Summary of the Invention

[0012] The purpose of this invention is to overcome the shortcomings of existing three-dimensional thermal network models in describing heat diffusion, boundary effects, and multi-chip thermal coupling. It proposes a method and system for constructing a three-dimensional thermal network model for power modules. This method extracts key heat transfer characteristics from single-chip calibration conditions and considers longitudinal heat conduction, lateral coupling, convective heat transfer, and node heat capacity in a multi-layered structure within a unified framework. This results in the construction of a three-dimensional thermal network model suitable for predicting steady-state and transient junction temperatures under multiple operating conditions. This model is applicable to junction temperature prediction and thermal design of multi-chip power modules such as IGBT / FRD modules and SiC modules.

[0013] To achieve the above-mentioned objectives, the present invention specifically adopts the following technical solution:

[0014] In a first aspect, the present invention provides a method for constructing a three-dimensional thermal network model for a power module, comprising the following steps:

[0015] S1. Obtain the parameters of each material layer in the power module, including the thickness, thermal conductivity, specific heat capacity at constant pressure, density of each material layer, and the position of each chip in each material layer in the plane of the power module. At the same time, obtain the convective heat transfer coefficient of the fluid medium used to cool the power module.

[0016] S2. For each chip type, select a calibration chip to perform single-chip conduction simulation, thereby sampling the average heat flux density of the chip projection area along the thickness direction in each material layer, and obtaining the distribution data of the heat flux density of each chip in each material layer as a function of the thickness coordinate of that layer.

[0017] S3. Based on the heat flux density distribution data obtained in S2, the heat flux density of each layer is fitted to obtain the heat flux density attenuation coefficient; further combined with the heat flux conservation relationship, the equivalent heat transfer area distribution of each chip in each material layer as a function of thickness coordinate is obtained.

[0018] S4. The equivalent heat transfer area is abstracted into an equal-area ellipse. The major and minor axes of the ellipse are determined according to the orientation of the chip in the power module plane. When the ellipse exceeds the physical boundary of any material layer in the power module plane, the area exceeding the physical boundary is subtracted from the corresponding equivalent heat transfer area and the ellipse, thereby obtaining the true heat transfer area distribution of each chip in each material layer as the thickness coordinate changes.

[0019] S5. In each layer, if the two ellipses obtained in S4 overlap, the two intersection points generated by the overlap are connected to divide the overlapping area into sub-regions belonging to different chips, so as to obtain the effective heat transfer area distribution of each chip in each material layer as the thickness coordinate changes under multi-chip conditions.

[0020] S6. Based on the effective heat transfer area of ​​each layer, model the heat conduction path of each chip in the thickness direction and construct the longitudinal thermal resistance; for two chips that overlap in the same layer, establish the lateral coupling thermal resistance based on the center distance between the two chips and the area of ​​the overlapping area.

[0021] S7. Based on the heat sink structure, fin parameters and convective heat transfer coefficient, map the effective heat transfer area of ​​the chip on the bottom surface of the heat sink to the side surface of the fins or the surface of the root plate, and calculate the corresponding convective heat transfer thermal resistance.

[0022] S8. The effective heat transfer area of ​​each chip in each material layer is used as the temperature node in the three-dimensional thermal network model to represent the temperature distribution of each chip in each material layer. For other temperature nodes except the fin root layer, the volume of the material layer is discretely integrated based on the effective heat transfer area distribution in the corresponding material layer to obtain the equivalent heat capacity of the temperature node.

[0023] S9. The longitudinal thermal conduction resistance, the transverse coupling thermal resistance, the convective heat transfer resistance, and the equivalent heat capacity corresponding to each temperature node are used as the basic components of the three-dimensional thermal network model to form a three-dimensional thermal network model with multiple temperature nodes, which is used to model the heat conduction process of the power module.

[0024] Based on the above scheme, each step can be implemented in the following preferred manner.

[0025] As a preferred embodiment of the first aspect, in S1, each material layer of the power module is sequentially connected in the thickness direction by a chip layer, a chip solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer, a heat sink layer, and a fin root layer.

[0026] As a preferred option of the first aspect mentioned above, the specific process of S2 is as follows: For each chip type, only one chip is activated to generate heat, while the other chips do not generate heat, forming a single-chip calibration condition. Numerical simulation is performed under this condition. Multiple cross sections are set along the thickness coordinate direction of the chip's projection area, and the average heat flux density within the chip's projection area of ​​each cross section is extracted. Finally, the distribution data of the heat flux density in each material layer as a function of the layer's thickness coordinate is obtained.

[0027] As a preferred embodiment of the first aspect mentioned above, the specific process of S3 is as follows:

[0028] S31. In the Within the layer, a first-order linear model is used to approximate the heat flux density distribution data:

[0029] ;

[0030] in, For chips In the In-layer and thickness coordinates The average heat flux density at that location; For chips In the Average heat flux density at the upper surface of the layer; For chips In the The heat flux density attenuation coefficient of the layer;

[0031] S32. Based on the heat flux conservation principle, the equivalent heat transfer area distribution is obtained:

[0032] ;

[0033] in, For chips In the In-layer and thickness coordinates The heat transfer area at that location; For chips Entering the The equivalent heat transfer area of ​​the layer.

[0034] As a preferred embodiment of the first aspect mentioned above, in S4, under the single-chip calibration condition, the equivalent heat transfer area of ​​each layer is abstracted into an ellipse with the same area. The major axis of the ellipse is parallel to the long side of the chip, the minor axis of the ellipse is parallel to the short side of the chip, the center of the ellipse coincides with the projection center of the chip in that layer, and the ratio of the major axis to the minor axis of the ellipse is equal to the ratio of the long side to the short side of the chip.

[0035] As a preferred embodiment of the first aspect mentioned above, in S5, for a pair of chips that overlap... Define the pair of chips in the first... Layer thickness location The area of ​​the overlapping region at that location is After dividing the overlapping area by connecting the intersection points, it will be closer to the chip. The area allocated to the chip The area of ​​the sub-region is denoted as . , will be close to the chip The area allocated to the chip The sub-region is defined, and its area is denoted as . Then the chip In the Layer thickness location Effective heat transfer area at the location for:

[0036] ;

[0037] in, For chips In the Layer thickness location The actual heat transfer area at that location.

[0038] As a preferred embodiment of the first aspect mentioned above, in S6, the chip... and chips In the Lateral coupling thermal resistance of the layer Defined as:

[0039] ;

[0040] in, For the first The lateral thermal resistance correction factor of the layer; For chips Center and chip Distance from the center; For the first Layer thickness; For the first The thermal conductivity of the layer; For chips and chips In the The overlapping heat transfer area at the center thickness of the layer.

[0041] In a second aspect, the present invention provides a three-dimensional thermal network model construction system for power modules, for implementing the three-dimensional thermal network model construction method for power modules as described in any of the solutions in the first aspect above.

[0042] Thirdly, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method for constructing a three-dimensional thermal network model for a power module as described in any of the solutions of the first aspect above.

[0043] Fourthly, the present invention provides a computer electronic device, which includes a memory and a processor;

[0044] The memory is used to store computer programs;

[0045] The processor is configured to, when executing the computer program, implement the method for constructing a three-dimensional thermal network model for a power module as described in any of the first aspects above.

[0046] Compared with the prior art, the present invention has the following advantages:

[0047] The heat flux density attenuation coefficient of this invention has a clear physical meaning: by fitting the linear change of heat flux density of each layer under single-chip calibration conditions, the obtained heat flux density attenuation coefficient directly reflects the strength of heat diffusion, so that the evolution of the real heat transfer area and the effective heat transfer area with depth has a clear physical explanation.

[0048] This invention designs a unified elliptical geometric modeling and boundary treatment framework: This invention uses an equal-area ellipse to abstract the shape of the heat transfer area of ​​each layer, and combines it with the encapsulation plane boundary for geometric trimming. Under the same framework, it simultaneously handles the finite size effect and the constraint of the approximate adiabatic boundary on heat diffusion, avoiding a large number of empirical boundary corrections.

[0049] This invention constructs longitudinal thermal conduction resistance and lateral coupling thermal resistance: the longitudinal thermal conduction resistance is calculated based on the effective heat transfer area, and the lateral coupling thermal resistance is determined by the chip center distance and the area of ​​the elliptical overlapping region. The multi-chip coupling relationship is naturally mapped to the thermal network through geometric overlap, which is more physically interpretable and scalable than the traditional empirical coupling thermal resistance model.

[0050] This invention has a wide range of applications and is easy to couple with other models: The method of this invention can be applied to multi-chip power modules such as IGBT / FRD and SiC with different sizes and arrangements, as well as various heat sink / cold plate structures. The final three-dimensional thermal network is expressed in the form of thermal conductivity matrix and thermal capacity matrix, which is convenient to couple with circuit simulation, control algorithm or neural network model to realize applications such as rapid thermal design, online prediction and health management. Attached Figure Description

[0051] Figure 1 This is a flowchart of the method of the present invention;

[0052] Figure 2 This is a schematic diagram of the chip arrangement of the single-phase half-bridge arm of the power module in the upper copper layer plane in an embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram of an elliptical heat transfer region of equal area within a copper layer of a chip of limited size in an embodiment of the present invention.

[0054] Figure 4 This is a schematic diagram of the node connections of the three-dimensional thermal network model in an embodiment of the present invention;

[0055] Figure 5 A comparison chart showing the chip temperature calculated using the three-dimensional thermal network model constructed by the method of this invention and the numerical simulation value. Detailed Implementation

[0056] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. Technical features in the various embodiments of the present invention can be combined accordingly without mutual conflict.

[0057] In the description of this invention, it should be understood that the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include at least one of those features.

[0058] like Figure 1 As shown, in a preferred embodiment of the present invention, the method for constructing a three-dimensional thermal network model for a power module includes the following steps S1 to S9. The specific implementation process of each step will be described in detail below.

[0059] S1. Obtain the parameters of each material layer in the power module, including the thickness, thermal conductivity, specific heat capacity at constant pressure, density of each material layer, and the position of each chip in each material layer in the plane of the power module. And obtain the convective heat transfer coefficient of the fluid medium used to cool the power module through simulation or experiment.

[0060] It should be noted that in S1 of this invention, as Figure 2 As shown, the single-phase half-bridge arm of the power module includes 3 IGBT chips and 3 diode chips, for a total of 6 chips. The chip numbers are denoted as follows: The chip is soldered to the upper copper layer using chip solder. The upper copper layer is sequentially connected to the ceramic layer, the lower copper layer, and the substrate solder layer. Below this is the heat sink and its fins. The material layers are numbered sequentially along their thickness direction. These correspond to the chip layer, chip solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer, heat sink layer, and fin root layer, respectively. The encapsulating adhesive in the power module provides approximately thermally insulating constraints to the planar boundaries of the chip, upper copper layer, and ceramic layer. The position of each chip within the power module plane includes its long side dimension, short side dimension, and chip center coordinates within the power module plane.

[0061] S2. For each chip type, select a calibration chip to perform single-chip conduction simulation, thereby sampling the average heat flux density of the chip projection area along the thickness direction in each material layer, and obtaining the distribution data of the heat flux density of each chip in each material layer as a function of the thickness coordinate of that layer.

[0062] It should be noted that the specific process of S2 in this invention is as follows: For each chip type, only one chip is excited to conduct and generate heat, while the other chips do not generate heat, forming a single-chip calibration condition. Numerical simulation is performed under this condition. Multiple cross sections are set along the thickness coordinate direction of the chip's projection area, and the average heat flux density in the chip's projection area of ​​each cross section is extracted. Finally, the distribution data of the heat flux density in each material layer as a function of the layer's thickness coordinate is obtained.

[0063] In this embodiment, a chip location far from the upper copper layer boundary and the substrate boundary is typically selected as the heat-generating chip. Definition For chips In the In-layer and thickness coordinates The average heat flux density at that location, This indicates the chip type; it can be either an IGBT or a diode. Indicates the first The thickness coordinates within the layer along the heat transfer direction. between 0 and Changes between Indicates the first The upper surface of the layer, Indicates the first On the lower surface of the layer, heat is transferred from top to bottom, with the direction of heat transfer being positive.

[0064] S3. Based on the heat flux density distribution data obtained in S2, the heat flux density of each layer is fitted to obtain the heat flux density attenuation coefficient, which is used to reflect the heat flux attenuation relationship of heat diffusion characteristics; further combined with the heat flux conservation relationship, the equivalent heat transfer area distribution of each chip in each material layer as the thickness coordinate changes is obtained.

[0065] It should be noted that the specific process of S3 in this invention is as follows:

[0066] S31. In the Within the layer, a first-order linear model is used to approximate the heat flux density distribution data:

[0067] ;

[0068] in, For chips In the In-layer and thickness coordinates The average heat flux density at that location; For chips In the Average heat flux density at the upper surface of the layer; For chips In the The heat flux density attenuation coefficient of the layer.

[0069] S32. Based on the heat flux conservation principle, the equivalent heat transfer area distribution is obtained:

[0070]

[0071] in, For chips In the In-layer and thickness coordinates The heat transfer area at that point is used to represent the cross-sectional area of ​​the material that actually participates in the heat transfer of the chip at that thickness coordinate. For chips Entering the The equivalent heat transfer area of ​​the layer.

[0072] In this embodiment, considering that almost no thermal diffusion occurs between the chip layer and the chip solder layer, therefore... The constant is the chip area; for the upper copper layer, that is, when hour, For chip area; and when hour, , For the first This type of chip is far away from the first The equivalent heat transfer area of ​​the layer.

[0073] S4. The equivalent heat transfer area is abstracted into an equal-area ellipse. The major and minor axes of the ellipse are determined according to the orientation of the chip in the power module plane. When the ellipse exceeds the physical boundary of any material layer in the power module plane, the area exceeding the physical boundary is subtracted from the corresponding equivalent heat transfer area and the ellipse. This process handles the finite-size boundary, thereby obtaining the true heat transfer area distribution of each chip in each material layer as the thickness coordinate changes.

[0074] It should be noted that in S4 of the present invention, under the single-chip calibration condition, the equivalent heat transfer area of ​​each layer is abstracted as an ellipse with the same area. The major axis of the ellipse is parallel to the long side of the chip, the minor axis of the ellipse is parallel to the short side of the chip, the center of the ellipse coincides with the projection center of the chip in that layer, and the ratio of the major axis of the ellipse to the minor axis of the chip is equal to the ratio of the long side to the short side of the chip.

[0075] In this embodiment, each chip is matched with a heat flux density attenuation coefficient and equivalent heat transfer area corresponding to its chip type, i.e., chip... correspond ,chip correspond .exist In the material layer, the chip equivalent heat transfer area Represented by ellipses of equal area, draw ellipses corresponding to the equivalent heat transfer areas of each chip in the same plane, such as... Figure 3 As shown. When the ellipse extends beyond the physical boundary of any layer of material within the power module plane, it is assumed that the portion extending beyond the physical boundary no longer transfers heat outward. The chip's geometric intersection with the physical boundary of this layer is calculated to obtain the chip's... Area beyond physical boundaries And this area is subtracted from the equivalent heat transfer area and the corresponding ellipse, that is:

[0076]

[0077] in, For chips In the Layer thickness location The actual heat transfer area at that location.

[0078] S5. In each layer, if the two ellipses obtained in S4 overlap, the two intersection points generated by the overlap are connected, thereby dividing the overlapping area into sub-regions belonging to different chips, so as to obtain the effective heat transfer area distribution of each chip in each material layer as the thickness coordinate changes under multi-chip conditions.

[0079] It should be noted that in S5 of the present invention, as Figure 3 As shown, the ellipse corresponding to the chip intersects not only the boundary of the upper copper layer, but also between different chips. Therefore, for a pair of overlapping chips... In this embodiment, the pair of chips is defined in the first... Layer thickness location The area of ​​the overlapping region at that location is After dividing the overlapping area by connecting the intersection points, it will be closer to the chip. The area allocated to the chip The area of ​​the sub-region is denoted as . , will be close to the chip The area allocated to the chip The sub-region is defined, and its area is denoted as . Then the chip In the Layer thickness location Effective heat transfer area at the location for:

[0080] .

[0081] The above processing only affects the effective heat transfer area of ​​each layer and does not change the recursive relationship of the area between layers. For each chip, the area of ​​the sub-region allocated to other chips is subtracted from its actual heat transfer area to obtain the effective heat transfer area of ​​each chip in each layer under multi-chip operation, forming a heat transfer area distribution that can characterize the thermal coupling of multiple chips.

[0082] S6. Based on the effective heat transfer area of ​​each layer, model the heat conduction path of each chip in the thickness direction and construct the longitudinal thermal resistance; for two chips that overlap in the same layer, establish the lateral coupling thermal resistance based on the center distance between the two chips and the area of ​​the overlapping area.

[0083] It should be noted that, in this embodiment, as Figure 4 As shown, for each chip, a vertical thermal resistance link is constructed from the chip layer to the heat sink layer. Simultaneously, a lateral coupling thermal resistance link is constructed between chips in each layer according to their intersections. Since all chips are already connected on the upper copper layer, as the ellipse area increases in lower layers, lateral coupling thermal resistance connections will no longer be constructed for newly added intersections.

[0084] Specifically, chips In the Longitudinal thermal resistance of the layer Defined as:

[0085]

[0086] in, For the first Layer thickness; For chips In the The effective heat transfer area at the center thickness of the layer; For the first The thermal conductivity of the layer; The thickness coefficient is set to 0.5 for the chip layer and 1 for the other layers.

[0087] In this embodiment, for the chip layer and chip solder layer, a one-dimensional thermal conductivity model based on the chip geometry is used to calculate the corresponding longitudinal thermal resistance; for the remaining layers, the effective heat transfer area at the middle thickness of the corresponding layer is used as the heat transfer cross section to calculate the corresponding longitudinal thermal resistance. Of course, the above formula can also be used for all calculations.

[0088] Specifically, chips and chips In the Lateral coupling thermal resistance of the layer Defined as:

[0089]

[0090] in, For the first In this embodiment, the lateral thermal resistance correction factor of the layer can be taken as 0.1-1; For chips Center and chip Distance from the center; For the first Layer thickness; For the first The thermal conductivity of the layer; For chips and chips In the The overlapping heat transfer area at the center thickness of the layer.

[0091] It should be noted that the aforementioned lateral coupling thermal resistance is only constructed in the upper copper layer, ceramic layer, lower copper layer, substrate solder layer, and heat sink layer, i.e. The chip center distance, layer thickness, thermal conductivity and overlapping heat transfer area are respectively taken from the calculation results of the corresponding layers; the lateral thermal resistance correction coefficient can be calibrated by minimizing the error between the temperature predicted by the three-dimensional thermal network model and the reference simulation or measured temperature under the single chip conduction condition.

[0092] S7. Based on the heat sink structure, fin parameters and convective heat transfer coefficient, map the effective heat transfer area of ​​the chip on the bottom surface of the heat sink to the side surface of the fins or the surface of the root plate, and calculate the corresponding convective heat transfer resistance.

[0093] It should be noted that the calculation of convective heat transfer thermal resistance in this invention is a prior art method. In this embodiment, it is briefly described as follows: For the heat sink layer, based on the heat sink channel geometry and fin parameters, the total area at the root of the heat sink, the fin side area, and the net flat plate area at the root are calculated; through the area deduction in the above steps, the chip is obtained. The effective heat transfer area at the bottom of the radiator is mapped proportionally to the fin side surface and the root plate surface. Given the convective heat transfer coefficient and fin efficiency, the corresponding equivalent convective heat transfer area is calculated. This allows us to obtain the convective heat transfer resistance between each chip and the reference coolant node. The convective heat transfer resistance of each chip is equal to the reciprocal of the product of the convective heat transfer coefficient and the equivalent convective heat transfer area. This convective heat transfer resistance is used to connect the bottom node of the heat sink to the reference coolant node, where the reference node temperature is taken as the coolant inlet temperature or average temperature.

[0094] S8. The effective heat transfer area corresponding to each chip in each material layer is used as the temperature node in the three-dimensional thermal network model to represent the temperature distribution of each chip in each material layer; for other temperature nodes except the fin root layer, the volume of the material layer is discretely integrated according to the effective heat transfer area distribution in the corresponding material layer to obtain the equivalent heat capacity of the temperature node.

[0095] It should be noted that the calculation of the equivalent heat capacity of temperature nodes in this invention is a prior art method. In this embodiment, it is briefly described as follows: The effective heat transfer area is calculated by subtracting the invalid region caused by boundary truncation and the region allocated to other chips in the case of overlapping heat diffusion among multiple chips, based on the equivalent heat transfer area of ​​a single chip. This ensures that the material volume corresponding to each temperature node is consistent with the material region actually involved in the heat transfer at that temperature node. For each temperature node, the thickness direction of the material layer is discretized, and the effective heat transfer area at the center of each segment is weighted and integrated. Multiplying this by the density of the material layer and the specific heat capacity at constant pressure yields the equivalent heat capacity of that temperature node. (i.e., chip) In the (Equivalent heat capacity of the layer)

[0096]

[0097] in, For the first The number of small segments discrete out along the thickness direction of the layer; For the first The center thickness coordinates of each small segment; For chips In the layer Effective heat transfer area at the location; For the first Layer density; For the first The specific heat capacity at constant pressure of the layer; To keep the distance from the walk, usually take .

[0098] For the chip layer, since the temperature node at the root of the chip is usually located at the chip's heat-generating surface or a representative position in the chip's thickness direction, its equivalent heat capacity is calculated based on the chip's actual geometric volume or half-thickness equivalent volume. For the chip solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer, and heat sink layer, the equivalent heat capacity of the node is calculated using the above-mentioned discrete integration method along the thickness direction.

[0099] S9. The longitudinal thermal conduction resistance, the transverse coupling thermal resistance, the convective heat transfer resistance, and the equivalent heat capacity corresponding to each temperature node are used as the basic components of the three-dimensional thermal network model to form a three-dimensional thermal network model with multiple temperature nodes, which is used to model the heat conduction process of the power module.

[0100] It should be noted that after constructing the three-dimensional thermal network model, this invention establishes the topological relationship of the three-dimensional thermal network model structure based on the connection relationship between each thermal resistance element and each temperature node. This allows the model's steady-state and transient thermal behaviors to be described through its state equations, which are then used to solve for the steady-state or transient temperature of the power module. Specifically, to facilitate the matrix-style construction, this embodiment uses chip numbers... With material layer number Corresponding two-dimensional temperature nodes Unified mapping to global node number Specifically, the number of chips is The number of material layers is Therefore, the total number of nodes in the three-dimensional heat network model is The reference coolant node is used as the known temperature boundary node, excluding globally unknown temperature nodes. The mapping relationship can be expressed as follows: Let all unknown temperature nodes, the equivalent heat capacity of nodes, and the chip power injection be represented as follows: , and And further written as a nodal temperature vector. Equivalent heat capacity matrix and chip power vector .in , , , This is the matrix transpose. Indicates matrix diagonalization. These represent the individual temperature values ​​in the node temperature vector. These represent the equivalent heat capacity values ​​in the equivalent heat capacity matrix. These represent the power values ​​of each chip in the equivalent thermal capacity matrix. Each thermal resistance branch is uniformly represented as a global node. and global nodes The connections between these include longitudinal thermal resistance links between adjacent material layers, lateral coupling thermal resistance links between chips within the same material layer, and convective heat transfer thermal resistance links between the heat sink bottom temperature node and the reference coolant temperature node. For global nodes... and global nodes thermal resistance between The corresponding thermal conductivity is defined as And according to Kirchhoff's current law, the thermal conductivity matrix is ​​assembled based on the connection relationship between each node, that is, the diagonal elements are the nodes. The sum of all connected thermal conductivities, with off-diagonal elements representing the connection nodes. and The thermal conductivity is negative; the corresponding element is zero when there is no direct connection. Finally, the state equation of the three-dimensional thermal network model consists of the equivalent heat capacity matrix, thermal conductivity matrix, node temperature vector, and chip power vector. Through steady-state solutions or time-stepped solutions, the steady-state and transient junction temperature distributions of the power module under various operating conditions can be obtained. Under steady-state conditions, the equilibrium temperature of each temperature node under power injection is solved based on the three-dimensional thermal network model; under transient conditions, the change process of each temperature node over time is numerically solved based on the three-dimensional thermal network model, thereby obtaining the chip junction temperature and internal key node temperatures of the power module under different operating conditions.

[0101] To better demonstrate the specific implementation and technical effects of the present invention, the method for constructing a three-dimensional thermal network model for a power module shown in steps S1 to S9 of the above preferred implementation will be applied to a specific example.

[0102] Example

[0103] The specific implementation process of the three-dimensional thermal network model construction method for the power module used in this embodiment is as described above and will not be repeated here.

[0104] To verify the computational accuracy of the three-dimensional thermal network model proposed in this invention, this embodiment tests a single-phase half-bridge power module using computer simulation. The power module contains 3 IGBT chips and 3 diode chips, totaling 6 chips. The dynamic response of the junction temperature of each chip is predicted under variable power periodic excitation, and compared with the numerical simulation results based on numerical heat transfer (first comparison method) as a reference benchmark.

[0105] like Figure 5 As shown, under the same power excitation, the transient temperature prediction results of the junction of chip 1 and chip 2 obtained by the method of the present invention are in high agreement with the numerical simulation. The peak junction temperature and dynamic thermal response process can be accurately reproduced. It can be seen that the three-dimensional thermal network model proposed in this invention can effectively characterize the thermal diffusion characteristics of multi-layer packaging structure and the thermal coupling effect of multi-chips, while the calculation accuracy is close to that of numerical simulation, and the calculation amount is much lower than that of the latter. It provides a technical means with both accuracy and efficiency for real-time junction temperature prediction and thermal reliability assessment of power modules.

[0106] It should also be noted that the method for constructing a three-dimensional thermal network model for a power module in the above embodiments can essentially be executed by a computer program or module. Therefore, similarly, based on the same inventive concept, another preferred embodiment of the present invention also provides a system for constructing a three-dimensional thermal network model for a power module, corresponding to the method for constructing a three-dimensional thermal network model for a power module provided in the above embodiments, for implementing the method for constructing a three-dimensional thermal network model for a power module provided in the above embodiments.

[0107] Similarly, based on the same inventive concept, another preferred embodiment of the present invention also provides a computer electronic device corresponding to the three-dimensional thermal network model construction method for power modules provided in the above embodiments, which includes a memory and a processor;

[0108] The memory is used to store computer programs;

[0109] The processor is configured to implement the three-dimensional thermal network model construction method for power modules in the above embodiments when executing the computer program.

[0110] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0111] Therefore, based on the same inventive concept, another preferred embodiment of the present invention also provides a computer-readable storage medium corresponding to the three-dimensional thermal network model construction method for power modules provided in the above embodiments. The storage medium stores a computer program, which, when executed by a processor, can implement the three-dimensional thermal network model construction method for power modules in the above embodiments.

[0112] It is understood that the aforementioned storage media may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Furthermore, the storage media may also be various media capable of storing program code, such as USB flash drives, external hard drives, magnetic disks, or optical discs.

[0113] It is understood that the processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0114] It should also be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the embodiments provided in this application, the division of steps or modules in the system and method is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple modules or steps may be combined or integrated together, and a module or step may also be split.

[0115] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, all technical solutions obtained through equivalent substitution or transformation fall within the protection scope of the present invention.

Claims

1. A method for constructing a three-dimensional thermal network model for a power module, characterized in that, Includes the following steps: S1. Obtain the parameters of each material layer in the power module, including the thickness, thermal conductivity, specific heat capacity at constant pressure, density of each material layer, and the position of each chip in each material layer in the plane of the power module. At the same time, obtain the convective heat transfer coefficient of the fluid medium used to cool the power module. S2. For each chip type, select a calibration chip to perform single-chip conduction simulation, thereby sampling the average heat flux density of the chip projection area along the thickness direction in each material layer, and obtaining the distribution data of the heat flux density of each chip in each material layer as a function of the thickness coordinate of that layer. S3. Based on the heat flux density distribution data obtained in S2, the heat flux density of each layer is fitted to obtain the heat flux density attenuation coefficient; further combined with the heat flux conservation relationship, the equivalent heat transfer area distribution of each chip in each material layer as a function of thickness coordinate is obtained. S4. Abstract the equivalent heat transfer area into an equal-area ellipse, and determine the major and minor axis directions of the ellipse according to the orientation of the chip in the power module plane; When the ellipse extends beyond the physical boundary of any material layer in the power module plane, the area extending beyond the physical boundary is subtracted from the corresponding equivalent heat transfer area and the ellipse, thereby obtaining the true heat transfer area distribution of each chip in each material layer as the thickness coordinate changes. S5. In each layer, if the two ellipses obtained in S4 overlap, the two intersection points generated by the overlap are connected to divide the overlapping area into sub-regions belonging to different chips, so as to obtain the effective heat transfer area distribution of each chip in each material layer as the thickness coordinate changes under multi-chip conditions. S6. Based on the effective heat transfer area of ​​each layer, model the heat conduction path of each chip in the thickness direction and construct the longitudinal thermal resistance; for two chips that overlap in the same layer, establish the lateral coupling thermal resistance based on the center distance between the two chips and the area of ​​the overlapping area. S7. Based on the heat sink structure, fin parameters and convective heat transfer coefficient, map the effective heat transfer area of ​​the chip on the bottom surface of the heat sink to the side surface of the fins or the surface of the root plate, and calculate the corresponding convective heat transfer thermal resistance. S8. The effective heat transfer area of ​​each chip in each material layer is used as the temperature node in the three-dimensional thermal network model to represent the temperature distribution of each chip in each material layer. For other temperature nodes except the fin root layer, the volume of the material layer is discretely integrated based on the effective heat transfer area distribution in the corresponding material layer to obtain the equivalent heat capacity of the temperature node. S9. The longitudinal thermal conduction resistance, the transverse coupling thermal resistance, the convective heat transfer resistance, and the equivalent heat capacity corresponding to each temperature node are used as the basic components of the three-dimensional thermal network model to form a three-dimensional thermal network model with multiple temperature nodes, which is used to model the heat conduction process of the power module.

2. The method for constructing a three-dimensional thermal network model for a power module as described in claim 1, characterized in that, In S1, the material layers of the power module are sequentially connected in the thickness direction as follows: chip layer, chip solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer, heat sink layer, and fin root layer.

3. The method for constructing a three-dimensional thermal network model for a power module as described in claim 1, characterized in that, The specific process of S2 is as follows: For each chip type, only one chip is excited to conduct and generate heat, while the other chips do not generate heat, forming a single-chip calibration condition. Numerical simulation is performed under this condition. Multiple cross sections are set along the thickness coordinate direction of the chip's projection area, and the average heat flux density in the chip's projection area of ​​each cross section is extracted. Finally, the distribution data of the heat flux density in each material layer as a function of the thickness coordinate of that layer is obtained.

4. The method for constructing a three-dimensional thermal network model for a power module as described in claim 1, characterized in that, The specific process of S3 is as follows: S31. In the Within the layer, a first-order linear model is used to approximate the heat flux density distribution data: ； in, For chips In the In-layer and thickness coordinates The average heat flux density at that location; For chips In the Average heat flux density at the upper surface of the layer; For chips In the The heat flux density attenuation coefficient of the layer; S32. Based on the heat flux conservation principle, the equivalent heat transfer area distribution is obtained: ； in, For chips In the In-layer and thickness coordinates The heat transfer area at that location; For chips Entering the The equivalent heat transfer area of ​​the layer.

5. The method for constructing a three-dimensional thermal network model for a power module as described in claim 1, characterized in that, In S4, under single-chip calibration conditions, the equivalent heat transfer area of ​​each layer is abstracted as an ellipse with the same area. The major axis of the ellipse is parallel to the long side of the chip, the minor axis of the ellipse is parallel to the short side of the chip, the center of the ellipse coincides with the projection center of the chip in that layer, and the ratio of the major axis to the minor axis of the ellipse is equal to the ratio of the long side to the short side of the chip.

6. The method for constructing a three-dimensional thermal network model for a power module as described in claim 1, characterized in that, In S5, for a pair of overlapping chips... Define the pair of chips in the first... Layer thickness location The area of ​​the overlapping region at that location is After dividing the overlapping area by connecting the intersection points, it will be closer to the chip. The area allocated to the chip The area of ​​the sub-region is denoted as . , will be close to the chip The area allocated to the chip The sub-region is defined, and its area is denoted as . Then the chip In the Layer thickness location Effective heat transfer area at the location for: ； in, For chips In the Layer thickness location The actual heat transfer area at that location.

7. The method for constructing a three-dimensional thermal network model for a power module as described in claim 1, characterized in that, In S6, the chip and chips In the Lateral coupling thermal resistance of the layer Defined as: ； in, For the first The lateral thermal resistance correction factor of the layer; For chips Center and chip Distance from the center; For the first Layer thickness; For the first The thermal conductivity of the layer; For chips and chips In the The overlapping heat transfer area at the center thickness of the layer.

8. A three-dimensional thermal network model construction system for power modules, characterized in that, This method is used to implement the three-dimensional thermal network model construction method for power modules as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method for constructing a three-dimensional thermal network model for a power module as described in any one of claims 1 to 7.

10. A computer electronic device, characterized in that, Including memory and processor; The memory is used to store computer programs; The processor is configured to, when executing the computer program, implement the method for constructing a three-dimensional thermal network model for a power module as described in any one of claims 1 to 7.

Images